Memory cell and memory device for computing-in-memory

Abstract

Memory device comprising an array of memory cells, each column of the array driven by a current to generate a column output voltage and each row controlled by an input voltage, wherein a memory cell may comprise a first path with a first ohmic resistance and a first transistor, and a second path with a second transistor arranged in parallel wherein the first transistor is configured to switch between an active and an inactive state based on the input voltage such that, when the first transistor is active, an output voltage of the memory cell is proportional to the current driving the column and to the first ohmic resistance, and when the first transistor is inactive the output voltage of the memory cell is proportional to the current driving the column.

Description

[0001] 1

[0002] Memory cell and memory device for computing-in-memory FIELD OF THE INVENTION The invention relates to a memory cell for performing computing-in-memory operations. The invention also relates to a memory device comprising said memory cell for performing computing-in-memory operations. The invention further relates to a method for performing computing-in-memory operations using said memory cell. BACKGROUND OF THE INVENTION The advent of Artificial Intelligence (AI) and Internet-of-things (IoT) has led to a significant demand for edge computing and enabling Neural Network Implementation on edge devices. However, due to complex computations such as multiple-and- accumulate (MAC) operations, involved in the implementation of some of these technologies such as Neural networks, the traditional digital hardware based on the von- Neumann architecture is not well suited. Computation-in-Memory (CIM) is an attractive alternative in mitigating the challenges involved with traditional hardware by directly processing the data within the memory. It utilizes emerging non-volatile memory devices, for instance, Resistive Random Access Memory (RRAM) to perform in-place computations in the analogue domain, thereby, eliminating the bottlenecks associated with the constant movement of data in the von-Neumann architecture. However, the standard implementation of CIM comes with several challenges, with the primary being high power consumption. This is a problem for several applications running Neural networks, where large amounts of computations is required. Figure 1 depicts a typical implementation of a MAC operation over CIM, where M×N bit cells implemented with memresistive components are arranged in a 2D crossbar array and programmed to certain conductance states. Each memristor is connected across its respective Source line (SL) and Bit line (BL), which are the corresponding inputs and outputs of the crossbar. As seen in figure 1, a set of analogue voltages inputs are applied as inputs to the row Source Lines SL1…SLM, while the column Bit Lines BL1…BLNare maintained at a fixed voltage, in this instance 0 Volts (V). Now, utilizing Ohm’s law, the currents across each memristor ikj may be determined as follows: ikj= Vk.Gkj(equation 1) 2 wherein k = 1,…, M and j = 1,…, N, Vkis the k-th input voltage and Gkjis the conductance of the memresistor of the bitcell located at the position (k, j) of the 2D crossbar. From equation 1, it can be observed that the magnitude of memristor currents ikjconstitute one multiply operation, where the input voltage Vink is the first operand and memristor conductance Gkj is the second operand. Thus, a memristor crossbar of size M×N can perform M×N multiply operations simultaneously. Moreover, according to Kirchoff’s Current law, the memristor currents i1j …. iMj accumulate at their respective jth BL giving rise to final column currents Ij as depicted below: (equation 2) The magnitude of each column current Ij constitutes M addition operations, between M operands, i.e., the M memristor currents in jth column. Subsequently, a crossbar of size M×N can perform N such addition operations, of M operands through each column, in parallel. By substituting equation 1 in equation 2, it can be rewritten as below equation 3, to illustrate that the column current (Ij) is analogous to a single MAC operation between the input voltages and the memristor conductances in jth column. Accordingly, a crossbar of size M×N can perform N MAC operations simultaneously. (equation 3) 3

[0003] (equation 4) (equation 5) Consider now that the set of applied input voltages represent a vector ’V’ of size 1×M and the conductance values of the memristors constitute a matrix ’G’ of size M×N. It can be shown from equation 4 and equation 5 that the magnitude of resulting currents across N columns is equivalent to the final vector ’I’ of size 1×N, obtained on the multiplication of vector ’V’ and matrix ’G’. Therefore a standard CIM memristor crossbar of size M×N is capable of performing one Vector-Matrix Multiplication (VMM) operation between a vector of size M and a matrix of size M×N with complete parallelism, finishing the operation in one cycle. However, the conventional CIM crossbar as depicted in the figure 1, has issues with scalability owing to the parallel configuration of all the memristors as the total current througth the crossbar increases proportionally to the number of inputs as well as weights. Although, the currents through a single memristor is in the orders of sub µA, the total current through the crossbar can easily accumulate to the orders of mA if given enough size. This results in high power consumption that is unsuitable for edge devices expecting power consumption in the order of µW. It would be advantageous to implement a more power efficient architecture for performing computer-in-memory operations. SUMMARY OF THE INVENTION An objective of the invention is to implement a method and apparatus for performing computer-in-memory operations in an efficient and cost-effective way. In a first aspect, the invention provides a memory device comprising an array of memory cells, wherein each column of the array of memory cells may be respectively driven by a current and configured to respectively generate a column output voltage and each row of the array of memory cells may be respectively controlled by an input voltage, wherein a memory cell may comprise a first path with a first ohmic resistance and comprising a first transistor, and a second path may comprise a second ohmic resistance along with a second transistor, wherein the first path may be arranged in parallel with the second path. 4

[0004] Both the first and second transistor may be configured to switch between an active and an inactive state based on the input voltage controlling the row of the memory cell such that, when the first transistor is in the active state, the second transistor is in inactive state, an output voltage of the memory cell is proportional to the current driving the column of that memory cell and to the first ohmic resistance. When the first transistor is in the inactive state, the second transistor is in active state and the output voltage of the memory cell is proportional to the current driving the column of that memory cell and to second ohmic resistance. In this way, the power consumption of the memory device is independent from the number of input signals provided as input voltages as well as the number of memory cells while still allowing to perform operations in a flexible way. A multiply operation per column could be performed wherein, depending on the state of the input voltages, the column current I serves as the first operand, and the first ohmic resistance serves as the second operand while the second ohmic resistance is negligible (to represent off state of the memory cell in case the input voltage is low). Since all of the memory cells are connected in series, the output voltage of the memory cell (that is, voltage drop across the memory cell) accumulates as a result, constituting an addition operation of as many operands as rows in the column. A gate of the first transistor may be configured to receive the input voltage and to control the first transistor to switch between an active and an inactive state. This provides an efficient way of controlling the first path of the memory cell. The second transistor may be configured to switch between the active and the inactive state based on the input voltage controlling the corresponding row of the memory cell such that, when the first transistor is in the active state, the second transistor is in the inactive state, and when the first transistor is in the inactive state, the second transistor is in the active state. Thus, the memory cell may further comprise an inverter element electrically connected to a gate of the second transistor and configured to receive the input voltage of the corresponding column, to invert the input voltage, and to control the second transistor to switch between the active state and the inactive state based on the inverted input voltage, thus providing an efficient way of controlling both the first and second paths simultaneously. The first path may comprise a first non-volatile memory device, electrically connected in series with the first transistor and configured to switch among a plurality of resistance values. The second path may comprise a second non-volatile memory device, 5 electrically connected with the second transistor and configured to a fixed low resistance value. There may be no second non-volatile device as well. The first ohmic resistance corresponds to a resistance of the first non-volatile device or first path when the first transistor is in the active state and the second ohmic resistance corresponds to a resistance of the second non-volatile device or second path when the second transistor is in the active state. This is an efficient way of implementing the memory cell, providing extensive amount of operands for performing the intended operation. Each of the memory cells may further comprise of more paths, for instance a third and a fourth part, each with their respective ohmic resistances, electrically connected in parallel with the first and second paths. These additional paths may respectively comprise of a non-volatile memory device, configured to switch among a plurality of resistance values and each electrically connected in series with a transistor to control the respective paths. This allows to further expand the amount of operands available for performing operations. The non-volatile memory device may be configured to switch among a plurality of resistance values comprised between a low resistance value and a high resistance value. Each column may further comprise a current source arranged to generate a constant current and electrically connected in series with the memory cells of the corresponding column. In this way, by limiting the current generated by the current source, the current consumed by the memory device can be limited thereby also limiting the power consumed by the memory device. It also reduces the read disturb within memory devices which can otherwise corrupt the data if a high read current is used. The current source may be a reversible current source configured to invert a direction of the constant current. This way, by periodically reversing the current, it can be used to compensate for the deviated resistance states, which might happen over multiple read cycles, while still supporting the MAC operation. The current maybe further scaled down to different values from its initial value to further expand on the amount of input operands available to perform intended operations. The invention further relates to a method of performing a computing-in-memory operation using the memory device for a Neural network that involves massive MAC operations 6

[0005] The person skilled in the art will understand that the features described above may be combined in any way deemed useful. Moreover, modifications and variations described in respect of the system may likewise be applied to a method. BRIEF DESCRIPTION OF THE DRAWINGS In the following, aspects of the invention will be elucidated by means of examples, with reference to the drawings. The drawings are diagrammatic and are not drawn to scale. Figure 1 shows a scheme of a known implementation of MAC operation over CIM. Figure 2A shows a scheme of a memory device according to an embodiment of the invention. Figure 2B shows a scheme of the memory cell of Figure 2A according to an embodiment of the invention. Figure 2C shows a scheme of the memory cell of Figure 2A according to an alternative embodiment of the invention. Figures 3A-3B, 4A-4B, 5, and 6A-C show schemes of the memory cells bijof the memory device 200 of figure 2A according to embodiments of the invention. Figure 7 shows a flow chart of a method of performing a computing-in-memory operation using the memory device 200 shown in figure 2A. DETAILED DESCRIPTION OF EMBODIMENTS Figure 2A shows a scheme of a memory device for computing-in-memory applications according to an embodiment of the invention. Figure 2B shows a schematic view of one of the memory cells bijof the memory device 200 shown in figure 2A. The same refence number is used through the figures to refer to the same component. The memory device 200 of figure 2A comprises an array of M*N memory cells bijwith i=1,…,M and j=1,…,N. The memory cells bijof the array of figure 2A are organized in a number N of columns cj and a number M of rows ri such that a memory cell bij is located in column cj and row ri. Each column cj of the array of memory cells comprises a current source Ijthat generates a current I to drive the corresponding column cj. Fig.2B shows an example of the memory cells bij of figure 2A. As shown in figure 2B, the memory cell bij comprises an upper end uij and a lower end lij such that a first path p1ijand a second path p1ijrun in parallel to each other from the upper end uijto the 7 lower end lij. The first path p1ijof the memory cell bijin figure 2B comprises a first ohmic resistance R1ij and a first transistor T1ij. The second path p2ij of the memory cell bij in figure 2B comprises a second transistor T2ij. The first and second transistors T1ijand T2ijshown through the figures are N-channel metal-oxide semiconductor (NMOS). However any other kind of suitable transistor or switching device may be used such as, for instance, P-channel metal-oxide semiconductor (PMOS) or Transmission Gates, which are a combination of NMOS and PMOS connected in parallel. These gates are most suitable for switching, since they support the entire voltage range from VDD to GND, but also costs a lot more area. Thus, an appropriate analysis is required before the selection of these switches are made for the memory cell. The first ohmic resistance R1ij of the memory cell bij of figure 2B comprises a first end e1ij and a second end e2ij, the first transistor T1ij comprises a first gate G1ij, a first source S1ij and a first drain D1ij, and the second transistor T2ij comprises a second gate G2ij, a second source S2ijand a second drain D2ij. The first ohmic resistance R1ijand the first transistor T1ij are connected in series in the first path p1ij such that the second end e2ijof the first ohmic resistance e1ijis electrically connected to the first source S1ijof the first transistor T1ij. The first path p1ijis arranged in parallel with the second path p2ij such that the first end e1ij of the first ohmic resistance R1ij is electrically connected to the second source S2ij of the second transistor T2ij at the upper end uij and the second drain D2ijof the second transistor T2ijis electrically connected to the first drain D1ijof the first transistor T1ijat the lower end lij. The memory cells bij of the memory device 200 of figure 2A located in the same in column are connected in series configuration (rather than in parallel configuration as in prior art crossbars) such that, for each column cjwith j = 1, …, N, a memory cell bijin row ri with i =1, …, (M-1) has the lower end lij electrically connected to the upper end u(i+1)j of a memory cell b(i+1)j in the same column cj, and has the upper end uij electrically connected to the lower end l(i-1)jof memory cell b(i-1)jin the same column cj. The lower end e2Mj of the memory cells bMj located in the last rowM of the memory device 200 of figure 2A are electrically connected to the ground GND. As said, the memory device 200 of figure 2A comprises a number N of current sources Ij. such that each column cj is driven by the corresponding current source Ij that generates a current I and said current I flows across the entire corresponding column cj. 8

[0006] In this way, the current source Ijin said column cjid connected between a voltage source VDD and the upper end u1j of the memory cell b1j in said column cj. The first transistor T1ijof a memory cell bijis configured to switch between an active and an inactive state based on an input voltage Viniapplied at the first gate G1ijand which controls the row ri to which the memory cell bij belongs. When the first transistor T1ij is in the active state, a cell output voltage Vij of the memory cell bij is proportional to the current I generated by the current source Ijdriving the column cjto which said memory cell bij belongs and to the first ohmic resistance R1ij, and when the first transistor T1ij is in the inactive state, the cell output voltage Vij of the memory cell bijis proportional to the current I generated by the current source Ijdriving the column cjto which said memory cell bij belongs. The second transistor T2ij of a memory cell bij is configured to also switch between the active and the inactive state based on the inverse of the input voltage Vini which is applied at the second gate G2ij such that, when the first transistor first transistor T1ijof the memory cell bijis in the active state, the second transistor second transistor T2ij of said memory cell bij is in the inactive state, and when the first transistor T1ijof the memory cell bijis in the inactive state, the second transistor T2ijof the memory cell bijis in the active state. As shown in figure 2A, the memory device 200 also comprises M*N inverter elements invi,j with i=1,…,M and j=1,…,M wherein the input of the inverter element invi,jis configured to receive the input voltage Viniand the output of the inverter element invi,jis electrically connected to the second gate G2ijof the second transistor T2ijsuch that the inverter element invi,j inverts the input voltage Vini and controls the second transistor T2i,jto switch between the active state and the inactive state based on the inverted version of the input voltage Vini. As said, the first transistor T1i, j and second transistor T2ij, may be an NMOS transistor or any other kind of suitable transistor or switching device. Furthermore, it is assumed the first transistor T1i, jand the second transistor T2i, jare operating in the triode region and has an "on" resistance negligible in comparison to the resistance of the first ohmic resistance R1ij. In this way, the current through a memory cell bij either flows via the first ohmic resistance R1ijor via the second transistor T2i j, depending on the state of the first transistor T1ij and the second transistor T2ij. Considering a binary input, if the input voltage Vini in row i is high such that Vini equals a voltage VDDequivalent to a binary one, then the first transistor T1i, jin the 9 memory cell bi,jreceives VDDvolts at the first gate G1i,jsuch that a voltage between the first gate G1i,j and the first source S1i,j is above a threshold voltage thereby switching the first transistor T1i,jto an "on" or active status. Accordingly, the inverter element invi,jwill receive the input voltage Viniequal to VDDvolts equivalent to a binary one and output the invert of said binary one, which would be a binary zero, to the second gate G2ij such that a voltage between the second gate G2ij and the second source S2ij is below the threshold voltage thereby switching the second transistor T2ijto an "off" or inactive status. In this situation, the current I generated by the current source Ij will flow through the first ohmic resistance R1ij (through the first path p1ij) causing that the cell voltage Vi,j depends on the first ohmic resistance R1ijas follows: Vij = I . R1ij (equation 6) In contrast, if the input voltage Viniis low such that Viniequals a voltage zero equivalent to a binary zero, then the first transistor T1i, j is in an “off” or inactive status and the second transistor T2i, jis in an “on” or active status, such that the current I generated by the first current source Ijwill follow through the second path p2ijwith least resistance and flow via the transistor T2i, j, resulting in a negligible cell voltage drop Vij. This constitutes one multiply operation in which, depending on the state of the input voltage Vij, the column current I serves as the first operand, and the first ohmic resistance R1ijserves as the second operand. Since all of these memory cells bijare connected in series, the cell voltage drop Vij across each memory cell bij accumulates as a result, constituting an addition operation of M operands. As shown below in equation 7, the final output voltage Voutjof each j-th column cjis the result equivalent to one MAC operation between the input voltages Vini and the first ohmic resistances R1ij in the jth column cj. Consequently, the memory array shown in figure 2A can perform a single VMM operation in the same manner as the standard CIM crossbar, obtaining the following result: (equation 7) 10 If the column currents I are maintained within the order of nanoamperes (nA), the overall current in the memory device 200 may be confined within the range of microamperes (µA), resulting in a power reduction by one-to-two orders compared to prior art memory arrays. Furthermore, if the resistances of the first ohmic resistances R1ijare maintained on the order of kilo ohm, the read voltages Vij across the first ohmic resistances R1ij may be decreased to the microvolt (µV) range, considerably reducing the phenomenon of read disturb and boosting the overall reliability of the memory device. In addition, since the inputs are applied at the first and second gates G1ij and G2ij of the first and second transistors T1ij and T2ij and each columnj is driven by its own current source Ij, there is no coupling between any two different columns and the problem of parasitic currents is eliminated. There are drawbacks associated with this method of implementation, which must be trade-off against the benefits received in power and reliability. Firstly, the massive chain of networks formed by several memory cells arranged in series within a columnjincreases the operation’s latency and is also affected by the magnitude of the column current I. Secondly, this kind of memory array requires an extra transistor in addition to the first ohmic resistance to perform the required computation, hence increasing the overall area of the circuit. Thirdly, it can only accept binary inputs since the signals are applied at the gate of an NMOS operating in the triode / linear region as a switch. Finally, additional circuits may be required to convert the output voltage into suitable currents for driving subsequent stages, such as in the case of Spiking Neural Networks. A MAC unit implemented with the memory device 200 shown in figure 2A is composed of N*M memory cells stacked in series to represent N*M synaptic weights. The memory cells bijcomprise a 2T1R (a first and second transistor T1ijand T2ijand a first ohmic resistance R1ij) configuration in which a non-volatile device, such as for instance but not limited to RRAM and represented as the first ohmic resistance R1ij in figure 2B is in series with an access transistor represented as the first transistor T1ijin figure 2B, and their combination is in parallel configuration with another identical access NMOS transistor represented as the second transistor T2ij in figure 2B. Since memory cells bijreceive complementary input signals applied at the first and second gates G1ijand G2ij, only one path among the first and second paths p1ij and p2ij in a memory cell bij is active at a given time. When the memory cells bij receive a "high" signal Vini , the the first path p1ijor weighted (RRAM) path is active. The primary objective of employing 11 the 2T1R configuration in a memory cell is to counteract the non-negligible "on" resistances of the first and second transistors T1ij and T2ij. The presence of identical in first and second transistors T1ijand T2ijboth first and second paths p1ijand p2ijfixes the number of active access transistors in a column at any given time, since one of the paths is always active in a memory cell. Subsequently, M transistors are always active in a given column, regardless of the input states Vini. Consequently, the combined resistance posed by the active transistors in the column remains nearly constant across the entire operating range and can be treated as a constant offset at the output. This helps maintain the linear output response of the memory device with respect to the number of memory cells with the first transistor T1ij"on" at the expense of some area overhead. To further maintain the minimal "on" resistance of the access transistors, low Vt (high-speed) first and second transistors may be utilised. As an alternative, the current sources Ij of the memory device 200 of figure 2A may be connected at the low part of the corresponding columnjas shown in figure 2C. Also alternatively, the current source Ij may be a reversible current source configured to invert a direction of the constant current I. This way, by periodically reversing the current, this provides the advantage of compensating for the deviated resistance states, which might happen over multiple read cycles, while still supporting the MAC operation. Furthermore, the first ohmic resistance R1ij of the memory cells bij may comprise a memristor configured to switch among a plurality of resistance values. For instance, the memristor may be configured to switch among a plurality of resistance values comprised between a low resistance value and a high resistance value. Furthermore, the memory cells bijmay further comprise at least a third and a fourth paths with respectively ohmic resistances, each of the at least third and fourth paths electrically connected in parallel with the first and second paths and comprising respectively a transistor for each path respectively connected in series with memristor their respective ohmic resistance. In alternative configurations for memory cells bij,the first path P1ij may comprises a first non-volatile memory device and the second path P2ij may comprise a second non-volatile memory device such that the first ohmic resistance R1ijcorresponds to a resistance of the first non-volatile device and a second ohmic resistance corresponds to a resistance of the second non-volatile device and wherein the resistance of the first non-volatile device is configured to switch among a plurality of resistance values. 12 Figures 3A-3B, 4A-4B, 5 and 6A-C show schemes of the memory cells bijof the memory device 200 of figure 2A according to embodiments of the invention. The difference between the memory cell bijshown in figure 3A and the one shown in figure 2B is that the first ohmic resistance R1ijof the memory cell bijof figure 3A is a memristor that can switch between 4 different resistance values, namely RH, 2RH / 3, RH / 3 and RL. In this way, the second operand of the operation can take 4 different values. Figure 3C shows an alternative way of implementing a memory cell bijcapable of performing the same operation as the memory cell bij shown in figure 3A but using two configurations of the memory cell of figure 3A in series and comprising each one a memristors able to switch between two different resistance values RHand RLwherein a further current source generating a current equal to half of the current I generated by the current source Ij is connected between the middle section of said memory cell and ground GND. The difference between the memory cell bijshown in figure 4A and the one shown in figure 2B is that the memory cell bij of figure 4A, comprises a third and a fourth paths p3ijand p4ijparallel to the first and second paths p1ijand p2ijwherein the first ohmic resistance R1ijof the first path p1ijcomprises a first memristor that can switch between 2 different resistance values, namely RH and RL, the second path comprises a second memristor R2ij that can switch between other two different resistance values, namely 2RH / 3 and RL,the third path p3ijcomprises a third transistor T3ijand a third memristor that can switch between resistance values RH / 3 and RLand the fourth path p4ijcomprises a fourth transistor T4ij. In this way, by using multiplexer 402 with inputs the input voltage Viniand a further input voltage V’ini, and outputs X0, X1, X2and X3, which are respectively connected to the gates of the first second, third and fourth transistor, the different paths of the memory cell may be selected by changing the two input voltages Vini and V’ini between zero and one as explained above. This again expands the number of first operands available for performing operations. Figure 4B^shows an alternative way of implementing a memory cell bijcapable of performing the same operation as the memory cell bij shown in figure 4A but using two configurations 406 and 408 of the memory cell of figure 3A in series and comprising each one a memristors able to switch between two different resistance values RH and RL wherein a second current source 410 generating a current equal to half of the current I generated by the current source Ij is connected between ground GND and the middle 13 section of the two configurations 406 and 408. The first and second transistors of the upper configuration 406 are controlled by the input voltage Vini and the invert of said input voltage Vinirespectively, and the transistors of the lower configuration 408 are also controlled in a similar manner by the same input voltage V’iniand its inverted counterpart V’ini.. Figure 5 shows a further alternative for implementing a memory cell bij according to the invention using two configurations 506 and 508 of the memory cell of figure 4A in series in a similar way as shown in figure 4B and also with a second current source 510 generating a current equal to half of the current I generated by the current source Ij is connected between ground GND and the middle section two configurations 506 and 508. The multiplexer 402 is identical to multiplexer 502 shown in figure 4A. This configuration allows to provide several input voltages to a memory cell as the first operand and several ohmic resistance values as the second operand thereby expanding the memory in computing capabilities of the memory cell. Figure 6A shows an implementation of the memory cell bij of figure 2B wherein the first ohmic resistance R1ijis a memristor that can switch between resistance values RLand RHand the second path p2ijcomprises a second ohmic resistance R2ijconnected in series between the current source Ij and the second drain D2ij of the second transistor T2ij. The second ohmic resistance R2ij may be also a memristor configured to a fixed resistance value. This configuration also helps in compensating for the non-zero resistance of the non-volatile memory device when it ideally must exhibit zero resistance in case, the second operand is zero. Figures 6B-C show different implementations of the memory cell bijusing respectively flash and Ferroelectric field-effect transistor (FeFET) non-volatile memory technologies according to the invention. However, any kind of suitable non-volatile memory technology may be used to implement the memory cell bij. The first path may comprise a first non-volatile memory device and the second path may comprise a second non-volatile memory device, wherein the first ohmic resistance corresponds to a resistance of the first non-volatile device and the second ohmic resistance corresponds to a resistance of the second non-volatile device and wherein the resistance of the first non- volatile device is configured to switch among a plurality of resistance values. Figure 7 shows a flow chart of a method of performing a computing-in-memory operation using the memory device 200 shown in figure 2A. In step 802, the input 14 voltages Viniare set up and applied at the corresponding first gates G1ijas the first operand such that either the first transistor T1ij or the second transistor T2ij of the corresponding memory cell bijis active. In step 804, the output voltage Voutjof each j- th column cjis provided as the result equivalent to one MAC operation between the input voltages Vini and the first ohmic resistances R1ij in the jth column cj in the memory cells wherein the first transistor TR1ij is active such that a single computing-in-memory operation is performed obtaining the following result for each column j: Voutj=(I. Vin1). R11j+(I. Vin2). R12j+ ⋯ + (I. VinM). R1MjThe memory device 200 may be used to implement a neural network. The examples and embodiments described herein serve to illustrate rather than limit the invention. The person skilled in the art will be able to design alternative embodiments without departing from the scope of the claims. Reference signs placed in parentheses in the claims shall not be interpreted to limit the scope of the claims. Items described as separate entities in the claims or the description may be implemented as a single hardware or software item combining the features of the items described.

Claims

15 CLAIMS:

1. A memory device (200) for computing-in-memory applications, the memory device comprising an array of memory cells, wherein each column (columnj) of the array of memory cells is respectively driven by a current (I) and configured to respectively generate a column output voltage (Voutj) and each row (rowi) of the array of memory cells is respectively controlled by an input voltage (Vini), wherein a memory cell (bij) comprises: a first path (p1ij) with a first ohmic resistance (R1ij) and comprising a first transistor (T1ij); and a second path (p2ij) comprising a second transistor (T2ij) ; wherein the first path (p1ij) is arranged in parallel with the second path (p2ij) and the first transistor (T1ij) is configured to switch between an active and an inactive state based on the input voltage (Vini) controlling the row (ri) of the memory cell such that, when the first transistor (T1ij) is in the active state, an output voltage (Vij) of the memory cell is proportional to the current (I) driving the column (columnj) of that memory cell (bij) and to the first ohmic resistance (R1ij), and when the first transistor (T1ij) is in the inactive state, the output voltage (Vij) of the memory cell (bij) is proportional to the current (I) driving the column (columnj) of that memory cell (bij).

2. The memory device according to claim 1 wherein a gate (G1ij) of the first transistor (T1ij) is configured to receive the input voltage and to control the first transistor to switch between an active and an inactive state.

3. The memory device according to any of the previous claims, wherein the first ohmic resistance (R1ij) comprises a memristor electrically connected in series with the first transistor (T1ij) and configured to switch among a plurality of resistance values, and wherein the first ohmic resistance (R1ij) corresponds to a resistance of the memristor when the first transistor (T1ij) is in the active state.16 4. The memory device according to claim 3, wherein each of the memory cells (bij) further comprises at least a third and a fourth paths with respectively ohmic resistances, each of the at least third and fourth paths electrically connected in parallel with the first and second paths and comprising respectively a transistor for each path respectively connected in series with memristor their respective ohmic resistance.

5. The memory device according to claim 3 wherein the memristor is configured to switch among a plurality of resistance values comprised between a low resistance value and a high resistance value.

6. The memory device according to any of the previous claims, wherein the second transistor (T2ij ) is configured to switch between the active and the inactive state based on the input voltage controlling the corresponding row (rowi) of the memory cell (bij) such that, when the first transistor (T1ij) is in the active state, the second transistor (T2ij) is in the inactive state, and when the first transistor (T1ij) is in the inactive state, the second transistor (T2ij) is in the active state.

7. The memory device according to claim 6, wherein the memory cell (bij) further comprises an inverter element (invij) electrically connected to a gate (G2ij) of the second transistor (T2ij) and configured to receive the input voltage (Vini) of the corresponding column (columnj), to invert the input voltage, and to control the second transistor (T2ij) to switch between the active state and the inactive state based on the inverted input voltage.

8. The memory device according to claim 1 wherein the first path (p1ij) comprises a first non-volatile memory device and wherein the second (p2ij) path comprises a second non-volatile memory device, wherein the first ohmic resistance corresponds to a resistance of the first non-volatile device and the second ohmic resistance corresponds to a resistance of the second non-volatile device and wherein the resistance of the first17 non-volatile device is configured to switch among a plurality of resistance values.

9. The memory device according to any of the previous claims wherein each column (columnj) further comprises a current source (Ij) arranged to generate a constant current (I) and electrically connected in series with the memory cells (bij) of the corresponding column (columnj).

10. The memory device according to claim 9, wherein the current source (Ij) is reversible current source configured to invert a direction of the constant current (I).

11. The memory device according to any of the previous claims wherein the second path further comprises a second ohmic resistance.

12. The memory device of claim 11, wherein the second ohmic resistance is a memristor.

13. The memory device according to claim 4 further comprising a multiplexor arranged to receive multiple input voltages and to generate multiple control signals to control transistors in the first, second, and at least third and fourth paths.

14. A method of performing a computing-in-memory operation using the memory device according to any of the previous claims.

15. A neural network comprising the memory device according to any of the previous claims.

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