Light-emitting driving circuit and display panel

Abstract

The present invention relates to the field of display panels, and provides a light-emitting driving circuit and a display panel. The light-emitting driving circuit comprises multiple stages of light-emitting driving units and a timing controller. Each stage of light-emitting driving unit comprises ten transistors, three capacitors, a signal input end, a signal output end, and two timing control ends. The timing controller comprises a first timing control signal line and a second timing control signal line. According to the light-emitting driving circuit and the display panel of the present invention, by providing a new 10T3C light-emitting driving unit circuit, the switching between high and low levels of an output signal is achieved without step-type stepped pull-down, so that an intermediate voltage is prevented from being affected by the threshold voltage or process fluctuation of transistors, thereby reducing the falling edge time, increasing the turn-on speed of the transistors, and shortening the response time of the circuit; in addition, by reducing the use of timing control signal lines and transistors, the number of components in the circuit is reduced, so that the bezel width of a display panel is reduced, thereby adapting to the narrow-bezel trend of display panels.

Description

Light-emitting driving circuit and display panel Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a light-emitting drive circuit and a display panel. Background Art

[0002] A display panel includes a pixel array, a scanning driver circuit, and a light-emitting driver circuit that control the pixel array. The display panel uses a row-by-row scanning display method. The scanning driver circuit generates scanning signals to sequentially turn on each row of pixels, while the light-emitting driver circuit provides data signals to each row of pixels when they turn on, enabling pixel display. The light-emitting driver circuit includes multiple cascaded light-emitting driver units. Each stage of the light-emitting driver unit typically consists of several transistors and capacitors. Clock signals and start pulse signals are input to the light-emitting driver units, resulting in output signals at their output terminals.

[0003] In current light-emitting driver circuits, the output of the circuit must be pulled down from a high level to a low level in a "step-like" manner, i.e., it needs to completely step down from a high level to a low level in two steps. This "step-like" step results in a long fall time, also known as the "falling time" (Tf), which slows down the turn-on speed of the transistor (TFT) and increases the circuit's response time.

[0004] Figure 1 shows a circuit diagram of a prior art light-emitting driver unit. As shown in Figure 1, Chinese patent CN105741749A discloses a light-emitting driver circuit. The reason for the "step" in this circuit is that when the potential of the clock signal c1 changes from high to low, the potential of the gate node N4 of the M2 transistor is pulled down to the same potential as the power supply VEE by the low-level input signal. The M2 transistor is turned on, but limited by the threshold voltage Vth, the output voltage Vout-V(N4) = Vth < 0. When the potential of c2 changes from high to low, the gate node N4 of the M2 transistor is pulled down to below VEE through capacitive coupling to exceed the Vth value, and Vout can be pulled down to the VEE voltage.

[0005] Figure 2 shows a circuit diagram of another prior art light-emitting driver unit. As shown in Figure 2, U.S. Patent No. 9,548,026 B2 discloses a light-emitting driver circuit. The reason for the "step" in this circuit is that when the potential of the clock signal CLK1 changes from high to low, the potential of the gate node N1 of the M10 transistor is pulled down to the same potential as the power supply VGL by the low-level input signal, turning on the M10 transistor. However, due to the threshold voltage Vth, the output voltage Vout - V(N1) = Vth < 0. When the potential of CLK2 changes from high to low, the gate node N1 of the M10 transistor is pulled down to below VGL through capacitive coupling, and when the voltage exceeds the Vth value, Vout can be pulled down to the VGL voltage.

[0006] This "step" transition requires two sets of clock signals to pull down the output signal potential. When one clock signal's potential changes from high to low, the output signal En steps from a high level to an intermediate level. When the other clock signal's potential changes from high to low, the output signal En steps from an intermediate level to a low level. The intermediate level is affected by the TFT's threshold voltage and is significantly affected by process fluctuations.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field.

[0008] Summary of the Invention

[0009] In view of this, the present invention provides a light-emitting drive circuit and a display panel. By providing a novel 10T3C light-emitting drive unit circuit, the light-emitting drive circuit and display panel of the present invention enable switching between high and low levels of the output signal without a step-down pull-down, thus preventing the intermediate voltage from being affected by transistor threshold voltage or process fluctuations. This reduces the falling edge time, accelerates the transistor turn-on speed, and shortens the circuit's response time. Furthermore, by reducing the number of timing control signal lines and transistors used, the present invention reduces the number of components in the light-emitting drive circuit, thereby reducing the bezel width of the display panel and adapting to the trend of narrow bezels for display panels.

[0010] One aspect of the present invention provides a light-emitting driving circuit, including a multi-stage light-emitting driving unit, wherein the light-emitting driving unit includes:

[0011] a first transistor, wherein a first electrode of the first transistor is connected to the first power supply, a second electrode is connected to the third node, and a gate is connected to the signal input terminal;

[0012] a second transistor, wherein a first electrode of the second transistor is connected to the first node, a second electrode of the second transistor is connected to the fourth node, and a gate of the second transistor is connected to the third node;

[0013] a third transistor, wherein a first electrode of the third transistor is connected to the third node, a second electrode of the third transistor is connected to the second power supply, and a gate of the third transistor is connected to the first timing control terminal;

[0014] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the fourth node, a second electrode of the fourth transistor is connected to the second timing control terminal, and a gate of the fourth transistor is connected to the second timing control terminal;

[0015] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to the first node;

[0016] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first power supply, a second electrode of the sixth transistor is connected to the first node, and a gate of the sixth transistor is connected to the second node;

[0017] a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first power supply, a second electrode of the seventh transistor is connected to the signal output terminal, and a gate of the seventh transistor is connected to the first node;

[0018] an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal output terminal, a second electrode of the eighth transistor is connected to the second power supply, and a gate of the eighth transistor is connected to the fifth node;

[0019] a ninth transistor, wherein a first electrode of the ninth transistor is connected to the second node, a second electrode of the ninth transistor is connected to the fifth node, and a gate of the ninth transistor is connected to the second power supply;

[0020] a tenth transistor, wherein a first electrode of the tenth transistor is connected to the second node, a second electrode is connected to the signal input terminal, and a gate is connected to the second timing control terminal;

[0021] a first capacitor, wherein a first electrode of the first capacitor is connected to the fifth node, and a second electrode of the first capacitor is connected to the signal output end;

[0022] a second capacitor, wherein a first electrode of the second capacitor is connected to the first power supply, and a second electrode of the second capacitor is connected to the first node;

[0023] A third capacitor has a first electrode connected to the fourth node and a second electrode connected to the third node.

[0024] In some embodiments, a timing controller is further included, and the timing controller includes a first timing control signal line and a second timing control signal line.

[0025] In some embodiments, the first timing control signal line is used to output a first timing control signal; and the second timing control signal line is used to output a second timing control signal.

[0026] In some embodiments, the first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0027] In some embodiments, the light driving unit is configured to perform delay processing on the signal received from the signal input end under the control of the first timing control signal and the second timing control signal, and the processed signal is output from the signal output end.

[0028] In some embodiments, the light-emitting driving unit at the previous stage outputs a light-emitting driving signal to the light-emitting driving unit at the next stage, and the light-emitting driving unit at the last stage outputs a light-emitting driving signal.

[0029] In some embodiments, in the odd-numbered light-emitting driving units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

[0030] In some embodiments, in the even-numbered light-emitting driving units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

[0031] In some embodiments, the first to tenth transistors are all P-type MOS transistors.

[0032] Another aspect of the present invention further provides a display panel, characterized by comprising any one of the above-mentioned light-emitting driving circuits.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present invention, and together with the description, serve to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0035] FIG1 shows a circuit diagram of a light-emitting driving unit in the prior art;

[0036] FIG2 shows a circuit diagram of another light-emitting driving unit in the prior art;

[0037] FIG3 is a schematic diagram showing a display panel according to an embodiment of the present invention;

[0038] FIG4 shows a schematic diagram of a cascade connection of a light-emitting driving circuit according to an embodiment of the present invention;

[0039] FIG5 shows a circuit diagram of a light-emitting driving unit according to an embodiment of the present invention;

[0040] FIG. 6 shows a waveform diagram of the light-emitting driving unit shown in FIG. 5 when it is in operation.

[0041] Reference Signs: 10 display panel 11 display area 20 timing controller 30 light emitting driving circuit CKE1 first timing control signal line CKE2 second timing control signal line c1 first timing control terminal c2 second timing control terminal IN signal input terminal Eout signal output terminal T1 first transistor T2 second transistor T3 third transistor T4 fourth transistor T5 fifth transistor T6 sixth transistor T7 seventh transistor T8 eighth transistor T9 ninth transistor T10 tenth transistor C1 first capacitor C2 second capacitor C3 third capacitor VDD first power supply VEE second power supply n1 first node n2 second node n3 third node n4 fourth node n5 fifth node DETAILED DESCRIPTION

[0042] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the figures represent identical or similar structures, and thus a repeated description thereof will be omitted.

[0043] The terms "first," "second," and similar terms used in the specific description do not denote any order, quantity, or importance, but are simply used to distinguish different components. Furthermore, in the description of the present invention, the terms "upper," "lower," and similar terms indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely for ease of description and do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0044] It should be noted that, in the absence of conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

[0045] Through careful and in-depth research, the inventors of this case have provided a solution to the problems existing in the prior art. Figure 3 shows a schematic diagram of a display panel according to an embodiment of the present invention; Figure 4 shows a cascade schematic diagram of a light-emitting driving circuit according to an embodiment of the present invention; and Figure 5 shows a circuit diagram of a light-emitting driving unit according to an embodiment of the present invention. As shown in Figures 3 to 5, the present invention discloses a light-emitting driving circuit 30 and a display panel 10, wherein the light-emitting driving circuit 30 includes a multi-stage light-emitting driving unit and a timing controller 20. Each stage of the light-emitting driving unit specifically includes 10 transistors, 3 capacitors, a signal input terminal, a signal output terminal, and two timing control terminals. The timing controller 20 includes two timing control signal lines. The light-emitting drive circuit and display panel of the present invention, by providing a new 10T3C light-emitting drive unit circuit, enable switching between high and low levels of the output signal without step-wise pull-down, thereby preventing the intermediate voltage from being affected by transistor threshold voltage or process fluctuations, reducing the falling edge time, accelerating the turn-on speed of the transistor, and shortening the response time of the circuit. In addition, the present invention reduces the number of components in the light-emitting drive circuit by reducing the use of timing control signal lines and transistors, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of display panels.

[0046] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0047] As shown in FIG3 , an embodiment of the present invention provides a display panel 10 comprising a display area 11 and a non-display area. A light-emitting driver circuit 30, a data driver, and a scan driver circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes an array of light-emitting pixels and pixel circuits. The light-emitting pixels emit light under the combined action of the light-emitting driver circuit 30, the data driver, the scan driver circuit, and the pixel circuit.

[0048] As shown in FIG. 3 and FIG. 4 , an embodiment of the present invention further provides a light-emitting driving circuit 30 , which includes a multi-stage light-emitting driving unit and a timing controller 20 .

[0049] In some embodiments, as shown in FIG5 , a light-emitting driver unit includes 10 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Eout, a first timing control terminal c1, and a second timing control terminal c2. Each level of light-emitting driver unit outputs a light-emitting drive signal, which is input to a row of pixel circuits in the display area 11 of the display panel 10 to drive the pixels in that row to emit light. The previous level of light-emitting driver unit simultaneously outputs the light-emitting drive signal to the signal input terminal IN of the next level of light-emitting driver unit as a start signal. Since the last level of light-emitting driver unit does not exist in the next level, the light-emitting drive signal it outputs is only input to the pixel circuits in that row.

[0050] Specifically, FIG4 shows five cascaded light-emitting driver units as an example. A start pulse signal STE is input to a signal input terminal IN1 of a first-stage light-emitting driver unit E1. A signal output terminal Eout1 of the first-stage light-emitting driver unit E1 outputs a light-emitting driver signal as an input signal for a second-stage light-emitting driver unit E2. The signal output terminal Eout1 of the first-stage light-emitting driver unit E1 is connected to a signal input terminal IN2 of the second-stage light-emitting driver unit E2. The signal output terminal Eout2 of the second-stage light-emitting driver unit E2 outputs a light-emitting driver signal as an input signal for a third-stage light-emitting driver unit E3. The signal output terminal Eout2 of the second-stage light-emitting driver unit E2 is connected to a signal input terminal IN3 of the third-stage light-emitting driver unit E3. The signal output terminal Eout3 of the third-stage light-emitting driver unit E3 outputs a light-emitting driver signal as an input signal for a fourth-stage light-emitting driver unit E4. The signal output terminal Eout3 of the third-stage light-emitting driver unit E3 is connected to a signal input terminal IN4 of the fourth-stage light-emitting driver unit E4. The signal output terminal Eout4 of the fourth-stage light-emitting driving unit E4 outputs a light-emitting driving signal as an input signal of the fifth-stage light-emitting driving unit E5. The signal output terminal Eout4 of the fourth-stage light-emitting driving unit E4 is connected to the signal input terminal IN5 of the fifth-stage light-emitting driving unit E5. The subsequent-stage light-emitting driving units are repeated in this manner to form a light-emitting driving circuit 30.

[0051] Figure 6 shows a waveform diagram of the light-emitting drive unit shown in Figure 5 during operation. In some embodiments, as shown in Figures 3 to 6, the timing controller 20 includes a first timing control signal line CKE1 and a second timing control signal line CKE2. The first timing control signal line CKE1 is used to output a first timing control signal. The second timing control signal line CKE2 is used to output a second timing control signal. The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0052] In some embodiments, as shown in Figure 4, in the first-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. In the second-level light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. In the third-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. In the fourth-level light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. In the fifth-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal... and so on, it is obtained that: in the odd-numbered light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 for receiving the first timing control signal, and the second timing control terminal c2 is connected to the second timing control signal line CKE2 for receiving the second timing control signal. In the even-numbered light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 for receiving the second timing control signal, and the second timing control terminal c2 is connected to the first timing control signal line CKE1 for receiving the first timing control signal.

[0053] In some embodiments of the present invention, as shown in FIG5 , each light-emitting driving unit specifically includes 10 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Eout, a first timing control terminal c1 and a second timing control terminal c2.

[0054] In this embodiment, the light-emitting drive unit specifically includes: first to tenth transistors T1 to T10. The first transistor T1 has a first electrode connected to the first power supply VDD, a second electrode connected to the third node n3, and a gate connected to the signal input terminal IN. The second transistor T2 has a first electrode connected to the first node n1, a second electrode connected to the fourth node n4, and a gate connected to the third node n3. The third transistor T3 has a first electrode connected to the third node n3, a second electrode connected to the second power supply VEE, and a gate connected to the first timing control terminal c1. The fourth transistor T4 has a first electrode connected to the fourth node n4, a second electrode connected to the second timing control terminal c2, and a gate connected to the second timing control terminal c2. The fifth transistor T5 has a first electrode connected to the first power supply VDD, a second electrode connected to the second node n2, and a gate connected to the first node n1. The sixth transistor T6 has a first electrode connected to the first power supply VDD, a second electrode connected to the first node n1, and a gate connected to the second node n2. The seventh transistor T7 has a first electrode connected to the first power supply VDD, a second electrode connected to the signal output terminal Eout, and a gate connected to the first node n1. The eighth transistor T8 has a first electrode connected to the signal output terminal Eout, a second electrode connected to the second power supply VEE, and a gate connected to the fifth node n5. The ninth transistor T9 has a first electrode connected to the second node n2, a second electrode connected to the fifth node n5, and a gate connected to the second power supply VEE. The tenth transistor T10 has a first electrode connected to the second node n2, a second electrode connected to the signal input terminal IN, and a gate connected to the second timing control terminal c2.

[0055] In this embodiment, the light-emitting drive unit further includes: a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first electrode of the first capacitor C1 is connected to the fifth node n5, and the second electrode is connected to the signal output terminal Eout. The first electrode of the second capacitor C2 is connected to the first power supply VDD, and the second electrode is connected to the first node n1. The first electrode of the third capacitor C3 is connected to the fourth node n4, and the second electrode is connected to the third node n3.

[0056] In this embodiment, the first transistor T1 to the tenth transistor T10 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, the first terminal is the source, and the second terminal is the drain, or the first terminal is the drain and the second terminal is the source. The on-level of the PMOS transistor is a low level, and the off-level is a high level. In other embodiments, those skilled in the art will readily appreciate that the light-emitting drive unit provided by the present invention can be easily modified to include all N-type MOS transistors. Furthermore, the light-emitting drive unit provided by the present invention can also be easily modified to include CMOS transistors, etc.

[0057] In some embodiments of the present invention, referring to Figures 3 to 6, Figure 6 specifically illustrates waveform diagrams of each stage of two cycles of operation of the light-emitting drive unit of the present invention, and also indicates the process from t1 to t6 within one cycle. During these stages, the output signal of the signal output terminal Eout of the light-emitting drive unit completes a process from set to reset. The relationship between the input and output of the light-emitting drive unit during the above six processes is analyzed below in conjunction with the waveform diagram of Figure 6 and the circuit diagram of Figure 5:

[0058] In this embodiment, referring to Figures 5 and 6 , during process t1, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. Consequently, a high level is written to the fourth node n4, and an intermediate level is written to the third node n3. Furthermore, a high level is written to the first node n1, and a low level is written to the fifth node n5. Only the third node n3 and the fifth node n5 can exist in the three states of high, intermediate, and low. The same applies to the following stages and will not be further described. Ultimately, the signal output terminal Eout outputs a low level.

[0059] In this embodiment, referring to Figures 5 and 6 , during process t2, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKE1, and a low level is input to the second timing control signal line CKE2. Consequently, a low level is written to the fourth node n4, and a low level is written to the third node n3. Furthermore, a low level is written to the first node n1, and a high level is written to the fifth node n5. Ultimately, the signal output terminal Eout outputs a high level.

[0060] In this embodiment, referring to Figures 5 and 6 , during process t3, a high level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. Consequently, a low level is written to the fourth node n4, and a low level is written to the third node n3. Furthermore, a low level is written to the first node n1, and a high level is written to the fifth node n5. Ultimately, the signal output terminal Eout outputs a high level.

[0061] In this embodiment, referring to Figures 5 and 6 , during process t4, a high level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKE1, and a low level is input to the second timing control signal line CKE2. Consequently, a low level is written to the fourth node n4, and a low level is written to the third node n3. Furthermore, a low level is written to the first node n1, and a high level is written to the fifth node n5. Ultimately, the signal output terminal Eout outputs a high level.

[0062] In this embodiment, referring to Figures 5 and 6 , during process t5, a low level is input to the signal input terminal IN, a low level is input to the first timing control signal line CKE1, and a high level is input to the second timing control signal line CKE2. Consequently, a low level is written to the fourth node n4, and an intermediate level is written to the third node n3. Furthermore, a low level is written to the first node n1, and a high level is written to the fifth node n5. Ultimately, the signal output terminal Eout outputs a high level.

[0063] In this embodiment, referring to Figures 5 and 6 , during process t6, a low level is input to the signal input terminal IN, a high level is input to the first timing control signal line CKE1, and a low level is input to the second timing control signal line CKE2. Consequently, a low level is written to the fourth node n4, and a high level is written to the third node n3. Furthermore, a high level is written to the first node n1, and a low level is written to the fifth node n5. Ultimately, the signal output terminal Eout outputs a low level.

[0064] In this embodiment, the light driving unit starts to display the next frame after the process t6, and the start pulse signal STE or the signal input terminal IN inputs a high potential, and re-enters the next round t1 process.

[0065] In this embodiment, the relationship between the input and output of the light-emitting driving unit is as follows: when the start pulse signal STE or the signal input terminal IN inputs a high-level signal at the beginning of a process, the signal output terminal Eout outputs a high-level signal when the next process starts; when the start pulse signal STE or the signal input terminal IN inputs a low-level signal during a process, the signal output terminal Eout outputs a low-level signal when the current process ends and the next process starts. At other times, the signal output by the signal output terminal Eout and the signal input by the start pulse signal STE or the signal input terminal IN are both low-level signals.

[0066] In this embodiment, the light-emitting driver circuit of the present invention provides a novel 10T3C light-emitting driver unit circuit, enabling the third node n3 and the fifth node n5 to exist in three states: a high potential, an intermediate potential, and a low potential. This allows the step-by-step pull-down switching between high and low levels to be completed at the third node n3. Consequently, the output signal at the signal output terminal Eout switches between high and low levels without a step-by-step pull-down. This prevents the intermediate voltage from being affected by transistor threshold voltage or process fluctuations, reduces the falling edge time, accelerates the transistor turn-on speed, and shortens the circuit's response time. Furthermore, by reducing the number of timing control signal lines and transistors used, the present invention reduces the number of components in the light-emitting driver circuit, thereby reducing the bezel width of the display panel and adapting to the trend toward narrower bezels for display panels.

[0067] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel 10 described above. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. For implementation of the display device, reference can be made to the embodiments of the display panel 10 described above, and any overlapping technical solutions and effects will not be further described.

[0068] In summary, the light-emitting drive circuit and display panel of the present invention, by providing a new 10T3C light-emitting drive unit circuit, enable switching between high and low levels of the output signal without step-by-step pull-down, thereby avoiding the intermediate voltage being affected by the transistor threshold voltage or process fluctuations, reducing the falling edge time, accelerating the turn-on speed of the transistor, and reducing the response time of the circuit; in addition, the present invention reduces the number of components of the light-emitting drive circuit by reducing the use of timing control signal lines and transistors, thereby reducing the border width of the display panel and adapting to the trend of narrow borders of display panels.

[0069] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A light-emitting driving circuit, characterized in that: A multi-stage light-emitting driving unit is included, and the light-emitting driving unit includes: A first transistor, wherein a first electrode of the first transistor is connected to a first power supply, a second electrode is connected to a third node, and a gate is connected to a signal input terminal; a second transistor, wherein a first electrode of the second transistor is connected to the first node, a second electrode of the second transistor is connected to the fourth node, and a gate of the second transistor is connected to the third node; a third transistor, wherein a first electrode of the third transistor is connected to the third node, a second electrode of the third transistor is connected to the second power supply, and a gate of the third transistor is connected to the first timing control terminal; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the fourth node, a second electrode of the fourth transistor is connected to the second timing control terminal, and a gate of the fourth transistor is connected to the second timing control terminal; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to the first node; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first power supply, a second electrode of the sixth transistor is connected to the first node, and a gate of the sixth transistor is connected to the second node; a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first power supply, a second electrode of the seventh transistor is connected to the signal output terminal, and a gate of the seventh transistor is connected to the first node; an eighth transistor, wherein a first electrode of the eighth transistor is connected to the signal output terminal, a second electrode of the eighth transistor is connected to the second power supply, and a gate of the eighth transistor is connected to the fifth node; a ninth transistor, wherein a first electrode of the ninth transistor is connected to the second node, a second electrode of the ninth transistor is connected to the fifth node, and a gate of the ninth transistor is connected to the second power supply; a tenth transistor, wherein a first electrode of the tenth transistor is connected to the second node, a second electrode of the tenth transistor is connected to the signal input terminal, and a gate of the tenth transistor is connected to the second timing control terminal; a first capacitor, wherein a first electrode of the first capacitor is connected to the fifth node, and a second electrode of the first capacitor is connected to the signal output end; a second capacitor, wherein a first electrode of the second capacitor is connected to the first power supply, and a second electrode of the second capacitor is connected to the first node; A third capacitor, wherein a first electrode of the third capacitor is connected to the fourth node, and a second electrode of the third capacitor is connected to the third node.

2. The light-emitting driving circuit according to claim 1, characterized in that: The invention also includes a timing controller, wherein the timing controller includes a first timing control signal line and a second timing control signal line.

3. The light-emitting driving circuit according to claim 2, characterized in that: The first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal.

4. The light-emitting driving circuit according to claim 3, characterized in that: The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

5. The light-emitting driving circuit according to claim 3, characterized in that: The light-emitting driving unit is used for delaying the signal received from the signal input end under the control of the first timing control signal and the second timing control signal, and the processed signal is outputted from the signal output end.

6. The light-emitting driving circuit according to claim 2, characterized in that: The light-emitting driving unit of the previous stage outputs a light-emitting driving signal to the light-emitting driving unit of the next stage, and the light-emitting driving unit of the last stage outputs a light-emitting driving signal.

7. The light-emitting driving circuit according to claim 6, characterized in that: In the odd-numbered light-emitting driving units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

8. The light-emitting driving circuit according to claim 7, characterized in that: In the even-numbered light-emitting driving units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

9. The light-emitting driving circuit according to claim 1, characterized in that: The first transistor to the tenth transistor are all P-type MOS transistors.

10. A display panel, characterized in that: The invention comprises a light emitting driving circuit according to any one of claims 1 to 9.

Images