Memory, memory circuit, and working method for memory circuit

Abstract

A memory, a memory circuit, and a working method for a memory circuit. The memory circuit comprises: several memory cells, which are arranged in an array, wherein during a programming operation, control gates (206) are used for applying first programming voltages, such that electrons are pulled from the control gates (206) to floating gates (204), and during an erasing operation, the control gates (206) are used for applying erasing voltages, such that the electrons are pulled from the floating gates (204) to the control gates (206); source-line doped regions (207), each of which is located in a substrate (200) at the bottom of a source-line layer (202); bit-line doped regions (208), each of which are located in the substrate (200) between word-line gates (201) of two adjacent memory cell structures; word lines (WLi), which are electrically connected to the word-line gates (201) of the memory cells in the same row; bit lines (BLj), which are electrically connected to the bit-line doped regions (208) of the memory cells in the same column; source lines (SLj), which are electrically connected to the source-line layers (202) of the memory cells in the same column; and control gate lines (EPHGi), which are electrically connected to the control gates (206) of the memory cells in the same row. The transconductance stability of the memory cell structures is thus improved.

Description

Memory, memory circuit, and memory circuit operating method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 18, 2023, with application number 202311050044.0 and invention name “Memory, memory circuit and working method of memory circuit”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a memory, a memory circuit, and a working method of the memory circuit. Background Art

[0003] The rapid development of artificial neural network algorithms (ANNs) has triggered a new wave of research in artificial intelligence (AI), and has achieved a large number of outstanding results in fields such as image recognition, natural language processing, and autonomous driving.

[0004] The basic principle of a neural network algorithm is to multiply and add an input vector with the weights stored in abstract "neurons," then perform nonlinear activation before outputting the result. This interconnected network of multiple layers of "neurons" allows for the fitting of complex functional relationships. In recent years, integrated computing systems based on memory arrays have garnered widespread attention. Existing neural network algorithm systems based on flash memory arrays program the weights of the "neurons" into the array's memory devices. Vectors are input to the array in the form of voltage, and the multiplication and addition results are obtained in the form of current.

[0005] However, the existing technology for implementing neural network algorithm systems based on flash memory arrays needs further improvement.

[0006] Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a memory, a memory circuit and a working method of the memory circuit to improve the reliability of the calculation accuracy of the neural network algorithm system.

[0008] To solve the above technical problems, the technical solution of the present invention provides a memory, comprising: a substrate; a plurality of memory cell structures arranged in an array on the substrate, each memory cell structure comprising a word line gate, a source line layer and a gate structure, the gate structure being located between the source line layer and the word line gate, the gate structure comprising a gate oxide layer, a floating gate located on the gate oxide layer, a tunneling oxide layer located on the floating gate, and a control gate located on a portion of the tunneling oxide layer, the source line layer being located between the gate structures of two adjacent memory cell structures, the control gate being used to apply a first programming voltage during a programming operation to pull electrons from the control gate to the floating gate, and the control gate being used to apply an erase voltage during an erase operation to pull electrons from the floating gate to the control gate; a source line doping region being located in the substrate at the bottom of the source line layer; and a bit line doping region being located in the substrate between the word line gates of two adjacent memory cell structures.

[0009] Optionally, each storage cell structure further includes: a sidewall structure located between the gate structure and the source line layer, the sidewall structure including a first sidewall located on the control gate, a second sidewall located between the control gate and the sidewall of the first sidewall and the source line layer, and a third sidewall located between the second sidewall and the floating gate sidewall and the source line layer; and a fourth sidewall located on the sidewall surface of the word line gate away from the gate structure.

[0010] Correspondingly, the technical solution of the present invention also provides a method for forming the above-mentioned memory.

[0011] Correspondingly, the technical solution of the present invention further provides a memory circuit, comprising: a plurality of memory cells arranged in an array, wherein the structure of each memory cell comprises: a substrate; a word line gate, a source line layer and a gate structure located on the substrate, wherein the gate structure is located between the source line layer and the word line gate, wherein the gate structure comprises a gate oxide layer, a floating gate located on the gate oxide layer, a tunneling oxide layer located on the floating gate, and a control gate located on a portion of the tunneling oxide layer, wherein the source line layer is located between the gate structures of two adjacent memory cell structures, and during a programming operation, the control gate is used to apply the first A programming voltage is used to pull electrons from the control gate into the floating gate. During an erase operation, the control gate is used to apply an erase voltage to pull electrons from the floating gate into the control gate. A source line doping region is located in the substrate at the bottom of the source line layer. A bit line doping region is located in the substrate between the word line gates of two adjacent memory cell structures. A word line is electrically connected to the word line gates of memory cells in the same row. A bit line is electrically connected to the bit line doping region of memory cells in the same column. A source line is electrically connected to the source line layer of memory cells in the same column. A control gate line is electrically connected to the control gates of memory cells in the same row.

[0012] Optionally, it also includes: a programming unit, used to apply a first programming voltage to the control gate line of the selected memory cell and a second programming voltage to the source line of the memory cell, wherein the first programming voltage is less than the second programming voltage to program the floating gate of the memory cell to form the required transconductance.

[0013] Optionally, the method further includes: a signal reading unit, configured to apply an input voltage to the control gate line of the selected memory cell and read the current output from each bit line.

[0014] Optionally, the signal reading unit further includes a device for applying a first reading voltage to a word line of a selected memory cell and applying a second reading voltage to a bit line of the memory cell.

[0015] Optionally, it further includes: an erasing unit, used to apply an erasing voltage to the control gate line of the selected memory cell, wherein the erasing voltage is a positive voltage to erase the storage information in the memory cell.

[0016] Optionally, the erasing unit is further configured to apply an anti-erase voltage to the source line of the unselected memory cell, where the anti-erase voltage is a positive voltage to prevent an erroneous erase operation.

[0017] Correspondingly, the technical solution of the present invention also provides a working method of the above-mentioned memory circuit, which is used in a neural network computing system, including: performing a programming operation on a selected single memory cell, applying a first programming voltage to the control gate line corresponding to the memory cell, and applying a second programming voltage to the source line corresponding to the memory cell, wherein the first programming voltage is less than the second programming voltage; a reading operation, applying an input voltage to the control gate line corresponding to the memory cell, and reading the output current output from each bit line; an erasing operation, applying an erasing voltage to the control gate line corresponding to the memory cell, wherein the erasing voltage is a positive voltage to erase the storage information in the memory cell.

[0018] Optionally, the input voltage range is 0V to 2.5V; the first programming voltage range is -5V to -15V; and the second programming voltage range is 5V to 10V.

[0019] Optionally, the read operation further includes: applying a first read voltage to a word line of the selected memory cell, and applying a second read voltage to a bit line of the memory cell, wherein both the first read voltage and the second read voltage are positive voltages.

[0020] Optionally, the first read voltage ranges from 1 volt to 2 volts; and the second read voltage ranges from 0.5 volts to 2 volts.

[0021] Optionally, the erasing operation further includes: applying an anti-erase voltage to the source line of the unselected memory cell, wherein the anti-erase voltage is a positive voltage to prevent an erroneous erasure operation.

[0022] Optionally, the anti-erase voltage ranges from 5V to 10V.

[0023] Optionally, the erase voltage ranges from 10V to 15V.

[0024] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the memory provided by the technical solution of the present invention, during a programming operation, the control gate is used to apply a first programming voltage to pull electrons from the control gate to the floating gate; during an erasing operation, the control gate is used to apply an erasing voltage to pull electrons from the floating gate to the control gate. Both the programming operation and the erasing operation are achieved by electron tunneling through a tunneling oxide layer located between the control gate and the floating gate. Therefore, no hot electrons are generated in the channel, and thus they are not injected into the gate oxide layer below the floating gate to cause damage to the gate oxide layer, thereby reducing the impact on the threshold voltage of the memory cell structure, thereby improving the stability of the transconductance of the memory cell structure.

[0026] In the memory circuit provided by the technical solution of the present invention, during a programming operation, the control gate is used to apply a first programming voltage to pull electrons from the control gate to the floating gate; during an erasing operation, the control gate is used to apply an erasing voltage to pull electrons from the floating gate to the control gate. Both the programming operation and the erasing operation are achieved by electron tunneling through a tunneling oxide layer located between the control gate and the floating gate. Therefore, no hot electrons are generated in the channel, and thus they are not injected into the gate oxide layer below the floating gate to cause damage to the gate oxide layer, thereby reducing the impact on the threshold voltage of the memory cell structure, thereby improving the stability of the transconductance of the memory cell structure; in addition, each memory cell in the memory circuit can perform erase operations, read operations, and programming operations separately without affecting other memory cells. When the memory circuit is used for neural network calculations, the transconductance value of each memory cell can be used as a weight connecting input and output in the neural network. Due to the stability of the transconductance of each memory cell structure, the reliability of the calculation accuracy of the neural network system is improved.

[0027] The technical solution of the present invention provides a working method for a memory circuit used in a neural network system, in which each storage unit in the memory circuit can be individually erased, read, and programmed without affecting other storage units. The memory circuit is used in neural network calculations, and the transconductance value of each storage unit is used as the weight connecting the input and output in the neural network. Due to the stability of the transconductance of each storage unit structure, it is beneficial to improve the reliability of the calculation accuracy of the neural network system. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a schematic structural diagram of a memory;

[0029] FIG2 is a schematic diagram of a memory circuit;

[0030] FIG3 is a schematic structural diagram of a memory according to an embodiment of the present invention;

[0031] FIG4 is a schematic diagram of a memory circuit according to an embodiment of the present invention;

[0032] 5 is a flow chart of an operating method of a memory circuit according to an embodiment of the present invention;

[0033] FIG6 is a schematic diagram of a memory circuit used in a neural network computing system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0035] As described in the background art, the existing technology for implementing neural network algorithms based on flash memory arrays needs to be further improved. A memory structure and a memory circuit based on the memory structure are now described and analyzed.

[0036] FIG1 is a schematic diagram of the structure of a memory.

[0037] Please refer to Figure 1. The memory includes: a substrate 100; a plurality of memory cell structures located on the substrate 100, each of the memory cell structures including two word line gates 101 and an erase gate 102 located between the two word line gates 101, a floating gate 103 located between the erase gate 102 and each word line gate 101, a control gate 104 located on the floating gate 103, and a gate oxide layer 105 located between the floating gate 103 and the substrate 100; a source doped region 106 located in the substrate 100 at the bottom of the erase gate 102; and drain doped regions 107 located in the substrate 100 on both sides of the memory cell structure.

[0038] The above structure is a flash memory. FIG2 is a memory circuit based on the above flash memory structure for implementing a neural network algorithm.

[0039] FIG2 is a schematic diagram of a memory circuit.

[0040] Please refer to FIG2 based on FIG1. ​​The memory circuit includes: a plurality of memory cells arranged in an array (as shown by the dotted line), each memory cell includes two multi-gate transistors, an erase gate, a source, and two drains. Each multi-gate transistor includes a floating gate, a control gate coupled to the floating gate, and a word line gate for controlling the multi-gate transistor to be turned on. The source is a terminal shared by the two multi-gate transistors, and each drain corresponds to the other terminal of each multi-gate transistor. The word line WL i , electrically connected to the word line gate of the memory cell in the same row; control gate line CG i , electrically connected to the control gate of the memory cell in the same row; bit line BL j , electrically connected to the drain of the memory cell in the same column; source line SL i , electrically connected to the source of the memory cell in the same row; an erase line EG j , electrically connected to the erase gate of the memory cell in the same column.

[0041] In the above memory cell array, i and j are positive integers corresponding to the row and column numbers of the memory cells. The following is the relationship between input voltage and output current, taking a 4×4 array as an example:

[0042] Among them, V i The control gate line CG is applied during the read operation. i Input voltage, I j BL j Get the output current, G ji When the above memory circuit is used in a neural network algorithm, it maps each neuron value of the network input layer to the corresponding array control gate line CG. i The input voltage V i ; Map each neuron value of the network output layer to the array bit line BL j The corresponding cumulative output current I j =Σ j G ji V i ; Map the weights connecting the input and output in the network to the transconductance G of the corresponding cross-point storage unit in the array ji .

[0043] When the memory circuit is in operation, when programming a selected memory cell, a voltage difference needs to be generated between the source and drain of the memory cell to pull hot electrons in the channel into the floating gate 103. However, the hot electrons will be injected into the gate oxide layer 105 below the floating gate 103, causing damage to the gate oxide layer 105 and forming defect charges. The defect charges are not stable and will escape over a long period of time or at high temperatures, causing the transconductance G corresponding to the memory cell to decrease. ji , which in turn leads to a decrease in the reliability of the calculation accuracy in neural network calculations.

[0044] In order to solve the above problems, the present invention provides a memory, a memory circuit and a working method of a memory circuit. Each storage unit in the storage circuit can be individually erased, read and programmed without affecting other storage units. The memory circuit is used in neural network calculations, and the transconductance value of each storage unit is used as the weight connecting the input and output in the neural network. Due to the stability of the transconductance of each storage unit structure, it is beneficial to improve the reliability of the calculation accuracy of the neural network system.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] FIG3 is a schematic diagram of the structure of a memory according to an embodiment of the present invention.

[0047] Referring to FIG3 , the memory device includes: a substrate 200; a plurality of memory cell structures arranged in an array on the substrate 200, each memory cell structure including a word line gate 201, a source line layer 202, and a gate structure. The gate structure is located between the source line layer 202 and the word line gate 201. The gate structure includes a gate oxide layer 203, a floating gate 204 located on the gate oxide layer 203, a tunneling oxide layer 205 located on the floating gate 204, and a control gate 206 located on a portion of the tunneling oxide layer 205. The source line layer 202 is located between the gate structures of two adjacent memory cell structures. During a programming operation, the control gate 206 is used to apply a first programming voltage to pull electrons from the control gate 206 to the floating gate 204. During the erase operation, the control gate 206 is used to apply an erase voltage to pull electrons from the floating gate 204 into the control gate 206; the source line doping region 207 is located in the substrate 200 at the bottom of the source line layer 202; the bit line doping region 208 is located in the substrate 200 between the word line gates 201 of two adjacent storage cell structures.

[0048] Here, the programming operation and the erasing operation are both achieved by electron tunneling through the tunneling oxide layer 205 located between the control gate 206 and the floating gate 204. Therefore, no hot electrons are generated in the channel, and thus they are not injected into the gate oxide layer 203 under the floating gate 204 to cause damage to the gate oxide layer 203, thereby reducing the impact on the threshold voltage of the storage cell structure, thereby improving the stability of the transconductance of the storage cell structure.

[0049] In this embodiment, each storage cell structure further includes: a sidewall structure located between the gate structure and the source line layer 202, the sidewall structure including a first sidewall 209 located on the control gate 206, a second sidewall 210 located between the sidewalls of the control gate 206 and the first sidewall 209 and the source line layer 202, and a third sidewall 211 located between the second sidewall 210 and the sidewall of the floating gate 204 and the source line layer 202; and a fourth sidewall 212 located on the sidewall surface of the word line gate 201 away from the gate structure.

[0050] In this embodiment, a word line gate oxide layer 213 is further provided between the word line gate 201 and the substrate 200 .

[0051] Accordingly, an embodiment of the present invention further provides a method for forming the above-mentioned memory. Please continue to refer to Figure 3. The method for forming the memory includes: providing a substrate 200; forming a gate oxide material layer (not shown in the figure), a floating gate material layer (not shown in the figure) located on the gate oxide material layer, a tunneling oxide material layer (not shown in the figure) located on the floating gate material layer, and a control gate material layer (not shown in the figure) located on the tunneling oxide material layer on the substrate 200; forming a first mask layer (not shown in the figure) on the control gate material layer, the first mask layer having a first opening (not shown in the figure), the bottom of the first opening exposing a portion of the control gate material layer; forming a first sidewall 209 on the sidewall of the first opening; and The first sidewall 209 and the first mask layer are used as masks to etch the control gate material layer, forming a second opening (not shown in the figure) in the control gate material layer, with the bottom of the second opening exposing a portion of the tunneling oxide material layer; a second sidewall 210 is formed on the first sidewall 209 and the sidewall of the second opening; the second sidewall 210, the first sidewall 209 and the first mask layer are used as masks to etch the tunneling oxide material layer, the floating gate material layer and the gate oxide material layer, forming a third opening (not shown in the figure) in the tunneling oxide material layer and the floating gate material layer, with the bottom of the third opening exposing a portion of the surface of the substrate 200; a third sidewall is formed on the sidewall of the third opening and the sidewall of the second sidewall 210 211; forming a source line doping region 207 in the substrate 200 at the bottom of the third opening; after forming the source line doping region 207, forming a source line layer 202 in the first opening, the second opening and the third opening; forming a second mask layer (not shown in the figure) on the source line doping region 207, the second mask layer exposing the first mask layer; using the second mask layer as a mask, etching the first mask layer, the control gate material layer, the tunneling oxide material layer, the floating gate material layer and the gate oxide material layer until the surface of the substrate 200 is exposed, forming two gate structures, each of the gate structures including a gate oxide layer 203, a floating gate 204 located on the gate oxide layer 203, and a gate oxide layer located on the floating gate 204. a tunneling oxide layer 205 on the substrate 200, and a control gate 206 located on part of the tunneling oxide layer 205, the control gate 206 is formed with the control gate material layer, the tunneling oxide layer 205 is formed with the tunneling oxide material layer, the floating gate 204 is formed with the floating gate material layer, and the gate oxide layer 203 is formed with the gate oxide material layer; a word line gate oxide layer 213 and a word line gate 201 located on the surface of the word line gate oxide layer 213 are formed on the substrate 200 and on the sidewall of the gate structure away from the source line layer 202, so as to form two memory cell structures, each memory cell structure including the word line gate 201, the source line layer 202 and the gate structure, and the source line layer 202 is located between the gate structures of two adjacent memory cell structures;A fourth spacer 212 is formed on the sidewall of the word line gate 201 away from the gate structure; after the fourth spacer 212 is formed, a bit line doping region 208 is formed in the substrate 200 between the word line gates 201 of two adjacent memory cell structures.

[0052] Accordingly, an embodiment of the present invention further provides a memory circuit using the above-mentioned memory. Referring to FIG4 on the basis of FIG3 , the memory circuit includes: a plurality of memory cells arranged in an array, each of the memory cells including: a substrate 200; a word line gate 201, a source line layer 202, and a gate structure located on the substrate 200, the gate structure located between the source line layer 202 and the word line gate 201, the gate structure including a gate oxide layer 203, a floating gate 204 located on the gate oxide layer 203, a tunneling oxide layer 205 located on the floating gate 204, and a control gate 206 located on a portion of the tunneling oxide layer 205, the source line layer 202 being located between the gate structures of two adjacent memory cell structures, and during a programming operation, the control gate 206 is located between the gate structures of two adjacent memory cell structures. 06 is used to apply a first programming voltage to pull electrons from the control gate 206 to the floating gate 204. During an erase operation, the control gate 206 is used to apply an erase voltage to pull electrons from the floating gate 204 to the control gate 206; a source line doping region 207 is located in the substrate 200 at the bottom of the source line layer 202; a bit line doping region 208 is located in the substrate 200 between the word line gates 201 of two adjacent memory cell structures; a word line WLi is electrically connected to the word line gate 201 of a memory cell in the same row; a bit line BLj is electrically connected to the bit line doping region 208 of a memory cell in the same column; a source line SLj is electrically connected to the source line layer 202 of the memory cell in the same column; and a control gate line EPHGi is electrically connected to the control gate 206 of a memory cell in the same row.

[0053] Here, the programming and erasing operations are both performed by electron tunneling through the tunneling oxide layer 205 located between the control gate 206 and the floating gate 204. Therefore, no hot electrons are generated in the channel, and thus are not injected into the gate oxide layer 203 below the floating gate 204, causing damage to the gate oxide layer. This reduces the impact on the threshold voltage of the memory cell structure, thereby improving the stability of the transconductance of the memory cell structure. Furthermore, each memory cell in the memory circuit can be individually erased, read, and programmed without affecting other memory cells. When the memory circuit is used for neural network calculations, the transconductance value of each memory cell can be used as a weight connecting the input and output of the neural network. Due to the stability of the transconductance of each memory cell structure, the reliability of the calculation accuracy of the neural network system is improved.

[0054] It should be noted that, i and j are natural numbers, where i represents the row number of the memory cell in the array, and j represents the column number of the memory cell in the array. The row and column numbers in FIG4 are for illustration only and can be adjusted according to actual needs in other embodiments.

[0055] In this embodiment, the memory circuit further includes a programming unit (not shown) configured to apply a first programming voltage to the control gate line EPHGi of a selected memory cell and a second programming voltage to the source line SLj of the memory cell, wherein the first programming voltage is lower than the second programming voltage, so as to program the floating gate 204 of the memory cell and form the desired transconductance. Accordingly, the voltage applied to the control gate 206 is lower than the voltage applied to the floating gate 204, causing electrons to be drawn from the control gate 206 to the floating gate 204, thereby implementing the programming operation.

[0056] In this embodiment, the memory circuit further includes a signal reading unit (not shown in the figure) for applying an input voltage to the control gate line EPHGi of the selected memory cell and reading the current output from each bit line BLj.

[0057] In this embodiment, the signal reading unit further includes a device for applying a first reading voltage to the word line WLi of the selected memory cell and applying a second reading voltage to the bit line BLj of the memory cell.

[0058] In this embodiment, the memory circuit further includes an erasing unit (not shown in the figure) for applying an erasing voltage to the control gate line EPHGi of the selected memory cell, where the erasing voltage is a positive voltage to erase the stored information in the memory cell.

[0059] In this embodiment, the erasing unit is further configured to apply an anti-erase voltage to the source line SLj of the unselected memory cell, where the anti-erase voltage is a positive voltage to prevent an erroneous erase operation.

[0060] Correspondingly, an embodiment of the present invention further provides a working method of the above-mentioned memory circuit, where the memory circuit is used in a neural network computing system, as shown in FIG5 .

[0061] FIG5 is a flow chart of an operating method of a memory circuit according to an embodiment of the present invention.

[0062] Referring to FIG5 , the operating method of the memory circuit includes the following steps:

[0063] S301, performing a programming operation on a selected single memory cell, applying a first programming voltage to a control gate line corresponding to the memory cell, and applying a second programming voltage to a source line corresponding to the memory cell, wherein the first programming voltage is lower than the second programming voltage;

[0064] S302, a read operation, applying an input voltage to the control gate line corresponding to the memory cell and reading the output current output from each bit line;

[0065] S303, an erase operation, applying an erase voltage to the control gate line corresponding to the memory cell, wherein the erase voltage is a positive voltage, so as to erase the storage information in the memory cell.

[0066] Each storage unit in the storage circuit can be individually erased, read, and programmed without affecting other storage units. The memory circuit is used in neural network calculations, and the transconductance value of each storage unit is used as the weight connecting the input and output in the neural network. Due to the stability of the transconductance of each storage unit structure, it is beneficial to improve the reliability of the calculation accuracy of the neural network system.

[0067] In order to illustrate each operating state in the memory circuit, a detailed description will be given below in conjunction with Table 1 and the accompanying drawings.

[0068] Table 1 Operation status of memory circuit

[0069] Please continue to refer to FIG3 and FIG4, and in combination with Table 1, the working state of the memory circuit is as follows:

[0070] 1. Programming operation:

[0071] A programming operation is performed on a selected single memory cell, a first programming voltage is applied to the control gate line EPHGi corresponding to the memory cell, and a second programming voltage is applied to the source line SLj corresponding to the memory cell, wherein the first programming voltage is lower than the second programming voltage.

[0072] Taking Cell0 (as shown by the dotted line in FIG4 ) as an example (for ease of explanation, the memory cell in the figure has been bolded), a first programming voltage is applied to EPHG0 and a second programming voltage is applied to SL0, and a programming operation can be performed on Cell0 to form the required transconductance.

[0073] In this embodiment, the first programming voltage ranges from -5V to -15V; the second programming voltage ranges from 5V to 10V.

[0074] 2. Read operation

[0075] In a read operation, an input voltage is applied to the control gate line EPHGi corresponding to the memory cell, and an output current output from each bit line BLj is read.

[0076] In this embodiment, the input voltage range is 0V to 2.5V.

[0077] In this embodiment, the read operation further includes: applying a first read voltage to the word line WLi of the selected memory cell, and applying a second read voltage to the bit line BLj of the memory cell, wherein both the first read voltage and the second read voltage are positive voltages.

[0078] Continuing with the read operation on Cell0 as an example, an input voltage is applied to EPHG0, a first read voltage is applied to word line WL0, a second read voltage is applied to bit line BL0 of the memory cell, and the output current output from each bit line BL0 is read to obtain the storage information in Cell0.

[0079] In this embodiment, the first read voltage ranges from 1V to 2V; the second read voltage ranges from 0.5V to 2V.

[0080] 3. Erase operation

[0081] In the erase operation, an erase voltage is applied to the control gate line EPHGi corresponding to the memory cell, where the erase voltage is a positive voltage, so as to erase the storage information in the memory cell.

[0082] In this embodiment, the erase voltage ranges from 10V to 15V.

[0083] In this embodiment, the erasing operation further includes: applying an anti-erase voltage to the source line SLj of the unselected memory cell, where the anti-erase voltage is a positive voltage to prevent an erroneous erasure operation.

[0084] Continuing with the example of erasing Cell0, an erase voltage is applied to EPHG0, where the erase voltage is a positive voltage, to erase the storage information in Cell0. At the same time, an anti-erase voltage is applied to the source lines SL1 to SLn+1 to prevent accidental erasure operations on storage cells other than Cell0.

[0085] In this embodiment, the anti-erase voltage ranges from 5V to 10V.

[0086] FIG6 is a schematic diagram of a memory circuit used in a neural network computing system according to an embodiment of the present invention.

[0087] Please refer to FIG6 , the above storage circuit can be used in a neural network computing system, specifically for implementing a product operation. i The neuron value X as the input layer of the neural network i , based on the accumulated output current I from the bit line BLi j The neuron value Y as the output layer of the neural network j , with the transconductance G of a single memory cell ji As the weight W connecting the input layer and the output layer in the neural networkji .

[0088] Specifically, continuing to take Cell0 as an example, the input voltage V0 applied to the control gate line EPHG0 in the read operation is used as the neuron value X0 of the input layer of the neural network, the accumulated output current I0 from the bit line BL0 is used as the neuron value Y0 of the output layer of the neural network, and the transconductance G of a single storage cell is used as the output layer of the neural network. 00 As the weight W connecting the input layer and the output layer in the neural network 00 .

[0089] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A memory, characterized in that: include: substrate; A plurality of memory cell structures arranged in an array on a substrate, each memory cell structure comprising a word line gate, a source line layer and a gate structure, wherein the gate structure is located between the source line layer and the word line gate, the gate structure comprising a gate oxide layer, a floating gate located on the gate oxide layer, a tunneling oxide layer located on the floating gate, and a control gate located on a portion of the tunneling oxide layer, the source line layer is located between the gate structures of two adjacent memory cell structures, during a programming operation, the control gate is used to apply a first programming voltage to pull electrons from the control gate to the floating gate, and during an erasing operation, the control gate is used to apply an erasing voltage to pull electrons from the floating gate to the control gate; A source line doping region, located in the substrate at the bottom of the source line layer; The bit line doping region is located in the substrate between the word line gates of two adjacent memory cell structures.

2. The memory according to claim 1, wherein: Each storage cell structure also includes: a sidewall structure located between the gate structure and the source line layer, the sidewall structure including a first sidewall located on the control gate, a second sidewall located between the control gate and the sidewall of the first sidewall and the source line layer, and a third sidewall located between the second sidewall and the floating gate sidewall and the source line layer; and a fourth sidewall located on the sidewall surface of the word line gate away from the gate structure.

3. A method for forming a memory according to any one of claims 1 to 2.

4. A memory circuit, characterized in that: include: A plurality of storage units arranged in an array, each of the storage units comprising: substrate; A word line gate, a source line layer and a gate structure located on the substrate, wherein the gate structure is located between the source line layer and the word line gate, the gate structure includes a gate oxide layer, a floating gate located on the gate oxide layer, a tunneling oxide layer located on the floating gate, and a control gate located on a portion of the tunneling oxide layer, the source line layer is located between the gate structures of two adjacent memory cell structures, during a programming operation, the control gate is used to apply a first programming voltage to pull electrons from the control gate to the floating gate, and during an erasing operation, the control gate is used to apply an erasing voltage to pull electrons from the floating gate to the control gate; A source line doping region, located in the substrate at the bottom of the source line layer; A bit line doping region is located in the substrate between word line gates of two adjacent memory cell structures; A word line electrically connected to the word line gate of a memory cell in the same row; A bit line electrically connected to the bit line doping region of the memory cell in the same column; A source line electrically connected to the source line layer of the memory cells in the same column; The control gate line is electrically connected to the control gates of the memory cells in the same row.

5. The memory circuit according to claim 4, wherein: Also includes: The programming unit is used to apply a first programming voltage to the control gate line of the selected storage cell and a second programming voltage to the source line of the storage cell, wherein the first programming voltage is less than the second programming voltage, so as to program the floating gate of the storage cell and form the required transconductance.

6. The memory circuit according to claim 4, wherein: Also includes: The signal reading unit is used to apply an input voltage to the control gate line of the selected storage unit and read the current output from each bit line.

7. The memory circuit according to claim 6, wherein: The signal reading unit also includes a device for applying a first reading voltage to a word line of a selected memory cell and applying a second reading voltage to a bit line of the memory cell.

8. The memory circuit according to claim 4, wherein: Also includes: The erasing unit is used to apply an erasing voltage to the control gate line of the selected storage unit, wherein the erasing voltage is a positive voltage to erase the storage information in the storage unit.

9. The memory circuit according to claim 8, wherein: The erasing unit is also used to apply an anti-erase voltage to the source line of the unselected storage unit, and the anti-erase voltage is a positive voltage to prevent an erroneous erasure operation.

10. A method for operating a memory circuit according to any one of claims 4 to 9, wherein the memory circuit is used in a neural network computing system, characterized in that: include: Performing a programming operation on a selected single memory cell, applying a first programming voltage to a control gate line corresponding to the memory cell, and applying a second programming voltage to a source line corresponding to the memory cell, wherein the first programming voltage is less than the second programming voltage; A read operation is performed by applying an input voltage to a control gate line corresponding to the memory cell and reading an output current output from each bit line; In the erasing operation, an erasing voltage is applied to the control gate line corresponding to the storage cell, wherein the erasing voltage is a positive voltage, so as to erase the storage information in the storage cell.

11. The operating method of the memory circuit according to claim 10, characterized in that: include: The input voltage range is 0V to 2.5V; The first programming voltage ranges from -5 volts to -15 volts; The second programming voltage ranges from 5V to 10V.

12. The operating method of the memory circuit according to claim 10, characterized in that: The reading operation further includes: applying a first reading voltage to a word line of a selected memory cell, and applying a second reading voltage to a bit line of the memory cell, wherein both the first reading voltage and the second reading voltage are positive voltages.

13. The operating method of the memory circuit according to claim 12, characterized in that: include: The first read voltage ranges from 1V to 2V; The second read voltage ranges from 0.5V to 2V.

14. The operating method of the memory circuit according to claim 10, characterized in that: The erasing operation further includes: applying an anti-erase voltage to the source line of the unselected memory cell, wherein the anti-erase voltage is a positive voltage to prevent an erroneous erasure operation.

15. The operating method of the memory circuit according to claim 14, characterized in that: The mis-erasure prevention voltage ranges from 5V to 10V.

16. The operating method of the memory circuit according to claim 10, characterized in that: The erase voltage ranges from 10V to 15V.

Images