Display substrate and display apparatus

Abstract

Provided are a display substrate and a display apparatus. The display substrate comprises a base, a first direct-current voltage line (VSS), a second direct-current voltage line (VI2), and a voltage-stabilizing capacitor (Cw), wherein an orthographic projection of the first direct-current voltage line (VSS) on the base and an orthographic projection of the second direct-current voltage line (VI2) on the base are arranged adjacent to each other; the voltage-stabilizing capacitor (Cw) comprises a first electrode plate (C1a) and a second electrode plate (C1b); the first electrode plate (C1a) is electrically connected to the first direct-current voltage line (VSS), and the second electrode plate (C1b) is electrically connected to the second direct-current voltage line (VI2); and an orthographic projection of the first electrode plate (C1a) on the base at least partially overlaps with the orthographic projection of the second direct-current voltage line (VI2) on the base, and an orthographic projection of the second electrode plate (C1b) on the base at least partially overlaps with the orthographic projection of the second direct-current voltage line (VI2) on the substrate base. By means of providing a voltage-stabilizing capacitor (Cw) between a first direct-current voltage line (VSS) and a second direct-current voltage line (VI2), the fluctuation in the voltage value of a second initial voltage caused by a load difference of a second initial voltage line can be greatly reduced, thereby greatly ameliorating a screen-tearing phenomenon.

Description

Display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311062813.9 filed in China on August 22, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] When the relevant pixel circuit is working, when the light-emitting control line controls the light-emitting control transistor to be turned off, controls the first electrode of the driving transistor to be connected to the reference voltage, controls the anode of the organic light-emitting diode to be connected to the second initial voltage Vi2, initializes the first electrode of the driving transistor and the anode of the organic light-emitting diode, and when 3 pulses appear on the screen, the load of the second initial voltage line for providing the second initial voltage is the first load Lx; when the first pulse enters the Blank area and 2 pulses appear on the display screen, the load of the second initial voltage line is the second load Ly; when the anode of the organic light-emitting diode is controlled to be connected to the second initial voltage Vi2 to charge the anode of the organic light-emitting diode in the pixel circuit, the voltage value of Vi2 is pulled up, and the load in the Blank area is relatively small, so the amplitude by which the voltage value of Vi2 is pulled up is relatively small, and then in the Blank area, the potential of the anode of the organic light-emitting diode is relatively low, and the corresponding pixel is relatively dark.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising a substrate, and a first DC voltage line, a second DC voltage line, and a voltage-stabilizing capacitor disposed on the substrate; an orthographic projection of the first DC voltage line and an orthographic projection of the second DC voltage line on the substrate are disposed adjacent to each other;

[0007] The voltage-stabilizing capacitor includes a first plate and a second plate; the first plate and the second plate are formed on different conductive layers;

[0008] The first electrode plate is electrically connected to the first DC voltage line, and the second electrode plate is electrically connected to the second DC voltage line;

[0009] The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second DC voltage line on the substrate;

[0010] An orthographic projection of the second electrode plate on the substrate at least partially overlaps with an orthographic projection of the second DC voltage line on the substrate.

[0011] Optionally, the first electrode plate includes a first electrode plate portion and a second electrode plate portion;

[0012] The first electrode portion is formed on the first conductive layer, the second electrode portion is formed on the second conductive layer, and the second electrode portion is formed on the third conductive layer;

[0013] The second electrode plate is located between the first electrode plate portion and the second electrode plate portion;

[0014] The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate portion on the substrate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate portion on the substrate.

[0015] Optionally, the first electrode portion is electrically connected to the first DC voltage line, and the second electrode portion is electrically connected to the first DC voltage line.

[0016] Optionally, the first DC voltage line includes a first voltage line portion and a second voltage line portion electrically connected to each other;

[0017] The first voltage line portion is formed in the fourth conductive layer, and the second voltage line portion is formed in the fifth conductive layer;

[0018] The first electrode portion and the second electrode portion are both electrically connected to the first voltage line portion.

[0019] Optionally, the second DC voltage line is formed in the fifth conductive layer;

[0020] The second electrode plate is electrically connected to the second DC voltage line through a conductive pattern formed on the fourth conductive layer.

[0021] Optionally, the first conductive layer is a semiconductor layer, the second conductive layer is a first gate metal layer, the third conductive layer is a second gate metal layer, the fourth conductive layer is a first source-drain metal layer, and the fifth conductive layer is a second source-drain metal layer;

[0022] The semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer are arranged in sequence along a direction away from the substrate.

[0023] Optionally, the orthographic projection of the first electrode portion on the substrate at least partially overlaps with the orthographic projection of the first DC voltage line on the substrate;

[0024] An orthographic projection of the second electrode portion on the substrate at least partially overlaps with an orthographic projection of the first DC voltage line on the substrate.

[0025] Optionally, the first electrode plate is formed on the first conductive layer, and the second electrode plate is formed on the second conductive layer;

[0026] An orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate.

[0027] Optionally, the first electrode plate is formed on the third conductive layer, and the second electrode plate is formed on the second conductive layer;

[0028] An orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate.

[0029] Optionally, the first electrode plate includes a first electrode plate portion and a second electrode plate portion;

[0030] The first electrode portion is formed on the sixth conductive layer, the second electrode portion is formed on the second conductive layer, and the second electrode is formed on the third conductive layer;

[0031] The second electrode plate is located between the first electrode plate portion and the second electrode plate portion;

[0032] The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate portion on the substrate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate portion on the substrate.

[0033] Optionally, the first electrode plate is formed on the sixth conductive layer, and the second electrode plate is formed on the third conductive layer;

[0034] An orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate.

[0035] Optionally, the first electrode plate is formed on the sixth conductive layer, and the second electrode plate is formed on the second conductive layer.

[0036] Optionally, the sixth conductive layer is a third gate metal layer.

[0037] Optionally, the capacitance value of the voltage-stabilizing capacitor is greater than or equal to 5 μF and less than or equal to 20 μF.

[0038] In a second aspect, an embodiment of the present disclosure provides a display substrate, including a display area, characterized in that it includes a substrate, a first DC voltage line and a second DC voltage line; the first DC voltage line and the second DC voltage line are provided on the substrate;

[0039] The first DC voltage line and the second DC voltage line are arranged around the display area;

[0040] The first DC voltage line is formed in the seventh conductive layer, and the second DC voltage line is formed in the eighth conductive layer; a dielectric layer is provided between the seventh conductive layer and the eighth conductive layer;

[0041] An orthographic projection of the first DC voltage line on the substrate at least partially overlaps with an orthographic projection of the second DC voltage line on the substrate.

[0042] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a circuit diagram of a pixel circuit;

[0044] FIG2 is an operation timing diagram of the related pixel circuit shown in FIG1 ;

[0045] FIG3 is a structural diagram of at least one embodiment of a voltage-stabilizing capacitor;

[0046] FIG4 is a layout diagram of the semiconductor layer in FIG3 ;

[0047] FIG5 is a layout diagram of the first gate metal layer in FIG3 ;

[0048] FIG6 is a layout diagram of the second gate metal layer in FIG3;

[0049] FIG7 is a layout diagram of the first source / drain metal layer in FIG3 ;

[0050] FIG8 is a layout diagram of the second source / drain metal layer in FIG3 ;

[0051] 9A and 9B are AA' cross-sectional views in FIG. 3;

[0052] 10A and 10B are BB' cross-sectional views in FIG. 3;

[0053] 11A and 11B are CC' cross-sectional views in FIG. 3;

[0054] FIG12 is a layout diagram of the low voltage line, the second initial voltage line and the voltage stabilizing capacitor in the lower frame of the display panel;

[0055] FIG13 is a layout diagram of the semiconductor layer in FIG12;

[0056] FIG14 is a layout diagram of the first gate metal layer in FIG12;

[0057] FIG15 is a layout diagram of the second gate metal layer in FIG12;

[0058] FIG16 is a layout diagram of the first source / drain metal layer in FIG12 ;

[0059] FIG17 is a layout diagram of the second source / drain metal layer in FIG12 ;

[0060] FIG18 is a stack diagram of the first gate metal layer and the second gate metal layer in FIG12;

[0061] FIG19 is a stacked diagram of the semiconductor layer and the first gate metal layer in FIG12;

[0062] FIG20 is a stacked diagram of the semiconductor layer, the first gate metal layer, and the second gate metal layer in FIG12 ;

[0063] FIG21 is a layout diagram of the semiconductor layer, the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in FIG12 ;

[0064] FIG22 is a layout diagram of the first source-drain metal layer and the second source-drain metal layer in FIG12;

[0065] FIG23 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor;

[0066] FIG24 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor;

[0067] FIG25 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor;

[0068] FIG26 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor;

[0069] FIG27 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor;

[0070] FIG28 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor;

[0071] FIG29 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor;

[0072] FIG30 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor;

[0073] FIG31 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0074] FIG32 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0075] FIG33 is a DD′ cross-sectional view of FIG32 . DETAILED DESCRIPTION

[0076] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0077] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0078] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0079] FIG. 1 is a circuit diagram of at least one embodiment of a pixel circuit.

[0080] As shown in FIG1 , at least one embodiment of the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a storage capacitor Cs, and an organic light emitting diode O1;

[0081] T3 is a driving transistor; the gate of T3 is electrically connected to the first node N1, and the source of T3 is electrically connected to the second node N2;

[0082] The gate of T1 is electrically connected to the first reset line PR1, the source of T1 is connected to the first initial voltage Vi1, and the drain of T1 is electrically connected to the third node N3;

[0083] The gate of T2 is electrically connected to the first scan line GN, the source of T2 is electrically connected to the first node N1, and the drain of T2 is electrically connected to the third node N3;

[0084] The gate of T4 is electrically connected to the second scan line GP, the source of T4 is electrically connected to the data line DT, and the drain of T4 is electrically connected to the second node N2;

[0085] The gate of T5 is electrically connected to the light emitting control line EM, the source of T5 is electrically connected to the high voltage line VDD, and the drain of T5 is electrically connected to the second node N2;

[0086] The gate of T6 is electrically connected to the light emitting control line EM, the source of T6 is electrically connected to the third node N3, and the drain of T6 is electrically connected to the anode of O1;

[0087] The anode of O1 is electrically connected to the fourth node N4, and the cathode of O1 is connected to the low voltage signal Vs;

[0088] The gate of T7 is electrically connected to the second reset line PR2, the source of T7 is connected to the second initial voltage Vi2, and the drain of T7 is electrically connected to the anode of O1;

[0089] The gate of T8 is electrically connected to the second reset line PR2, the source of T8 is connected to the reference voltage Vref, and the drain of T8 is electrically connected to the second node N2;

[0090] A first end of Cs is electrically connected to the first node N1 , and a second end of Cs is electrically connected to the high voltage line VDD.

[0091] In at least one embodiment of the pixel circuit shown in FIG. 1 , T2 is an n-type transistor to reduce the drain of N1 , and the other transistors are p-type transistors, but the present invention is not limited thereto.

[0092] FIG. 2 is an operation timing diagram of the related pixel circuit shown in FIG. 1 .

[0093] In FIG2 , the frame labeled F1 is a refresh frame, the frame labeled F21 is a first hold frame, and the frame labeled F22 is a second hold frame.

[0094] When the relevant pixel circuit shown in Figure 1 is working, assuming that the basic refresh rate is 120Hz, a refresh rate of 40Hz can be achieved through the above-mentioned Frame Skip method; and similarly, display effects with different refresh rates can be achieved by changing the number of maintained frames.

[0095] In order to solve the three-part screen problem caused by writing the load on the second initial voltage line (the number of split screens is related to the number of pulses, and at least one embodiment of the present disclosure takes the three-part screen as an example), a larger voltage stabilizing capacitor is added in the design for compensation.

[0096] The display substrate of the embodiment of the present disclosure includes a substrate, a first DC voltage line, a second DC voltage line, and a voltage-stabilizing capacitor; the first DC voltage line, the second DC voltage line, and the voltage-stabilizing capacitor are arranged on the substrate; the orthographic projection of the first DC voltage line on the substrate and the orthographic projection of the second DC voltage line on the substrate are arranged adjacent to each other;

[0097] The voltage-stabilizing capacitor includes a first plate and a second plate; the first plate and the second plate are formed on different conductive layers;

[0098] The first electrode plate is electrically connected to the first DC voltage line, and the second electrode plate is electrically connected to the second DC voltage line;

[0099] The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second DC voltage line on the substrate;

[0100] An orthographic projection of the second electrode plate on the substrate at least partially overlaps with an orthographic projection of the second DC voltage line on the substrate.

[0101] In an embodiment of the present disclosure, the display substrate may include a first DC voltage line, a second DC voltage line and a voltage-stabilizing capacitor arranged on the substrate, and the orthographic projection of the first DC voltage line on the substrate and the orthographic projection of the second DC voltage line on the substrate are arranged adjacent to each other; the first plate of the voltage-stabilizing capacitor is electrically connected to the first DC voltage line, and the second plate of the voltage-stabilizing capacitor is electrically connected to the second DC voltage line, wherein the first DC voltage line can be a low voltage line (but not limited to this, the first DC voltage line can be other signal lines providing DC voltage), and the second DC voltage line can be a second initial voltage line for providing a second initial voltage; by arranging a voltage-stabilizing capacitor between the first DC voltage line and the second DC voltage line, the fluctuation of the voltage value of the second initial voltage caused by the load difference of the second initial voltage line can be greatly reduced, thereby greatly improving the split screen phenomenon.

[0102] Optionally, the capacitance value of the voltage-stabilizing capacitor is greater than or equal to 5 μF and less than or equal to 20 μF. For example, the capacitance value of the voltage-stabilizing capacitor may be 10 μF, but is not limited thereto.

[0103] In at least one embodiment of the present disclosure, a large-size display product may include 4 ICs (integrated circuits) and 4 FPCs (flexible circuit boards), and each FPC is electrically connected to two first DC voltage lines and two second DC voltage lines, that is, the large-size display product may include eight first DC voltage lines and eight second DC voltage lines, and a voltage-stabilizing capacitor is symmetrically designed in parallel on each second DC voltage line to improve the split-screen phenomenon.

[0104] In at least one embodiment of the present disclosure, the first electrode plate includes a first electrode plate portion and a second electrode plate portion;

[0105] The first electrode portion is formed on the first conductive layer, the second electrode portion is formed on the second conductive layer, and the second electrode portion is formed on the third conductive layer;

[0106] The second electrode plate is located between the first electrode plate portion and the second electrode plate portion;

[0107] The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate portion on the substrate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate portion on the substrate.

[0108] Optionally, the first conductive layer, the second conductive layer and the third conductive layer can be arranged in sequence along the direction away from the substrate, the first conductive layer can be a semiconductor layer, the second conductive layer can be a first gate metal layer, and the third conductive layer can be a second gate metal layer, but is not limited to this.

[0109] In a specific implementation, the first electrode plate may include a first electrode plate portion formed on the first conductive layer and a second electrode plate portion formed on the third conductive layer, the second electrode plate is formed on the second conductive layer, the first electrode plate portion, the second electrode plate and the second electrode plate portion.

[0110] When the first conductive layer is a semiconductor layer, the second conductive layer is a first gate metal layer, and the third conductive layer is a third gate metal layer, a larger capacitance can be obtained because the dielectric of each conductive layer is thinner and has a larger dielectric constant.

[0111] In a specific implementation, the first electrode portion is electrically connected to the first DC voltage line, and the second electrode portion is electrically connected to the first DC voltage line.

[0112] In at least one embodiment of the present disclosure, the first DC voltage line includes a first voltage line portion and a second voltage line portion electrically connected to each other;

[0113] The first voltage line portion is formed in the fourth conductive layer, and the second voltage line portion is formed in the fifth conductive layer;

[0114] The first electrode portion and the second electrode portion are both electrically connected to the first voltage line portion.

[0115] In a specific implementation, the first DC voltage line may include a first voltage line portion and a second voltage line portion electrically connected to each other, the first voltage line portion may be formed in a fourth conductive layer, the second voltage line portion may be formed in a fifth conductive layer, the first electrode portion and the second electrode portion may both be electrically connected to the first voltage line portion, wherein the fourth conductive layer may be a first source-drain metal layer, the fifth conductive layer may be a second source-drain metal layer, and the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may be arranged in sequence along a direction away from the substrate.

[0116] In at least one embodiment of the present disclosure, the second DC voltage line is formed in the fifth conductive layer;

[0117] The second electrode plate is electrically connected to the second DC voltage line through a conductive pattern formed on the fourth conductive layer.

[0118] In a specific implementation, the second electrode plate may be electrically connected to the second DC voltage line formed in the fifth conductive layer through a conductive pattern, and the conductive pattern may be formed in the fourth conductive layer.

[0119] Optionally, the first conductive layer is a semiconductor layer, the second conductive layer is a first gate metal layer, the third conductive layer is a second gate metal layer, the fourth conductive layer is a first source-drain metal layer, and the fifth conductive layer is a second source-drain metal layer;

[0120] The semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer are arranged in sequence along a direction away from the substrate.

[0121] FIG3 is a structural diagram of a first embodiment of a voltage-stabilizing capacitor.

[0122] Figure 4 is a layout diagram of the semiconductor layer in Figure 3, Figure 5 is a layout diagram of the first gate metal layer in Figure 3, Figure 6 is a layout diagram of the second gate metal layer in Figure 3, Figure 7 is a layout diagram of the first source and drain metal layer in Figure 3, and Figure 8 is a layout diagram of the second source and drain metal layer in Figure 3.

[0123] In Figure 4, the first electrode portion is labeled C1a1, in Figure 5, the second electrode portion is labeled C1b, and the second electrode portion is labeled C1a2; in Figure 7, the first conductive portion is formed in the first source-drain metal layer, and in Figure 8, the second conductive portion is formed in the second source-drain metal layer.

[0124] As shown in FIG3 , the orthographic projection of C1a1 on the substrate, the orthographic projection of C1b on the substrate, the orthographic projection of C1a2 on the substrate, the orthographic projection of B1 on the substrate, and the orthographic projection of B2 on the substrate at least partially overlap.

[0125] 9A and 9B are AA′ cross-sectional views in FIG. 3 , FIG. 10A and 10B are BB′ cross-sectional views in FIG. 3 , and FIG. 11A and 11B are CC′ cross-sectional views in FIG. 3 .

[0126] As shown in Figures 9A, 10A and 11A, the semiconductor layer is labeled 91, the first insulating layer is labeled 92, the first gate metal layer is labeled 93, the second insulating layer is labeled 94, the second gate metal layer is labeled 95, the first source-drain metal layer is labeled 96, the third insulating layer is labeled 97, and the second source-drain metal layer is labeled 98.

[0127] As shown in FIG9B , the first conductive pattern D1 formed on the second source / drain metal layer 98 is electrically connected to the second conductive pattern D2 formed on the first source / drain metal layer 96; the first conductive pattern D1 is electrically connected to the second voltage line portion, and the second conductive pattern D2 is electrically connected to the first voltage line portion; the second conductive pattern D2 is electrically connected to the second electrode portion C1a2 formed on the second gate metal layer;

[0128] As shown in FIG11B , the second conductive pattern D2 formed on the first source / drain metal layer overlaps the first electrode portion C1a1 formed on the semiconductor layer;

[0129] As shown in Figure 10B, the third conductive pattern D3 formed in the first source and drain metal layer is electrically connected to the second initial voltage line, and the third conductive pattern D3 is overlapped with the fourth conductive pattern D4 formed in the first gate metal layer. The fourth conductive pattern D4 is electrically connected to the second electrode C1b arranged between the second gate metal layer and the semiconductor layer 91 to form a sandwich capacitor structure to maximize the formation of a voltage-stabilizing capacitor structure.

[0130] In FIG10B , the first electrode portion is labeled C1a1 , the second electrode portion is labeled C1a2 , and the second electrode portion is labeled C1b .

[0131] FIG12 is a layout diagram of a first DC voltage line, a second DC voltage line, and a voltage-stabilizing capacitor in the lower frame of the display panel.

[0132] Optionally, the first DC voltage line may be a low voltage line, and the second DC voltage line may be a second initial voltage line, but is not limited thereto.

[0133] In FIG12 , the capacitor labeled Cw is a voltage stabilizing capacitor, the capacitor labeled VSS is a first DC voltage line, and the capacitor labeled VI2 is a second DC voltage line.

[0134] Figure 13 is a layout diagram of the semiconductor layer in Figure 12, Figure 14 is a layout diagram of the first gate metal layer in Figure 12, Figure 15 is a layout diagram of the second gate metal layer in Figure 12, Figure 16 is a layout diagram of the first source and drain metal layer in Figure 12, and Figure 17 is a layout diagram of the second source and drain metal layer in Figure 12.

[0135] In FIG13 , the first electrode portion is labeled C1a1;

[0136] In FIG14 , the second electrode plate is labeled C1b;

[0137] In FIG15 , the portion labeled C1a2 is the second electrode plate portion;

[0138] In FIG16 , the first voltage line portion labeled VSS1 is included in the first DC voltage line;

[0139] In FIG17 , the second voltage line portion labeled VSS2 is included in the second DC voltage line, and the second DC voltage line is labeled VI2.

[0140] In at least one embodiment shown in FIG. 12 to FIG. 17 , the first voltage line portion VSS1 is electrically connected to the second voltage line portion VSS2 through a via hole penetrating the third insulating layer, thereby achieving electrical connection between the first voltage line portion VSS1 and the second voltage line portion VSS2 .

[0141] In FIG14 , the resistor labeled R0 is used for electrostatic protection.

[0142] Figure 18 is a stacking diagram of the first gate metal layer and the second gate metal layer in Figure 12, Figure 19 is a stacking diagram of the semiconductor layer and the first gate metal layer in Figure 12, Figure 20 is a stacking diagram of the semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 12, Figure 21 is a layout diagram of the semiconductor layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer in Figure 12, and Figure 22 is a layout diagram of the first source-drain metal layer and the second source-drain metal layer in Figure 12.

[0143] In at least one embodiment of the present disclosure, the orthographic projection of the first electrode portion on the substrate at least partially overlaps with the orthographic projection of the first DC voltage line on the substrate;

[0144] An orthographic projection of the second electrode portion on the substrate at least partially overlaps with an orthographic projection of the first DC voltage line on the substrate.

[0145] As shown in FIG12 to FIG22 , the orthographic projection of the first electrode plate portion C1a1 on the substrate at least partially overlaps with the orthographic projection of the first voltage line portion VSS1 on the substrate, and the orthographic projection of the first electrode plate portion C1a1 on the substrate at least partially overlaps with the orthographic projection of the second voltage line portion VSS2 on the substrate;

[0146] The orthographic projection of the second electrode portion C1a2 on the substrate at least partially overlaps with the orthographic projection of the first voltage line portion VSS1 on the substrate, and the orthographic projection of the second electrode portion C1a2 on the substrate at least partially overlaps with the orthographic projection of the second voltage line portion VSS2 on the substrate.

[0147] Optionally, the first electrode plate is formed on the first conductive layer, and the second electrode plate is formed on the second conductive layer;

[0148] An orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate.

[0149] In a specific implementation, the first electrode plate may be formed on a first conductive layer, and the second electrode plate may be formed on a second conductive layer.

[0150] FIG. 23 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor, and FIG. 24 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor.

[0151] FIG23 is a cross-sectional view of the junction between C1a and D5 of at least one embodiment of a voltage-stabilizing capacitor;

[0152] FIG. 24 is a cross-sectional view of a voltage-stabilizing capacitor formed by C1 a and C1 b of at least one embodiment of a voltage-stabilizing capacitor.

[0153] As shown in FIG23 , the fifth conductive pattern D5 formed on the first source / drain metal layer is electrically connected to the first voltage line portion, and the fifth conductive pattern D5 is electrically connected to the first electrode C1a formed on the semiconductor layer;

[0154] As shown in FIG24 , the first plate of the voltage-stabilizing capacitor is labeled C1a, and the second plate is labeled C1b;

[0155] A sixth conductive pattern D6 formed on the second source-drain metal layer is electrically connected to a seventh conductive pattern D7 formed on the first source-drain metal layer, and the sixth conductive pattern D6 is electrically connected to the second initial voltage line;

[0156] The seventh conductive pattern D7 is electrically connected to the eighth conductive pattern D8 formed in the first gate metal layer, and the eighth conductive pattern D8 is electrically connected to the second electrode plate C1b.

[0157] As shown in FIG. 23 and FIG. 24 , the reference numeral 92 is a first insulating layer, the reference numeral 94 is a second insulating layer, and the reference numeral 97 is a third insulating layer.

[0158] Optionally, the first electrode plate is formed on the third conductive layer, and the second electrode plate is formed on the second conductive layer;

[0159] An orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate.

[0160] In a specific implementation, the first electrode plate may be formed on the third conductive layer, and the second electrode plate may be formed on the second conductive layer.

[0161] FIG. 25 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor.

[0162] As shown in FIG25 , the ninth conductive pattern D9 formed on the first source / drain metal layer is electrically connected to the first electrode plate C1a formed on the second gate metal layer; D9 is electrically connected to the low voltage line;

[0163] A tenth conductive pattern D10 formed on the first source / drain metal layer is electrically connected to an eleventh conductive pattern D11 formed on the first gate metal layer, and the tenth conductive pattern D10 is electrically connected to the second initial voltage line;

[0164] The eleventh conductive pattern D11 is electrically connected to the second electrode plate C1b formed in the first gate metal layer.

[0165] In at least one embodiment of the present disclosure, the first electrode plate includes a first electrode plate portion and a second electrode plate portion;

[0166] The first electrode portion is formed on the sixth conductive layer, the second electrode portion is formed on the second conductive layer, and the second electrode is formed on the third conductive layer;

[0167] The second electrode plate is located between the first electrode plate portion and the second electrode plate portion;

[0168] The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate portion on the substrate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate portion on the substrate.

[0169] Optionally, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer, a sixth conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence in a direction away from the base;

[0170] The first conductive layer may be a semiconductor layer, the second conductive layer may be a first gate metal layer, the third conductive layer may be a second gate metal layer, the sixth conductive layer may be a third gate metal layer, the fourth conductive layer may be a first source-drain metal layer, and the fifth conductive layer may be a second source-drain metal layer.

[0171] In a specific implementation, the first plate of the voltage-stabilizing capacitor may include a first plate portion formed on the third gate metal layer and a second plate portion formed on the first gate metal layer; the second plate of the voltage-stabilizing capacitor may be formed on the second gate metal layer.

[0172] FIG26 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor, FIG27 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor, and FIG28 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor.

[0173] FIG26 is a cross-sectional view of the electrical connection between C1a1 and D12 of at least one embodiment of a voltage-stabilizing capacitor;

[0174] FIG27 is a cross-sectional view of a voltage-stabilizing capacitor formed by C1a1, C1b, and C1a2 of at least one embodiment of a voltage-stabilizing capacitor;

[0175] FIG. 28 is a cross-sectional view of the electrical connection between C1a2 and D13 of at least one embodiment of a voltage-stabilizing capacitor.

[0176] As shown in FIG26 , the first electrode portion C1a1 is electrically connected to a twelfth conductive pattern D12 formed on the first source / drain metal layer, and the twelfth conductive pattern D12 is electrically connected to a low voltage line. As shown in FIG28 , the second electrode portion C1a2 formed on the first gate metal layer is electrically connected to a thirteenth conductive pattern D13 formed on the first source / drain metal layer, and the thirteenth conductive pattern D13 is electrically connected to a low voltage line.

[0177] As shown in FIG27 , the fourteenth conductive pattern D14 formed on the second gate metal layer is electrically connected to the fifteenth conductive pattern D15 formed on the first source / drain metal layer, and the fifteenth conductive pattern D15 is electrically connected to the second initial voltage line;

[0178] In FIG27 , the first electrode portion is labeled C1a1 and is formed in the third gate metal layer. The second electrode portion is labeled C1a2 and is formed in the first gate metal layer. The second electrode portion is labeled C1b and is formed in the second gate metal layer.

[0179] C1b is electrically connected to D14.

[0180] In FIG. 26 and FIG. 27 , reference numeral 90 denotes an insulating layer.

[0181] Optionally, the first electrode plate is formed on the sixth conductive layer, and the second electrode plate is formed on the third conductive layer;

[0182] An orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate.

[0183] In a specific implementation, the first electrode plate may be formed on the third gate metal layer, and the second electrode plate may be formed on the second gate metal layer.

[0184] FIG. 29 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor.

[0185] As shown in FIG29 , the first plate of the voltage-stabilizing capacitor is labeled C1a, and C1a is formed in the third gate metal layer;

[0186] The second plate of the voltage-stabilizing capacitor is labeled C1b, and C1b is formed in the second gate metal layer.

[0187] In FIG. 29 , reference numeral 90 denotes an insulating layer.

[0188] Optionally, the first electrode plate is formed on the sixth conductive layer, and the second electrode plate is formed on the second conductive layer.

[0189] In a specific implementation, the first electrode plate may be formed on the third gate metal layer, and the second electrode plate may be formed on the first gate metal layer.

[0190] FIG. 30 is a cross-sectional view of at least one embodiment of a voltage-stabilizing capacitor.

[0191] As shown in FIG30 , the first plate of the voltage-stabilizing capacitor is labeled C1a, and C1a is formed in the third gate metal layer;

[0192] The second plate of the voltage-stabilizing capacitor is labeled C1b, and C1b is formed in the first gate metal layer.

[0193] In FIG. 29 and FIG. 30 , reference numeral 90 denotes an insulating layer.

[0194] In at least one embodiment of the present disclosure, the semiconductor layer is labeled 91, the first insulating layer is labeled 92, the first gate metal layer is labeled 93, the second insulating layer is labeled 94, the second gate metal layer is labeled 95, the first source-drain metal layer is labeled 96, the third insulating layer is labeled 97, and the second source-drain metal layer is labeled 98.

[0195] As shown in FIG31 , the display area of ​​the display panel is labeled A0. In the lower pad area, a first integrated circuit I1, a first flexible circuit board F1, a second integrated circuit I2, a second flexible circuit board F2, a third integrated circuit I3, a third flexible circuit board F3, a fourth integrated circuit I4, a fourth flexible circuit board F4, a first low-voltage line VS1, a first second initial voltage line VI21, a second low-voltage line VS2, a second second initial voltage line VI22, a third low-voltage line VS3, a third second initial voltage line VI23, and a fourth low-voltage line VS 4. fourth second initial voltage line VI24, fifth low-voltage line VS5, fifth second initial voltage line VI25, sixth low-voltage line VS6, sixth second initial voltage line VI26, seventh low-voltage line VS7, seventh second initial voltage line VI27, eighth low-voltage line VS8, eighth second initial voltage line VI28, first voltage-stabilizing capacitor Cw1, second voltage-stabilizing capacitor Cw2, third voltage-stabilizing capacitor Cw3, fourth voltage-stabilizing capacitor Cw4, fifth voltage-stabilizing capacitor Cw5, sixth voltage-stabilizing capacitor Cw6, seventh voltage-stabilizing capacitor Cw7, and eighth voltage-stabilizing capacitor Cw8;

[0196] F1 is electrically connected to VS1, VI21, VS2 and VI22 respectively; F2 is electrically connected to VS3, VI23, VS4 and VI24 respectively; F3 is electrically connected to VS5, VI25, VS6 and VI26 respectively; F4 is electrically connected to VS7, VI27, VS8 and VI28 respectively;

[0197] Cw1 is electrically connected to VS1 and VI21, respectively, and Cw2 is electrically connected to VS2 and VI22, respectively;

[0198] Cw3 is electrically connected to VS3 and VI23, respectively, and Cw4 is electrically connected to VS2 and VI24, respectively;

[0199] Cw5 is electrically connected to VS5 and VI25, respectively, and Cw6 is electrically connected to VS6 and VI26, respectively;

[0200] Cw7 is electrically connected to VS7 and VI27, respectively, and Cw8 is electrically connected to VS8 and VI28, respectively.

[0201] In at least one embodiment shown in FIG. 31 , the first DC voltage line VSS may be a low voltage line, and the second DC voltage line VI2 may be a second initial voltage line.

[0202] The display substrate of the embodiment of the present disclosure includes a display area; the display substrate includes a base, a first DC voltage line and a second DC voltage line; the first DC voltage line and the second DC voltage line are arranged on the base;

[0203] The first DC voltage line and the second DC voltage line are arranged around the display area;

[0204] The first DC voltage line is formed in the seventh conductive layer, and the second DC voltage line is formed in the eighth conductive layer; a dielectric layer is provided between the seventh conductive layer and the eighth conductive layer;

[0205] An orthographic projection of the first DC voltage line on the substrate at least partially overlaps with an orthographic projection of the second DC voltage line on the substrate.

[0206] Optionally, the seventh conductive layer may be a first source-drain metal layer, and the eighth conductive layer may be a second source-drain metal layer, but the present invention is not limited thereto.

[0207] In a specific implementation, the first DC voltage line and the second DC voltage line can be arranged around the display area, and the orthographic projection of the first DC voltage line on the substrate at least partially overlaps with the orthographic projection of the second DC voltage line on the substrate to form a voltage-stabilizing capacitor.

[0208] As shown in FIG32 , the display area of ​​the display panel is labeled A0. In the lower pad area, a first integrated circuit I1, a first flexible circuit board F1, a second integrated circuit I2, a second flexible circuit board F2, a third integrated circuit I3, a third flexible circuit board F3, a fourth integrated circuit I4, a fourth flexible circuit board F4, a first low-voltage line VS1, a first second initial voltage line VI21, a second low-voltage line VS2, a second second initial voltage line VI22, a third low-voltage line VS3, a third second initial voltage line VI23, a fourth low-voltage line VS4, a fourth second initial voltage line VI24, a fifth low-voltage line VS5, a fifth second initial voltage line VI25, a sixth low-voltage line VS6, a sixth second initial voltage line VI26, a seventh low-voltage line VS7, a seventh second initial voltage line VI27, an eighth low-voltage line VS8, and an eighth second initial voltage line VI28 are provided.

[0209] F1 is electrically connected to VS1, VI21, VS2 and VI22 respectively; F2 is electrically connected to VS3, VI23, VS4 and VI24 respectively; F3 is electrically connected to VS5, VI25, VS6 and VI26 respectively; F4 is electrically connected to VS7, VI27, VS8 and VI28 respectively;

[0210] The first DC voltage line VSS and the second DC voltage line VI2 are arranged around the display area A0. The orthographic projection of the first DC voltage line VSS on the base partially overlaps with the orthographic projection of the second DC voltage line VI2 on the substrate to form a voltage stabilizing capacitor.

[0211] FIG33 is a DD′ cross-sectional view of FIG32 .

[0212] As shown in FIG33 , a dielectric layer J1 is provided between the first DC voltage line VSS and the second DC voltage line VI2 .

[0213] In at least one embodiment shown in FIG. 32 and FIG. 33 , the first DC voltage line VSS may be a low voltage line, and the second DC voltage line VI2 may be a second initial voltage line.

[0214] The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0215] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a substrate, and a first DC voltage line, a second DC voltage line and a voltage stabilizing capacitor arranged on the substrate; an orthographic projection of the first DC voltage line on the substrate and an orthographic projection of the second DC voltage line on the substrate are arranged adjacent to each other; The voltage-stabilizing capacitor comprises a first plate and a second plate; the first plate and the second plate are formed on different conductive layers; The first electrode plate is electrically connected to the first DC voltage line, and the second electrode plate is electrically connected to the second DC voltage line; The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second DC voltage line on the substrate; An orthographic projection of the second electrode plate on the substrate at least partially overlaps with an orthographic projection of the second DC voltage line on the substrate.

2. The display substrate according to claim 1, wherein: The first electrode plate includes a first electrode plate portion and a second electrode plate portion; The first electrode portion is formed on the first conductive layer, the second electrode portion is formed on the second conductive layer, and the second electrode portion is formed on the third conductive layer; The second electrode plate is located between the first electrode plate portion and the second electrode plate portion; The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate portion on the substrate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate portion on the substrate.

3. The display substrate according to claim 2, wherein: The first electrode portion is electrically connected to the first DC voltage line, and the second electrode portion is electrically connected to the first DC voltage line.

4. The display substrate according to claim 3, wherein: The first DC voltage line includes a first voltage line portion and a second voltage line portion electrically connected to each other; The first voltage line portion is formed in the fourth conductive layer, and the second voltage line portion is formed in the fifth conductive layer; The first electrode portion and the second electrode portion are both electrically connected to the first voltage line portion.

5. The display substrate according to claim 4, wherein: The second DC voltage line is formed in the fifth conductive layer; The second electrode plate is electrically connected to the second DC voltage line through a conductive pattern formed on the fourth conductive layer.

6. The display substrate according to claim 5, wherein: The first conductive layer is a semiconductor layer, the second conductive layer is a first gate metal layer, the third conductive layer is a second gate metal layer, the fourth conductive layer is a first source-drain metal layer, and the fifth conductive layer is a second source-drain metal layer; The semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer are arranged in sequence along a direction away from the substrate.

7. The display substrate according to claim 2, wherein: The orthographic projection of the first electrode portion on the substrate at least partially overlaps with the orthographic projection of the first DC voltage line on the substrate; An orthographic projection of the second electrode portion on the substrate at least partially overlaps with an orthographic projection of the first DC voltage line on the substrate.

8. The display substrate according to claim 1, wherein: The first electrode plate is formed on the first conductive layer, and the second electrode plate is formed on the second conductive layer; An orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate.

9. The display substrate according to claim 1, wherein: The first electrode plate is formed on the third conductive layer, and the second electrode plate is formed on the second conductive layer; An orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate.

10. The display substrate according to claim 1, wherein: The first electrode plate includes a first electrode plate portion and a second electrode plate portion; The first electrode portion is formed on the sixth conductive layer, the second electrode portion is formed on the second conductive layer, and the second electrode is formed on the third conductive layer; The second electrode plate is located between the first electrode plate portion and the second electrode plate portion; The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate portion on the substrate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate portion on the substrate.

11. The display substrate according to claim 1, wherein: The first electrode plate is formed on the sixth conductive layer, and the second electrode plate is formed on the third conductive layer; An orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate.

12. The display substrate according to claim 1, wherein: The first electrode plate is formed on the sixth conductive layer, and the second electrode plate is formed on the second conductive layer.

13. The display substrate according to any one of claims 10 to 12, wherein: The sixth conductive layer is a third gate metal layer.

14. The display substrate according to any one of claims 1 to 12, wherein: The capacitance value of the voltage stabilizing capacitor is greater than or equal to 5 μF and less than or equal to 20 μF.

15. A display substrate, comprising a display area, a substrate, a first DC voltage line and a second DC voltage line; the first DC voltage line and the second DC voltage line are arranged on the substrate; The first DC voltage line and the second DC voltage line are arranged around the display area; The first DC voltage line is formed on the seventh conductive layer, and the second DC voltage line is formed on the eighth conductive layer; A dielectric layer is provided between the seventh conductive layer and the eighth conductive layer; An orthographic projection of the first DC voltage line on the substrate at least partially overlaps with an orthographic projection of the second DC voltage line on the substrate.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

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