Regeneration chip for ink cartridge and manufacturing method therefor

Abstract

A regeneration chip for an ink cartridge and a manufacturing method therefor, the regeneration chip comprising: a substrate, a memory and a plurality of regeneration terminals, the substrate having a front surface and a back surface, the memory being provided on the back surface of the substrate, and the plurality of regeneration terminals being arranged on the front surface of the substrate. The plurality of regeneration terminals are arranged into a plurality of rows. The plurality of regeneration terminals comprise a first regeneration terminal, a second regeneration terminal, a third regeneration terminal, a fourth regeneration terminal, a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal and a ninth regeneration terminal. The first regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal. The regeneration chip of such structure can be applied to new imaging devices, thereby achieving reusing.

Description

Regeneration chip for ink cartridge and manufacturing method thereof

[0001] The present invention claims priority to the Chinese prior application with the application date of August 22, 2023, the invention title of “A Regeneration Chip and Its Manufacturing Method” and the application number of 202311063126.9, as well as the Chinese prior application with the application date of August 24, 2023, the invention title of “A Regeneration Chip for Ink Cartridge and Its Manufacturing Method” and the application number of 202311078271.4, and the Chinese prior application with the application date of August 25, 2023, the invention title of “A Regeneration Chip for Ink Cartridge and Its Manufacturing Method” and the application number of 202311089094.X. All contents of the said prior applications are cross-referenced in this application. Technical Field

[0002] The present invention relates to the technical field of printers, and in particular to a regeneration chip for an ink cartridge and a manufacturing method thereof. Background Art

[0003] Currently, ink cartridges are often equipped with a memory chip to enable imaging devices (printers) to promptly identify relevant information about ink cartridges to prevent incorrect cartridge installation and to record the consumption of printed materials in real time to prevent damage to the imaging device. The memory chip stores information about the ink cartridge, such as the printing material capacity, cartridge identification information, and production date, and is therefore expensive to manufacture.

[0004] However, with the continuous development of imaging technology, the size of imaging devices has become increasingly smaller. Correspondingly, the size of ink cartridges, which serve as storage containers for printing materials, has also been limited. Therefore, users need to constantly replace ink cartridges. However, most old ink cartridges are discarded. These discarded ink cartridges contain plastics and chips, most of which are non-biodegradable. Chips, in particular, contain circuits and metals that can cause significant environmental pollution. Moreover, due to their high production cost, discarding old ink cartridges means that users must spend a lot of money to purchase the chips inside new ink cartridges, which undoubtedly leads to excessively high printing costs for users.

[0005] Therefore, prior art has proposed recycling the chips on ink cartridges for reuse, thereby reducing environmental pollution and lowering users' printing costs. Currently, the number of nine-terminal chips, such as those disclosed in Chinese patent CN101712239B, far exceeds the number of five-terminal chips, such as those disclosed in US11535038B1. These five-terminal chips are currently in short supply on the market. Therefore, how to modify and recycle these nine-terminal chips and apply them to new imaging devices (printers) is a major research topic for researchers in this field.

[0006] Summary of the Invention

[0007] The invention provides a chip for an ink cartridge and a manufacturing method thereof, so as to solve the technical problem of recycling and remanufacturing the existing nine-terminal chip for the ink cartridge.

[0008] In order to achieve the first purpose, the present invention discloses a regeneration chip for an ink cartridge, comprising: a substrate, a memory and a plurality of regeneration terminals, the substrate comprising a front side and a back side, the memory being arranged on the back side of the substrate, and the plurality of regeneration terminals being arranged on the front side of the substrate; the plurality of regeneration terminals being arranged in multiple rows, the plurality of regeneration terminals comprising a first regeneration terminal, a second regeneration terminal, a third regeneration terminal, a fourth regeneration terminal, a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal and a ninth regeneration terminal; the first regeneration terminal being electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal.

[0009] Preferably, the regeneration terminals are arranged into a first row and a second row, the first row including a first regeneration terminal, a second regeneration terminal, a third regeneration terminal and a fourth regeneration terminal arranged from left to right; the second row including a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal and a ninth regeneration terminal arranged from left to right.

[0010] Preferably, at least one of the fifth regeneration terminal and the ninth regeneration terminal is electrically connected to the memory.

[0011] Preferably, the fifth regeneration terminal is electrically connected to the memory via a third conductor, and the third conductor is at least partially located on the back side of the substrate.

[0012] Preferably, the ninth regeneration terminal is electrically connected to the memory via a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate.

[0013] Preferably, at least one of the third regeneration terminal, the seventh regeneration terminal and the eighth regeneration terminal is electrically connected to the memory via a fifth conductor, and the fifth conductor is at least partially located on the back side of the substrate.

[0014] Preferably, the fifth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a third conductor, and the third conductor is at least partially located on the back surface of the substrate.

[0015] Preferably, the fifth regeneration terminal is electrically connected to any one of the fifth conductors via a third conductor, and the third conductor is at least partially located on the back side of the substrate.

[0016] Preferably, the ninth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a fourth conductor, and the fourth conductor is at least partially located on the back surface of the substrate.

[0017] Preferably, the ninth regeneration terminal is electrically connected to any one of the fifth conductors via a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate.

[0018] Preferably, the first regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a first conductor, and the first conductor is at least partially located on the front surface of the substrate.

[0019] Preferably, the first regeneration terminal is electrically connected to the fourth regeneration terminal through the second conductor, the fourth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through the first conductor, the first conductor is at least partially located on the front surface of the substrate, and the second conductor is at least partially located on the front surface of the substrate.

[0020] Preferably, the first regeneration terminal is electrically connected to any one of the fifth conductors through the first conductor.

[0021] Preferably, the first regeneration terminal is electrically connected to the fourth regeneration terminal through the second conductor, and the fourth regeneration terminal is electrically connected to any fifth conductor through the first conductor. The first conductor is at least partially located on the front surface of the substrate, and the second conductor is at least partially located on the front surface of the substrate.

[0022] Preferably, the first regeneration terminal is a data terminal, which is configured to contact a corresponding data contact pin among a plurality of imaging device contact pins; the second regeneration terminal is a reset terminal, which is configured to contact a corresponding reset contact pin among a plurality of imaging device contact pins; the fifth regeneration terminal is a clock terminal, which is configured to contact a corresponding clock contact pin among a plurality of imaging device contact pins; the sixth regeneration terminal is a power supply terminal, which is configured to contact a corresponding power supply contact pin among a plurality of imaging device contact pins; and the ninth regeneration terminal is a ground terminal, which is configured to contact a corresponding ground contact pin among a plurality of imaging device contact pins.

[0023] Preferably, the memory includes a data pin, a reset pin, a clock pin, a power pin and a ground pin, the fifth regeneration terminal is electrically connected to the clock pin through a third conductor, and the ninth regeneration terminal is electrically connected to the ground pin through a fourth conductor.

[0024] In order to achieve the second objective, the present invention discloses a method for manufacturing a regeneration chip for an ink cartridge, the manufacturing method comprising the following steps:

[0025] A. Remove the nine-terminal chip from the ink cartridge;

[0026] B. electrically connecting the first terminal to the eighth terminal;

[0027] C. electrically connecting the fifth terminal to a clock pin of the memory;

[0028] D. Electrically connect the ninth terminal to the ground pin of the memory.

[0029] Preferably, the manufacturing method further comprises: before electrically connecting the fifth terminal and the clock pin of the memory, providing an insulating isolation layer on the back side of the substrate, wherein the isolation layer is used to isolate the conductor electrically connected between the fifth terminal and the clock pin from other conductors.

[0030] Preferably, the manufacturing method further comprises: before electrically connecting the ninth terminal and the ground pin of the memory, providing an insulating isolation layer on the back side of the substrate, wherein the isolation layer is used to isolate the conductor electrically connected between the ninth terminal and the ground pin from other conductors.

[0031] Preferably, the manufacturing method further comprises rewriting the program inside the memory.

[0032] Preferably, the manufacturing method according to claim 7 is characterized in that the manufacturing method also includes replacing the memory.

[0033] Preferably, the manufacturing method further comprises welding an insulating layer on the back side of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a front view schematic diagram of a nine-terminal chip in the prior art;

[0035] FIG2 is a schematic diagram of the back side of a nine-terminal chip in the prior art;

[0036] FIG3 is a front view of the regeneration chip according to Example 1 of the present invention;

[0037] FIG4 is a schematic diagram of the back side of the regeneration chip according to Example 1 of the present invention.

[0038] FIG5 is a schematic structural diagram of the combined state of the regeneration chip and the external substrate according to embodiment 2 of the present invention.

[0039] FIG6 is an exploded schematic diagram of the regeneration chip and the external substrate according to Example 2 of the present invention.

[0040] FIG7 is a front view schematic diagram of an external substrate according to embodiment 2 of the present invention.

[0041] FIG8 is a schematic diagram of the back side of the external substrate according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0042] In the following description, many specific details are set forth in conjunction with the embodiments to facilitate a full understanding of the present invention. However, it should be understood that the following embodiments and detailed descriptions are only for illustrative purposes and do not limit the scope of protection of the present invention.

[0043] Existing nine-terminal chips

[0044] Figures 1-2 show an existing nine-terminal chip 10 (part of the circuit and structure are hidden) that is detachably mounted on an ink cartridge. The structure and principle of the nine-terminal chip 10 are basically the same as those of the circuit board disclosed in Chinese patent CN101712239B, and the identical parts are not repeated here.

[0045] As shown in FIG1 , a nine-terminal chip 10 is removable from a chip mounting seat of an ink cartridge. The nine-terminal chip 10 includes a substrate 101, terminals disposed on the substrate 101, and a memory 102. The substrate 101 includes a front surface and a back surface disposed opposite the front surface. A plurality of terminals are disposed on the front surface of the substrate 101, and the memory 102 is disposed on the back surface of the substrate 101. The plurality of terminals disposed on the front surface of the substrate 101 are arranged in two rows. The first row includes four terminals, which can be defined as a first terminal 11, a second terminal 12, a third terminal 13, and a fourth terminal 14 from left to right. The second row includes five terminals, which can be defined as a fifth terminal 15, a sixth terminal 16, a seventh terminal 17, an eighth terminal 18, and a ninth terminal 19 from left to right. The first terminal 11, the second terminal 12, the third terminal 13, the fourth terminal 14, the sixth terminal 16, the seventh terminal 17, and the eighth terminal 18 are defined as low-voltage terminals, while the fifth terminal 15 and the ninth terminal 19 are defined as high-voltage terminals. In other words, the voltage received by the high-voltage terminals from the imaging device is higher than the voltage received by the low-voltage terminals from the imaging device. Preferably, multiple terminals are electrically connected to the memory 102. More preferably, the second terminal 12, the third terminal 13, the sixth terminal 16, the seventh terminal 17, and the eighth terminal 18 are electrically connected to the memory 102 respectively; and the first terminal 11, the fourth terminal 14, the fifth terminal 15, and the ninth terminal 19 are not electrically connected to the memory 102.

[0046] In Figure 2, the second terminal 12, the third terminal 13, the fifth terminal 15, the sixth terminal 16, the seventh terminal 17, the eighth terminal 18 and the ninth terminal 19 respectively have circuits extending to the back side of the substrate 101. For ease of understanding, the circuit on the back side of the substrate 101 can be understood as part of the terminal electrically connected thereto.

[0047] Preferably, as shown in FIG. 1 , the first terminal 11 and the fourth terminal 14 are electrically connected via a first conductor 101 on the substrate 101 ; more preferably, the first conductor 101 is located on the front surface of the substrate 10 .

[0048] Preferably, as shown in Figure 2, the fifth terminal 15 is connected to the second circuit portion 102, the second circuit portion 102 has a conductive function, and at least a portion of the second circuit portion 102 is arranged on a surface of the substrate 101 other than the front surface, for example, at least a portion of the second circuit portion 102 is located on the back surface of the substrate 101 or at least a portion of the second circuit portion 102 is located on the side wall adjacent to the back surface of the substrate 101; more preferably, at least a portion of the second circuit portion 102 is located on the back surface of the substrate 101, wherein neither the fifth terminal 15 nor the second circuit portion 102 forms an electrical connection with the memory 102.

[0049] Preferably, as shown in Figure 2, the ninth terminal 19 is connected to the third circuit part 103, the third circuit part 103 has a conductive function, and at least a portion of the third circuit part 103 is arranged on a surface other than the front surface of the substrate 101, for example, at least a portion of the third circuit part 103 is located on the back surface of the substrate 101 or at least a portion of the third circuit part 103 is located on the side wall adjacent to the back surface of the substrate 101; more preferably, at least a portion of the third circuit part 103 is located on the back surface of the substrate 101; wherein, neither the ninth terminal 19 nor the third circuit part 103 forms an electrical connection with the memory 102.

[0050] Specifically, in the first row, the first terminal 11, the second terminal 12, the third terminal 13, and the fourth terminal 14 correspond to the first detection terminal, the reset terminal, the clock terminal, and the second detection terminal, respectively. In the second row, the fifth terminal 15, the sixth terminal 16, the seventh terminal 17, the eighth terminal 18, and the ninth terminal 19 correspond to the first high-voltage terminal, the power terminal, the ground terminal, the data terminal, and the second high-voltage terminal, respectively. More specifically, the first detection terminal and the second detection terminal are electrically connected via the first circuit portion 101 disposed on the front surface of the substrate 101. Neither the first high-voltage terminal 101 nor the second circuit portion 102 are electrically connected to the memory. Neither the second high-voltage terminal nor the third circuit portion 103 are electrically connected to the memory. The first high-voltage terminal can be connected to a resistor element / sensor element via the second circuit portion 102, and the second high-voltage terminal can be connected to a resistor element / sensor element via the third circuit portion 103.

[0051] Example 1

[0052] The regeneration chip provided by the present invention is suitable for a new imaging device, the structure and working principle of which are basically the same as those of the imaging device disclosed in US Patent No. 11535038B1. That is, the regeneration chip provided by the present invention can be electrically connected to and operate with the coupling mechanism 400 described in the specification of US Patent No. 11535038B1 (refer to Figures 7B-7C of the patent). It can be understood that the regeneration chip provided by the present invention has basically the same function as the circuit board 120 described in US Patent No. 11535038B1.

[0053] The coupling mechanism 400 described in the above-mentioned document (US11535038B1) includes a terminal holding portion and a plurality of contact portion forming components 403 (referred to as contact pins) held by the terminal holding portion 405. The contact pins 403 are conductive and elastic. In this embodiment, each coupling mechanism 400 has five contact pins 403. When the regeneration chip is installed in the new imaging device, the five contact pins 403 are respectively electrically connected to the corresponding terminals on the regeneration chip. The five contact pins 403 include a data contact pin for electrically connecting to the data terminal, a clock contact pin for electrically connecting to the clock terminal, a reset contact pin for electrically connecting to the reset terminal, a power contact pin for electrically connecting to the power terminal, and a ground contact pin for electrically contacting the ground terminal.

[0054] The circuit board 120 described in the aforementioned document (US Pat. No. 11,535,038 B1) includes a substrate 120bd, a plurality of terminals 290, a device 130 (storage device / controller), and wiring (not shown). The circuit board 120 may also include other components. The substrate 120bd has a front surface 120fa and a rear surface 120fb. The plurality of terminals 290 include a data terminal 210, a clock terminal 220, a power terminal 230, a reset terminal 240, and a ground terminal 250. Each of the terminals 210, 220, 230, 240, and 250 is connected to the device 130. Each of the terminals 210, 220, 230, 240, and 250 is electrically coupled to the device 130 via a wiring pattern layer and vias (not shown). The wiring pattern layer is provided on the front surface 120fa and rear surface 120fb of the base member 120bd.

[0055] FIG3 and FIG4 show a simplified structural diagram of the regeneration chip of the present invention (partial circuitry and structure are hidden). As shown in FIG3 and FIG4, an embodiment of the present invention provides a regeneration chip 20, which includes a substrate 101, terminals disposed on the substrate 101, and partial circuitry. The substrate 101 includes a front surface and a back surface opposite the front surface. A plurality of terminals are disposed on the front surface of the substrate 101, and a memory 102 (equivalent to the device 130 in US Patent No. 11535038B1) is disposed on the back surface of the substrate 101. The terminals disposed on the front surface of the substrate 101 are arranged in two rows, wherein the first row, from left to right, comprises a first regeneration terminal 21, a second regeneration terminal 22, a third regeneration terminal 23, and a fourth regeneration terminal 24. The second row, from left to right, comprises a fifth regeneration terminal 25, a sixth regeneration terminal 26, a seventh regeneration terminal 27, an eighth regeneration terminal 28, and a ninth regeneration terminal 29. In FIG4 , the second regeneration terminal 22 , the third regeneration terminal 23 , the fifth regeneration terminal 25 , the eighth regeneration terminal 28 , and the ninth regeneration terminal 29 each have a circuit extending to the back side of the substrate 101 . For ease of understanding, the circuit on the back side of the substrate 101 may be understood as part of the terminal electrically connected thereto.

[0056] The memory includes multiple pins. In this embodiment, the multiple pins include a data pin, a reset pin, a clock pin, a power pin and a ground pin. The first regeneration terminal 21 is electrically connected to the data pin, the fifth regeneration terminal 25 is electrically connected to the clock pin, and the ninth regeneration terminal 29 is electrically connected to the ground pin.

[0057] Specifically, the first regeneration terminal 21 is electrically connected to the data pin via the eighth regeneration terminal 28 , the fifth regeneration terminal is electrically connected to the clock pin via the third conductor, and the ninth regeneration terminal is electrically connected to the ground pin via the fourth conductor.

[0058] In some embodiments, the first regeneration terminal 21 is electrically connected to the eighth regeneration terminal 28 via a first conductor 31. Preferably, the first regeneration terminal 21 and the eighth regeneration terminal 28 are electrically connected via a fourth regeneration terminal 28. More preferably, the first regeneration terminal 21 and the fourth regeneration terminal 24 are electrically connected via a second conductor 32, and the fourth regeneration terminal 24 and the eighth regeneration terminal 28 are electrically connected via a first conductor 31. Specifically, the first conductor 31 and the second conductor 32 are at least partially located on the front surface of the substrate 101.

[0059] In some embodiments, the fifth regeneration terminal 25 is electrically connected to the clock pin via the third conductor 33. In another embodiment, the fifth regeneration terminal 25 is electrically connected to the third regeneration terminal 23 via the third conductor 33, and the third regeneration terminal 23 is electrically connected to the clock pin via the fifth conductor electrically connected thereto. More specifically, the fifth regeneration terminal 25 is electrically connected to the circuit portion of the third regeneration terminal 23 located on the back side of the substrate 20 via the third conductor 33.

[0060] In some embodiments, the ninth regeneration terminal 29 is electrically connected to the ground pin via the fourth conductor 34. In other embodiments, the ninth regeneration terminal 29 is electrically connected to the seventh regeneration terminal 27 via the fourth conductor 34, and the seventh regeneration terminal 27 is electrically connected to the ground pin via a fifth conductor electrically connected thereto. More specifically, the ninth regeneration terminal 29 is electrically connected to the circuit portion of the seventh regeneration terminal 27 located on the back side of the substrate 20 via the fourth conductor 34.

[0061] The specific way of electrically connecting the first regeneration terminal 21 to the data pin, the specific way of electrically connecting the fifth regeneration terminal 25 to the clock pin, and the specific way of electrically connecting the ninth regeneration terminal 29 to the ground pin can be freely combined based on the above specific ways and are not limited here.

[0062] Regarding the specific arrangement of the first conductor 31, in some embodiments, the first conductor 31 is entirely disposed on the front surface of the substrate 101. In other embodiments, one end of the first conductor 31 is disposed on the front surface of the substrate 101 and electrically connected to the first regeneration terminal 21, while the other end of the first conductor 31 extends to the back surface of the substrate 101 and electrically connects to the eighth regeneration terminal 28. The extension can be achieved by extending the first conductor 31 from the front surface of the substrate 101 through a side surface adjacent to the front surface of the substrate 101 to the back surface of the substrate 101. Alternatively, the extension can be achieved by providing a through-hole in the front surface of the substrate 101, with the first conductor 31 extending from the front surface of the substrate 101 through the through-hole to the back surface of the substrate 101 and electrically connecting to the eighth regeneration terminal 28. Specifically, the first conductor can be a wire formed by soldering, or a metal wire disposed on the substrate.

[0063] It is understandable that the arrangement of the second conductor 32 , the third conductor 33 and the fourth conductor 34 may refer to the arrangement of the first conductor 31 .

[0064] Preferably, the first regeneration terminal 21 is configured as a data terminal, which is configured to contact a corresponding data contact pin among a plurality of imaging device contact pins (the imaging device is equivalent to the aforementioned "new imaging device"); the second regeneration terminal 22 is configured as a reset terminal, which is configured to contact a corresponding reset contact pin among a plurality of imaging device contact pins; the fifth regeneration terminal 25 is configured as a clock terminal, which is configured to contact a corresponding clock contact pin among a plurality of imaging device contact pins; the sixth regeneration terminal 26 is configured as a power supply terminal, which is configured to contact a corresponding power supply contact pin among a plurality of imaging device contact pins; the ninth regeneration terminal 29 is configured as a ground terminal, which is configured to contact a corresponding ground contact pin among a plurality of imaging device contact pins.

[0065] The regeneration chip having the above structure has the first regeneration terminal 21, the second regeneration terminal 22, the fifth regeneration terminal 25, the sixth regeneration terminal 26, and the ninth regeneration terminal 29 configured to be electrically connected to a new imaging device (such as the device disclosed in US Patent No. 11535038B1), wherein the first regeneration terminal 21 is configured as a data terminal, the second regeneration terminal 22 is configured as a reset terminal, the fifth regeneration terminal 25 is configured as a clock terminal, the sixth regeneration terminal 26 is configured as a power terminal, and the ninth regeneration terminal 29 is configured as a ground terminal. Thus, the nine-terminal chip can be recycled and used in a new imaging device equipped with the aforementioned coupling mechanism 400.

[0066] In some implementations, a new memory may be replaced according to actual needs. The new memory has at least a data pin, a reset pin, a clock pin, a power pin, and a ground pin.

[0067] Next, a method for manufacturing the regeneration chip 20 will be described with reference to FIG. 1 to FIG. 3 .

[0068] The first method for manufacturing the regeneration chip 20 includes the following steps:

[0069] A. Remove the nine-terminal chip 10 from the ink cartridge; preferably, clean the surface of the nine-terminal chip 10 to remove dirt, such as ink, impurities and other foreign matter;

[0070] B. removing the insulating layer on the back side of the substrate 101 of the nine-terminal chip 10 (e.g., milling it off);

[0071] C. Electrically connecting the first terminal 11 to the eighth terminal 18, and preferably, electrically connecting the fourth terminal 12 to the eighth terminal 18. Since the first terminal 11 and the fourth terminal 14 are electrically connected via the first circuit portion 101, the first terminal 11 and the eighth terminal 18 can also be electrically connected via the first circuit portion 101 and the fourth terminal 14. It is understandable that the first circuit portion 101 can also be directly electrically connected to the eighth terminal 18. Preferably, the electrical connection is made by soldering.

[0072] D. Electrically connecting the fifth terminal 15 to the clock pin of the memory 102. Preferably, the fifth terminal 15 is electrically connected thereto and extends to the second circuit portion 102 on the back of the substrate 101 and is electrically connected to the clock pin. More preferably, an insulating isolation layer 35 (such as the dotted line portion in FIG. 3 ) is provided on the back of the substrate 101, and the conductor electrically connecting the second circuit portion 102 and the clock pin is provided on the isolation layer 35. The isolation layer 35 is used to isolate the conductor electrically connected between the fifth terminal 15 and the clock pin (the third conductor) from other conductors (conductors electrically connected to other terminals). Optionally, the fifth terminal 15 can also be electrically connected to the clock pin of the memory 102 through the third terminal 13. Preferably, the electrical connection is made by soldering or external metal wires.

[0073] E. Electrically connect the ninth terminal 19 to the ground pin of the memory 102. Preferably, the ninth terminal 19 is electrically connected to the ground pin through the third circuit portion 103 electrically connected thereto and extending to the back of the substrate 101. More preferably, an insulating isolation layer 35 (such as the dotted line portion in FIG3 ) is provided on the back of the substrate 101, and the conductor electrically connected to the third circuit portion 103 and the ground pin is provided on the isolation layer 35. The isolation layer is used to isolate the conductor (fourth conductor) electrically connected between the fifth terminal 15 and the ground pin from other conductors (conductors electrically connected to other terminals). Optionally, the ninth terminal 19 is electrically connected to the ground pin of the memory 102 through the seventh terminal 17, and the electrical connection is performed by soldering. More preferably, an insulating isolation layer 35 is provided on the back of the substrate. The isolation layer is used to isolate the conductor electrically connected between the ninth terminal 15 and the ground pin from other conductors. A conductor is provided on the isolation layer 35 to be electrically connected to the ground pin of the memory.

[0074] F. Rewrite the program in the memory 102 according to actual needs;

[0075] G. Solder an insulating layer on the back side of the substrate 101.

[0076] The second method for manufacturing the regeneration chip 20 includes the following steps:

[0077] A. Remove the nine-terminal chip 10 from the ink cartridge; preferably, clean the surface of the nine-terminal chip 10 from dirt, such as ink, impurities and other foreign matter; B. Remove the insulating layer on the back of the substrate 101 of the nine-terminal chip 10 (e.g., by milling it off);

[0078] C. Electrically connecting the first terminal 11 to the eighth terminal 18, and preferably, electrically connecting the fourth terminal 12 to the eighth terminal 18. Since the first terminal 11 and the fourth terminal are electrically connected via the first circuit portion 101, the first terminal 11 and the eighth terminal 18 can also be electrically connected via the first circuit portion 101 and the fourth terminal 14. It is understandable that the first circuit portion 101 can also be directly electrically connected to the eighth terminal 18. Preferably, the electrical connection is made by soldering.

[0079] D. Electrically connecting the fifth terminal 15 to the clock pin of the memory 102. Preferably, the fifth terminal 15 is electrically connected thereto and extends to the second circuit portion 102 on the back of the substrate 101 and is electrically connected to the clock pin. More preferably, an insulating isolation layer 35 (such as the dotted line portion in FIG. 3 ) is provided on the back of the substrate 101, and the conductor electrically connecting the second circuit portion 102 and the clock pin is provided on the isolation layer 35. The isolation layer 35 is used to isolate the conductor electrically connected between the fifth terminal 15 and the clock pin (the third conductor) from other conductors (conductors electrically connected to other terminals). Optionally, the fifth terminal 15 can also be electrically connected to the clock pin of the memory 102 through the third terminal 13. Preferably, the electrical connection is made by soldering or external metal wires.

[0080] E. Electrically connecting the ninth terminal 19 to the ground pin of the memory 102. Preferably, the ninth terminal 19 is electrically connected to the ground pin via the third circuit portion 103 electrically connected thereto and extending to the back side of the substrate 101. More preferably, an insulating isolation layer 35 (such as the dotted line portion in FIG3 ) is provided on the back side of the substrate 101, and the conductor electrically connecting the third circuit portion 103 to the ground pin is provided on the isolation layer 35. The isolation layer is used to isolate the conductor (fourth conductor) electrically connected between the fifth terminal 15 and the ground pin from other conductors (conductors electrically connected to other terminals). Optionally, the ninth terminal 19 is electrically connected to the ground pin of the memory 102 via the seventh terminal 17, and the electrical connection is performed by soldering. More preferably, an insulating isolation layer 35 is provided on the back side of the substrate. The isolation layer is used to isolate the conductor electrically connected between the ninth terminal 19 and the clock pin from other conductors. A conductor is provided on the isolation layer to be electrically connected to the ground pin of the memory.

[0081] F. Replace the memory 102 according to actual needs;

[0082] G. Solder an insulating layer on the back side of the substrate 101.

[0083] This shows that the nine-terminal chip can be recycled and used in new imaging devices.

[0084] It should be noted that, unless there are any contradictions or exclusions, the different embodiments disclosed above can be quoted, referenced or combined with each other, and the technical features / components of different embodiments can also be combined and / or replaced with each other.

[0085] Example 2

[0086] As shown in Figures 5 to 8, the difference between this embodiment and Example 1 is that this embodiment further includes an external substrate 40 and a plurality of contact portions arranged on the external substrate. The external substrate 40 is attached to the regeneration chip 20, and the plurality of pins of the memory are electrically connected to the plurality of contact portions to form components 403 (referred to as contact pins) to achieve electrical connection. That is to say, this embodiment does not need to change the circuit connection relationship on the back of the regeneration chip 20; wherein, the first conductor 31, the third conductor 33 and the fourth conductor 34 are all arranged on the external substrate 40.

[0087] Figure 5 is a structural schematic diagram of the combined state of the regeneration chip and the external substrate in embodiment 2 of the present invention; Figure 6 is an exploded schematic diagram of the regeneration chip and the external substrate in embodiment 2 of the present invention; Figure 7 is a front schematic diagram of the external substrate in embodiment 2 of the present invention; and Figure 8 is a back schematic diagram of the external substrate in embodiment 2 of the present invention.

[0088] Preferably, the external substrate 40 includes a front surface 401 away from the regeneration chip 20 , a back surface 402 close to the regeneration chip and opposite to the front surface 401 , and a side surface 403 located between the front surface 401 and the back surface 402 .

[0089] Preferably, the plurality of contact portions are five in number, including a first contact portion 41, a second contact portion 42, a third contact portion 43, a fourth contact portion 44, and a fifth contact portion 45. Each of the plurality of contact portions is used to electrically connect to the five contact pins 403 of the coupling mechanism 400. Therefore, the arrangement of the plurality of contact portions is preferably corresponding to the positions of the five contact pins 403 of the coupling mechanism 400. More preferably, the plurality of contact portions are all disposed on the front surface 401. In some embodiments, at least a portion of at least one of the plurality of contact portions may be disposed on the back surface 402 and / or the side surface 403.

[0090] Preferably, the first conductor 31 , the third conductor 33 and the fourth conductor 34 are all disposed on the back surface 402 of the external substrate 40 , but may also be disposed on the side surface 403 of the external substrate.

[0091] Preferably, the eighth regeneration terminal 28 is electrically connected to the first contact portion 41 through the first conductor 31; more preferably, the first conductor 31 includes a first conductive portion 311, a first conductive end portion 312 located at one end of the first conductive portion 311, and a second conductive end portion 313 located at the other end of the first conductive portion 311, the first conductive end portion 312 is arranged at a position corresponding to the eighth regeneration terminal 28 on the back side 402, and the second conductive end portion 312 is electrically connected to the first contact portion; optionally, the second conductive end portion 313 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the first contact portion 41.

[0092] Preferably, the third regeneration terminal 23 is electrically connected to the third contact portion 43 through the third conductor 33; more preferably, the third conductor 33 includes a third conductive portion 331, a third conductive end portion 332 located at one end of the third conductive portion 331, and a fourth conductive end portion 333 located at the other end of the third conductive portion 331, the third conductive end portion 332 is arranged at a position corresponding to the third regeneration terminal 23 on the back side 402, and the fourth conductive end portion 333 is electrically connected to the third contact portion 43; optionally, the fourth conductive end portion 333 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the third contact portion 43.

[0093] Preferably, the seventh regeneration terminal 27 is electrically connected to the fifth contact portion 45 through the fourth conductor 34; more preferably, the fourth conductor 34 includes a fourth conductive portion 341, a fifth conductive end portion 342 located at one end of the fourth conductive portion 341, and a sixth conductor end portion 343 located at the other end of the fourth conductive portion 341, the fifth conductive end portion 342 is arranged at a position corresponding to the seventh regeneration terminal 27 on the back side 402, and the sixth conductive end portion 343 is electrically connected to the fifth contact portion 45. Optionally, the sixth conductive end portion 343 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the fifth contact portion 45.

[0094] In this embodiment, an insulating layer is formed on the first conductive portion 311 , the third conductive portion 331 and the fourth conductive portion 341 , thereby preventing the terminal ends on the regeneration chip from being damaged.

[0095] Preferably, a sixth conductor 36 is provided on the back surface 402 of the external substrate 40, and the second contact portion 42 is electrically connected to the second regeneration terminal 22 through the sixth conductor 36. The position of the sixth conductor 36 corresponds to the position of the second regeneration terminal 22. Optionally, the sixth conductor 36 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the second contact portion 42.

[0096] Preferably, a seventh conductor 37 is provided on the back surface 402 of the external substrate 40, and the fourth contact portion 44 is electrically connected to the sixth regeneration terminal 26 through the seventh conductor 37. The position of the seventh conductor 37 corresponds to the position of the sixth regeneration terminal 26. Optionally, the seventh conductor 37 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the fourth contact portion 44.

[0097] Preferably, the external substrate 40 can be connected to the regeneration chip 20 by bonding, welding or engaging with other components. [Beneficial Effects]

[0098] In this embodiment, by pre-arranging the multiple contact portions and wiring (i.e., the first conductor, the third conductor, the fourth conductor, the sixth conductor, and the seventh conductor) on the external substrate 40, there is no need to scrape the insulating layer on the back of the regenerated chip for the regeneration process, thereby simplifying the chip regeneration steps and costs.

[0099] Although the present invention has been described above through embodiments, it should be understood that the above embodiments are only used to exemplify the possible implementation methods of the present invention and should not be interpreted as limiting the scope of protection of the present invention. That is, any substitutions or changes made by those skilled in the art in accordance with the present invention should also be covered by the scope of protection of the claims of the present invention.

Claims

1. A regeneration chip for an ink cartridge, comprising: A substrate, a memory and a plurality of regeneration terminals, wherein the substrate includes a front side and a back side, the memory is arranged on the back side of the substrate, and the plurality of regeneration terminals are arranged on the front side of the substrate; characterized in that: The plurality of regeneration terminals are arranged in a plurality of rows, the plurality of regeneration terminals comprising a first regeneration terminal, a second regeneration terminal, a third regeneration terminal, a fourth regeneration terminal, a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal and a ninth regeneration terminal; The first regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal, or the eighth regeneration terminal.

2. The ink cartridge regeneration chip according to claim 1, wherein: The regeneration terminals are arranged into a first row and a second row, the first row includes a first regeneration terminal, a second regeneration terminal, a third regeneration terminal and a fourth regeneration terminal arranged from left to right; the second row includes a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal and a ninth regeneration terminal arranged from left to right.

3. The ink cartridge regeneration chip according to claim 1, wherein: At least one of the fifth regeneration terminal and the ninth regeneration terminal is electrically connected to the memory.

4. The ink cartridge regeneration chip according to claim 1, wherein: The fifth regeneration terminal is electrically connected to the memory through a third conductor, and the third conductor is at least partially located on the back side of the substrate; the ninth regeneration terminal is electrically connected to the memory through a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate.

5. The ink cartridge regeneration chip according to claim 1, wherein: At least one of the third regeneration terminal, the seventh regeneration terminal and the eighth regeneration terminal is electrically connected to the memory through a fifth conductor, and the fifth conductor is at least partially located on the back side of the substrate.

6. The ink cartridge regeneration chip according to claim 5, wherein: The fifth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a third conductor, and the third conductor is at least partially located on the back side of the substrate; The fifth regeneration terminal is electrically connected to any one of the fifth conductors through a third conductor, and the third conductor is at least partially located on the back side of the substrate.

7. The ink cartridge regeneration chip according to claim 6, wherein: The ninth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate; The ninth regeneration terminal is electrically connected to any one of the fifth conductors through a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate; The first regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a first conductor, and the first conductor is at least partially located on the front surface of the substrate; The first regeneration terminal is electrically connected to the fourth regeneration terminal through the second conductor, the fourth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through the first conductor, the first conductor is at least partially located on the front surface of the substrate, and the second conductor is at least partially located on the front surface of the substrate; The first regeneration terminal is electrically connected to any one of the fifth conductors through the first conductor; The first regeneration terminal is electrically connected to the fourth regeneration terminal through the second conductor, the fourth regeneration terminal is electrically connected to any fifth conductor through the first conductor, the first conductor is at least partially located on the front surface of the substrate, and the second conductor is at least partially located on the front surface of the substrate; The first regeneration terminal is a data terminal configured to contact a corresponding data contact pin of the plurality of imaging device contact pins; The second regeneration terminal is a reset terminal configured to contact a corresponding reset contact pin among the plurality of imaging device contact pins; The fifth regeneration terminal is a clock terminal configured to contact a corresponding clock contact pin of the plurality of imaging device contact pins; The sixth regeneration terminal is a power supply terminal configured to contact a corresponding power supply contact pin of the plurality of imaging device contact pins; The ninth regeneration terminal is a ground terminal configured to contact a corresponding ground contact pin of the plurality of imaging device contact pins; The memory includes a data pin, a reset pin, a clock pin, a power pin and a ground pin. The fifth regeneration terminal is electrically connected to the clock pin through a third conductor, and the ninth regeneration terminal is electrically connected to the ground pin through a fourth conductor.

8. A method for manufacturing a regeneration chip for an ink cartridge, the method comprising the following steps: A. Remove the nine-terminal chip from the ink cartridge; B. electrically connecting the first terminal to the eighth terminal; C. electrically connecting the fifth terminal to a clock pin of the memory; D. Electrically connect the ninth terminal to the ground pin of the memory.

9. The manufacturing method according to claim 8, characterized in that: The manufacturing method further comprises: before electrically connecting the fifth terminal and the clock pin of the memory, providing an insulating isolation layer on the back side of the substrate, the isolation layer being used to isolate the conductor electrically connected between the fifth terminal and the clock pin from other conductors; The manufacturing method further comprises: before electrically connecting the ninth terminal to the ground pin of the memory, providing an insulating isolation layer on the back side of the substrate, the isolation layer being used to isolate the conductor electrically connected between the ninth terminal and the ground pin from other conductors; The manufacturing method further includes rewriting the program inside the memory; The manufacturing method further comprises replacing the memory; The manufacturing method also includes welding an insulating layer on the back side of the substrate.

10. A regeneration chip for an ink cartridge, comprising: A substrate, a memory and a plurality of regeneration terminals, wherein the substrate includes a front side and a back side, the memory is arranged on the back side of the substrate, and the plurality of regeneration terminals are arranged on the front side of the substrate; characterized in that: The regeneration chip further comprises an external substrate and a plurality of contact parts arranged on the external substrate, the external substrate is attached to the substrate, and the memory is electrically connected to a plurality of contact pins on the imaging device by being electrically connected to the plurality of contact parts; The plurality of regeneration terminals are arranged in a plurality of rows, and the plurality of regeneration terminals include a first regeneration terminal, a second regeneration terminal, a third regeneration terminal, a fourth regeneration terminal, a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal, and a ninth regeneration terminal.

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