Amplifier for driving a variable capacitive load

Abstract

It is disclosed a hybrid amplifier (1) for driving a variable capacitive load (5). The hybrid amplifier (1) is configured to operate in a calibration mode in which, for each maximum value of the voltage analog signal in output from the hybrid amplifier (1), the possible values of configuration parameters of the hybrid amplifier (1) are calculated as the value from the capacitance of the capacitive load (5) changes comprised between a minimum value and a maximum value. The hybrid amplifier (1) is further configured to operate in a subsequent configuration / control mode in which use is made of a sequence of values of the configuration parameters precalculated in the calibration mode corresponding to a plurality of different values of the capacitance of the capacitive load (5), for a defined maximum value of the output voltage analog signal.

Description

[0001] AMPLIFIER FOR DRIVING A VARIABLE CAPACITIVE LOAD

[0002] DESCRIPTION

[0003] TECHNICAL FIELD OF THE INVENTION

[0004] The present invention generally relates to the electronics field.

[0005] More in particular, the present invention concerns a parallel hybrid type amplifier for driving a variable capacitive load, such as for example piezoelectric printheads having a plurality of nozzles.

[0006] PRIOR ART

[0007] Several electronic amplification circuits are known for driving a capacitive load, such as for example piezoelectric type printheads.

[0008] A first example of electronic amplification circuit for driving a capacitive load is a linear amplifier (for example in class AB), which allows obtaining a high reproduction fidelity of the desired waveform at the ends of the capacitive load (i.e. reduced signal distortion), but has the disadvantage of dissipating a high power (i.e. it has a low efficiency) and of not recovering the energy stored in the capacitive load when it discharges.

[0009] A second example of electronic amplification circuit for driving a capacitive load is the switching amplifier (commonly indicated with class D), which allows to minimize the dissipated power (i.e. it has a high efficiency), but has the disadvantage that the reproduction fidelity (i.e. high distortion) of the desired waveform at the ends of the capacitive load is reduced, when a high bandwidth and a high dynamic (slew rate) of the desired voltage signal are required at the ends of the capacitive load.

[0010] Hybrid amplifiers for driving resistive loads are known.

[0011] Hybrid amplifiers are a combination of a linear amplifier (for example, in class AB) with a switching amplifier and therefore seek to exploit the advantages provided by the two amplifiers.

[0012] More in particular, the hybrid amplifiers may have a serial or parallel type architecture.

[0013] In the series type hybrid amplifiers a linear amplification stage is connected in cascade with a switching amplification stage: in this case the switching amplification stage continuously changes the power supply of the linear amplification stage so as to decrease the power dissipated by the latter, but it is not possible to recover at least part of the energy stored in the capacitive load when it discharges. In the parallel type hybrid amplifiers the linear amplification stage is connected in parallel to the switching amplification stage: in this case the linear amplification stage controls the voltage on the load thus ensuring a low signal distortion, while the switching amplification stage manages most of the current on the load thus obtaining a low power dissipation (i.e. high efficiency).

[0014] Parallel type hybrid amplifiers are used to drive resistive and resistive-inductive loads, such as for example audio speakers.

[0015] The Applicant has observed that if the known parallel type hybrid amplifiers are used to drive a capacitive load (such as for example piezoelectric printheads), to obtain a low current delivered by the linear amplifier stage in a wide range of values of the capacitive load it is necessary to have a very high switching frequency (for example, at least equal to 10 MHz) of the devices that make up the switching amplification stage, requiring the use of high-performance electronic devices and above all increasing the dissipated power (i.e. decreasing efficiency), at least partially cancelling the advantage of using a parallel hybrid amplifier.

[0016] EP 3744000 describes a parallel type hybrid amplifier for driving a capacitive load.

[0017] The Applicant has observed that the output of the linear amplifier of the hybrid amplifier described in EP 3744000 is disturbed by pulses generated by the switching amplifier: this causes distortion of the signal in output and also causes instability of the overall amplifier.

[0018] Furthermore, the Applicant has observed that the hybrid amplifier described in EP 3744000 is not optimized for input signal waveforms having different amplitude values and for different capacitive load values.

[0019] SUMMARY OF THE INVENTION

[0020] The present invention concerns an amplifier for driving a variable capacitive load as defined in the appended claim 1 and the preferred embodiments thereof described in the dependent claims 2 to 7.

[0021] The Applicant has perceived that the amplifier in accordance with the present invention is able to amplify an input signal with a very high dynamic in order to drive one or more capacitive loads, maintaining a reduced distortion thanks to the presence of a linear amplification stage and maintaining a reduced dissipated power thanks to the presence of a switching amplification stage, without requiring to excessively increase the switching frequency of the switching amplification stage for a wide range of values of the variable capacitive load.

[0022] Furthermore, the amplifier in accordance with the present invention allows to recover a large part of the energy stored in the capacitive load when it discharges, further decreasing the energy consumption and therefore decreasing the consequent dissipative losses.

[0023] Furthermore, the amplifier in accordance with the present invention minimizes (at most eliminates) pulses on the output of the linear amplification stage, thus reducing the distortion of the output signal.

[0024] Furthermore, the amplifier in accordance with the present invention reduces (at most eliminates) the overshoot of the output voltage signal at the angular points, thus reducing the power consumption of the hybrid amplifier.

[0025] Finally, the amplifier in accordance with the present invention improves the print quality, because it generates a signal in output that is optimized for the specific value of the maximum amplitude of the input signal and for different values of the variable capacitive load.

[0026] It is also an object of the present invention a tile printing machine as defined in the appended claim 8.

[0027] It is also an object of the present invention a method for driving a variable capacitive load as defined in the appended claim 9 and the preferred embodiments thereof described in the dependent claims 10 and 11.

[0028] It is also an object of the present invention a non-transitory computer-readable storage medium as defined in the appended claim 12.

[0029] It is also an object of the present invention an computer program comprising software code portions adapted to perform the steps of the method for driving a variable capacitive load, when said program is run on at least one computer.

[0030] BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Further features and advantages of the invention will become more apparent from the description which follows of a preferred embodiment and the variants thereof, provided by way of example with reference to the appended drawings, in which:

[0032] Figure 1 shows a block diagram of a parallel hybrid type amplifier according to the invention;

[0033] Figure 2A shows in more detail a switching amplification stage included in the hybrid amplifier of Figure 1 ; Figure 2B shows in more detail a measurement and control circuit included in the hybrid amplifier of Figure 1 ;

[0034] Figure 3 shows a truth table of a decoder used in the switching amplification stage included in the hybrid amplifier of Figure 1 ;

[0035] Figure 4A schematically shows a possible trend of some voltage signals of the hybrid amplifier of Figure 1 , during a first period of a calibration mode of the hybrid amplifier;

[0036] Figure 4B schematically shows a possible trend of configuration signals of the hybrid amplifier of Figure 1 , during the first period of the calibration mode;

[0037] Figure 5A schematically shows a possible trend of some voltage signals of the hybrid amplifier of Figure 1 , during a second period of the calibration mode of the hybrid amplifier or during a period of a configuration / control mode of the hybrid amplifier;

[0038] Figure 5B schematically shows a possible trend of the configuration signals of the hybrid amplifier of Figure 1 , during the second period of the calibration mode of the hybrid amplifier or during the period of the configuration / control mode of the hybrid amplifier;

[0039] Figure 5C schematically shows a possible trend of the current signals generated in output from the linear amplification stage and from the switching amplification stage included in the amplifier of Figure 1 , during the period of the configuration / control mode of the hybrid amplifier;

[0040] Figures 6A-6C show a flowchart of the method for calculating configuration parameters during a calibration mode of the amplifier of Figure 1 ;

[0041] Figure 7 shows a flowchart of the method for setting the configuration parameters during the configuration / control mode of the amplifier of Figure 1 .

[0042] DETAILED DESCRIPTION OF THE INVENTION

[0043] Note that, in the following description, identical or analogous blocks, components or modules are indicated in the figures with the same numerical references, even if they are shown in different embodiments of the invention.

[0044] With reference to Figure 1 , a parallel hybrid type amplifier 1 according to an embodiment of the invention is shown.

[0045] The amplifier 1 is an electronic circuit having the function of driving one or more capacitive loads, such as for example one or more piezoelectric printheads. For the purposes of explaining the invention, it is assumed for the sake of simplicity that the amplifier 1 is such as to drive a single variable capacitive load 5 (as shown in Figure 1 ) having a capacitance C_o with values comprised between a minimum value C_o-min (for example, equal to 160 picoFarad) and a maximum value C_o-max (for example, equal to 160 nanoFarad); more generally, the amplifier 1 is such as to drive two or more capacitive loads connected to each other in parallel and having an equivalent capacitance equal to C_o having a variable capacitance comprised between a minimum value and a maximum value.

[0046] For example, the capacitive load 5 consists of one or more piezoelectric printheads, each having a number of nozzles equal to for example 1024 or 1536: in this case the equivalent capacitance C_o has values comprised between 160 pF (in case a single nozzle of an inkjet printhead with piezoelectric command is used) and 160 nF (in case 1024 nozzles of the printhead are used).

[0047] The amplifier 1 comprises: an input terminal IIN adapted to receive an input voltage signal v_i; an output terminal Io adapted to generate an output voltage signal v_L to drive the capacitive load 5; a linear type amplification stage 2; a switching type amplification stage 3; a first switch 10-1 ; a measurement and control circuit 8; a second switch 10-2.

[0048] The amplifier 1 is of parallel hybrid type, wherein the linear type amplification stage 2 is connected in parallel to the switching type amplification stage 3, so that the current i_L flowing through the capacitive load 5 is equal to the sum of the current i_lin generated in output from the linear amplification stage 2 and of the current i_sw generated in output from the switching amplification stage 3, i.e. i_L= i_lin+ i_sw.

[0049] The amplifier 1 is such as to operate according to two operating modes:

[0050] - a calibration mode:

[0051] - a configuration / control mode subsequent to the calibration mode.

[0052] The calibration mode can be performed for example at the time of testing at the end of the production step of the machine or device on which the hybrid amplifier 1 is mounted, therefore it is prior to the use of the hybrid amplifier 1 mounted on the machine or device installed at the end user for the application of interest (for example, inside a digital printing machine): in this case the user receives the machine or device in which the amplifier 1 has already been calibrated for the possible waveforms of the analog output signal v_L and for the possible values of the capacitance of the capacitive load 5 for each waveform of the analog output signal v_L, as will be explained in more detail below.

[0053] Alternatively, the calibration mode may be performed directly when the hybrid amplifier 1 is mounted on the machine or device installed at the end user for the application of interest, before the start of normal operation of the machine or device.

[0054] The configuration / control mode is that of normal (i.e. working) operation, in which the hybrid amplifier 1 operates in real time in the application of interest (for example, on an electronic board mounted inside a digital printing machine), using the values of configuration parameters that have been precalculated in the calibration step, as will be explained in more detail below.

[0055] The input terminal IIN of the amplifier 1 is adapted to receive an input voltage signal v_i of periodic type, having in each period AT1 , AT2,... a substantially trapezoidal trend with monotone upward and downward phases that are respectively increasing and decreasing, as shown with the solid line in Figures 4A and 5A.

[0056] With reference to a period AT1 , AT2 of the input voltage analog signal v_i, it consists of four phases (see again Figures 4A and 5A): a first upward phase comprised between the instant ti and the instant ts in which the input voltage signal v_i has a monotone trend increasing from a null value to a maximum input value V_i-max substantially equal to the value of a power supply voltage VCC (for example, equal to 5 Volts); a second high holding phase comprised between the instant ts and the instant tio in which the input voltage signal v_i has a substantially constant trend equal to the maximum input value V_i-max; a third downward phase comprised between the instant tio and the instant tis in which the input voltage signal v_i has a monotone trend decreasing from the maximum input value V_i-max to the null value; a fourth low holding phase comprised between the instant tis and the instant t2o in which the input voltage signal v_i has a substantially constant trend equal to the null value.

[0057] It is therefore possible to identify four respective operating phases of the amplifier 1. Preferably, in the first upward phase comprised between ti and ts the input voltage signal v_i is an upward ramp having a trend linearly increasing from a null value to a maximum input value V_i-max, therefore it will be indicated below with “upward phase”; similarly, in the third downward phase comprised between tio and tis the input voltage signal v_i is a downward ramp having a trend linearly decreasing from the maximum input value V_i-max to the null value, therefore it will be indicated below with “downward phase”.

[0058] For example, the value of the period AT1 is equal to 12 microseconds, the maximum input value V_i-max is equal to 5 Volts, the duration of the first upward phase is equal to 3 microseconds, the duration of the second high holding phase (maximum substantially constant value) is equal to 3 microseconds, the duration of the third downward phase is equal to 3 microseconds, and the duration of the fourth low holding phase (null substantially constant value) is equal to 3 microseconds.

[0059] The input voltage signal v_i therefore has a high dynamic (i.e. it has high variations of its value in short time intervals) and has a high frequency of repetition of the signal itself.

[0060] The output terminal Io of the amplifier 1 is adapted to generate the output voltage signal v_L, it also having a substantially trapezoidal trend with monotone upward and downward phases that are respectively increasing and decreasing (typically a linearly increasing upward ramp and a linearly decreasing downward ramp), as shown with the dotted line in Figure 4A in which the values of the output voltage signal v_L are scaled by a factor equal to the gain G of the hybrid amplifier, for example equal to 27.

[0061] It can be observed that the output voltage signal v_L oscillates between a null value (i.e. the ground reference voltage) and the maximum output value V_L-max (for example, 135 Volts) equal to the maximum input value V_i-max (for example, equal to 5 Volts) multiplied by the gain of the hybrid amplifier.

[0062] Furthermore, in Figures 4A and 5A it can be observed that the output voltage signal v_L is also composed in each period of four phases similarly to the input voltage signal v_i, with the difference that the duration of the four phases is slightly translated with respect to that of the input voltage signal v_i: therefore the output voltage signal v_L tracks the input voltage signal v_i.

[0063] Also note that for the purposes of explaining the invention, only two periods AT1 , AT2 of the input voltage signal v_i have been considered in the figures, but this comprises further periods ATs, AT4,... subsequent to AT2. The linear amplification stage 2 is powered by the power supply voltage VCC and comprises an input terminal adapted to receive the input voltage signal v_i and comprises an output terminal lo in adapted to generate an amplified voltage signal v_lin reproducing the input voltage signal v_i and adapted to generate an output current i_lin.

[0064] The linear amplification stage 2 is active during all four operating steps, but imposes the voltage on the output terminal only when the switch 10-1 is closed, i.e. in the second high holding phase.

[0065] In particular, during the second high holding phase and the fourth low holding phase the linear amplification stage 2 has the function of accurately imposing the value of the desired output voltage v_L at the ends of the capacitive load 5 (i.e. on the output terminal Io of the amplifier 1 ), as will be explained in more detail below.

[0066] Preferably, the linear amplification stage 2 is of class AB type.

[0067] The measurement and control circuit 8 is powered by the power supply voltage VCC and has the function, during the calibration mode, of calculating and storing appropriate values of internal configuration parameters S1 , S2, S3, S4 of the hybrid amplifier 1 , by means of an appropriate iterative algorithm which will be explained in more detail below with reference to the flowchart of Figures 6A-6C.

[0068] In addition, the measurement and control circuit 8 also has the function, during the configuration / control mode, of providing as output the amplification stage 3-5 with the values of the internal configuration parameters S1 , S2, S3, S4 that were calculated in the previous calibration mode, as the possible values of the capacitance of the capacitive load 5 change.

[0069] The measurement and control circuit 8 comprises a first input terminal adapted to receive a plurality of input samples v_i_d representative of the input voltage analog signal v_i, a second input terminal adapted to receive the output voltage analog signal v_L, at least a first output terminal adapted to generate values of the internal configuration parameters S1 , S2, S3, S4 of the hybrid amplifier 1 , a second output terminal adapted to generate a first error signal S_buck_err and a third output terminal adapted to generate a second error signal S_boost_err.

[0070] The operation of the measurement and control circuit 8 will be explained in more detail below with reference to Figure 2B.

[0071] The switching type amplification stage 3 comprises at least one input terminal IIN_SW adapted to receive the first error signal S_buck_err and the second error signal S_boost_err, comprises at least one further input terminal adapted to receive the values of the internal configuration parameters S1 , S2, S3, S4 of the hybrid amplifier 1 , and comprises an output terminal adapted to generate the output voltage signal v_L oscillating between the value of a power supply voltage VCC and the ground reference voltage and adapted to generate an output current i_sw.

[0072] The current i_L flowing in the capacitive load 5 is given by the sum of the current i_lin generated in output from the linear amplification stage 2 and by the current i_sw generated in output from the switching amplification stage 3, i.e. i_L= i_lin+ i_sw.

[0073] The switching amplification stage 3 has the function of managing most of the current on the capacitive load 5 during the first upward phase of the input voltage signal v_i and during the third downward phase of the input voltage signal v_i, thus obtaining a low power dissipation with recovery of the energy previously stored in the capacitive load 5 and therefore a low energy consumption.

[0074] In addition, the use of the switching amplification stage 3 allows a bidirectional current flow through the capacitive load 5, allowing most of the energy stored in the capacitive load 5 to be recovered.

[0075] Note that the switching amplification stage 3 is commanded by the measurement and control circuit 8 with a self-oscillating control in voltage, as will be explained in more detail below.

[0076] More in particular, with reference to Figures 1 and 2A, the switching amplification stage 3 comprises: a switching amplification circuit 3-5; an inductor 3-6 connected in series to the switching amplification circuit 3-5, wherein the inductor 3-6 has a terminal connected to the output of the switching amplification circuit 3-5 and another terminal connected to the output terminal Io of the amplifier 1 .

[0077] Note that the inductor 3-6 and capacitive load 5 together form a low-pass filter.

[0078] The switching amplification circuit 3-5 is powered by the power supply voltage VDC (equal for example to 5 V) and comprises in turn: a first input terminal adapted to receive the first error signal S_buck_err; a second input terminal adapted to receive the second error signal S_boost_err; at least one third input terminal adapted to receive the internal configuration parameters S1 , S2, S3, S4 of the hybrid amplifier 1 ; an output terminal adapted to generate a switching internal analog voltage signal v_sw_i. More in particular, the switching amplification circuit 3-5 comprises: a decoder 3-9; an upper side switch 3-1 having a first terminal connected to the power supply voltage VCC, wherein the upper side switch 3-1 is configured to switch between an open position in which it is electrically equivalent to an open circuit and a closed position in which it is electrically equivalent to a short circuit, as a function of the value of a first internal driving signal S1_drv_i; a lower side switch 3-2 connected in series to ground to the upper side switch 3- 1 , the lower side switch 3-2 having a first terminal connected to a second terminal of the upper side switch 3-1 and a second terminal connected to a ground reference voltage, wherein the lower side switch 3-2 is configured to switch between an open position in which it is electrically equivalent to an open circuit and a closed position in which it is electrically equivalent to a short circuit, as a function of the value of a second internal driving signal S2_drv_i; preferably, a first diode 3-7 and a second diode 3-8 connected in parallel respectively to the switches 3-1 and 3-2; a first enable circuit 3-3 having the function of generating the first internal driving signal S1_drv_i to control the opening / closure of the upper side switch 3-1 , as a function of the value of a first enable signal S_buck_on and of the value of a first error signal S_buck_err; a second enable circuit 3-4 having the function of generating the second internal driving signal S2_drv_i to control the opening / closure of the lower side switch 3-2, as a function of the value of a second enable signal S_boost_on and of the value of a second error signal S_boost_err.

[0079] The upper side switch 3-1 has the function of controlling, when it is closed, the generation of the switching internal voltage signal v_sw_i (and therefore of the output voltage signal v_L) equal to the value of the power supply voltage VCC, whereas the lower side switch 3-2 has the function of controlling, when it is closed, the generation of the switching internal voltage signal v_sw_i (and therefore of the output voltage signal v_L) equal to the value of the ground reference voltage (i.e. null value).

[0080] The switching amplification circuit 3-5 is therefore such as to generate the switching internal voltage analog signal v_sw_i oscillating between the value of the power supply voltage VCC and the ground reference voltage (i.e. the null value), as a function respectively of the closed state of the upper side switch 3-1 and of the closed state of the lower side switch 3-2.

[0081] Therefore the switching amplification stage 3 is such as to impose the output voltage signal v_L equal to the power supply voltage VCC when the upper side switch 3-1 is closed and is such as to impose the output voltage analog signal v_L equal to the ground reference voltage (i.e. 0 Volt) when the lower side switch 3-2 is closed.

[0082] More in particular, the first enable circuit 3-3 is realized with an AND logical gate comprising an output terminal adapted to generate the first internal driving signal S1_drv_ having a high logical value when both the first error signal S_buck_err and the first enable signal S_buck_on have a high logical value, and having a low logical value when at least one between the first error signal S_buck_err and the first enable signal S_buck_on have a low logical value.

[0083] Similarly, the second enable circuit 3-4 is realized with an AND logical gate comprising an output terminal adapted to generate the second internal driving signal S2_drv_i having a high logical value when both the second error signal S_boost_err and the second enable signal S_boost_on have a high logical value, and having a low logical value when at least one between the second error signal S_boost_err and the second enable signal S_boost_on have a low logical value.

[0084] In one embodiment, the switching amplification circuit 3-5 is of the class D type by means of a bridge and the upper side switch 3-1 is made with an n-channel MOSFET transistor having the drain terminal connected to the power supply voltage VCC, the source terminal connected to the output terminal of the switching amplification circuit 3-5 and the gate terminal connected to the output of the first enable circuit 3-3: therefore the source terminal carries the switching internal voltage signal v_sw_i and the gate terminal receives the first internal driving signal S1_drv_i.

[0085] Similarly, the lower side switch 3-2 is realized with an n-channel MOSFET transistor having the source terminal connected to the ground reference voltage, the drain terminal connected to the output terminal of the switching amplification circuit 3-5 and the gate terminal connected to the output of the second enable circuit 3-4: therefore the drain terminal carries the switching internal voltage signal v_sw_i and the gate terminal receives the second internal driving signal S2_drv_i.

[0086] In one embodiment, the switching amplification circuit 3-5 further comprises the first recirculation diode 3-7 connected in parallel to the MOSFET transistor 3-1 and having the cathode terminal connected to the drain terminal of the MOSFET transistor 3-1 (and therefore connected to the power supply voltage VCC) and the anode terminal connected to the source terminal of the MOSFET transistor 3-1 (and therefore connected to the output terminal of the switching amplification circuit 3-5 carrying the switching internal voltage signal v_sw_i).

[0087] Similarly, the switching amplification circuit 3-5 further comprises the second recirculation diode 3-8 connected in parallel to the MOSFET transistor 3-2 and having the cathode terminal connected to the drain terminal of the MOSFET transistor 3-2 (and therefore carrying switching internal voltage signal v_sw_i) and the anode terminal connected to the source terminal of the MOSFET transistor 3-2 (and therefore connected to the ground reference voltage).

[0088] In one embodiment (not shown in the figures), a first protection diode is connected in series to the MOSFET transistor 3-1 and has the function of preventing the switching on of the intrinsic diode of the MOSFET 3-1 ; similarly, a second protection diode is connected in series to the MOSFET transistor 3-2 and has the function of preventing the switching on of the intrinsic diode of the MOSFET 3-2.

[0089] The first switch 10-1 is connected between the output terminal lo in of the linear amplification stage 2 and the output terminal Io of the amplifier 1 and is configured to switch between an open position in which it is electrically equivalent to an open circuit and a closed position in which it is electrically equivalent to a short circuit, as a function of the value of a first switching signal S3.

[0090] The first switch 10-1 has the function of disconnecting the linear amplification stage 2 from the output terminal Io of the hybrid amplifier in the upward and downward phase and has the function of connecting the linear amplification stage 2 to the output terminal Io of the hybrid amplifier in the second high holding phase (i.e. the output terminal lo in of the linear amplification stage 2 is short-circuited with the output terminal Io of the amplifier 1 ), allowing the linear amplification stage 2 to accurately fix the value of the output voltage v_L at the ends of the capacitive load 5 in the second high holding phase.

[0091] The second switch 10-2 is connected in parallel to the capacitive load 5 and is configured to switch between an open position in which it is electrically equivalent to an open circuit and a closed position in which it is electrically equivalent to a short circuit, as a function of the value of a second switching signal S4.

[0092] The second switch 10-2 has the function of short-circuiting the capacitive load 5 in the fourth low holding phase with substantially null trend of the input voltage signal v_i, so as to bring towards null value the possible output voltage v_L that is slightly greater than zero present on the capacitive load 5 at the end of the third downward phase.

[0093] Note that the use of the second switch 10-2 is not essential for the purposes of the invention, as the same function of discharging the capacitive load 5 towards the null value can be obtained by closing the first switch 10-1 and the linear amplification stage 2 which is such as to generate (during the fourth low holding phase) as output the amplified substantially null voltage signal v_lin as will be explained in more detail below.

[0094] The decoder 3-9 is a combinatorial type logical circuit having the function of enabling, at a certain instant of the first upward phase, second high holding phase, third downward phase and fourth high holding phase, no more than one of the outputs as a function of the values of the inputs.

[0095] In particular, the decoder 3-9 comprises four input terminals adapted to receive four respective values of the internal configuration parameters S1 , S2, S3, S4 having a high or low logical value and comprises four output terminals adapted to generate four logical values of configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d of the hybrid amplifier 1.

[0096] Figure 3 shows a truth table 1 of the decoder 3-9 operating both in the calibration mode and in the configuration / control mode.

[0097] In particular, table 1 shows the values of the inputs of the decoder 3-9 which are the internal configuration parameters S1 , S2, S3, S4, shows the values of the outputs of the decoder 3-9 which are the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d of the hybrid amplifier 1 and also shows, for each value of the inputs-outputs, to which phase of the operating period the values of the inputs-outputs correspond.

[0098] It can be observed (see the second, third, fourth and fifth line) that considering in input to the decoder 3-9 a particular set of values of the internal configuration parameters S1 , S2, S3, S4, only one of the four configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d at the output has a high logical value (indicated with “H”) for a determined instant of time and the other three of the configuration signals S_pass, S_buck_on, S_boost_on, S_clamp_d have a low logical value (indicated with “L”) at the same instant of time.

[0099] The use of the decoder 3-9 has the advantage of guaranteeing at the hardware level the closure at a certain instant of no more than one of the switches 3-1 , 3-2, 10-3, 10-4, in particular avoiding closing simultaneously at a certain instant for example the switches 3-1 , 3-2, which would be the cause of failures of the switching amplification stage 3.

[0100] In particular, the decoder 3-9 is configured to generate the following values of the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d for each period of the input voltage analog signal v_i:

[0101] - the configuration parameter S_buck_on has a high logical value (third line) for at least part of the first upward phase of the input voltage analog signal v_i and has a low logical value in the second high holding phase, third downward phase and fourth low holding phase of the input voltage analog signal v_i;

[0102] - the configuration parameter S_pass has a high logical value (second line) for at least part of the second high holding phase of the input voltage analog signal v_i and has a low logical value in the first upward phase, third downward phase and fourth low holding phase of the input voltage analog signal v_i;

[0103] - the configuration parameter S_boost_on (fourth line) has a high logical value for at least part of the third downward phase of the input voltage analog signal v_i and has a low logical value in the first upward phase, second high holding phase and fourth low holding phase of the input voltage analog signal v_i; the configuration parameter S_clamp_d has a high logical value for at least part of the fourth low holding phase of the input voltage analog signal v_i and has a low logical value in the first upward phase, second high holding phase and third downward phase of the input voltage analog signal v_i.

[0104] It can also be observed in Table 1 (see the first line) that the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d all have low logical values when the internal configuration parameter S4 has a high logical value, regardless of the value of the internal configuration parameters S1 , S2, S3, therefore the internal configuration parameter S4 has the function of enabling the operation of the decoder 3- 9.

[0105] Finally, it can be observed in Table 1 (see the last line) that the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d all have low logical values even when the internal configuration parameters S1 , S3, S3, S4 have a particular value different from the values of the others illustrated above, in particular when the internal configuration parameter S1 has a low logical value, the internal configuration parameter S2 has a high logical value, the internal configuration parameter S3 has a low logical value and the internal configuration parameter S4 has a high logical value: this allows to temporarily disable the operation of the hybrid amplifier 1 in the switching instants (indicated below with “dead times”) between several successive steps of the operating period.

[0106] Note that the decoder 3-9 has been shown inside the switching amplification circuit 3-5, but more generally the decoder 3-9 can be positioned also outside the switching amplification circuit 3-5, i.e. inside the amplifier 1.

[0107] With reference to Figure 2B, a block diagram of the measurement and control circuit 8 is shown in more detail, which comprises an analog chain formed by the series connection of a compensation circuit 8-6, an error measurement circuit 8-1 , a delayer 8- 2 and a control unit 8-3.

[0108] Furthermore, the measurement and control circuit 8 comprises a non-volatile memory 8-4 configured to store a data structure (for example, an array of numerical values) containing the values of the internal configuration parameters S1 , S2, S3, S4 of the hybrid amplifier 1 as possible values of the capacitance of the capacitive load 5 change for each maximum input value V_i-max of the input voltage analog signal v_i, as will be explained in more detail below.

[0109] In one embodiment, said data structure is a look-up table 8-4.1 .

[0110] The compensation circuit 8-6 comprises an input terminal adapted to receive the output voltage analog signal v_L at the ends of the capacitive load 5 and comprises an output terminal adapted to generate a feedback signal v_L_dl, which is obtained by attenuating and conditioning (for example, anticipating) the output voltage analog signal v_L.

[0111] The compensation circuit 8-6 therefore has the function, during the calibration mode, of compensating for delays in the command chain of the hybrid amplifier 1 , improving the tracking of the input voltage analog signal v_i by the output voltage analog signal v_L.

[0112] The error measurement circuit 8-1 comprises a first input terminal adapted to receive the feedback signal v_L_dl, comprises a second input terminal adapted to receive the input voltage analog signal v_i and comprises an output terminal adapted to generate an error signal S_err generated by means of the difference between corresponding time values of the input voltage analog signal v_i and of the output voltage analog signal v_L. The error measurement circuit 8-1 therefore has the function, during the calibration mode, of amplifying the error signal S_err.

[0113] The delayer 8-2 comprises an input terminal adapted to receive the error signal S_err and comprises an output terminal adapted to generate a delayed error signal S_err_dl.

[0114] Therefore the delayer 8-2 has the function of delaying the error signal S_err, so as to limit the switching frequency of the switches 3-1 , 3-2 in the event that the capacitive load 5 has very low values, i.e. limiting the self-oscillation band of the switching amplification stage 3.

[0115] The delayer 8-2 is therefore configured to generate the delayed error signal S_err_dl obtained by means of an appropriate time delay of the error signal S_err.

[0116] The delayer 8-2 is made, for example, with an RC circuit.

[0117] The control unit 8-3 comprises a first input terminal adapted to receive the delayed error signal S_err_dl, a second input terminal adapted to receive the output voltage analog signal v_L, a third input terminal adapted to receive a plurality of samples v_i_d representative of the input voltage analog signal v_i, a fourth input terminal adapted to receive data read from the non-volatile memory 8-4, at least a first output terminal adapted to generate the values of the internal configuration parameters S1 , S2, S3, S4 of the hybrid amplifier 1 , a second output terminal adapted to generate the first error signal S_buck_err and a third output terminal adapted to generate the second error signal S_boost_err.

[0118] Note that the control unit 8-3 has been shown inside the measurement and control circuit 8, but more generally the control unit 8-3 can be positioned also outside the measurement and control circuit 8, i.e. inside the amplifier 1 .

[0119] The control unit 8-3 has the function of generating, during the calibration mode, appropriate values of the first error signal S_buck_err and of the second error signal S_boost_err, as will be explained in more detail below.

[0120] In addition, the control unit 8-3 has the function of generating, during the configuration / control mode, appropriate values of the internal configuration parameters S1 , S2, S3, S4 and appropriate values of the first and second error signal S_buck_err, S_boost_err, as will be explained in more detail below.

[0121] In particular, the control unit 8-3 comprises a comparator 8-3.1 , an analog / digital converter 8-3.2 and a processing unit 8-3.3 connected with the analog / digital converter 8-3.2. The comparator 8-3.1 has the function, during the calibration mode and during the configuration / control mode, of comparing the delayed error signal S_err_dl with respect to a defined threshold value, using for example a hysteresis, generating as output the first error signal S_buck_err and the second error signal S_boost_err.

[0122] The analog / digital converter 8-3.2 has the function, during the calibration mode, of sampling and digitizing the output voltage analog signal v_L, while the analog / digital converter 8-3.2 is inactive during the configuration / control mode.

[0123] The analog / digital converter 8-3.2 is therefore configured, during the calibration mode, to receive the output voltage analog signal v_L and to perform an analog / digital conversion of the output voltage analog signal v_L, generating a plurality of output digital samples v_L_d representative of the output voltage analog signal v_L.

[0124] The processing unit 8-3.3 has the function, during the calibration mode, of calculating with an appropriate iterative algorithm a plurality of appropriate values of the internal configuration parameters S1 , S2, S3, S4 of the hybrid amplifier 1 as the value of the capacitance of the capacitive load 5 changes for each possible maximum output value V_L-max of the output voltage analog signal v_L, as will be explained in more detail below with reference to the flowcharts of Figures 6A-6C.

[0125] Furthermore, the processing unit 8-3.3 has the function, during the configuration / control mode, of providing as output a sequence of appropriate precalculated values (during the calibration step) of the internal configuration parameters S1 , S2, S3, S4 as the value of the capacitance of the capacitive load 5 changes during operation of the hybrid amplifier 1 , for a determined maximum output value V_L-max of the output voltage analog signal v_L, as will be explained in more detail below with reference to the flowcharts of Figure 7.

[0126] The processing unit 8-3.3 is for example a microcontroller or a microprocessor or a digital signal processor (abbreviated as DSP) or a programmable integrated circuit (for example, a Field Programmable Gate Array, abbreviated as FPGA), or a combination thereof.

[0127] For the purposes of explaining the invention, it is considered below that the processing unit 8-3.3 is made with a microcontroller 8-3.5 having a volatile memory 8- 3.6 and an FPGA 8-3.4, wherein:

[0128] - during the calibration mode, the microcontroller 8-3.5 is such as to calculate with an appropriate iterative algorithm a plurality of appropriate values of the internal configuration parameters S1 , S2, S3, S4 of the hybrid amplifier 1 as the value of the capacitance of the capacitive load 5 changes for each possible maximum output value V_L-max of the output voltage analog signal v_L, wherein said values of the internal configuration parameters S1 , S2, S3, S4 are stored in the non-volatile memory 8.4, therefore FPGA 8-3.4 is such as to iteratively generate the calculated values of said plurality of values of the internal configuration parameters S1 , S2, S3, S4; during the configuration / control mode, the microcontroller 8-3.5 calculates an estimate of the capacitance of the variable capacitive load 5 and FPGA 8-3.4 is such as to provide as output the sequence of the precalculated values (during the calibration step) of the internal configuration parameters S1 , S2, S3, S4 as the value of the capacitance of the capacitive load 5 changes during operation of the hybrid amplifier 1 , for a determined maximum output value V_L-max of the output voltage analog signal v_L.

[0129] In addition, the volatile memory 8-3.6 has the function of storing a plurality of input digital samples v_i_d representative of the input voltage analog signal v_i_d and the function of storing, during the configuration / control mode, the values of the internal configuration parameters S1 , S2, S3, S4 that have been previously calculated in the calibration mode.

[0130] Note that the use of a hardware-separated decoder 3-9 is not essential, i.e. it is possible to obtain the same values of the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d by means of an appropriate software-level control by the control unit 8-3, in particular by means of the processing unit 8-3.3.

[0131] For example, it is possible to appropriately program FPGA 8-3.4 so as to directly generate the values of the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d having the values shown in Table 1 , i.e. ensuring that at a determined instant of time of the configuration / control mode no more than one of the switches 3-1 , 3-2, 10-3, 10-4 is closed: in this case, therefore, the internal configuration parameters S1 , S2, S3, S4 are not generated, i.e. the measurement and control circuit 8 is such as to generate as output the values of the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d, which are received from the switches 3-1 , 3-2 of the switching amplification stage 3-5 and from the switches 10-1 and 10-2.

[0132] With reference to Figures 6A-6C, a flowchart 100 of a method for calculating configuration parameters performed during the calibration mode is shown. Note that the calculated configuration parameters can be the values of the internal configuration parameters S1 , S2, S3 in case of realization of the control unit 8-3 with microcontroller and FPGA, or they can be the values of the configuration parameters S_pass, S_buck_on, S_boost_on in case of realization of the control unit 8- 3 with a microprocessor or with an FPGA.

[0133] The method for calculating configuration parameters is carried out by means of an appropriate program run on the processing unit 8-3.3 (in particular, on the microcontroller 8-3.5), wherein said program can be run during the production step of the machine or device on which the amplifier 1 is mounted (for example, at the time of testing at the end of the production step) or can be run directly on the machine or device (on which the amplifier 1 is mounted) installed at the end user for the application of interest, before the start of normal operation of the machine or device.

[0134] The flowchart 100 starts with step 101 .

[0135] Step 101 is followed by step 102 in which a plurality of input digital samples v_i_d representative of an input voltage signal v_i is selected, comprising a first upward phase with monotone trend increasing from a substantially null value to a maximum value of input voltage v_i-max, a second high holding phase with substantially constant trend equal to the maximum value of input voltage v_i-max and a third downward phase with monotone trend decreasing from the maximum value of input voltage v_i-max to a minimum value less than the maximum value v_i-max.

[0136] Step 102 is followed by step 103 in which the plurality of the input digital samples v_i_d is stored into a volatile memory 8-3.6.

[0137] For example, the non-volatile memory 8-3.6 is positioned inside the control unit 8-3, in particular inside the processing unit 8-3.3.

[0138] Step 103 is followed by step 104 in which, as a function of the plurality of input digital samples v_i_d, an input voltage analog signal v_i is generated, comprising the first upward phase, the second high holding phase and the third downward phase.

[0139] In particular, the input voltage analog signal v_i is generated by means of a digital-to-analog converter (DAC) receiving as input the input digital samples v_i_d.

[0140] Step 104 is followed by step 105 in which initial values of configuration parameters of the hybrid amplifier 1 are set.

[0141] Step 105 is followed by step 106 in which the hybrid amplifier 1 is driven with the input voltage analog signal v_i and an output voltage analog signal v_L is generated therefrom, comprising the first upward phase with monotone trend increasing from a substantially null value to a maximum value of output voltage v_L-max equal to the maximum value of input voltage v_i-max multiplied by a gain of the hybrid amplifier, a second high holding phase with substantially constant trend equal to the maximum value of output voltage v_L-max and a third downward phase with monotone trend decreasing from the maximum value of output voltage v_L-max to a minimum value less than the maximum value v_L-max.

[0142] Step 106 is followed by step 107 in which the amplified output voltage analog signal v_L is sampled and a plurality of output digital samples v_L_d of the amplified output voltage analog signal v_L are generated therefrom.

[0143] Step 107 is followed by step 108 in which, in the time interval of the second high holding phase, at least a part of the plurality of stored input digital samples v_i_d and at least a part of the output digital samples v_L_d are selected.

[0144] Step 108 is followed by step 109 in which, in corresponding instants of the time interval of the second high holding phase, the at least one selected part of the plurality of stored input digital samples v_i_d is compared with respect to the at least one selected part of the output digital samples v_L_d as a function of a defined comparison criterion.

[0145] Step 109 is followed by step 110 in which, as a function of said comparison, a value of an error or a value of a cost function is calculated using, for example, a distance-weighted method.

[0146] Step 110 is followed by step 111 in which it is verified whether a stop criterion associated with the calculated value of the error or the calculated value of the cost function is met: in the affirmative case (i.e. the stop criterion of the error or cost function is met), step 111 is followed by 112; in the negative case (i.e. the stop criterion of the error or cost function is not met), step 111 is followed by step 113.

[0147] In step 112 the values of the configuration parameters of the hybrid amplifier are modified and from step 112 a return to step 106 is made, therefore the cycle composed of steps 106, 107, 108, 109, 110 and 111 restarts and the cycle is performed until a value of the configuration parameters of the hybrid amplifier such as to meet the stop criterion associated with the error or the cost function is found.

[0148] In step 113, the current values of the configuration parameters of the hybrid amplifier corresponding to the maximum current value v_i-max of the input voltage analog signal v_i and to the current value of the capacitance of the capacitive load are stored in the non-volatile memory 8-4.

[0149] Step 113 is followed by step 114 in which it is verified whether a plurality of possible values of the capacitive load 5 comprised between a minimum value and a maximum value has been analysed: in the positive case (i.e. the whole plurality of possible values of the capacitive load 5 has been analysed), step 114 is followed by step 116; in the negative case (i.e. the whole plurality of possible values of the capacitive load 5 has not been analysed), step 114 is followed by step 115.

[0150] In step 115 the value of the capacitive load is modified and from step 115 a return to step 105 is made, therefore the cycle composed of steps 105, 106, 107, 108, 109, 110, 111 , 113, 115 restarts and the cycle is performed until all the possible values of the capacitive load 5 comprised between the minimum value and the maximum value have been analysed.

[0151] In step 116 it is verified whether the whole plurality of maximum input values V_i- max of the input voltage analog signal v_i has been analysed: in the positive case (i.e. the whole plurality of maximum input values V_i-max of the input voltage analog signal v_i has been analysed), step 116 is followed by step 120 in which the flowchart 100 ends; in the negative case (i.e. the whole plurality of maximum input values V_i-max of the input voltage analog signal v_i has not been analysed), step 116 is followed by step 117.

[0152] In step 117 the maximum input value V_i-max of the input voltage analog signal v_i is modified and from step 117 a return to step 102 is made, therefore the cycle composed of steps 102, 103, 104, 105, 106, 107, 108, 109, 110, 111 , 113, 114, 116 restarts and the cycle is performed until all the maximum input values V_i-max of the input voltage analog signal v_i have been analysed.

[0153] Therefore, at the end of the calibration mode a plurality of N vectors corresponding to the plurality N of the possible maximum input values V_i-max of the input voltage analog signal v_i (for example, comprised between 20 Volts and 140 Volts in steps of 2.5 Volts) have been stored in the non-volatile memory 8-4 (for example, in a matrix), wherein each vector (corresponding to a line of the matrix) comprises the calculated values of the configuration parameters of the hybrid amplifier 1 (i.e. the values of the internal configuration parameters S1 , S2, S3, S4 or the values of the configuration parameters S_buck_on, S_boost_on, S_pass) as the possible M values (M integer) of the capacitance of the capacitive load 5 comprised between a minimum value C_o_min (for example equal to 160 picofarad) and a maximum value C_o_max (for example equal to 160 nanofarad) change.

[0154] With reference to Figure 7, there is shown a flowchart 150 of a method for setting configuration parameters performed during the configuration / control mode of the amplifier 1 , i.e. when it operates in real time in the application of interest (e.g. on an electronic board mounted inside a digital printing machine).

[0155] The method for setting the configuration parameters is carried out by means of an appropriate program run on the processing unit 8-3.3, wherein said program is run directly on the machine or device (on which the amplifier 1 is mounted) installed at the end user for the application of interest, partly before the start of normal operation of the machine or device and partly during normal operation of the machine or device.

[0156] The set configuration parameters can be the values of the internal configuration parameters S1 , S2, S3 in case of realization of the control unit 8-3 with microcontroller and FPGA, or they can be the values of the configuration parameters S_pass, S_buck_on, S_boost_on in case of realization of the control unit 8-3 with a microprocessor or with an FPGA.

[0157] In particular, the set of steps 152, 153, 154, 155, 156 is performed during a period AT (e.g., period AT2 shown in Fig.5A-5B) of the input voltage periodic analog signal v_i.

[0158] The flowchart 150 starts with step 151 .

[0159] Step 151 is followed by step 152 in which a waveform representative of an input voltage analog signal v_i is configured in real time, comprising a first upward phase with monotone trend increasing from a substantially null value to a maximum value of input voltage V_i-max, a second high holding phase with substantially constant trend equal to the maximum value of input voltage V_i-max and a third downward phase with monotone trend decreasing from the maximum value of input voltage V_i-max to a minimum value less than the maximum value V_i-max.

[0160] Step 152, is followed by step 153, in which a plurality of different values of configuration parameters of a hybrid amplifier 1 corresponding to respective different values of the capacitance of a capacitive load of the hybrid amplifier 1 are read from a non-volatile memory 8-4, wherein said plurality of read values of the configuration parameters is associated with a maximum input value V_i-max of the input voltage analog signal v_i and wherein said plurality of read values of the configuration parameters has been previously calculated in the calibration mode.

[0161] For example, in step 153 a line of a matrix is read, wherein said line is a vector containing the values of the configuration parameters as the values of the capacitance of the capacitive load change, for a determined maximum input value V_i-max of the input voltage analog signal V_i.

[0162] Step 153 is followed by step 154 in which it is verified whether there is a synchronism signal indicative of an operation to be performed, such as for example printing a line of an image: in the affirmative case (i.e. the synchronism signal is present), step 154 is followed by step 155; in the negative case (i.e. the synchronism signal is not present), step 154 is followed by step 160 in which the flowchart 150 ends.

[0163] In step 155 the current value of the capacitance of the capacitive load 5 is determined.

[0164] Step 155 is followed by step 156 in which a read value of the configuration parameters corresponding to the determined value of the capacitance of the variable capacitive load is set (for the hybrid amplifier 1 ).

[0165] Step 156 is followed by step 157 in which the hybrid amplifier 1 is driven with the input voltage analog signal v_i which has been received in step 152.

[0166] From step 157 a return to step 154 is made and the cycle composed of steps 154, 155, 156, 157 restarts for a subsequent period AT of the input voltage signal v_i.

[0167] With reference to Figure 5C, a possible trend of the current signal i_lin generated in output from the linear amplification stage 2 is shown with a solid line and a possible trend of the current signal i_sw generated in output from the switching amplification stage 3, during a period AT2 of the configuration / control step is shown with a dotted line.

[0168] It can be observed that during the first upward phase (corresponding to the upward ramp of the input voltage signal v_i) and during the third downward phase (corresponding to the downward ramp of the input voltage signal v_i) the value of the current i_lin generated in output from the linear amplification stage 2 has small values close to the null value, whereas instead the value of the current i_sw generated in output from the switching amplification stage 3 has high values: therefore during the first upward phase and third downward phase the operation of the switching amplification stage 3 is enabled at least in part, while the linear amplification stage 2 delivers a current i_lin limited to a small value close to zero due to the injection of current by the switching amplification stage 3.

[0169] It can also be observed that during the second high holding phase (corresponding to the maximum constant value V_i-max of the input voltage signal v_i) the value of the current i_lin generated in output from the linear amplification stage 2 has non-negligible values greater than zero, whereas instead the value of the current i_sw generated in output from the switching amplification stage 3 has smaller values: therefore during the second high holding phase the linear amplification stage 2 accurately imposes the voltage on its output terminal lojin (and therefore accurately imposes the voltage on the output terminal Io of the amplifier 1 , as the first switch 10-1 is closed), while the operation of the switching amplification stage 3 is substantially disabled.

[0170] Finally, it can be observed that during the fourth low holding phase (corresponding to the constant null value of the input voltage signal v_i) the value of the current i_lin generated in output from the linear amplification stage 2 is null and also the value of the current i_sw generated in output from the switching amplification stage 3 has small values: therefore during the fourth low holding phase the linear amplification stage 2 imposes a null value on the terminal of the capacitive load 5, while the operation of the switching amplification stage 3 is substantially disabled.

[0171] The operation of the amplifier 1 in the calibration mode during a first period AT1 comprised between ti=3 ps and t2o= 15 ps and a second period AT2 (subsequent to the first period) comprised between t2o=15 ps and t4o= 24 ps will now be described, also referring to Figures 1 , 2A-B, 3, 4A-4B, 5 and 6A-6C.

[0172] It is further assumed that the hybrid amplifier 1 is used for a tile printing machine with capacitive load 5 consisting of one or more piezoelectric printheads, each having 1024 nozzles.

[0173] For the purposes of explaining the invention, an input voltage analog signal v_i comprising two periods AT1 and AT2 is considered, each having a trapezoidal trend with linearly increasing ramp in the first upward phase, linearly decreasing ramp in the third downward phase and maximum input value V_i-max in the second high holding phase.

[0174] It is also assumed that the capacitance of the piezoelectric printheads 5 has a defined initial value C_o1 . Finally, it is assumed that in the first period AT1 the internal configuration parameters S1 , S2, S3, S4 have predefined initial values such as to generate (based on the truth table of Fig.3) the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d having the trends shown in Figure 4B, namely:

[0175] S_buck_on has a high logical value having a duration AT1_r= 2.98 ps between the instant ti= 3 ps and the instant t4= ti +2.98 ps= 5.98 ps of the first upward phase comprised between ti= 3 ps and ts= 6 ps, has a low logical value in the remaining part of the first upward phase comprised between t2= 5.98 ps and ts= 6 ps, and has a low logical value in the remaining part of the first period AT1 comprised between ts= 6 ps and t20= 15 ps;

[0176] S_pass has a high logical value in the second high holding phase comprised between ts= 6 ps and tio= 9 ps and has a low logical value in the remaining part of the first period AT 1 ;

[0177] S_boost_on has a high logical value in the third downward phase comprised between tio= 9 ps and tis= 12 ps and has a low logical value in the remaining part of the first period AT 1 ;

[0178] S_clamp_d has a high logical value in the fourth low holding phase comprised between tis= 12 ps and t2o= 15 ps and has a low logical value in the remaining part of the first period AT1 .

[0179] The initial values of the internal configuration parameters S1 , S2, S3, S4 are stored into the volatile memory 8-3.6 and are read by the microcontroller 8-3.5.

[0180] During the first upward phase of the first period AT1 comprised between ti= 3 ps and ts= 6 ps, the analog chain composed of the compensation circuit 8-6, error measurement circuit 8-1 , delayer 8-2 and comparator 8-3.1 operates: said analog chain receives as input the input voltage analog signal v_i and the output voltage analog signal v_L, thus generating the feedback signal v_L_dl in output from the compensation circuit 8-6, the error signal S_err in output from the error measurement circuit 8-1 as a function of the difference between the output voltage analog signal v_L and the input voltage analog signal v_i, the delayed error signal S_err_dl in output from the delayer 8- 2, the first error signal S_buck_err in output from the comparator 8-3.1 and the second error signal S_boost_err in output from the comparator 8-3.1 , wherein Figure 4A shows the trends of the input voltage analog signal v_i, output voltage analog signal v_L, feedback signal v_L_, error signal S_err, delayed error signal S_err_dl and first error signal S_buck_err. It can be observed in Fig. 4A that during the first upward phase the error signal S_err and the delayed error signal S_err_dl have a trend oscillating between a minimum value and a maximum value, in which the difference between them has a fairly high value and a rather low oscillation frequency; consequently, the first error signal S_buck_err also has a trend oscillating between a low logical value (for example, 0 Volt) and a high logical value (for example, 5 Volt), with a rather low oscillation frequency.

[0181] Furthermore, during the first upward phase of the first period AT1 comprised between ti= 3 ps and ts= 6 ps, the analog / digital converter 8-3.2 also operates, which receives as input the output voltage analog signal v_L and generates therefrom a first plurality of output digital samples v_L_d representative of the output voltage analog signal v_L during the first upward phase.

[0182] The processing unit 8-3.3 receives as input said first plurality of output digital samples v_L_d, reads from the volatile memory 8-3.6 a plurality of input digital samples v_i_d representative of the input voltage analog signal v_i_d during the first upward phase, then FPGA 8-3.4 reads from the volatile memory 8-3.6 the initial values of the internal configuration parameters S1 , S2, S3, S4 during the first upward phase and generates as output said initial values of the internal configuration parameters S1 , S2, S3, S4 during the first upward phase.

[0183] The decoder 3-9 receives as input the initial values of the internal configuration parameters S1 , S2, S3, S4 during the first upward phase and generates as output the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d having in the first upward phase the trends shown in Figure 4B, that is, S_buck_on has a high logical value between the instant ti= 3 ps and the instant t4= ti+2.98 ps= 5.98 ps and a low logical value between the instant t4= 5.98 ps and the instant ts= 6 ps, while S_boost_on, S_pass, S_clamp_d have low logical values, wherein: the switch 10-1 is open because the value of the configuration parameter S_pass has a low logical value; the switch 10-2 is open because the value of the configuration parameter S_clamp_d has a low logical value, therefore the output terminal Io of the amplifier 1 is connected to the ground reference through the piezoelectric printheads 5; the first enable circuit 3-3 receives on a first input the configuration parameter S_buck_on having a high logical value with a duration AT1_r= 2.98 ps and a low logical value for a duration equal to 0.02 ps, and receives on a second input the first error signal S_buck_err generated by the analog chain, therefore the first enable circuit 3-3 generates as output the first internal driving signal S1_drv_i having a value equal to the first error signal S_buck_err, i.e. with a trend oscillating between a low logical value and a high logical value, with a rather low oscillation frequency; the second enable circuit 3-4 receives on a first input the configuration parameter S_boost_on having a low logical value disabling the second enable circuit 3-4, therefore the second error signal S_boost_err is ignored and the switch 3-2 is open.

[0184] During the first upward phase the linear amplification stage 2 receives the input voltage analog signal v_i and the first switch 10-1 is open, therefore the linear amplification stage 2 does not affect the driving of the output terminal of the hybrid amplifier 1 .

[0185] Otherwise, during the first upward phase the switching stage 3-5 imposes the voltage on the output terminal of the hybrid amplifier 1.

[0186] In fact, the first internal driving signal S1_drv_i oscillates between a high logical value in which the upper side switch 3-1 is closed (and therefore the switching amplification stage 3 imposes the output voltage signal v_L with trend increasing towards the value of the power supply voltage VCC) and a low logical value in which the upper side switch 3-1 is opened (and therefore the switching amplification stage 3 imposes the output voltage signal v_L with trend decreasing towards the value of the ground reference voltage by switching on the recirculation diode 3-8) as shown in Fig.4A, thus carrying out the self-oscillating control of the switching amplification stage 3.

[0187] During the second high holding phase of the first period AT1 comprised between ts= 6 ps and tio= 9 ps, the analog chain composed of the compensation circuit 8-6, error measurement circuit 8-1 , delayer 8-2 and comparator 8-3.1 continues to operate, which receives as input the input voltage analog signal v_i and the output voltage analog signal v_L, thus generating the feedback signal v_L_dl, the error signal S_err, the delayed error signal S_err_dl and the first error signal S_buck_err, which have the trend shown in Figure 4A.

[0188] Furthermore, during the second high holding phase of the first period AT1 comprised between ts= 6 ps and tio= 8 ps, also the analog / digital converter 8-3.2 continues to operate, which receives as input the output voltage analog signal v_L and generates therefrom a second plurality of output digital samples v_L_d representative of the output voltage analog signal v_L during the second high holding phase. The processing unit 8-3.3 receives as input said second plurality of output digital samples v_L_d, reads from the volatile memory 8-3.6 a plurality of digital samples v_i_d representative of the input voltage analog signal v_i_d during the second high holding phase, then FPGA 8-3.4 reads from the volatile memory 8-3.6 the initial values of the internal configuration parameters S1 , S2, S3, S4 during the second high holding phase and generates as output said initial values of the internal configuration parameters S1 , S2, S3, S4 during the second high holding phase.

[0189] The decoder 3-9 receives as input said initial values of the internal configuration parameters S1 , S2, S3, S4 during the second high holding phase and generates as output the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d having in the second high holding phase the trends shown in Figure 4B, i.e. S_pass_on has a high logical value, while S_buck, S_boost_on, S_clamp_d have low logical values, wherein: the switch 10-1 is closed because the configuration parameter S_pass has a high logical value; the switch 10-2 is open because the configuration parameter S_clamp_d has a low logical value; the first enable circuit 3-3 and the second enable circuit are disabled, as the configuration parameters S_buck and S_boost_on have low logical values, therefore the switches 3-1 and 3-2 are open.

[0190] Therefore during the second high holding phase the switching stage 3-5 does not affect the driving of the output terminal of the hybrid amplifier 1 .

[0191] Otherwise, during the second high holding phase the linear amplification stage 2 receives the input voltage analog signal v_i, the switch 10-1 is closed and then the linear amplification stage 2 imposes the voltage on the output terminal of the hybrid amplifier 1 and holds it at the desired value.

[0192] Furthermore, during the second high holding phase, the software program run on the microcontroller 8-3.5 executes the steps 107, 108, 109, 110, 111 of the flowchart 100 of Fig.6B and it is found that the stop criterion of the delayed error signal S_err_dl is not met and therefore a new iteration will be executed in the next period AT2 comprised between the instants t2o and t4o.

[0193] During the third downward phase of the first period AT1 comprised between tio= 9 ps and tis= 12 ps, the operation is analogous to that of the first upward phase, with the difference that the decoder 3-9 generates the configuration parameter S_boost_on having a high logical value (instead of S_buck_on) and then the second error signal S_boost_err (instead of the first error signal S_buck_err) is taken into consideration, therefore the closure and opening of the lower side switch 3-2 is controlled and the upper side switch 3-1 is opened.

[0194] Consequently, the second internal driving signal S2_drv_i oscillates between a high logical value in which the lower side switch 3-2 is closed (and therefore the switching amplification stage imposes the output voltage signal v_L with trend decreasing towards the value of the ground reference voltage) and a low logical value in which the lower side switch 3-2 is opened (and therefore the switching amplification stage 3 imposes the output voltage signal v_L with trend increasing towards the value of the power supply voltage VCC by switching on the recirculation diode 3-7), thus carrying out the self-oscillating control of the switching amplification stage 3 and recovering the energy previously stored in the piezoelectric printheads 5, while the value of the output current i_lin of the linear amplification stage 2 is minimal.

[0195] During the fourth low holding phase of the first period AT1 comprised between ti5= 12 ps and t2o= 15 ps, FPGA 8-3.4 reads from the volatile memory 8-3.6 the initial values of the internal configuration parameters S1 , S2, S3, S4 during the fourth low holding phase and generates as output said initial values of the internal configuration parameters S1 , S2, S3, S4 during the fourth low holding phase.

[0196] The decoder 3-9 receives as input said initial values of the internal configuration parameters S1 , S2, S3, S4 during the fourth low holding phase and generates as output the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d having in the fourth low holding phase the trends shown in Figure 4B, i.e. S_clamp_d has a high logical value, while S_buck, S_boost_on, S_pass have low logical values, wherein: the switch 10-2 is closed because the configuration parameter S_clamp_d has a high logical value; the switch 10-1 is open because the configuration parameter S_pass has a low logical value; the first enable circuit 3-3 and the second enable circuit are disabled, as the configuration parameters S_buck and S_boost_on have low logical values, therefore the switches 3-1 and 3-2 are open and the operation of the switching amplification stage 3 is disabled. Therefore, during the fourth low holding phase, the output terminal Io of the amplifier 1 is directly connected to the ground reference voltage and the piezoelectric printheads 5 are short-circuited and discharge any residual charge.

[0197] Alternatively, the second switch 10-2 is not present and in the fourth low holding phase it is possible to obtain the complete discharge of the piezoelectric printheads 5 by means of the linear amplification stage 2 and the closure of the switch 10-1 , i.e. the output terminal lojin of the linear amplification stage 2 is short-circuited with the output terminal Io of the amplifier 1 : the linear amplification stage 2 generates as output the amplified voltage signal v_lin having null value and absorbs the current i_lin necessary to completely discharge the piezoelectric printheads 5, then the linear amplification stage 2 sets the null value of the output voltage v_L at the ends of the piezoelectric printheads 5.

[0198] It can be observed that the output voltage analog signal v_L during the first period AT1 has an overshoot around the first angular point positioned between the end of the first upward phase and the beginning of the second high holding phase, wherein said overshoot is caused by an excessive duration of the high logical value of the configuration parameter S_buck_on; therefore if the initial values of the configuration parameters were used during the configuration / control mode, said overshoot would cause an increase in the power consumption of the hybrid amplifier.

[0199] Similar considerations can be made for the second angular point positioned between the end of the second high holding phase and the beginning of the third downward phase.

[0200] As indicated above during the second high holding phase it was found (by means of the software program run on the processing unit 8-3.3, in particular on the microcontroller 8-3.5) that the initial values of the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d are such as not to satisfy the stop criterion of step 111 of the cycle composed of steps 105, 106, 107, 108, 109, 110, 111 of the flowchart 100, therefore the software program executes step 112 in which the values of the internal configuration parameters S1 , S2, S3, S4 are modified and said modified values are stored into the volatile memory 8-3.6.

[0201] In particular, the value of the internal configuration parameter S1 is modified so that the high logical value of the configuration parameter S_buck_on inside the first upward phase has a duration AT2_r shorter than the duration AT1_r of the high logical value inside the first upward phase of the first period AT1 : for example, the case is considered in which the configuration parameter S_buck_on in the first upward phase of the second period AT2 has a duration AT2_r= 2.6 ps, as shown in Figure 5A.

[0202] The operation of the hybrid amplifier 1 during the second period AT2 is analogous to that described above for the first period AT1 , with the difference that the configuration parameter S_buck_on is generated having in the first upward phase (comprised between the instants t2o= 15 ps and t25= 18 ps) a high logical value for a duration AT2_r= 2.6 ps between the instants t2o= 15 ps and t2i= 17.6 ps and having a low logical value for a duration equal to 0.4 ps between the instant t2i and the instant t25= 18 pS.

[0203] Consequently, it can be observed in Figure 5A that during the first upward phase the error signal S_err and the delayed error signal S_err_dl have a trend oscillating between a minimum value and a maximum value, in which the difference between them has a fairly small value; consequently, the first error signal S_buck_err also has a trend oscillating between a low logical value (for example, 0 Volt) and a high logical value (for example, 5 Volt).

[0204] It can also be observed in Figure 5A that the overshoot around the first angular point positioned between the end of the first upward phase and the beginning of the second high holding phase (instant t2s) is greatly reduced (at most eliminated), as the duration of the high logical value of the configuration parameter S_buck_on has been reduced.

[0205] It is assumed that for the sake of simplicity at the end of the second period AT2 the software program run on the processing unit 8-3.3 (in particular on the microcontroller 8-3.5) detects that the modified values of the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d are such as to satisfy the stop criterion of step 111 of the cycle composed of steps 105, 106, 107, 108, 109, 110, 111.

[0206] Therefore, at the end of the second period AT2, the optimal values of the internal configuration parameters S1 , S2, S3, S4 of the amplifier 1 corresponding to a particular waveform of the output voltage analog signal v_L used in the first and second period and to a particular value C_o1 of the capacitance of the piezoelectric printheads 5 were calculated: said optimal values of the internal configuration parameters S1 , S2, S3, S4 are stored (step 113 of the flowchart 100) in the non-volatile memory 8-4, in order to be able to be used (if necessary) in the subsequent configuration / control step.

[0207] More generally, the operation of the hybrid amplifier 1 proceeds in the calibration step with a third, fourth, fifth period, etc., until it calculates the optimal values of the internal configuration parameters S1 , S2, S3, S4 which are such as to generate values of the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d which reduce (at most eliminate) the occurrence of an overshoot of the output voltage analog signal v_L around the first angular point and / or second angular point.

[0208] The operation of the hybrid amplifier 1 in the calibration step proceeds similarly to what is indicated above for the first and second period (and any further periods), changing the value of the capacitance of the piezoelectric printheads 5 (step 115 of the flowchart 100) from the minimum value C_o-min (for example, equal to 160 picoFarad) to the maximum value C_o-max (for example, equal to 160 nanoFarad), until all the values of the capacitance of the piezoelectric printheads 5 have been analysed and the corresponding optimal values of the internal configuration parameters S1 , S2, S3, S4 have been found: said optimal values of the internal configuration parameters S1 , S2, S3, S4 are then stored in the non-volatile memory 8-4, in particular in a line of a matrix.

[0209] The operation of the hybrid amplifier 1 in the calibration step proceeds further by changing the maximum output value V_L-max of the output voltage analog signal v_L, and the operation (for each maximum output value V_L-max) is analogous to that illustrated above, until all the maximum output values V_L-max have been analysed: at the end in the non-volatile memory 8-4 a plurality of lines equal to the number of possible maximum input values V_i-max are stored, each line containing the values of the internal configuration parameters S1 , S2, S3, S4 as the values of the capacitance of the piezoelectric printheads 5 corresponding to the maximum input value V_i-max of the selected line change.

[0210] It should also be noted that for the sake of simplicity in the second operating period of the calibration mode a modification only of the configuration parameter S_buck_on, in particular a reduction of its duration during the first upward phase has been considered.

[0211] More generally, it is possible to modify (in step 112) one or more values of the internal configuration parameters S1 , S2, S3, S4 (and therefore modify one or more of the configuration parameters S_pass, S_buck_on, S_boost_on, S_clamp_d), i.e. changing the duration of the latter so as to be able to meet the stop criterion in step 111 of the flowchart 100.

[0212] For example, it is possible to modify the values of the internal configuration parameters S1 , S2, S3, S4 so as to reduce both the duration of the configuration parameter S_buck_on during the first upward phase, and the duration of the configuration parameter S_boost_on during the third downward phase.

[0213] The operation of the amplifier 1 during the configuration / control mode will now be described, with reference also to Figures 1 , 2A-B, 3, 5A-5B and 7.

[0214] It is further assumed that the hybrid amplifier 1 is used for a tile printing machine with capacitive load 5 consisting of one or more piezoelectric printheads, each having 1024 nozzles.

[0215] When printing a drawing on the tile it is necessary to activate (for each print line) a different number of nozzles of the printheads 5, therefore the value of the capacitance of the printheads 5 changes while printing the pattern; the maximum input value V_i- max of the input voltage analog signal v_i is instead set based on user requirements (and therefore the maximum output value V_L-max of the output voltage analog signal v_L-max is set).

[0216] It is therefore necessary to select (for each print line) the set of the internal configuration parameters S1 , S2, S3, S4 that are optimal for each value of the capacitance of the printheads 5, wherein the values of the internal configuration parameters S1 , S2, S3, S4 were calculated in the previous calibration mode.

[0217] Therefore the microcontroller 8-3.5 reads, from the non-volatile memory 8-4, a line of the matrix (i.e. a vector) corresponding to the particular maximum input value V_i-max (step 153 of the flowchart 150) and said configuration vector is stored into the volatile memory 8-3.6.

[0218] The hybrid amplifier 1 receives the input voltage analog signal v_i having a trend comprising the first upward phase, the second high holding phase, the third downward phase and the fourth low holding phase, as shown in Fig.5A.

[0219] During the first upward phase of the period AT2 comprised between t2o= 15 ps and t25= 18 ps, the analog chain composed of the compensation circuit 8-6, error measurement circuit 8-1 , delayer 8-2 and comparator 8-3.1 operates: said analog chain receives as input the input voltage analog signal v_i and the output voltage analog signal v_L, thus generating the feedback signal v_L_dl in output from the compensation circuit 8-6, the error signal S_err in output from the error measurement circuit 8-1 as a function of the difference between the output voltage analog signal v_L and the input voltage analog signal v_i, the delayed error signal S_err_dl in output from the delayer 8- 2, the first error signal S_buck_err in output from the comparator 8-3.1 and the second error signal S_boost_err in output from the comparator 8-3.1 , wherein Figure 5A shows the trends in the first upward phase of the input voltage analog signal v_i, output voltage analog signal v_L, feedback signal v_L, error signal S_err, delayed error signal S_err_dl and first error signal S_buck_err.

[0220] The microcontroller 8-3.5 receives a synchronism signal having a value indicative of the beginning of printing a new line of the drawing (step 154 and transition from step 154 to step 155 of the flowchart 150).

[0221] Subsequently, the microcontroller 8-3.5 reads from the volatile memory 8-3.6 the values of the digital samples representative of the input voltage analog signal v_i and performs an estimate of the capacitance of the piezoelectric printheads 5 (step 155 of the flowchart 150): FPGA 8-3.4 reads, in the configuration vector stored into the volatile memory 8-3.6, the value of the internal configuration parameters S1 , S2, S3, S4 during the first upward phase corresponding to the estimated value of the capacitance of the piezoelectric printheads 5 in the first upward phase and then the value of the configuration parameters S_buck_on, S_boost_on, S_pass, S_clamp_d is set for the hybrid amplifier 1 by means of the decoder 3-9 (step 156 of the flowchart 150), which is then driven in the first upward phase with the input voltage analog signal v_i (step 157 of the flowchart 150).

[0222] In particular, the operation of the hybrid amplifier 1 in the first upward phase of the configuration / control mode in the period AT2 comprised between t2o= 15 ps and t25= 18 ps is similar in part to that of the first upward phase of the calibration mode, i.e. the configuration parameter S_buck_on has a high logical value for a duration AT2_r= 2.6 ps between the instants t2o= 15 ps and t2i= 17.6 ps and has a low logical value for a duration equal to 0.4 ps between the instant t21 and the instant t25= 18 ps, while the configuration parameters S_boost_on, S_pass, S_clamp_d have low logical values.

[0223] Therefore, during the first upward phase of the configuration / control mode, the linear amplification stage 2 does not affect the driving of the output terminal of the hybrid amplifier 1 , while the switching stage 3-5 imposes the voltage on the output terminal of the hybrid amplifier 1 by means of the first internal driving signal S1_drv_i oscillating between a high logical value in which the upper side switch 3-1 is closed (and therefore the switching amplification stage 3 imposes the output voltage signal v_L equal to the power supply voltage VCC by means of the closed upper side switch 3-1 , the inductor 3-6 and the piezoelectric head 5 which is charged with energy) and a low logical value in which the upper side switch 3-1 is opened (and therefore the switching amplification stage 3 imposes the output voltage signal v_L equal to the ground reference voltage by switching on the recirculation diode 3-8, the inductor 3-6 and the piezo head 5), while the lower side switch 3-2 is open.

[0224] The operation of the hybrid amplifier 1 in the second high holding phase of the configuration / control mode in the period AT2 comprised between t25= 18 ps and tso= 21 ps is analogous to that described above for the second high holding phase of the calibration mode, with the difference that FPGA 8-3.4 reads, in the configuration vector stored into the volatile memory 8-3.6, the value of the internal configuration parameters S1 , S2, S3, S4 during the second high holding phase corresponding to the current estimated value of the capacitance of the piezoelectric printheads 5 and therefore the value of the configuration parameters S_buck_on, S_boost_on, S_pass, S_clamp_d is set for the hybrid amplifier 1 by means of the decoder 3-9 (step 156 of the flowchart 150), which is then driven in the second high holding phase with the input voltage analog signal v_i (step 157 of the flowchart 150).

[0225] Therefore, during the second high holding phase, the linear amplification stage 2 imposes the voltage on the output terminal of the hybrid amplifier 1 and holds it at the desired value, while the switching stage 3-5 does not affect the driving of the output terminal of the hybrid amplifier 1 .

[0226] The operation of the hybrid amplifier 1 in the third downward phase of the configuration / control mode is similar in part to the third downward phase of the configuration mode and is analogous to that of the first upward phase of the configuration / control mode, with the difference that the configuration parameter S_boost_on has a high logical value (instead of S_buck_on) and therefore the second error signal S_boost_err (instead of the first error signal S_buck_err) is taken into consideration and the upper side switch 3-1 is opened; the second internal driving signal S2_drv_i oscillates between a high logical value in which the lower side switch 3- 2 is closed (and therefore the switching amplification stage imposes the output voltage signal v_L equal to the ground reference voltage) and a low logical value in which the lower side switch 3-2 is opened (and therefore the switching amplification stage 3 imposes the output voltage v_L equal to the power supply voltage VCC).

[0227] The operation of the amplifier 1 in the fourth low holding phase is analogous to that of the fourth low holding phase of the calibration mode in the second period AT2.

[0228] Therefore, a first cycle was performed in which a first line of the drawing was printed on the tile by means of the printheads 5. Figure 5A shows the trends of the signals of the hybrid amplifier 1 during the above-illustrated first cycle of the configuration / control mode.

[0229] It can be observed that the overshoot around the first angular point positioned between the end of the first upward phase and the beginning of the second high holding phase (instant t2s) is greatly reduced (at most eliminated), as the duration of the high logical value of the configuration parameter S_buck_on has been reduced.

[0230] Subsequently, the microcontroller 8-3.5 receives a new synchronism signal having a value indicative of the beginning of printing a new line of the drawing (step 154 and transition from step 154 to step 155 of the flowchart 150) and the software program run on the microcontroller 8-3.5 executes again the cycle composed of steps 155, 156, 157 of the flowchart 150.

[0231] In particular, the microcontroller 8-3.5 performs a new estimate of the capacitance of the piezoelectric printheads 5 (step 155 of the flowchart 150): FPGA 8- 3.4 reads, in the configuration vector stored into the volatile memory 8-3.6, the new value of the internal configuration parameters S1 , S2, S3, S4 corresponding to the estimated value of the capacitance of the piezoelectric printheads 5 and then the value of the configuration parameters S_buck_on, S_boost_on, S_pass, S_clamp_d is set for the hybrid amplifier 1 by means of the decoder 3-9 (step 156 of the flowchart 150), which is then driven with the input voltage analog signal v_i (step 157 of the flowchart 150).

[0232] A second cycle (not shown in the figures) is therefore carried out in which a second line of the drawing is printed on the tile by means of the printheads.

[0233] The operation of the hybrid amplifier 1 continues until all lines of the drawing of the tile have been printed.

[0234] In one embodiment, there are dead times between the switching instants between one step and the next one of the operating period in which the hybrid amplifier 1 is temporarily disabled, that is, neither the linear amplification stage 2 nor the switching amplification stage 3 operates, allowing the transient phenomena to run out: in this case the values of the configuration parameters S_buck_on, S_boost_on, S_pass, S_clamp_d have logical values (for example low) such as to open the upper side switch 3-1 , the switch 3-2, the first switch 10-1 and the second switch 10-2 (see the last line of Table 1 ). In particular, there is a dead time in switching between the first upward phase and the second high holding phase and between the second high holding phase and the third downward phase.

[0235] The use of dead times has the advantage of avoiding the simultaneous switching on / off of two elements between the upper side switch 3-1 , the switch, the first switch 10- 1 and the second switch 10-2, thus reducing the risk of overshoot of the output voltage analog signal v_L.

Claims

CLAIMS1. Parallel hybrid amplifier (1 ) for driving a variable capacitive load (5), the amplifier comprising: an input terminal (IIN) adapted to receive an input voltage analog signal (v_i) of periodic type, each period comprising a first phase (ti, ts) with monotone trend increasing from a substantially null value to a maximum input value (V_i-max), a second phase (t5, t10) with substantially constant trend equal to the maximum input value (V_i- max) and a third phase (t10, t15) with monotone trend decreasing from the maximum input value (V_i-max) to a minimum value less than the maximum input value; an output terminal (Io) adapted to generate an output voltage analog signal (v_L) to drive the variable capacitive load; a linear amplification stage (2) comprising an input terminal (IIN) adapted to receive the input voltage signal (v_i) and comprising an output terminal (lojin) adapted to generate an amplified voltage signal (v_lin); a switching amplification stage (3) comprising an output terminal connected to the output terminal (Io) of the amplifier, at least one input terminal (IIN_SW) adapted to receive a first and a second error signal (S_buck_err, S_boost_err), the switching amplification stage being configured to switch between a switched off mode and a switched on mode as a function of the value of a first configuration parameter (S_buck_on, S1 ), of a second configuration parameter (S_boost_on, S2) and of the first and second error signal (S_buck_err, S_boost_err); a switch (10-1 ) connected between the output terminal (lo in) of the linear amplification stage (2) and the output terminal (Io) of the amplifier, the switch being configured to switch between a closed position and an open position as a function of the value of a third configuration parameter (S_pass, S3); a measurement and control circuit (8) comprising a first input terminal adapted to receive the input voltage signal (v_i), a second input terminal adapted to receive the output voltage signal (v_L), at least one output terminal adapted to generate the first and second error signal (S_buck_err, S_boost_err) and at least one further output terminal adapted to generate the first and the second configuration parameter (S_buck_on, S_boost_on; S1 , S2); a non-volatile memory (8-4) configured to store a data structure comprising a plurality of vectors corresponding to a respective plurality of different maximum input values (V_i-max) of the input voltage analog signal (v_i), wherein each vector comprisesa plurality of values of the first, second and third configuration parameters as a plurality of values of the capacitive load change, wherein the measurement and control circuit (8) comprises:• an analog / digital converter (8-3.2) configured to receive as input the output voltage analog signal (v_L) and to generate therefrom as output an output voltage digital signal (v_L_d);• a processing unit (8-3.3) connected to the output of the analog / digital converter and connected to the non-volatile memory (8-4); wherein the measurement and control circuit (8) is configured, during an amplifier calibration mode and during an amplifier configuration / control mode subsequent to the calibration mode, to receive the input voltage analog signal (v_i) and the output voltage analog signal (v_L) and to generate, as a function of the comparison between the input voltage analog signal (v_i) and the output voltage analog signal (v_L), the first and the second error signal (S_buck_err, S_boost_err), wherein the processing unit (8-3.3) is configured, during the calibration mode, to:■ receive initial values of the first, second and third configuration parameters;■ receive a plurality of input digital samples (v_i_d) representative of the input voltage analog signal (v_i) having a first maximum input value (V_i-max) during a period;■ receive a plurality of output digital samples (v_L_d) representative of the output voltage digital signal (v_L) during the period;■ generate, as a function of at least a part of the plurality of input digital samples (v_i_d) and at least a part of the output digital samples (v_L_d), a plurality of vectors corresponding to a plurality of maximum input values (V_i-max) of the input voltage analog signal (v_i), wherein each vector comprises calculated values of the first, second and third configuration parameters of the hybrid amplifier as a plurality of values of the capacitance of the capacitive load change;■ store, in the non-volatile memory (8-4), said plurality of vectors of the configuration parameters; wherein the processing unit is configured, during the configuration / control mode, to:■ receive a plurality of digital samples (v_i_d) representative of the input voltage analog signal (v_i) having a configured maximum input value (V_i-max) during a period;■ receive a vector of the plurality of values of the first, second, third configurationparameters of said data structure corresponding to said configured maximum input value (V_i-max) of the input voltage analog signal (v_i);■ receive (154) a synchronism signal representative of an operation to be performed;■ perform (155) an estimation of the value of the capacitance of the capacitive load;■ read, in said vector, the values of the first, second and third configuration parameters corresponding to the estimated value of the capacitance of the capacitive load;■ set (156) the read value of the first configuration parameter (S_buck_on) to drive the switching amplification stage during at least part of the first upward phase of the period;■ set (156) the read value of the second configuration parameter (S_buck_on) to drive the switching amplification stage during at least part of the third downward phase;■ set (156) the read value of the third configuration parameter (S_pass) to drive the closure of the switch during at least part of the second high holding phase;■ repeat at least once said reception of the synchronism signal, said estimation of a further value of the capacitance, said reading in the vector of the first, second and third configuration parameters corresponding to the further estimated value of the capacitance, said setting of the read values of the first, second and third configuration parameters; and wherein the switching amplification stage (3) is configured, during the configuration / control mode, to:■ receive said set values of the first and second configuration parameters (S_buck_on, S_boost_on) and receive the first and second error signals (S_buck_err, S_boost_err);■ generate on the output terminal, during the first upward phase of the configuration / control mode, a switching signal (v_sw_i) as a function of the first error signal (S_buck_err) and of the first configuration parameter (S_buck_on, S1 );■ generate on the output terminal, during the third downward phase of the configuration / control mode, said switching signal (v_sw_i) as a function of the second error signal (S_boost_err) and of the second configuration parameter(S_boost_on; S2); and wherein the linear amplification stage is configured, during the second high holding phase of the configuration / control mode, to receive said set value of the third configuration parameter (S_pass; S3) having a value indicative of the closure of the switch (10-1 ) for at least part of the second high holding phase, so as to short-circuit the output terminal of the linear amplification stage (lo in) with the output terminal of the amplifier (Io).

2. Parallel hybrid amplifier (1 ) according to claim 1 , wherein the processing unit (8- 3.3) is further configured, during the calibration mode, to:■ select (108), in the time interval of the second high holding phase of a first period, at least part of the plurality of input digital samples (v_i_d) and at least part of the output digital samples (v_L_d);■ compare (109), in corresponding instants of the time interval of the second high holding phase, the at least one selected part of the plurality of input digital samples (v_i_d) with respect to the at least one selected part of the output digital samples (v_L_d) based on a defined comparison criterion;■ calculate (110), as a function of said comparison, a value of an error or a value of a cost function;■ verify (111 ) whether a stop criterion associated with the calculated value of the error or the calculated value of the cost function is met;■ detect that the stop criterion is not met, modify at least one of the values of the first, second and third configuration parameters and repeat said reception of the plurality of input digital samples (v_i_d), said reception of the plurality of output digital samples (v_L_d), said selection, said comparison, said calculation and said verification for a second period of the input voltage analog signal (v_i) subsequent to the first period;■ detect that the stop criterion is met and store (113), in a first vector of the data structure of the non-volatile memory (8-4), the modified values of the first, second and third configuration parameters;■ modify (115) the value of the capacitive load and repeat said reception of the plurality of input digital samples (v_i_d), said reception of the plurality of output digital samples (v_L_d), said selection, said comparison, said calculation and said verification for at least one further period of the input voltage analog signal (v_i), until when the stop criterion is met, by storing in the first vector of the datastructure of the non-volatile memory (8-4) further values of the first, second and third configuration parameters corresponding to the modified value of the capacitive load;■ assign (117) a second maximum input value (V_i-max) of the input voltage analog signal and repeat said reception of the plurality of input digital samples (v_i_d), said reception of the plurality of output digital samples (v_L_d), said selection, said comparison, said calculation and said verification for at least one further period of the input voltage analog signal (v_i), until when the stop criterion is met, by storing in a second vector of the data structure of the non-volatile memory (8-4) a plurality of further values of the first, second and third configuration parameters corresponding to a plurality of values of the capacitive load.

3. Parallel hybrid amplifier (1 ) according to claim 1 or 2, comprising a further switch (10-2) connected in parallel to the capacitive load and configured to switch between a closed position and an open position as a function of the value of a fourth configuration parameter (S_clamp_d; S4), wherein the input voltage signal (v_i) further comprises a fourth phase (t15, t20) with substantially constant trend equal to the minimum value, in particular null, wherein the non-volatile memory (8-4) is further configured to further store in each vector the values of the fourth configuration parameter as the plurality of values of the capacitive load change, wherein the processing unit is further configured, during the calibration mode, to:■ further receive initial values of the fourth configuration parameter;■ detect that the stop criterion is not met, modify at least one of the values of the first, second, third and fourth configuration parameters and repeat said reception of the plurality of input digital samples (v_i_d), said reception of the plurality of output digital samples (v_L_d), said selection, said comparison, said calculation and said verification for a second period of the input voltage analog signal (v_i) subsequent to the first period;■ detect that the stop criterion is met and store (113), in the first vector of the data structure of the non-volatile memory (8-4), the modified values of the first, second, third and fourth configuration parameters;■ modify (115) the value of the capacitive load and repeat said reception of the plurality of input digital samples (v_i_d), said reception of the plurality of outputdigital samples (v_L_d), said selection, said comparison, said calculation and said verification for at least one further period of the input voltage analog signal (v_i), until when the stop criterion is met, by storing in the first vector of the data structure of the non-volatile memory (8-4) further values of the first, second, third and fourth configuration parameters corresponding to the modified value of the capacitive load;■ assign (117) the second maximum input value (V_i-max) of the analog signal of input voltage and repeat said reception of the plurality of input digital samples (v_i_d), said reception of the plurality of output digital samples (v_L_d), said selection, said comparison, said calculation and said verification for at least one further period of the input voltage analog signal (v_i), until when the stop criterion is met, by storing in the second vector of the data structure of the non-volatile memory (8-4) a plurality of further values of the first, second, third and fourth configuration parameters corresponding to the plurality of values of the capacitive load; wherein the processing unit is further configured, during the configuration / control mode, to:■ read, in said vector, the value of the first, second, third and fourth configuration parameters corresponding to the estimated value of the capacitance of the capacitive load;■ set the read value of the fourth configuration parameter (S_clamp_d; S4) to drive the closure of the further switch (10-2) during at least part of the fourth low holding phase;■ repeat at least once said reception of the synchronism signal, said estimation of the further value of the capacitance, said reading in the vector of the first, second, third and fourth configuration parameters corresponding to the further estimated value of the capacitance, said setting of the read values of the first, second, third and fourth configuration parameters.

4. Parallel hybrid amplifier (1 ) according to any one of the preceding claims, wherein the measurement and control circuit (8) comprises a series connection of a compensation circuit (8-6) and an error measurement circuit (8-1 ), wherein the compensation circuit is configured to receive as input the output voltage analog signal (v_L) and to generate therefrom as output a feedback signal (v_L_dl) obtained by anticipating the analog signal of input voltage,wherein the error measurement circuit is configured to receive as input the input voltage analog signal (v_i) and the feedback signal (v_L_dl) and to generate as output a third error signal (S_err) as a function of the difference between the input voltage analog signal (v_i) and the feedback signal (v_L_dl), and wherein the measurement and control circuit is configured to generate the first and second error signals (S_buck_err, S_boost_err) as a function of the third error signal.

5. Parallel hybrid amplifier (1 ) according to any one of the preceding claims, further comprising a decoder (3-9) configured to generate as output the values of the first, second and third configuration parameters (S_buck_on, S_boost_on, S_pass) as a function of values in input of a first, second and third internal configuration parameters (S1 , S2, S3), wherein the decoder is configured, during the calibration mode, to:■ receive as input initial values of the first, second and third internal configuration parameters (S1 , S2, S3) and generate therefrom the initial values of the first, second and third configuration parameters (S_buck_on, S_boost_on, S_pass);■ receive as input modified values of the first, second and third internal configuration parameters (S1 , S2, S3) and generate therefrom the modified values of the first, second and third configuration parameters (S_buck_on, S_boost_on, S_pass); wherein the processing unit is configured, during the calibration mode, to:■ receive the initial values of the first, second and third internal configuration parameters instead of the first, second and third internal configuration parameters;■ detect that the stop criterion is not met, modify the values of the first, second and third internal configuration parameters and repeat said reception of the plurality of input digital samples (v_i_d), said reception of the plurality of output digital samples (v_L_d), said selection, said comparison, said calculation and said verification for a second period of the input voltage analog signal (v_i) subsequent to the first period■ detect that the stop criterion is met and store (113), in the first vector of the data structure of the non-volatile memory (8-4), the modified values of the first, second and third internal configuration parameters;■ modify (115) the value of the capacitive load and repeat said reception of the plurality of input digital samples (v_i_d), said reception of the plurality of outputdigital samples (v_L_d), said selection, said comparison, said calculation and said verification for at least one further period of the input voltage analog signal (v_i), until when the stop criterion is met, by storing in the first vector of the data structure of the non-volatile memory (8-4) further values of the first, second and third internal configuration parameters corresponding to the modified value of the capacitive load;■ assign (117) a second maximum input value (V_i-max) of the input voltage analog signal and repeat said reception of the plurality of input digital samples (v_i_d), said reception of the plurality of output digital samples (v_L_d), said selection, said comparison, said calculation and said verification for at least one further period of the input voltage analog signal (v_i), until when the stop criterion is met, by storing in the second vector of the data structure of the non-volatile memory (8-4) a plurality of further values of the first, second and third internal configuration parameters corresponding to the plurality of values of the capacitive load; wherein the non-volatile memory (8-4) is configured to store a plurality of values of the first, second, and third internal configuration parameters instead of the values of the first, second, and third configuration parameters, and wherein the decoder (3-9) is configured, during the configuration / control mode, to:■ receive as input the read value of the first, second and third internal configuration parameters corresponding to the estimated value of the capacitance of the capacitive load;■ generate as output, as a function of the read values of the first, second and third internal configuration parameters, the values of the first, second and third configuration parameters.

6. Parallel hybrid amplifier (1 ) according to any one of the preceding claims, wherein the processing unit (8-3.3) comprises a microcontroller (8-3.5), a programmable electronic device (8-3.4) and a volatile memory (8-3.6), wherein the microcontroller (8-3.5) is configured, during the configuration / control mode, to read from the non-volatile memory said vector of the plurality of values of the first, second, third configuration parameters and to store said vector in the volatile memory (8-3.6), and wherein the programmable electronic device (8-3.4) is configured, during the configuration / control mode, to read from the volatile memory in said vector the value ofthe first, second and third configuration parameters corresponding to the estimated value of the capacitance of the capacitive load.

7. Parallel hybrid amplifier (1 ) according to any one of the preceding claims, wherein the switching amplification stage is of half-bridge class D type and comprises: a series connection of an upper side switch (3-1 ) and a lower side switch (3-2), the upper side switch (3-1 ) being connected to a power supply voltage (VCC) and the lower side switch (3-2) being connected to a reference voltage lower than the power supply voltage, in particular a ground reference voltage; an inductor (3-6) connected between a terminal common to the upper and lower side switches and the output terminal (Io) of the amplifier; a first enable circuit (3-3) configured to control the opening / closure of the upper side switch (3-1 ), as a function of the value of the first configuration parameter (S_buck_on) and of the value of the first error signal (S_buck_err); a second enable circuit (3-4) configured to control the opening / closure of the lower side switch (3-2), as a function of the value of the second configuration parameter (S_boost_on) and of the value of the second error signal (S_boost_err) and wherein the linear amplification stage is of class AB type.

8. Tile printing machine comprising an amplifier according to any one of the preceding claims, wherein the variable capacitive load is at least one inkjet printhead.

9. Computer-implemented method (100) for driving a variable capacitive load (5) by means of a hybrid amplifier (1 ) of parallel type comprising a linear amplification stage (2) and a switching amplification stage (3), the method comprising, during a calibration mode, the steps of: a) selecting (102) a plurality of input digital samples (v_i_d) representative of a period of an input voltage signal (v_i) of periodic type, the period comprising a first upward phase with monotone trend increasing from a substantially null value to a maximum value of input voltage (v_i-max), a second high holding phase with substantially constant trend equal to the maximum value of input voltage (v_i-max) and a third downward phase with monotone trend decreasing from the maximum value of input voltage (v_i-max) to a minimum value less than the maximum value (v_i-max); b) storing (103) the plurality of input digital samples (v_i_d) into a volatile memory (8-3.6); c) generating (104), as a function of the plurality of input digital samples (v_i_d), an input voltage analog signal (v_i) comprising the first upward phase, the second highholding phase and the third downward phase; d) setting (105) initial values of configuration parameters of the hybrid amplifier; e) driving (106) the hybrid amplifier with the input voltage analog signal (v_i) and generating therefrom an output voltage analog signal (v_L) comprising the first upward phase with monotone trend increasing from a substantially null value to a maximum value of output voltage (V_L-max) equal to the maximum value of input voltage (V_i- max) multiplied by a gain of the hybrid amplifier, the second high holding phase with substantially constant trend equal to the maximum value of output voltage (V_L-max) and a third downward phase with monotone trend decreasing from the maximum value of output voltage (V_L-max) to a minimum value less than the maximum value (V_L- max); f) sampling (107) the amplified output voltage analog signal (v_L) and generating therefrom a plurality of output digital samples (v_L_d) of the amplified output voltage analog signal (v_L); g) generating, as a function of at least a part of the plurality of stored input digital samples (v_i_d) and at least a part of the output digital samples (v_L_d), a plurality of vectors corresponding to a plurality of maximum input values (V_i-max) of the input voltage analog signal (v_i), wherein each vector comprises calculated values of configuration parameters of the hybrid amplifier as a plurality of values of the capacitance of the capacitive load change; h) storing, in a non-volatile memory (8-4), said plurality of vectors of the configuration parameters; the method further comprising, during a configuration / control mode subsequent to the calibration mode, the steps of: a1 ) configuring (152) a waveform representative of an input voltage analog signal (v_i) comprising a first upward phase with monotone trend increasing from a substantially null value to a maximum value of input voltage (V_i-max), a second high holding phase with substantially constant trend equal to the maximum value of input voltage (V_i-max) and a third downward phase with monotone trend decreasing from the maximum value of input voltage (V_i-max) to a minimum value less than the maximum value (V_i-max); b1 ) reading (153), from said non-volatile memory (5-4), a vector of the configuration parameters corresponding to a configured maximum input value (V_i-max) of the input voltage analog signal (v_i);c1 ) detecting (154) the presence of a synchronism signal; d1 ) in case of positive verification, determining (155) the current value of the capacitance of the variable capacitive load; e1 ) setting (156), for the hybrid amplifier, values of the configuration parameters corresponding to said determined value of the capacitance of the variable capacitive load in the vector of the configuration parameters; f1 ) driving the hybrid amplifier with the received input voltage analog signal (v_i); g1 ) repeating steps c1 ), d1 ), e1 ), f1 ) until when the presence of the synchronism signal is detected.

10. Method according to claim 9, wherein steps g) and h) of the calibration mode comprise the steps of: g1 ) selecting (108), in the time interval of the second high holding phase, at least a part of the plurality of stored input digital samples (v_i_d) and at least a part of the output digital samples (v_L_d); g2) comparing (109), in corresponding instants of the time interval of the second high holding phase, the at least one selected part of the plurality of stored input digital samples (v_i_d) with respect to the at least one selected part of the output digital samples (v_L_d) based on a defined comparison criterion; g3) calculating (110), as a function of said comparison, a value of an error or a value of a cost function; g4) in case that a stop criterion associated with the calculated value of the error or the calculated value of the cost function is met (111 ), storing (113), in a non-volatile memory, the current values of the configuration parameters of the hybrid amplifier corresponding to the maximum current value (v_i-max) of the input voltage analog signal (v_i) and to the current value of the capacitance of the capacitive load; g5) in case that the stop criterion is not met (111 ), modifying (112) at least one of the values of the configuration parameters of the hybrid amplifier and repeating steps e)-j) at least once, until when the stop criterion is met; g6) verifying (114) whether all the plurality of possible values of the capacitance of the capacitive load has been analyzed; g7) in case of positive verification of the plurality of values of the capacitive load, verifying (116) whether all the plurality of maximum input values (V_i-max) of the input voltage analog signal (v_i) has been analyzed; g8) in case of negative verification of the plurality of values of the capacitive load,modifying (115) the value of the capacitive load and repeating steps d)-l) at least once until all the plurality of values of the capacitance of the capacitive load has been analyzed; g9) in case of negative verification of the plurality of maximum input values (V_i- max), modifying (117) the maximum input value of the input analog signal (v_i) and repeating steps a)-n) until when all the plurality of maximum input values (V_i-max) has been analyzed.11 . Method according to claim 8, wherein step f) of the calibration mode comprises: receiving as input the output voltage analog signal (v_L) and generating therefrom as output a feedback signal (v_L_dl) obtained by anticipating the analog signal of input voltage; generating a third error signal (S_err) as a function of the difference between the input voltage analog signal (v_i) and the feedback signal (v_L_dl); generating the first and second error signals (S_buck_err, S_boost_err) as a function of the third error signal.

12. Non-transitory computer-readable storage medium comprising instructions which, when executed by a computer, cause the computer to perform steps g), h) and steps c1 ), d1 ), e1 ), f1 ), g1 ) of the method of claim 9.

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