Semiconductor memory device

Abstract

A semiconductor memory device according to one embodiment of the present technology is provided with a control unit. The control unit controls the writing strength to a user area included in a memory area on the basis of the number of accesses to the user area. This makes it possible to extend the product operating life of semiconductor memory devices employing ferroelectric memory cells, by increasing the writing strength when the value of a counter linked to the number of accesses to the user area exceeds a predetermined number. Further, the semiconductor memory device is resistant to variability in initial memory characteristics and degradation, and a trade-off between endurance and retention after control processing can be eliminated. In addition, recovery allows the read margin to be maintained, and endurance and retention can be improved.

Description

semiconductor memory device

[0001] The present technology relates to a semiconductor memory device using a ferroelectric material.

[0002] In conventional semiconductor memory devices using ferroelectrics, ferroelectric memory cells including ferroelectric capacitors store data 0 or 1 depending on the polarization state of the ferroelectric. Here, it is desirable for semiconductor memory devices using ferroelectrics to have good rewrite endurance and data retention. However, it is known that a polarization fatigue phenomenon called fatigue occurs when the number of rewrites increases, and an imprinting phenomenon called imprinting occurs when the same data is retained for a long time.

[0003] The occurrence of fatigue reduces the amount of remanent polarization in the hysteresis characteristics of the ferroelectric material, thereby reducing the read margin between 0 and 1. Furthermore, the occurrence of imprint shifts the hysteresis characteristics, thereby reducing the read margin between 0 and 1. In other words, the reduction in endurance due to fatigue and the reduction in retention due to imprint may cause malfunctions in semiconductor memory devices that use ferroelectric materials and shorten the product lifespan.

[0004] Patent Document 1 describes a semiconductor memory device having a fatigue monitor and an imprint monitor using ferroelectric memory cells. In this semiconductor memory device, the degree of deterioration in reliability during memory operation is detected, and if deterioration due to fatigue progresses, the write strength is reduced to extend the memory's life. Furthermore, if deterioration due to imprint progresses, the write strength is increased to improve memory reliability in preparation for data retention. (See, for example, paragraphs

[0015] to

[0037] and Figure 1 of the specification of Patent Document 1).

[0005] Japanese Patent Application Laid-Open No. 2022-150998

[0006] In such semiconductor memory devices using ferroelectric materials, there is a demand for semiconductor memory devices that can achieve a longer product life.

[0007] In view of the above circumstances, an object of the present technology is to provide a semiconductor memory device that can achieve a longer product life.

[0008] In order to achieve the above object, a semiconductor memory device according to an embodiment of the present technology includes a control unit, and the control unit controls a write strength to a user area included in a memory area based on the number of accesses to the user area.

[0009] This semiconductor memory device has a control unit that controls the write strength to the user area based on the number of accesses to the user area included in the memory area, thereby making it possible to extend the product life.

[0010] The semiconductor memory device may further include a counter area that is provided independently of the memory area and that stores the number of accesses, and in this case, the control unit may control the write strength when the number of accesses stored in the counter area exceeds a predetermined number.

[0011] The control unit may increase the write strength by increasing a write voltage.

[0012] The control unit may increase the write voltage in stages.

[0013] The write intensity may include a normal mode in which the write voltage is in a normal state and an increased mode in which the write voltage is increased compared to the normal state. In this case, the control unit may control the write intensity to the increased mode when the write intensity is in the normal mode, and to the normal mode when the write intensity is in the increased mode.

[0014] The semiconductor memory device may further include a flag area provided independently of the memory area and storing settings for the user area. In this case, the settings for the user area may include the normal mode and the increasing mode. The control unit may control the writing intensity to the increasing mode when the setting for the user area stored in the flag area is the normal mode, and may control the writing intensity to the normal mode when the setting for the user area stored in the flag area is the increasing mode.

[0015] The control unit may increase the write intensity by increasing a write pulse width.

[0016] The control unit may increase the write pulse width in stages.

[0017] The write intensity may include a normal mode in which the write pulse width is normal, and an increased mode in which the write pulse width is increased compared to the normal mode. In this case, the control unit may control the write intensity to the increased mode when the write intensity is in the normal mode, and control the write intensity to the normal mode when the write intensity is in the increased mode.

[0018] The semiconductor memory device may further include a flag area provided independently of the memory area and storing settings for the user area. In this case, the settings for the user area may include the normal mode and the increasing mode. The control unit may control the writing intensity to the increasing mode when the setting for the user area stored in the flag area is the normal mode, and may control the writing intensity to the normal mode when the setting for the user area stored in the flag area is the increasing mode.

[0019] The semiconductor memory device may further include a random number generation unit that probabilistically outputs a random number indicating whether or not to increase the write strength. In this case, the control unit may control the write strength based on the random number.

[0020] The semiconductor memory device may further include a flag area that is provided independently of the memory area and that stores settings for the user area. In this case, the settings for the user area may include a volatile mode in which the user area functions as a volatile memory and a non-volatile mode in which the user area functions as a non-volatile memory.

[0021] The semiconductor memory device may further include a counter area that is provided independently of the memory area and that stores the number of accesses, and in this case, the control unit may increase the write strength when the setting of the user area stored in the flag area is the volatile mode and the number of accesses stored in the counter area exceeds a predetermined number.

[0022] The counter area may reset the stored number of accesses when the control unit increases the write strength, and may store the number of rewrites to the user area in the increased write strength state. In this case, the control unit may return the write strength to its original state when the number of rewrites in the increased write strength state reaches a specified number.

[0023] The semiconductor memory device may further include an intensity control unit that controls the intensity of reading data from the user area.

[0024] The semiconductor memory device may further include a flag area that is provided independently of the memory area and that stores settings for the user area. In this case, the settings for the user area may include a volatile mode in which the user area functions as a volatile memory and a non-volatile mode in which the user area functions as a non-volatile memory. The intensity control unit may increase the read intensity when the user area is in the non-volatile mode.

[0025] The semiconductor memory device may further include a counter area that is provided independently of the memory area and that stores the number of accesses, and in this case, the control unit may increase the write strength when the setting of the user area stored in the flag area is the volatile mode and the number of accesses stored in the counter area exceeds a predetermined number.

[0026] The settings of the user area may include a first mode in which the read strength and the write strength are increased, a second mode in which either the read strength or the write strength is increased, and a third mode in which the read strength and the write strength are maintained at normal levels.

[0027] The memory region may be a ferroelectric memory cell.

[0028] The ferroelectric memory cell may include hafnium oxide and zirconium oxide.

[0029] 1 is a block diagram showing an example of the configuration of a semiconductor memory device; FIG. 2 is a diagram showing an example of a ferroelectric memory cell array included in a memory region; FIG. 3 is a diagram showing an example of how polarization is recovered by increasing the write voltage; FIG. 4 is a diagram showing an example of a voltage adjustment circuit; FIG. 5 is a flowchart showing a control method of a control unit; FIG. 6 is a diagram showing an example of how the write voltage is increased; FIG. 7 is a block diagram showing an example of the configuration of a semiconductor memory device; FIG. 8 is a flowchart showing a control method of a control unit; FIG. 9 is a diagram showing an example of how the write pulse width is extended; FIG. 10 is a block diagram showing an example of the configuration of a semiconductor memory device; FIG. 11 is a flowchart showing a control method of a control unit; FIG. 12 is a flowchart showing a control method of a control unit; FIG. 13 is a diagram showing a simulation result in which read defects are improved by increasing the read voltage.

[0030] Hereinafter, embodiments of the present technology will be described with reference to the drawings.

[0031] 1 is a block diagram showing an example of the configuration of a semiconductor memory device 100 according to a first embodiment of the present disclosure. FIG. 2 is a diagram showing an example of a ferroelectric memory cell array included in a memory region 1.

[0032] As shown in FIG. 1, the semiconductor memory device 100 includes a memory area 1 , a control unit 4 , a booster circuit 20 , a flag area 2 , and a counter area 3 .

[0033] The memory area 1 has a ferroelectric memory cell array. The ferroelectric memory cell array functions as a user area 10 that can be accessed from outside by a user of the semiconductor memory device 100. Note that access includes reading from and writing to the user area 10.

[0034] As shown in FIG. 2, each ferroelectric memory cell included in the ferroelectric memory cell array is connected to a word line (WLn), a bit line (BLn), and a plate line (PLn).

[0035] Each ferroelectric memory cell has an n-channel MOSFET (access transistor) and a ferroelectric capacitor. For example, the ferroelectric memory cell 11 has an n-channel MOSFET 12 and a ferroelectric capacitor 13.

[0036] The gate of the n-channel MOSFET 12 is connected to WLn, one of the drain and source is connected to BLn, and the other of the drain and source is connected to one end of the ferroelectric capacitor 13. The other end of the ferroelectric capacitor 13 is connected to PLn. The other ferroelectric memory cells have a similar circuit configuration.

[0037] The memory area section 1 may include components such as decoders and drivers that select word lines, bit lines, or plate lines and apply a predetermined voltage depending on the input address, command, write data, etc., or a sense amplifier.

[0038] The control unit 4 controls the write strength to the user area 10. In this embodiment, the control unit 4 controls the write strength to the user area 10 based on a flag area 2 and a counter area 3, which will be described later. In this embodiment, the control unit 4 also increases the write strength by outputting a control signal to the boost circuit 20, which will be described later, to increase the write voltage.

[0039] Here, the recovery that occurs when the write strength is increased will be explained using Figure 3. In ferroelectric memory cells, a phenomenon called fatigue occurs in which the 2Pr (remanent polarization), which is the signal amount used for memory operation, decreases with each rewrite. On the other hand, there is a phenomenon in which the 2Pr recovers when rewrites are repeated with a write strength stronger than the initial condition. This is called recovery.

[0040] 3A and 3B are diagrams showing an example in which the polarization amount is recovered by increasing the write voltage. Fig. 3A is a diagram showing an example in which 2Pr is reduced by fatigue. Fig. 3B is a diagram showing an example in which 2Pr is recovered by recovery. Fig. 3C is a diagram showing an example in which 2Pr is reduced again by fatigue.

[0041] 3, the horizontal axis represents the number of write operations, and the vertical axis represents the remanent polarization (2 Pr.) The write voltage in FIG. 3A is A [V], the write voltage in FIG. 3B is B [V], which is greater than A [V], and the write voltage in FIG. 3C is A [V].

[0042] 3A, when the write voltage is A [V], fatigue occurs as the number of write operations increases, and 2Pr decreases.

[0043] In Figure 3B, the write voltage is increased to B [V] and writing is performed to the memory area. In this case, 2Pr increases with each write operation. In other words, recovery is occurring.

[0044] 3C, the recovered 2Pr decreases again as the number of write operations increases. In other words, by causing recovery each time the number of accesses exceeds a predetermined number, the amount of remanent polarization decreases, that is, the possibility of malfunction of the semiconductor memory device due to a decrease in the read margin between 0 and 1 can be reduced.

[0045] By utilizing recovery in this way, it is possible to improve rewrite durability (endurance) and data retention characteristics (retention).

[0046] This recovery phenomenon does not occur with PZT (lead zirconate titanate), which has been used conventionally in ferroelectric memory cells. In this embodiment, a mixed crystal containing hafnium oxide (HfO2) and zirconium oxide (ZrO2) is used for the ferroelectric memory cells. There are no restrictions on the material used for the ferroelectric memory cells, and any material that causes the recovery phenomenon may be used.

[0047] The boost circuit 20 increases the write voltage. In this embodiment, the write strength includes a normal mode in which the write voltage is in a normal state and an increased mode in which the write voltage is increased compared to the normal state. That is, the boost circuit 20 controls the write voltage to switch between the write voltage corresponding to the normal mode and the write voltage corresponding to the increased mode based on a control signal output from the control unit 4.

[0048] In this embodiment, the boost circuit 20 also includes a voltage adjustment circuit, as shown in FIG.

[0049] 4, the boost circuit 20 includes a comparator 21, a resistor 22 having one end connected to the output terminal of the comparator 21, and a variable resistor 23 having one end connected to the other end of the resistor 22 and the other end grounded. In FIG. 4, a power supply voltage VDD1 is supplied to the power supply terminal of the comparator 21, and a + input terminal thereof is set to a reference potential Vbgr. The - input terminal of the comparator 21 is connected to a node connecting the resistor 22 and the variable resistor 23.

[0050] In such a boost circuit 20, the resistance value of the variable resistance element 23 is adjusted by a control signal supplied from the control unit 4, thereby adjusting the magnitude of the power supply voltage VDD2, which is the output signal of the comparator 21.

[0051] The flag area 2 stores the settings of the user area 10. For example, the settings of the user area 10 include the state of the write intensity to the user area 10 (normal mode and increasing mode), the volatile mode in which the user area 10 functions as a volatile memory, and the non-volatile mode in which the user area 10 functions as a non-volatile memory. For example, the flag area 2 is set to 0 or 1, and is set to 0 when the write intensity is in the normal mode and to 1 when the write intensity is in the increasing mode. In this embodiment, the flag area 2 is provided independently of the memory area.

[0052] The counter area 3 stores the number of accesses to the user area 10. In this embodiment, the counter area 3 is provided independently of the memory area. For example, the counter area 3 increments a counter by one every time the user area 10 is accessed.

[0053] FIG. 5 is a flowchart showing a control method of the control unit 4.

[0054] 5, the counter area 3 is read every time the user area 10 is read (step 101). That is, the counter count stored in the counter area 3 is read.

[0055] It is determined whether the read counter value exceeds a predetermined number of times X (step 102). If the counter value does not exceed the predetermined number of times X (NO in step 102), +1 is written to the counter area 3 each time the user area 10 is accessed, and the stored counter value is incremented by one (step 107).

[0056] The counter is incremented in step 107, and when the counter exceeds a predetermined number of times X (YES in step 102), a check is made on flag area 2 (step 103).

[0057] In this embodiment, flag area 2 is set to 0 or 1. If flag area 2 is 0 (YES in step 103), the boost circuit 20 increases the write voltage, and flag area 2 becomes 1 (step 104). Typically, when the counter exceeds a predetermined number X, fatigue occurs as shown in FIG. 3, and 2Pr. decreases, requiring recovery. Therefore, at the initial stage when access to user area 10 begins (for example, at the time of initial startup), flag area 2 is set to 0.

[0058] Also, the counter stored in the counter area 3 is reset (step 105), and the counter stored in the counter area 3 is incremented by one each time the user area 10 is accessed (step 107).

[0059] Furthermore, after the above operations, the counter area 3 is read in step 101, and if the counter does not exceed the predetermined number of times X (NO in step 102), the counter stored in the counter area 3 is incremented by one each time the user area 10 is accessed (step 107). In other words, the recovery phenomenon occurs until the counter exceeds the predetermined number of times X, and 2Pr is recovered.

[0060] If the counter again exceeds the predetermined number of times X (YES in step 102), the flag area 2 is checked (step 103). As described above, since the flag area 2 was set to 1 in step 104 (NO in step 103), the write voltage is returned by the boost circuit 20, and the flag area 2 becomes 0 (step 105).

[0061] That is, the first time the counter exceeds the predetermined number of times X, the writing intensity is in normal mode (flag area 2 is 0), so the writing intensity changes to increased mode, and flag area 2 becomes 1. After that, every time the counter exceeds the predetermined number of times X, the mode alternates between switching from increased mode to normal mode and from normal mode to increased mode.

[0062] The predetermined number of times X may be set arbitrarily. For example, the predetermined number of times X may be set to the number of writes that are assumed to cause fatigue based on the simulation results shown in FIG. 3. Furthermore, the predetermined number of times X may be changed based on the number of times that a recovery phenomenon such as the first rising mode, the second rising mode, the third rising mode, etc. has occurred.

[0063] An example of increasing the write voltage will now be described with reference to Fig. 6. Fig. 6 is a diagram showing an example of increasing the write voltage.

[0064] As shown in FIG. 6, at timing t0, a predetermined voltage is applied to WLn and PLn, and if BL1 and BL2 remain at 0V, 0 is written into the ferroelectric memory cell.

[0065] At timing t1a, the voltage on PLn falls to 0V, a higher voltage is applied to WLn, and a voltage for writing 1 is applied to BL2, so that 1 is written into the ferroelectric memory cell.

[0066] At timing t2a, the voltages on WLn and BL2 fall, completing the writing of 1. When the power supply voltage VDD2 supplied to the memory area 1 rises (for example, to +0.1 V), the voltages on WLn, PLn, and BL2 during writing also rise, resulting in an increase in the write voltage.

[0067] In this embodiment, the control unit 4 increases the write voltage in stages. For example, as shown in FIG. 6 , the voltage applied while 0 is being written (between timing t0 and timing t1a) may increase by the amount indicated by arrow 30 (between dotted line 31 and solid line 32). For example, the voltage applied to WLn may be different between when 0 is being written and when 1 is being written (between timing t1a and timing t2a). Alternatively, the voltage applied between timing t0 and timing t1a may increase linearly.

[0068] As described above, the semiconductor memory device 100 according to the first embodiment is provided with a high-voltage driver including a ferroelectric memory cell array (user area 10), a flag area 2 independent of the user area 10, a counter area 3, and a boost circuit 20, and by increasing the write strength when the value of the counter linked to the number of accesses to the user area 10 exceeds a predetermined number, it is possible to extend the product life of a semiconductor memory device using ferroelectric memory cells.

[0069] Conventionally, for example, in Patent Document 1, it was necessary to prepare ferroelectric memory cells to monitor fatigue and imprint, which limited the user area having ferroelectric memory cells. Also, contrasting strength adjustments were performed, in which the rewrite strength was lowered to counter fatigue degradation and the write strength was increased to counter imprint degradation, but this conventional method resulted in a trade-off between the reliability of both, in that improving endurance resulted in a deterioration of retention.

[0070] In this technology, by providing a flag region 2 and a counter region 3 independent of the ferroelectric memory cell array, the user region 10 is not limited. Furthermore, the technology is resistant to variations in memory initial characteristics and degradation, and can eliminate the trade-off between endurance and retention after control processing. Furthermore, recovery makes it possible to maintain a read margin, improving endurance and retention.

[0071] Second Embodiment A semiconductor memory device 200 according to a second embodiment of the present technology will be described. In the following description, descriptions of parts having the same configurations and functions as those of the semiconductor memory device 100 described in the above embodiment will be omitted or simplified.

[0072] FIG. 7 is a block diagram showing an example of the configuration of a semiconductor memory device 200 according to the second embodiment.

[0073] 7, the semiconductor memory device 200 of the second embodiment differs from that of the first embodiment in that it does not have a boost circuit 20. Furthermore, the control unit 4 increases the write strength by extending the write pulse width instead of the write voltage.

[0074] FIG. 8 is a flowchart showing a control method of the control unit 4.

[0075] 8, the counter area 3 is read every time a read operation is performed on the user area 10 (step 201). That is, the counter count stored in the counter area 3 is read.

[0076] It is determined whether the read counter value exceeds a predetermined number of times X (step 202). If the counter value does not exceed the predetermined number of times X (NO in step 202), the counter value stored in the counter area 3 is incremented by one each time the user area 10 is accessed (step 207).

[0077] The counter is incremented in step 207, and when the counter exceeds a predetermined number of times X (YES in step 202), a check is made on flag area 2 (step 203).

[0078] In the second embodiment, the control unit 4 controls the write intensity between a normal mode in which the write pulse width is normal and an increased mode in which the write pulse width is increased compared to the normal mode. In Fig. 8, when flag area 2 is 0 (YES in step 203), the control unit 4 increases the write pulse width and sets flag area 2 to 1 (step 204). In other words, the write intensity is increased, and the recovery phenomenon occurs.

[0079] Also, the counter stored in the counter area 3 is reset (step 205), and the counter stored in the counter area 3 is incremented by one each time the user area 10 is accessed (step 207).

[0080] Furthermore, after the above operations, the counter area 3 is read in step 201, and if the counter does not exceed the predetermined number of times X (NO in step 202), +1 is written to the counter area 3 each time the user area 10 is accessed, and the stored counter is incremented by one (step 207). In other words, the recovery phenomenon occurs until the counter exceeds the predetermined number of times X, and 2Pr is recovered.

[0081] If the counter again exceeds the predetermined number of times X (YES in step 202), a check is made on flag area 2 (step 203). As described above, since flag area 2 was set to 1 in step 204 (NO in step 203), the control unit 4 returns the write pulse width and flag area 2 becomes 0 (step 205).

[0082] That is, the first time the counter exceeds the predetermined number of times X, the writing intensity is in normal mode (flag area 2 is 0) and fatigue has occurred, so the writing intensity changes to increased mode and flag area 2 becomes 1. After that, each time the counter exceeds the predetermined number of times X, the mode alternates between increasing mode and normal mode, and vice versa.

[0083] FIG. 9 is a diagram showing an example of extending the write pulse width.

[0084] As shown in FIG. 9, at timing t0, when a predetermined voltage is applied to WLn and PLn and BL1 and BL2 remain at 0 V, 0 is written into the ferroelectric memory cell.

[0085] At timing t1b, the voltage on PLn falls to 0 V, and a higher voltage is applied to WLn. When a voltage for writing 1 is applied to BL2, 1 is written into the ferroelectric memory cell.

[0086] At timing t2b, the voltages on WLn and BL2 fall, completing the writing of 1. As shown in Fig. 9, by lengthening the write time (the period from timing t0 to timing t1b and the period from timing t1b to timing t2b), the write pulse width is increased, for example, by +50 ns, and the write intensity increases.

[0087] In the second embodiment, the control unit 4 increases the write pulse width in stages. For example, when increasing the time of timing t1b or t2b in the period from timing t0 to timing t1b and the period from timing t1b to timing t2b, the time may be increased by 35 minutes, as indicated by the arrow. Furthermore, for example, the write pulse width may be increased by different lengths in the period from timing t0 to timing t1b and the period from timing t1b to timing t2b.

[0088] As described above, in the semiconductor memory device 200 according to the second embodiment, unlike conventional semiconductor memory devices that are equipped with a fatigue monitor for detecting fatigue degradation and an imprint monitor for detecting imprint degradation, the write strength is controlled based on the flag area 2 and the counter area 3 that are provided independently of the user area 10, so the user area 10 is not limited. This makes it possible to increase the memory capacity. Furthermore, since there is no need to mount a circuit that functions as a voltage adjustment circuit, this leads to a reduction in chip size. Furthermore, it is possible to improve rewrite durability and suppress deterioration of data retention characteristics.

[0089] Third Embodiment A semiconductor memory device 300 according to a third embodiment of the present technology will be described.

[0090] FIG. 10 is a block diagram showing an example of the configuration of a semiconductor memory device 300 according to the third embodiment.

[0091] 10, the semiconductor memory device 300 of the third embodiment differs from that of the first embodiment in that it does not have a flag area 2 or a counter area 3. The semiconductor memory device 300 also has a random signal generating circuit 40 in addition to a memory area section 1, a control section 4, and a boost circuit 20.

[0092] The random signal generating circuit 40 generates random pulses. For example, the random signal generating circuit 40 outputs a pulse of N=0 or a pulse of N=1 to the control unit 4. The probability of generating a pulse of 0 or 1 output from the random signal generating circuit may be random or biased.

[0093] The random signal generating circuit 40 corresponds to a random number generating unit that probabilistically outputs a random number indicating whether or not to increase the writing strength.

[0094] The control unit 4 controls the write intensity based on the random pulse. In the third embodiment, the control unit 4 does not change the write intensity when a pulse of N=0 is acquired, and increases the write intensity when a pulse of N=1 is acquired.

[0095] FIG. 11 is a flowchart showing a control method of the control unit 4.

[0096] As shown in FIG. 11, when a request for write access to the user area 10 is made (step 301), pre-access processing in steps 302 to 305 is performed.

[0097] A random pulse N is generated by the random signal generating circuit 40 and output to the control unit 4 (step 302). The control unit 4 determines whether the random pulse N is 0 or 1 (step 303).

[0098] In the third embodiment, if N=0 (YES in step 303), the write intensity is not changed (step 304). That is, the write intensity is maintained as it is in the normal mode. If N=1 (NO in step 303), the write intensity is increased (step 305).

[0099] Writing to the user area 10 is performed from step 304 or step 305 (step 306), and the control unit 4 returns the write intensity to its original state (step 307). That is, in step 304, writing to the user area 10 is performed in the normal mode, and the normal mode is maintained in step 307. In step 305, writing to the user area 10 is performed in the increase mode, and in step 307, the increase mode is returned to the normal mode.

[0100] As described above, in the semiconductor memory device 300 according to the third embodiment, compared to the case where a recovery phenomenon occurs when intensive rewriting is performed with the write strength increased, the possibility of continuous application of high write strength writes is reduced, thereby making it possible to prevent destruction of memory cells.

[0101] Fourth Embodiment A semiconductor memory device 400 according to a fourth embodiment of the present technology will be described.

[0102] The configuration of the semiconductor memory device 400 according to the fourth embodiment is similar to that of the semiconductor memory device 100 according to the first embodiment.

[0103] In the fourth embodiment, the ferroelectric memory cell (user area 10) is set to a volatile mode in which it functions as a volatile memory, or a non-volatile mode in which it functions as a non-volatile memory.

[0104] The volatile memory is set when data (stored contents) will be lost if the external power supply is interrupted, i.e., when data retention is not necessary. In the fourth embodiment, the memory is set to be volatile when recovery is performed at the next startup.

[0105] Furthermore, nonvolatile memory retains data even when power is cut off from the outside. In other words, it is set when data retention is necessary. Furthermore, since the same data is continuously retained, imprinting occurs, reducing 2Pr.

[0106] In the fourth embodiment, the flag area 2 is set to 0 when the user area 10 is in the non-volatile mode, and set to 1 when the user area 10 is in the volatile mode.

[0107] FIG. 12 is a flowchart showing a control method of the control unit 4 according to the fourth embodiment.

[0108] As shown in FIG. 12, the power supply is turned on (step 401), and the control unit 4 determines the flag area 2 (step 402).

[0109] If the flag area 2 is 1 (YES in step 402), that is, if the user area 10 is in volatile mode, it is determined whether the counter stored in the counter area 3 exceeds a predetermined number X (step 403).

[0110] If the counter exceeds the predetermined number X (YES in step 403), the semiconductor memory device 400 transitions to recovery operation, so the counter is reset and the write strength is increased (step 404). Note that in this case, as described in the first and second embodiments, the write strength may be increased by increasing the write voltage or by extending the write pulse width.

[0111] With the write strength increased, the rewrite operation of all user areas 10 is performed, and +1 is written to the counter (step 405). The operation of step 405 is repeated until the counter reaches the specified number of times Y (NO in step 406). Note that the specified number of times X and the specified number of times Y may be the same or different values, or either may be larger.

[0112] If rewriting has been performed until the counter reaches the designated number Y (YES in step 406), the writing strength is returned and the counter is reset (step 407).

[0113] After the counter is reset, +1 is written to the counter area 3 every time the user area 10 is accessed, and the stored counter is increased by one (step 408).

[0114] If the flag area 2 is 0 (NO in step 401 ), or if the counter does not exceed the predetermined number of times X (NO in step 402 ), the process proceeds to step 408 .

[0115] Before turning off the power (step 410), a command is issued to put the user area 10 into standby in either volatile mode or nonvolatile mode (step 409). For example, if the nonvolatile mode is to be used to retain data in the memory area 1, 0 is written to the flag area 2. If data retention is not required and the volatile mode is to be used to perform a recovery operation at the next startup, 1 is written to the flag area 2.

[0116] The command to set the user area 10 to standby in either volatile mode or nonvolatile mode may be instructed by the user. That is, the user can switch between a mode in which the nonvolatile memory device is to be stored and a mode in which it is not to be stored as needed. The number of accesses to the user area 10 may also be used as a criterion for selecting the volatile mode or nonvolatile mode. For example, the counter area 3 may be read to determine the mode when the power is turned off. If the number of accesses is less than a preset number, the nonvolatile mode (storable mode) may be selected, and if the number of accesses is more than a preset number, the volatile mode (nonstorable mode) may be selected.

[0117] Alternatively, the user may select (determine) which mode to use without switching between volatile mode and non-volatile mode during steps 401 to 410. For example, the mode may be selected based on learning or inference in an AI (artificial intelligence) neural network. For example, during learning, data with different synaptic weights needs to be updated, and the memory used is required to retain data, so non-volatile mode is selected. During inference, the memory is used only for calculations, so data retention is not required, and volatile mode is selected. In this way, the semiconductor memory device 400 may be instructed to switch between volatile mode and non-volatile mode in advance depending on the state and settings of an application including the control unit 4.

[0118] As described above, the semiconductor memory device 400 according to the fourth embodiment differs from conventional semiconductor memory devices in that it does not include a fatigue monitor or an imprint monitor using ferroelectric memory cells, thereby eliminating the limitations imposed by the user area 10 and enabling an increase in storage capacity. Furthermore, since recovery is performed simultaneously on the ferroelectric memory cell array, variations in the degree of polarization recovery between memory cells are suppressed. This makes it possible to improve rewrite durability and suppress deterioration of data retention characteristics.

[0119] Fifth Embodiment A semiconductor memory device 500 according to a fifth embodiment of the present technology will be described.

[0120] The configuration of the semiconductor memory device 500 according to the fifth embodiment is similar to that of the semiconductor memory device 100 according to the first embodiment.

[0121] In the fifth embodiment, the control unit 4 controls the read strength or the write strength based on the determination result of the flag area 2. Also in the fifth embodiment, the control unit 4 increases the read strength by increasing the read voltage.

[0122] Fig. 13 is a flowchart showing a control method of the control unit 4 according to the fifth embodiment. Fig. 14 is a diagram showing a simulation result showing that read failures are improved by increasing the read voltage.

[0123] As shown in FIG. 13, the power supply is turned on (step 501), and the control unit 4 determines the flag area 2 (step 502).

[0124] If the flag area 2 is 0 (YES in step 502), that is, if the nonvolatile mode is selected, the read voltage is increased to increase the read intensity (step 503), thereby improving the read failure.

[0125] If the flag area 2 is 1, that is, if the mode is volatile, it is determined whether the counter stored in the counter area 3 exceeds a predetermined number X (step 504).

[0126] If the counter exceeds the predetermined number X (YES in step 504), the semiconductor memory device 500 transitions to a recovery operation, so the write strength is increased and the counter is reset (step 505). Note that in this case, as described in the first and second embodiments, the write strength may be increased by increasing the write voltage or by extending the write pulse width.

[0127] This makes it possible to improve reliability without applying excessive stress to the memory cells.

[0128] After the processing of step 503, step 505, or step 504 (NO), +1 is written to the counter area 3 every time the user area 10 is accessed, and the stored counter is incremented by one (step 506).

[0129] A command is issued to place the user area 10 on standby in either volatile mode or nonvolatile mode (step 507). For example, if the nonvolatile mode is to be used to retain data in the memory area 1, 0 is written to the flag area 2. If data retention is not required and the volatile mode is to be used to perform a recovery operation at the next startup, 1 is written to the flag area 2.

[0130] After selecting either the volatile or nonvolatile mode, the write or read intensity is restored (step 508) and the power is turned off (step 509).

[0131] In the fifth embodiment, the control unit 4 also functions as an intensity control unit that controls the read intensity for the user area.

[0132] As described above, in the semiconductor memory device 500 according to the fifth embodiment, the write strength is increased in the volatile mode, and the read strength is increased in the nonvolatile mode.

[0133] Conventionally, the reliability of ferroelectric memory cells has been improved by increasing the write strength. However, since ferroelectric memories are generally expected to be accessed more frequently for writes than for reads, there is a concern that the conventional method may increase the stress applied to the memory cells more than necessary.

[0134] In the present invention, the rewrite durability is improved and made highly reliable by increasing the write strength, and the data retention characteristics are made highly reliable by increasing only the read strength. For example, Figure 14 shows the remanent polarization (2Pr.) at each write strength where the read voltage has the relationship A [V] > B [V] > C [V], with the vertical axis representing 2Pr. [μC / cm2] and the horizontal axis representing the hold time [s].

[0135] As shown in Figure 14, it can be seen that the longer the data retention time in the polarization state of the ferroelectric, the more the 2Pr decreases. However, it can be seen that the decrease in 2Pr is suppressed by increasing the read voltage (for example, read voltage A [V] and read voltage C [V]). In other words, unlike fatigue, imprint can be improved simply by increasing the read intensity. It can be seen that the fifth embodiment can achieve certain results in actual devices.

[0136] Other Embodiments The present technology is not limited to the above-described embodiments, and various other embodiments can be realized.

[0137] In the above embodiment, the flag area 2 is set to 0 or 1 based on the settings of the two user areas 10, the normal mode and the increase mode. However, this is not limited to this, and the flag area 2 may be set to any number of bits, and the user area 10 may be set to modes other than the above two modes. For example, a first increase mode in which the voltage increases at a first increase rate compared to the normal mode, a second increase mode in which the voltage increases at a second increase rate, and a third increase mode in which the voltage increases at a third increase rate may be set, and a 2-bit flag area 2 such as 00, 01, 10, and 11 may be set for the normal mode and each increase mode.

[0138] In the above embodiment, either the write strength or the read strength is increased. However, this is not limiting; both the write strength and the read strength may be in an increased mode. In this case, there are four patterns: increasing both strengths, not increasing both strengths (maintaining the normal state), or increasing only one strength. Therefore, a two-bit flag area (00, 01, 10, 11) may be set. Furthermore, the write strength and the read strength may be controlled based on the number of accesses stored in the counter area 3. In this way, increasing both the write strength and the read strength not only improves retention characteristics and durability, but also amplifies the signal amount until memory cell recovery is complete. In other words, when recovering a memory cell whose signal amount has decreased due to fading, one or two recovery attempts will not restore the initial signal amount. Therefore, by increasing the read strength (e.g., read voltage) and increasing the signal amount until recovery is complete, it is possible to suppress read failures during the recovery operation.

[0139] The present technology can also be configured as follows. (1) A semiconductor memory device including a control unit that controls a write strength to a user area included in a memory area based on the number of accesses to the user area. (2) The semiconductor memory device according to (1), further including a counter area that is provided independently of the memory area and that stores the number of accesses, and the control unit controls the write strength when the number of accesses stored in the counter area exceeds a predetermined number. (3) The semiconductor memory device according to (2), in which the control unit increases the write strength by increasing a write voltage. (4) The semiconductor memory device according to (3), in which the control unit increases the write voltage in stages. (5) The semiconductor memory device according to (3), wherein the write strength includes a normal mode in which the write voltage is in a normal state and an increasing mode in which the write voltage is increased compared to the normal state, and the control unit controls the write strength to the increasing mode when the write strength is in the normal mode, and controls the write strength to the normal mode when the write strength is in the increasing mode. (6) The semiconductor memory device according to (5), further comprising a flag area provided independently of the memory area and storing settings of the user area, the settings of the user area including the normal mode and the increasing mode, and the control unit controls the write strength to the increasing mode when the setting of the user area stored in the flag area is the normal mode, and controls the write strength to the normal mode when the setting of the user area stored in the flag area is the increasing mode. (7) The semiconductor memory device according to (2), wherein the control unit increases the write strength by extending a write pulse width. (8) The semiconductor memory device according to (7), in which the control unit increases the write pulse width in a stepwise manner.(9) The semiconductor memory device according to (7), wherein the write intensity includes a normal mode in which the write pulse width is normal and an increasing mode in which the write pulse width is increased compared to the normal mode, and the control unit controls the write intensity to the increasing mode when the write intensity is in the normal mode, and controls the write intensity to the normal mode when the write intensity is in the increasing mode. (10) The semiconductor memory device according to (9), further comprising a flag area provided independently of the memory area and storing settings of the user area, the settings of the user area including the normal mode and the increasing mode, and the control unit controls the write intensity to the increasing mode when the setting of the user area stored in the flag area is the normal mode, and controls the write intensity to the normal mode when the setting of the user area stored in the flag area is the increasing mode. (11) The semiconductor memory device according to (1), further comprising a random number generation unit that probabilistically outputs a random number indicating whether or not to increase the write strength, wherein the control unit controls the write strength based on the random number. (12) The semiconductor memory device according to (1), further comprising a flag area that is provided independently of the memory area and that stores a setting for the user area, wherein the setting for the user area includes a volatile mode in which the user area functions as a volatile memory and a non-volatile mode in which the user area functions as a non-volatile memory. (13) The semiconductor memory device according to (12), further comprising a counter area that is provided independently of the memory area and that stores the number of accesses, wherein the control unit increases the write strength when the setting for the user area stored in the flag area is the volatile mode and the number of accesses stored in the counter area exceeds a predetermined number.(14) The semiconductor memory device according to (13), wherein the counter area resets the stored number of accesses when the control unit increases the write strength, and stores the number of rewrites to the user area in a state where the write strength has been increased, and the control unit restores the write strength when the number of rewrites to the user area in a state where the write strength has been increased reaches a designated number. (15) The semiconductor memory device according to (1), further comprising: a strength control unit that controls a read strength for the user area. (16) The semiconductor memory device according to (15), further comprising: a flag area that is provided independently of the memory area and that stores settings for the user area, the settings for the user area including a volatile mode in which the user area functions as a volatile memory and a non-volatile mode in which the user area functions as a non-volatile memory, and the strength control unit increases the read strength when the user area is in the non-volatile mode. (17) The semiconductor memory device according to (16), further comprising a counter area provided independently of the memory area and storing the number of accesses, wherein the control unit increases the write strength when the setting of the user area stored in the flag area is the volatile mode and the number of accesses stored in the counter area exceeds a predetermined number. (18) The semiconductor memory device according to (16), wherein the setting of the user area includes a first mode in which the read strength and the write strength are increased, a second mode in which either the read strength or the write strength is increased, and a third mode in which the read strength and the write strength are maintained at normal states. (19) The semiconductor memory device according to (1), wherein the memory area is a ferroelectric memory cell. (20) The semiconductor memory device according to (19), wherein the ferroelectric memory cell contains hafnium oxide and zirconium oxide.

[0140] REFERENCE SIGNS LIST 1... memory area section 2... flag area 3... counter area 4... control section 10... user area 20... booster circuit 40... random signal generating circuit 100, 200, 300, 400, 500... semiconductor memory device

Claims

1. A semiconductor memory device having a control unit that controls the write strength to a user area included in a memory area based on the number of accesses to the user area.

2. A semiconductor memory device according to claim 1, further comprising a counter area provided independently of said memory area for storing said number of accesses, said control unit controlling said write strength when the number of accesses stored in said counter area exceeds a predetermined number.

3. A semiconductor memory device according to claim 2, wherein the control unit increases the write strength by increasing a write voltage.

4. A semiconductor memory device according to claim 3, wherein the control section increases the write voltage in stages.

5. A semiconductor memory device according to claim 3, wherein the write strength includes a normal mode in which the write voltage is in a normal state and an increased mode in which the write voltage is in a state increased compared to the normal state, and the control unit controls the write strength to the increased mode when the write strength is in the normal mode, and controls the write strength to the normal mode when the write strength is in the increased mode.

6. A semiconductor memory device as claimed in claim 5, further comprising a flag area provided independently of the memory area and storing settings of the user area, the settings of the user area including the normal mode and the increasing mode, and the control unit controls the write intensity to the increasing mode when the setting of the user area stored in the flag area is the normal mode, and controls the write intensity to the normal mode when the setting of the user area stored in the flag area is the increasing mode.

7. A semiconductor memory device according to claim 2, wherein the control section increases the write strength by extending a write pulse width.

8. A semiconductor memory device according to claim 7, wherein the control section extends the write pulse width in a stepwise manner.

9. A semiconductor memory device as described in claim 7, wherein the write strength includes a normal mode in which the write pulse width is in a normal state, and an increased mode in which the write pulse width is extended compared to the normal state, and the control unit controls the write strength to the increased mode when the write strength is in the normal mode, and controls the write strength to the normal mode when the write strength is in the increased mode.

10. A semiconductor memory device as described in claim 9, further comprising a flag area provided independently of the memory area and storing settings of the user area, the settings of the user area including the normal mode and the increasing mode, and the control unit controls the write intensity to the increasing mode when the setting of the user area stored in the flag area is the normal mode, and controls the write intensity to the normal mode when the setting of the user area stored in the flag area is the increasing mode.

11. A semiconductor memory device as claimed in claim 1, further comprising a random number generating unit which probabilistically outputs a random number indicating whether or not to increase the write strength, and the control unit controls the write strength based on the random number.

12. A semiconductor memory device as claimed in claim 1, further comprising a flag area provided independently of said memory area and configured to store settings for said user area, said settings for said user area including a volatile mode in which said user area functions as a volatile memory and a non-volatile mode in which said user area functions as a non-volatile memory.

13. A semiconductor memory device as claimed in claim 12, further comprising a counter area provided independently of the memory area and configured to store the number of accesses, wherein the control unit increases the write strength when the setting of the user area stored in the flag area is the volatile mode and when the number of accesses stored in the counter area exceeds a predetermined number.

14. A semiconductor memory device as described in claim 13, wherein the counter area resets the stored number of accesses when the write strength is increased by the control unit, and stores the number of rewrites to the user area in the state in which the write strength is increased, and the control unit restores the write strength when the number of rewrites in the state in which the write strength is increased reaches a designated number.

15. A semiconductor memory device according to claim 1, further comprising a strength control section for controlling a read strength for the user area.

16. A semiconductor memory device as described in claim 15, further comprising a flag area provided independently of the memory area and storing settings for the user area, the settings for the user area including a volatile mode in which the user area functions as a volatile memory and a non-volatile mode in which the user area functions as a non-volatile memory, and the intensity control unit increases the read intensity when the user area is in the non-volatile mode.

17. A semiconductor memory device as claimed in claim 16, further comprising a counter area provided independently of the memory area and configured to store the number of accesses, wherein the control unit increases the write strength when the setting of the user area stored in the flag area is the volatile mode and when the number of accesses stored in the counter area exceeds a predetermined number.

18. A semiconductor memory device as described in claim 16, wherein the settings of the user area include a first mode in which the read strength and the write strength are increased, a second mode in which either the read strength or the write strength is increased, and a third mode in which the read strength and the write strength are maintained at normal states.

19. The semiconductor memory device according to claim 1, wherein the memory area is a ferroelectric memory cell.

20. The semiconductor memory device according to claim 19, wherein the ferroelectric memory cell includes hafnium oxide and zirconium oxide.

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