Calculation device and data transfer method

Abstract

A calculation device (10) comprises a plurality of PEs (12) arranged two-dimensionally. Each of the PEs (12) includes a selector (24) that outputs inputted data in a set direction. By using a single process of a selector-setting command and an input / output command, each of the PEs (12) performs: data transfer with respect to another PE (12) located not adjacently, through the selector (24), such as data transfer with another PE (12) that is located not adjacently in a diagonal direction; or data transfer within the PE (12) through the selector (24), such as data transfer from a register (22) to a calculation circuit (20).

Description

Arithmetic device and data movement method CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2023-136237, filed on August 24, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a computing device and a data movement method.

[0003] A computing device has been developed that is composed of a plurality of processors arranged in an array (two-dimensionally).

[0004] In such computing devices, there is a demand for improved data processing speed. For example, Patent Document 1 describes a computing device including a first plurality of processing cores arranged in an array and a second plurality of processing cores arranged in an array. A subset of the first plurality of processing cores included in this computing device is disposed between a data processing circuit and the second plurality of processing cores.

[0005] U.S. Pat. No. 1,086,574

[0006] In a computing device in which processors are arranged in an array, broadcast or direct neighbors are used to input and output data between processors. Broadcast enables access between all processors (Processing Elements, hereinafter referred to as "PEs") 102 and the external memory 104, as represented by dashed lines in the computing device 10 shown in Fig. 31. Direct neighbors enable access between PEs 12 that are adjacent to each other in the vertical and horizontal directions, as represented by solid lines in Fig. 31.

[0007] Even if data input / output is attempted between two PEs 102 that are not adjacent vertically or horizontally using broadcast and direct neighbor, direct data input / output cannot be performed between two non-adjacent PEs 102. For example, when moving data from PE 102B to PE 102C, the data must be moved in two separate processes, such as moving the data from PE 102B to PE 102A and moving the data from PE 102A to PE 102C. For this reason, it takes time to move data between PEs 102 in processes such as sum processing and max processing that aggregate data stored in multiple PEs 102.

[0008] Furthermore, data movement within a single PE 102, such as data movement between a register and an arithmetic circuit, may require multiple processes. In such cases, data movement within the PE 102 also requires time.

[0009] The present disclosure aims to provide an arithmetic device and a data movement method that can move data faster in a processor.

[0010] The present disclosure employs the following technical solutions to solve the above problems. The reference symbols in parentheses in the claims and in this section are merely examples showing the correspondence with the specific solutions described in the embodiments below as one aspect, and do not limit the technical scope of the present disclosure.

[0011] An arithmetic device according to one aspect of the present disclosure is an arithmetic device comprising a plurality of processors, each of which has a selector that outputs input data in a set direction, and the processor moves the data via the selector between other non-adjacent processors, or moves the data via the selector within the processor, by processing a setting instruction for the selector and an input / output instruction for the data in a single operation.

[0012] For example, processor B may move data to a non-adjacent processor C in a diagonal direction. To do this, processor B outputs the data to processor C via adjacent processor A. In this case, according to this configuration, processor A, which passes the data, outputs the data from processor B to processor C in accordance with a selector setting command and a data input / output command, so processor A does not actually perform any processing on the data. In other words, data is essentially output directly from processor B to processor C. Also, looking at processor B, data from the processor adjacent to the right is output to processor D, the processor adjacent below, in accordance with a selector setting command, and data is input from the processor adjacent above. In this way, by giving the same selector setting command to all processors, all processors can simultaneously directly move data to diagonal processors (other non-adjacent processors).

[0013] Furthermore, data movement within a processor is also performed via a selector, such as between a register and an arithmetic circuit.

[0014] Data movement to other processors that are not adjacent to each other and data movement within a processor are performed by a single processing of a selector setting command and a data input / output command.

[0015] This configuration allows faster data movement within the processor by performing the movement process via such a selector.

[0016] In the above arithmetic device, the processor may include a register connected to the selector for holding the data.

[0017] In the above-described arithmetic device, the processor may include a plurality of the selectors.

[0018] In the above-mentioned arithmetic device, the processor may be provided with an arithmetic circuit connected to the selector and performing arithmetic processing on the data, and data movement between the processor and the arithmetic processing by the arithmetic circuit may be performed in a single process of a setting command and an input / output command for the selector.

[0019] In the above arithmetic device, the arithmetic circuit that performs a specific process may be provided in a portion of the processors, and when the specific process is performed, data may be moved to the portion of the processors via the selector.

[0020] In the above-described arithmetic device, wiring used for data transfer between the processors may be provided for each of the processors at a predetermined interval.

[0021] In the above-mentioned arithmetic device, when sorting process of score data indicating the magnitude held in multiple processors is performed, the processor may determine the magnitude of the score data moved between adjacent processors via the selector, and perform an exchange process to move the score data to the other processor depending on the result of the size determination, and the exchange process may be repeated with different combinations of two adjacent processors.

[0022] In this case, the data input to the processor is associated with score data indicating the size of the data, and the processor determines the size of the score data moved between adjacent processors via the selector, moves the score data to the other processor depending on the result of the size determination, and retains destination data indicating the destination of the score data, and the processor may move the data between adjacent processors based on the destination data.

[0023] In the above-mentioned arithmetic device, the data input to the processor is associated with score data indicating the size of the data or index data indicating the order of the data, and the processor determines whether the score data or the index data moved between adjacent processors via the selector is large or small, and moves the score data or the index data to the other processor depending on the result of the size determination, while retaining destination data indicating the destination of the score data or the index data, and the processor may move the data between adjacent processors based on the destination data.

[0024] In the above-mentioned arithmetic device, the processor is associated with a relative address indicating where the data is to be stored, and the processor determines whether the relative address moved between the processor and another adjacent processor via the selector is larger or smaller, and moves the relative address to the other processor depending on the result of the determination of the size, while retaining destination data indicating the destination of the relative address, and after the data is associated with the relative address after the move, the processor may move the data between the other adjacent processor based on the reverse order of the move indicated by the destination data.

[0025] In the above-mentioned arithmetic device, when the score data, the index data, or the data associated with the relative address is input from an external memory to the processor, the processor may move the data between adjacent other processors based on the destination data.

[0026] In the above-mentioned computing device, the processors may be virtually divided into first groups consisting of three or more adjacent processors, a size determination of the index data for each of the first groups may be performed, and a first sorting process may be performed in which the index data and the data associated with the index data are moved according to the determination result. After that, the three or more adjacent processors may be virtually divided into second groups different from the first groups, a size determination of the index data for each of the second groups may be performed, and the index data and the data associated with the index data are moved according to the determination result. The first sorting process and the second sorting process may be repeatedly performed.

[0027] In the above-mentioned arithmetic device, when the number of data to be sorted is greater than the number of processors, one of the processors assigns a number to each of the multiple pieces of data and holds them, and multiple processor groups are virtually set up as a collection of multiple processors that hold the data assigned the same number, and the multiple processor groups are set up so that the processors constituting the processor group are in reverse order in at least one of the row direction and the column direction relative to the reference processor group, and after performing the first sorting process for each of the first groups divided within the processor group, the second sorting is performed for each of the second groups including groups divided across the multiple processor groups, and the first sorting process and the second sorting process may be repeated.

[0028] In the above-mentioned computing device, a first spare processor may be provided adjacent to the outer edge processor located at the edge of the processors arranged two-dimensionally, which is a processor used to sort the multiple pieces of data held by the outer edge processor in the second sorting process.

[0029] In the above-mentioned arithmetic device, input data may be divided into a plurality of pieces of data each having a predetermined number of bits, and processing may be performed for each of the pieces of data divided by the predetermined number of bits between the plurality of processors that hold the input data.

[0030] The above arithmetic device may include a spare processor having no arithmetic circuit but having the selector and a register for holding the data, and data may be transferred between the processor and the spare processor via the selector.

[0031] In the above-described arithmetic device, the operation for executing the required function of the arithmetic device may be set in advance or by data for each of the processors, and each of the processors may perform a different operation in accordance with the request for the function.

[0032] A data movement method of one aspect of the present disclosure is a data movement method for an arithmetic device composed of multiple processors, wherein the processors are provided with selectors that output input data in a set direction, and the processors move the data via the selectors between non-adjacent processors, or move the data via the selectors within the processors, by processing a setting instruction for the selectors and an input / output instruction for the data in a single operation.

[0033] The present disclosure allows for faster data movement in a processor.

[0034] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, which are a schematic configuration diagram of a PE included in an arithmetic device of an embodiment, a schematic diagram illustrating data movement from a save register of a PE to a register of another non-adjacent PE of an embodiment, a schematic diagram illustrating data movement from a register of a PE to a save register of another non-adjacent PE of an embodiment, a schematic diagram illustrating data movement from one PE to multiple other PEs in the same row of an embodiment, a schematic diagram illustrating data movement from one PE to all other PEs of an embodiment, a schematic diagram illustrating data transfer from an external memory to one PE and data movement from that PE to all PEs of an embodiment, a schematic diagram illustrating data movement row by row from an external memory of an embodiment, a schematic diagram of another embodiment illustrating data movement from an external memory to all PEs of an embodiment, a schematic diagram illustrating data movement accompanying arithmetic processing by an arithmetic circuit of an embodiment, a schematic diagram illustrating data movement when the arithmetic device of an embodiment performs a convolution operation, a schematic diagram illustrating data movement when the arithmetic device of an embodiment includes a specific arithmetic circuit only in some PEs, and a schematic diagram illustrating data movement when the arithmetic device of an embodiment includes a specific arithmetic circuit in a particular arithmetic circuit. 1A is a schematic diagram showing data movement when a certain arithmetic circuit is provided only in some PEs; and FIG. 1B is a schematic diagram showing the configuration of wiring between PEs according to an embodiment, where (A) shows a form in which wiring is provided between all adjacent PEs, and (B) shows a form in which some wiring is thinned out; and FIG. 1C is a schematic diagram showing a first process of diagonal data movement in a form in which wiring is thinned out according to an embodiment, where (A) shows data movement in four adjacent PEs, and (B) shows the positions of four adjacent PEs in the arithmetic device with dashed lines; and FIG. 1D is a schematic diagram showing data movement when sorting is performed in the arithmetic device of an embodiment; and FIG. 1E is a schematic diagram showing data movement in the arithmetic device of an embodiment when sorting one row's worth of data in one process; and FIG. 1F is a schematic diagram showing data movement between PEs when sorting one row's worth of data in one process in the arithmetic device of an embodiment;1A and 1B are schematic diagrams showing data movement when sorting a number of rows of data in the arithmetic device of the embodiment; and a diagram showing the order of data associated with index data before and after sorting by the arithmetic device of the embodiment, where (A) is before sorting and (B) is after sorting.

[0033] FIG. 1B is a diagram showing the movement of data associated with index data of the embodiment, where (A) is the first or odd-numbered processing, and (B) is the second or even-numbered processing.

[0034] FIG. 1C is a diagram showing relative addresses and input data rearranged by the sorting process of the arithmetic device when moving to a relative address position of the embodiment; and a diagram showing sorting of data by group of the embodiment. FIG. 1 is a diagram showing a sorting process according to an embodiment when the number of data to be sorted is greater than the number of PEs; FIG. 2 is a diagram showing a second sorting process according to an embodiment when the number of data to be sorted is greater than the number of PEs; FIG. 3 is a schematic diagram showing a spare PE provided adjacent to an outer edge PE according to an embodiment; FIG. 4 is a diagram showing the relationship between data used in a convolution operation and PEs according to an embodiment;

[0035] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the embodiments described below are examples of how the present disclosure may be implemented, and the present disclosure is not limited to the specific configurations described below. When implementing the present disclosure, specific configurations according to the embodiments may be appropriately adopted.

[0036] FIG. 1 is a schematic diagram of a PE (Processing Element) 12, which is a processor included in a computing device 10 according to this embodiment.

[0037] The arithmetic device 10 is configured with a plurality of PEs 12. Note that, in the example of Fig. 1, four PEs 12 are arranged, such as PEs 12A to 12D, but the arithmetic device 10 may include any number of PEs 12. Furthermore, the plurality of PEs 12 may not only be arranged two-dimensionally (in an array), but may also be arranged in a multidimensional manner, such as three or more dimensions, as will be described later.

[0038] The PEs 12 constituting the arithmetic device 10 are electrically connected by wiring 14 for data movement between adjacent PEs 12. Even if the wiring 14 between PEs 12 is omitted in FIG. 2 etc., it is assumed that adjacent PEs 12 are connected by wiring 14. Furthermore, data movement in this embodiment is a concept that also includes copying of data.

[0039] The arithmetic device 10 is capable of various processes such as data movement and calculation for each PE 12. However, if settings are made for each PE 12 by a program, the amount of programming increases.

[0040] Therefore, the operation for executing the required function of the arithmetic device 10 may be set in advance or by data for each PE 12, and different operations may be performed for each PE 12 according to the requirements of the function. Note that this data is setting data input to the PE 12 and is different from data that moves between PEs 12. This eliminates the need to set the operation for each PE 12 by program, and reduces the amount of programming required for the arithmetic device 10 to function.

[0041] The PE 12 of this embodiment includes an arithmetic circuit 20, a register 22, a selector 24, and a save register 26.

[0042] The arithmetic circuits 20 are connected to the selector 24 and perform various arithmetic operations, such as ==, !=, >, >=, <, <=, >>, <<, or, and, min, max, clip, add, sub, mul, div, mod, and macc. The arithmetic circuits 20 that perform the arithmetic operations can be selected appropriately by the arithmetic device 10. In the arithmetic device 10 of this embodiment, one PE 12 includes multiple arithmetic circuits 20, and one PE 12 may select multiple different arithmetic operations or multiple identical arithmetic operations from among multiple prepared operations, and perform the arithmetic operations simultaneously. Furthermore, by each PE 12 performing a different arithmetic operation, the arithmetic device 10 may perform multiple different arithmetic operations simultaneously.

[0043] The register 22 is a storage unit that is connected to the selector 24 and that holds (stores) data. For example, the arithmetic circuit 20 performs arithmetic processing on the data held in the register 22 and holds the arithmetic result in the register 22.

[0044] The selector 24 outputs data input to the PE 12 in a set direction. The data output direction is to another adjacent PE 12, or to its own arithmetic circuit 20, register 22, save register 26, etc. The PE 12 of this embodiment moves data between itself and another non-adjacent PE 12 via the selector 24 by processing a setting instruction for the selector 24 (hereinafter referred to as a "selector setting instruction") and a data input / output instruction (hereinafter referred to as a "data input / output instruction") once.

[0045] The selector setting instruction sets the output direction of data by the selector 24. For example, the selector setting instruction sets the direction of another PE 12 to which data is to be output, or the direction of the arithmetic circuit 20, register 22, or save register 26 in the same PE 12 to which data is to be output. The data input / output instruction is an instruction to select data to be input / output via the selector 24, and this data is held in the register 22 or save register 26.

[0046] Furthermore, the PE 12 of this embodiment moves data via the selector 24 within the PE 12 by processing a selector setting instruction and a data input / output instruction once. Examples of data movement via the selector 24 within the PE 12 include movement of data between the save register 26 and the arithmetic circuit 20, movement of data between the arithmetic circuit 20 and the register 22, and movement of data between the register 22 and the save register 26.

[0047] The save register 26 is a register connected to the selector 24 and temporarily stores data. The save register 26 in this embodiment has a smaller storage capacity than the register 22, for example, a storage capacity sufficient to store one piece of data. Here, the register 22 is capable of storing multiple pieces of data for program processing, and therefore requires address specification for the stored data. On the other hand, the save register 26 stores only one piece of data, and therefore does not require address specification. Therefore, data can be input to and output from the save register 26 easily and quickly. Furthermore, one PE 12 may be provided with multiple save registers 26 and be capable of storing multiple pieces of data.

[0048] As described above, the PE 12 of this embodiment inputs and outputs data to the arithmetic circuit 20, the register 22, and the save register 26 via the selector 24. Data movement between the PEs 12 is also performed via the selector 24. This data movement between the PEs 12 includes not only data movement between adjacent PEs 12, but also data movement between non-adjacent PEs 12, such as data movement to a PE 12 in a diagonal direction or a PE 12 that is more than one unit away.

[0049] Data movement via the selector 24 will be described with reference to Figure 1. The dashed-dotted lines in Figure 1 indicate diagonal data movement paths. That is, in the example of Figure 1, data movement from PE 12B to PE 12C is illustrated as indicated by arrow A. In this case, data movement from PE 12B to PE 12C is executed in a single process of a selector setting instruction and a data input / output instruction.

[0050] More specifically, the data input to PE12B passes through the selector 24 of PE12B and is held (input) in the save register 26 of PE12B. Then, in accordance with a new processing instruction, PE12B outputs the data held in the save register 26, and the output data passes through the selector 24 and is output in the direction of PE12A. PE12A controls the selector 24 so that the data input from PE12B is output in the direction of PE12C. This control of the selector 24 is performed in accordance with the above-mentioned processing instruction. Note that the control of the selector 24 may be performed, for example, by the arithmetic circuit 20 or by a dedicated control circuit built into the selector 24.

[0051] Then, the PE 12C stores (inputs) the data input from the PE 12B via the PE 12A in the save register 26 via the selector 24. In the example of Fig. 1, the data stored in the save register 26 of the PE 12C is output to another adjacent PE 12 via the selector 24 in accordance with the second processing instruction.

[0052] In this way, the PE 12A, which receives the data, simply outputs the data to the PE 12C via the selector 24, and does not perform any processing on the data. Therefore, the data is essentially output directly from the PE 12B to the PE 12C. By performing such a transfer process via the selector 24, the arithmetic device 10 of this embodiment can transfer data between the PEs 12 faster without increasing the number of wirings 14 between the PEs 12.

[0053] Furthermore, PE12B outputs data from the PE12 adjacent to the right to PE12D in accordance with the selector setting instruction, and stores data from the PE12 adjacent above in the save register 26. In this way, by giving the same selector setting instruction to all PE12, all PE12 can simultaneously directly move data to PE12 in the diagonal direction (other non-adjacent PE12).

[0054] In this embodiment, one processing by a selector setting instruction and an input / output instruction refers to the process in which data output from a storage unit such as the save register 26 or the register 22 passes through the selector 24 and is input (stored) again in a storage unit such as the save register 26 or the register 22. As will be described later, one processing instruction may include, in addition to the selector setting instruction and the input / output instruction, an arithmetic processing instruction for causing the arithmetic circuit 20 to perform arithmetic processing on the data.

[0055] Furthermore, if the bit width of data movement between PEs 12 is, for example, 32 bits, and the data to be moved is 8 bits, then movement between PEs 12 can be performed for four pieces of data at a time. Therefore, for example, when performing a diagonal data movement, such as moving data from PE 12B to PE 12C, diagonal movements in four directions can be performed simultaneously. In this way, data may be moved in multiple directions simultaneously using a movement pattern that takes into account the bit width of data movement between PEs 12 and the number of bits of data.

[0056] Furthermore, one PE 12 may be provided with multiple selectors 24. By providing one PE 12 with multiple selectors 24, data can be moved simultaneously in multiple directions. For example, a PE 12 provided with four selectors 24 can move data simultaneously in four directions. For example, the PE 12 may be provided with multiple selectors 24 that move data in byte units, and each selector 24 may be capable of moving data independently for each byte. When moving four bytes of data, the PE 12 can move data simultaneously using four selectors 24, thereby enabling multiple data moves simultaneously.

[0057] In addition, when multiple selectors 24 are provided in one PE 12, the multiple selectors 24 may share one wiring 14, or multiple wirings 14 may be provided between the PEs 12 corresponding to each selector 24.

[0058] (Another Example of Data Movement Between PEs) Hereinafter, another example of data movement between PEs 12 will be described with reference to FIGS.

[0059] 2 is a schematic diagram showing data movement from the save register 26 of a PE 12 to the register 22 of another non-adjacent PE 12. In the example of FIG. 2, data held in the save register 26 of PE 12B is moved to the register 22 of PE 12C.

[0060] Furthermore, PE 12B outputs data from the PE 12 adjacent to the right to PE 12D in accordance with the selector setting instruction, and stores data from the PE 12 adjacent above in the register 22. In this way, by giving the same selector setting instruction to all PEs 12, all PEs 12 can simultaneously directly move data to PEs 12 in diagonal directions (other non-adjacent PEs 12).

[0061] 3 is a schematic diagram showing data movement from the register 22 of a PE 12 to the save register 26 of another non-adjacent PE 12. In the example of FIG. 3, data held in the register 22 of PE 12B is moved to the save register 26 of PE 12C.

[0062] Furthermore, PE12B outputs data from the PE12 adjacent to the right to PE12D in accordance with the selector setting instruction, and stores data from the PE12 adjacent above in the save register 26. In this way, by giving the same selector setting instruction to all PE12, all PE12 can simultaneously directly move data to PE12 in the diagonal direction (other non-adjacent PE12).

[0063] As shown in FIGS. 2 and 3, data is moved from the register 22 or the save register 26 of one PE 12 to the register 22 or the save register 26 of another PE 12 via a selector 24 .

[0064] 4 is a schematic diagram showing data movement from one PE 12 to multiple other PEs 12 in the same row. As an example, FIG. 4 shows a case where data is output from a PE 12X in the second column from the left of the arithmetic device 10 to other PEs 12 arranged in the same row. In this way, in the example of FIG. 4, data movement is performed to other PEs 12 in the left and right directions from PE 12X.

[0065] 5 is a schematic diagram showing data movement from one PE 12 to all other PEs 12. As an example, FIG. 5 shows a case where data is output from a PE 12X in the second column from the left and second row from the top of the arithmetic device 10 to all other PEs 12 arranged in the same row. In the example of FIG. 5, when a PE 12X outputs data to another PE 12 in the same column, the PE 12 to which the data was input outputs the data to another PE 12 in the same row. In this way, in the example of FIG. 5, data movement to other PEs 12 in the up, down, left, and right directions is performed with PE 12X at the center.

[0066] In the examples of FIGS. 4 and 5, the data input to the PE 12 is held in the save register 26, but this is not limiting and the data may be held in the register 22.

[0067] (Example of Data Movement from External Memory to PE) Hereinafter, an example of data transfer from the external memory 30 to the PE 12 will be described with reference to FIGS.

[0068] 6 is a schematic diagram showing data transfer from external memory 30 to one PE 12 and data movement from that PE 12 to all PEs 12 constituting the arithmetic device 10. In the example of FIG. 6, data is transferred from external memory 30 to PE 12A in the upper left, and the same data is output from this PE 12A to all other PEs 12. In the example of FIG. 6, each PE 12 holds data in register 22 via selector 24. This allows data to be transferred from external memory 30 to all PEs 12 in a single process.

[0069] 7 is a schematic diagram showing data movement from the external memory 30 on a row-by-row basis. In the example of FIG. 7, the same or different data is transferred from the external memory 30 to the PEs 12A, 12E, 12I, and 12M included in the leftmost column, and data is then transferred from the PEs 12A, 12E, 12I, and 12M to other PEs 12 in the same row. In the example of FIG. 7, each PE 12 holds data in the register 22 via the selector 24. This allows data to be transferred from all of the external memories 30 to the PEs 12 in a single process.

[0070] Alternatively, different data may be output from the external memory 30 in stages, and different data may be stored in the register 22 of each PE 12. For example, in the configuration of FIG. 7 , in a first processing run, data “1” is transferred from the external memory 30 to the PE 12A. In a second processing run, data “2” is transferred from the external memory 30 to the PE 12A, and data “1” is moved from the PE 12A to the PE 12B. In a third processing run, data “3” is transferred from the external memory 30 to the PE 12A, and data “2” is moved from the PE 12A to the PE 12B, and data “1” is moved from the PE 12B to the PE 12C. In a fourth processing run, data “4” is transferred from the external memory 30 to the PE 12A, and data “3” is moved from the PE 12A to the PE 12B, data “2” is moved from the PE 12B to the PE 12C, and data “1” is moved from the PE 12C to the PE 12D. As a result, after four processing steps, the PE 12A holds data "4", the PE 12B holds data "3", the PE 12C holds data "2", and the PE 12D holds data "1".

[0071] Furthermore, when data is transferred from the external memory 30 to each PE 12 by burst transfer, each PE 12 receives only the necessary data at the necessary timing from the external memory 30. In burst transfer, data may not be transferred one by one to each PE 12, but multiple pieces of data may be transferred together.

[0072] Furthermore, when data at an arbitrary address is transferred from the external memory 30 to each PE 12, each PE 12 holds a relative address and holds only the data at that relative address from among the data being transferred from the external memory 30 in the register 22 of the PE 12.

[0073] All PEs 12 do not necessarily need to have an access circuit to the external memory 30; for example, only the PEs 12 in the first column or the PEs 12 in odd-numbered columns may have such a circuit. A PE 12 to which data has been transferred from the external memory 30 may move the data to another PE 12 while performing other processing, or may receive data from another PE 12. The data may be compressed, and the PE 12 may have a function of decompressing compressed data and a function of compressing data.

[0074] Alternatively, the PEs 12 at the ends in the column direction may be provided with an access circuit to the external memory 30, and data may be transferred from the external memory 30 column by column. The PEs 12 at the left and right ends in the row direction may be provided with an access circuit to the external memory 30, and data may be transferred from the external memory 30 to the PEs 12 simultaneously from the left and right in the row direction. This further shortens the time required for data movement. Similarly, the PEs 12 at the top and bottom ends in the column direction may be provided with an access circuit to the external memory 30, and data may be transferred from the external memory 30 to the PEs 12 simultaneously from the top and bottom in the column direction. Data may be transferred from the external memory 30 to the PE 12 located in the center of the row or column, and then the data may be moved from there to the PEs 12 above, below, or to the left and right.

[0075] 8, a PE 12 may have two interconnections 14 between it and another adjacent PE 12 in the same row, so that the PE 12 may simultaneously transfer data to the other adjacent PE 12 and to the PE 12 that is not adjacent to it, which allows faster data transfer between PEs 12. The provision of two interconnections 14 between adjacent PEs 12 is hereinafter also referred to as "duplicating (multiplexing) the interconnections 14."

[0076] (Data Movement Accompanying Arithmetic Processing) The PE 12 of this embodiment performs arithmetic processing on data moved from another PE 12 via the selector 24 by connecting the selector 24 to the arithmetic circuit 20. That is, the PE 12 of this embodiment makes it possible to execute data movement between PEs 12 and arithmetic processing by the arithmetic circuit 20 in a single process of a selector setting instruction and a data input / output instruction. This enables the speed of processing that combines arithmetic processing and data movement.

[0077] 9 is a schematic diagram showing data movement accompanying arithmetic processing by the arithmetic circuit 20 of this embodiment. The example of FIG. 9 shows a case where the PE 12B located in the second column sums the results of arithmetic processing by each of the PEs 12A to 12D constituting a row, and outputs the summed result to another PE 12. Note that the PE 12B includes two save registers 26A and 26B.

[0078] First, in the first processing, the PEs 12A, 12C, and 12D perform arithmetic processing on the data held in the save register 26 using the arithmetic circuit 20, and output the results to the PE 12B. That is, the PE 12B aggregates the results of the operations performed by the multiple other PEs 12. Then, the PE 12B uses the arithmetic circuit 20 to add up the data input from the PEs 12A, 12C, and 12D and holds the sum in the save register 26B.

[0079] In the second processing, the arithmetic circuit 20 of the PE 12B adds together the data held in the save register 26B of the PE 12B and the data held in the save register 26A. The PE 12B then outputs (expands) the result of the addition to the other PEs 12A, 12C, and 12D. The other PEs 12A, 12C, and 12D store the data input from the PE 12B in the save register 26. The PE 12B also stores the result of the addition in the save register 26A.

[0080] In arithmetic operations such as and, or, and sum, data is aggregated in the PE 12 (PE 12B in the example of FIG. 9) located at the center in the row direction (left and right) or column direction (up and down) to shorten the overall data movement distance. Since the result of the arithmetic operation is obtained in the PE 12 located at the center, the data movement distance is also shortened when the arithmetic operation result is output (copied) to another PE 12.

[0081] A PE 12 that aggregates data from above, below, or from the left, right, or both may receive data via three or four inputs instead of two inputs and perform arithmetic processing. Therefore, the configuration of the PE 12 where data is aggregated may be different from that of the other PEs 12. In the example of FIG. 9 , the PE 12B where data is aggregated includes two save registers 26A and 26B. The PE 12 where data is aggregated may also perform arithmetic processing in multiple steps, such as by row or column. Furthermore, the wiring 14 between the PEs 12 may be doubled, and the first aggregation and second expansion as shown in FIG. 9 may be performed at the same time.

[0082] The PE 12 may include a plurality of arithmetic circuits 20. The arithmetic circuits 20 may have the same or different arithmetic processing functions. The PE 12 including a plurality of arithmetic circuits 20 may transfer data between the arithmetic circuits 20 via a selector 24.

[0083] 10 is a schematic diagram showing data movement when the arithmetic device 10 of this embodiment performs a convolution operation. In the example of FIG. 10, a 2×2 convolution operation is repeatedly performed in four processes. In FIG. 10, the diagram on the left side of each process shows data movement in one PE 12, and the diagram on the right side shows data movement in multiple PEs 12 included in the arithmetic device 10 with arrows.

[0084] First, in the first processing, data is stored (copied) from the register 22 in the PE 12 to the save register 26. This data is multiplied in advance by a weight for the convolution operation.

[0085] In the second processing, the PE 12 moves the data it holds in its register 22 to the PE 12 on the left. As a result, data is moved to the PE 12 from the PE 12 on the right, and the arithmetic circuit 20 adds this moved data to the data held in the save register 26. The result of this addition is held in the save register 26.

[0086] In the third processing, the PE 12 moves the data it holds in its register 22 to the upper PE 12. Therefore, data is moved to the PE 12 from the lower PE 12, and the arithmetic circuit 20 adds this moved data to the data held in the save register 26, and the addition result is saved in the save register 26.

[0087] In the fourth processing, the PE 12 moves the data it holds in its register 22 to the upper left PE 12. Therefore, data is moved from the lower right PE 12 to the PE 12, and the arithmetic circuit 20 adds this moved data to the data held in the save register 26, and the addition result is saved in the save register 26.

[0088] The calculation device 10 may perform convolution calculations with fewer iterations or may be able to calculate a larger kernel size by multiplexing the wiring 14 between the PEs 12 .

[0089] 11 and 12, data movement will be described when the arithmetic device 10 of this embodiment includes an arithmetic circuit 20 that performs a specific process in only some of the PEs 12. When performing a specific process, data is moved to some of the PEs 12 via a selector 24. Providing a specific arithmetic circuit 20 in only some of the PEs 12 means that, for example, an arithmetic circuit 20 that is used relatively infrequently, such as exp, log, sin, asin, or floating-point calculation, is not provided in all of the PEs 12, but is provided in every other row or column, for example.

[0090] Furthermore, specific arithmetic circuits 20 may be distributed among the PEs 12. For example, to prevent unevenness in the circuit scale of the PEs 12, the log arithmetic circuits 20 are provided only in the PEs 12 in odd-numbered rows and even-numbered columns, and the sin arithmetic circuits 20 are provided only in the PEs 12 in even-numbered rows and odd-numbered columns.

[0091] 11 and 12 show an example in which only the PE 12A in the odd-numbered rows and odd-numbered columns has the exp operation circuit 20, and the PE 12A performs the exp operation on the data held in the registers 22 of the PEs 12A to 12D.

[0092] First, in the first processing, the PE 12 A performs the arithmetic operation of exp on the data held in its own register 22 , and holds the result of the operation in the register 22 .

[0093] In the second processing, the PE 12B moves data to the PE 12A via the PEs 12D and 12C. The PE 12A performs the exponential operation on the data moved from the PE 12B, moves the operation result to the PE 12B, and the PE 12B stores the operation result in the register 22.

[0094] In the third processing, the PE 12C moves data to the PE 12A. The PE 12A performs the exponential operation on the data moved from the PE 12C, moves the operation result to the PE 12C via the PEs 12B and 12D, and the PE 12C stores the operation result in the register 22.

[0095] In the fourth processing, the PE 12D moves data to the PE 12A via the PE 12C. The PE 12A performs the exp operation on the data moved from the PE 12D, moves the operation result to the PE 12D via the PE 12B, and the PE 12D stores the operation result in the register 22.

[0096] (Row-by-Row Processing) The arithmetic unit 10 of this embodiment may assign multiple arithmetic operations to each row to process multiple rows at once. For example, the first row may be assigned mul, the second row to add, the third row to rshift, and the fourth row to clip.

[0097] Furthermore, the arithmetic device 10 of this embodiment may read (input) data and write (output) data simultaneously with the arithmetic processing, so that the arithmetic circuit 20 may perform processing similar to that of a pipeline.

[0098] For example, in the first processing, the PE 12 in the first row reads data 1 from the external memory 30. In the second processing, the PE 12 in the first row reads data 2 from the external memory 30, while processing data 1 in the arithmetic circuits 20 provided in the PEs 12 in the first to fourth rows, and stores the data in the register 22 of the PE 12 in the fourth row. In the third processing, the PE 12 in the first row reads data 3 from the external memory 30, while processing data 2 in the arithmetic circuits 20 provided in the PEs 12 in the first to fourth rows, and stores the data in the register 22 of the fourth row, and the PE 12 in the fourth row writes the processing result of data 1 to the external memory 30.

[0099] The arithmetic unit 10 repeats this series of processes in a pipeline process corresponding to the required data, thereby enabling the processing from the arithmetic processing on the data to the writing of the arithmetic processing results to the external memory 30 to be completed in the time it takes to read the data from the external memory 30.

[0100] Furthermore, instead of acquiring data from the external memory 30, the PE 12 may acquire the data from the register 22 of another PE 12 that stores data that has already been processed. Furthermore, the processed data may be output to the register 22 of a PE 12 that does not have an arithmetic circuit 20, rather than to the external memory 30. This reduces the time required for data input / output when different processes are executed consecutively. In this case, the data capacity that can be held by the register 22 of the PE 12 in the first and last rows may be increased. Furthermore, if arithmetic processing is performed in the column direction, the data capacity that can be held by the register 22 of the PE 12 in the first or last column may be increased.

[0101] In addition, a data storage unit may be provided outside the first row, outside the last row, outside the first column, and outside the last column, and data may be input from this data storage unit to PE12 or output from PE12 to the data storage unit.

[0102] Also, assuming that the number of rows to be processed is small, PEs 12 with larger capacity registers 22 may be provided for every several rows, and data may be transferred from these PEs 12 to the external memory 30 .

[0103] Furthermore, if the number of rows of PE12 provided in the calculation device 10 is insufficient and the processing to be executed needs to be performed in multiple processes, the first calculation processing performed by PE12 from the first row to the last row may be stored in register 22 provided in PE12 in the last row, and in the second calculation processing, the results of the calculation processing from the last row to the first row may be stored in register 22 of PE12 in the first row, and such processing may be repeated.

[0104] Furthermore, when an operation is being performed by a PE 12 in a different column, the operation may be performed while data is being moved from the PE 12 in the different column.

[0105] Furthermore, data for which arithmetic processing has been completed in the final row may be moved to the register 22 in the row above, and used in the next pipeline processing, without being stored in the save register 26 of the final row. This eliminates the need to provide multiple save registers 26 in the final row, and allows the next processing to be started consecutively from the row above. Similarly, data may not be stored in the save register 26 or register 22 of the PE 12 that has completed arithmetic processing, but may be stored in an available save register 26 or register 22 of another PE 12.

[0106] (Configuration of an arithmetic device in which some of the wiring connecting PEs is thinned out) In the arithmetic device 10 of this embodiment, wiring 14 used for moving data between PEs 12 may be provided for each PE 12 at a predetermined interval. Fig. 13 is a schematic diagram showing the configuration of the wiring 14 between PEs 12. Fig. 13(A) shows a normal configuration in which wiring 14 is provided between all adjacent PEs 12, and Fig. 13(B) shows a configuration in which some of the wiring 14 is thinned out.

[0107] 13B, the wiring 14 connecting the PEs 12 in the column direction is provided for every other PE 12. That is, in FIG. 13B, the number of wirings 14 in the column direction is half that of a normal wiring. Note that the wirings 14 may also be thinned out in the row direction.

[0108] 14 and 15, a diagonal data movement in a configuration in which the wiring 14 is thinned out will be described.

[0109] Fig. 14 shows the first processing of diagonal data movement in a configuration in which the wiring 14 has been thinned out, and Fig. 15 shows the second processing. Note that Figs. 14(A) and 15(A) show data movement in four adjacent PEs 12. Figs. 14(B) and 15(B) show the positions of the four adjacent PEs 12 shown in Figs. 14(A) and 15(A) in the arithmetic device 10 with dashed lines. As shown in Figs. 14 and 15, in a configuration in which the wiring 14 has been thinned out, as an example, the selectors 24 are set for four adjacent PEs 12 as a group, and data movement is performed in two stages.

[0110] Furthermore, it is assumed that the form of thinning out the wiring 14 will be used in a multidimensional array in which the PEs 12 are arranged in three, four or more dimensions.

[0111] In a multidimensional array, PEs 12 are represented in a multidimensional coordinate system that includes two dimensions indicating the up, down, left, and right directions (matrix and column directions, XY directions) as well as other directions (such as the ZW direction). In a multidimensional array, PEs 12 are capable of inputting and outputting data between adjacent PEs 12 in the XY direction, and are also capable of inputting and outputting data between adjacent PEs 12 in other dimensions such as the ZW direction. This configuration of the arithmetic device 10 makes it possible to reduce the number of wirings 14 between PEs 12 required for data movement.

[0112] When the PEs 12 are arranged in three or more dimensions, each PE 12 is connected to the PEs 12 in the XY direction and the ZW direction by wiring 40. However, data movement between PEs 12 in the ZW direction is less frequent than data movement between PEs 12 in the XY direction. Therefore, as described above, the circuit configuration may be simplified by thinning out some of the wiring 14 in the ZW direction, which is less frequently used.

[0113] (Sorting Process) A sorting process will be described below in which values ​​held in the registers 22 of multiple PEs 12 are sorted in ascending or descending order. The sorting process involves repeatedly determining whether the score data indicating the magnitudes held in the registers 22 of two PEs 12 is larger or smaller in the arithmetic circuit 20 of one of the PEs 12, and moving the data according to the magnitude relationship of the score data. The arithmetic circuit 20 for this purpose functions as a switching circuit that changes the PE 12 that holds the score data according to the magnitude relationship of the score data.

[0114] 16 is a schematic diagram showing the movement of score data when sorting is performed by the arithmetic device 10 of this embodiment. In this embodiment, the PEs 12 in the row direction are connected by two wires 14, and in one process, it is possible to input and output score data from one PE 12 to another PE 12, determine whether the score data is large or small, and move data according to the relationship in size of the score data.

[0115] 16 , in the first processing, score data exchange processing is performed between adjacent PEs 12A and 12B. Specifically, the score data held in the register 22 of PE 12B is input to the arithmetic circuit 20 of PE 12A via the selector 24, and the score data held in the register 22 of PE 12A is input to the arithmetic circuit 20 of PE 12A. The arithmetic circuit 20 of PE 12A determines whether the two pieces of score data are larger or smaller. The score data with the smaller value is then stored in the save register 26 of PE 12A, and the score data with the larger value is stored in the save register 26 of PE 12B.

[0116] Similarly, the arithmetic circuit 20 of PE12C determines whether the score data held in PE12C is larger or smaller than the score data held in PE12D, and the score data with the smaller value is held in the save register 26 of PE12C, and the score data with the larger value is held in the save register 26 of PE12D.

[0117] In the second processing, score data exchange processing is performed between adjacent PEs 12 in a direction different from that in the first processing. In the example of Fig. 16, the arithmetic circuit 20 of PE 12B determines whether the score data held in PE 12B is larger than the score data held in PE 12C, and the score data with the smaller value is held in the save register 26 of PE 12B, and the score data with the larger value is held in the save register 26 of PE 12C. Score data exchange processing is also performed between PE 12A and the PE 12 adjacent to it on the left side. Score data exchange processing is also performed between PE 12D and the PE 12 adjacent to it on the right side.

[0118] Then, by repeating the first and second processes, the score data held in the calculation device 10 is sorted.

[0119] In this way, when sorting score data held in a plurality of PEs 12, the arithmetic device 10 of this embodiment performs an exchange process in which a PE 12 determines the magnitude of the score data transferred between the PE 12 and another adjacent PE 12 via the selector 24, and transfers the score data to the other PE 12 depending on the result of the magnitude determination. The exchange process is then repeated with different combinations of two adjacent PEs 12. The arithmetic circuits 20 that determine the magnitude of the score data may use PE 12B or PE 12D in the first and second times, and the arrangement of the arithmetic circuits 20 that determine the magnitude of the score data may be thinned out.

[0120] Next, with reference to Figures 17 and 18, a case will be described in which the number of score data to be sorted is equal to or less than the number of PEs 12 in one row. In the example of Figures 17 and 18, there are eight PEs 12 in one row, and eight score data are to be sorted. That is, each PE 12 in the first row holds one piece of score data. In such a case, sorting can be performed in a single process. Note that Figure 17 is an overall diagram of the PEs 12 that make up the arithmetic device 10. Figure 18 shows data movement in the eight PEs 12 within the area surrounded by the dashed line in Figure 17.

[0121] 17, the PE 12 in the first row performs an exchange process in which a magnitude determination is made between two adjacent PEs 12 to move the score data to the PE 12 in the second row depending on the result of the magnitude determination. Referring to Fig. 18, the PE 12A and PE 12B perform a magnitude determination between two score data, and depending on the result of the magnitude determination, the score data with the smaller value is moved from PE 12A to PE 12E in the second row, which is adjacent to PE 12B in the column direction. The score data with the larger value is moved from PE 12A to PE 12F in the second row, which is adjacent to PE 12B in the column direction, via the selector 24 of PE 12B.

[0122] Similarly, PE12C and PE12D compare the two score data to determine which is larger, and based on the result of the comparison, the score data with the smaller value is moved from PE12C to PE12G in the second row adjacent to PE12C in the column direction. The score data moved to PE12G is then moved to PE12F via selector 24. On the other hand, the score data with the larger value is moved from PE12C to PE12H in the second row adjacent to PE12D in the column direction via selector 24 of PE12D.

[0123] The PE 12F determines which of the two input score data is larger or smaller. Depending on the result of the size determination, the PE 12F moves the score data with the smaller value to the PE 12 in the third row adjacent to the PE 12F in the column direction, and moves the score data with the larger value to the PE 12 in the third row adjacent to the PE 12G in the column direction via the selector 24 of the PE 12G.

[0124] Similarly, the score data moved to PE12E and PE12H is compared with the score data of other PE12 adjacent in the row direction to determine whether they are larger or smaller, and then moved to the PE12 in the third row adjacent in the column direction. Then, the same exchange process as in the first and second rows is performed on the third row and below. Then, the score data is output in ascending or descending order from the final matrix. The score data is output to, for example, the external memory 30.

[0125] 17 and 18 and the form of performing multiple processes described with reference to Fig. 16 is that, while in Fig. 16 the score data is temporarily stored in the save register 26 each time an exchange process is performed on the score data of two adjacent PEs 12, in the example of Fig. 17 and 18 the score data after the exchange process is not stored in the save register 26. That is, in the example of Fig. 17 and 18, instead of storing the score data in the save register 26 each time an exchange process is performed, the score data is moved to the PE 12 in the row below, and the exchange process is repeatedly performed by two adjacent PEs 12 in the row below.

[0126] In this way, in the examples of FIGS. 17 and 18, the score data is not stored in the save register 26 or the register 22 during the sorting process, so that the sorting is completed in one process.

[0127] 19, data movement when sorting score data for multiple rows in the arithmetic device 10 will be described. That is, this example is a case where the number of score data to be sorted is greater than the number of PEs 12 for one row.

[0128] In the example of Fig. 19, the calculation device 10 has a total of 16 PEs 12A to 12P arranged in 4 rows and 4 columns. Score data is stored in each of these 16 PEs 12. That is, Fig. 19 illustrates a case where 16 pieces of score data are sorted using PEs 12 arranged in 4 rows and 4 columns.

[0129] In the first (odd-numbered) processing, the score data of two adjacent PEs 12 is exchanged. That is, in the first row, the score data is exchanged between PE 12A and PE 12B, and the score data is exchanged between PE 12C and PE 12D. The same applies to the second to fourth rows.

[0130] In the second (even-numbered) processing, the score data exchange process is performed between PE 12B and PE 12C in the same row, but the PE 12 at the end of each row exchanges score data with other PE 12 adjacent in the column direction. In the example of Figure 19, the score data exchange process is performed between PE 12D and PE 12H, between PE 12E and PE 12I, and between PE 12L and PE 12P. The even-numbered exchange process and the odd-numbered exchange process are then repeated until sorting is completed.

[0131] When sorting score data for multiple rows in the arithmetic device 10 in this manner, the PE 12 at the end of each row is virtually adjacent to the PE 12 at the end of the row below, and the PE 12 at the front end of the second row and onward is virtually adjacent to the PE 12 at the front end of the row below. That is, the score data is sorted by virtually treating the PEs 12 forming multiple rows as one row. In the example of Figure 19, the order of PEs 12A to 12D, 12H, 12G, 12F, 12E, 12I to 12L, 12P, 12D, 12N, and 12M is considered to be one row. This makes it possible to sort score data even if there are multiple rows.

[0132] As shown in FIG. 19, the PE 12 at the end in the row direction is connected to the PE 12 adjacent in the column direction by two wirings 14 .

[0133] Furthermore, if there are more score data than the number of PEs 12, for example, 64 score data, then as described above, four score data will be held in each of the 16 PEs 12 that are virtually considered to be one row. The four score data held in each PE 12 are distinguished by being assigned the same identification number, such as "1," "2," "3," and "4." Then, the odd-numbered exchange process shown in FIG. 19 is performed four times for each piece of score data with the same identification number among the four score data held in the PE 12, and then the even-numbered exchange process shown in FIG. 19 is performed four times for each piece of score data with the same identification number among the four score data held in the PE 12.

[0134] Here, PE12A and PE12M, which are at the ends of PE12 considered to be one row, require score data exchange processing within the same PE12 in even-numbered processing. In the example of 64 score data, PE12M exchanges the score data with identification number "1" and the score data with identification number "2" within the same PE12M, PE12A exchanges the score data with identification number "2" and the score data with identification number "3" within the same PE12A, and PE12M exchanges the score data with identification number "3" and the score data with identification number "4" within the same PE12M. This makes it possible to sort even if the number of score data is greater than the number of PE12.

[0135] Furthermore, when an exchange process is performed between adjacent PEs 12, destination data indicating the destination of the score data in the score data exchange process may be held, and other data may be moved in the same order as the score data based on the destination data. Note that the other data and the score data are associated with each other.

[0136] The destination data is data that indicates the movement of score data as a result of the exchange process according to the result of the magnitude judgment of the score data. The destination data is stored for the location where the score data exchange process is performed and the number of times the score data exchange process is performed. However, depending on the score data, exchange may not be performed as the number of exchange processes increases, in which case the exchange process may be terminated midway.

[0137] Furthermore, as described above, if the PEs 12 of the arithmetic device 10 are arranged not two-dimensionally but three-dimensionally or four-dimensionally, the PEs 12 located at the ends of the three or four dimensions may be virtually regarded as adjacent in the row direction, as described above, and sorting may be performed with fewer processing operations.

[0138] (Sorting by Index Order) In addition to sorting a plurality of data in ascending or descending order by determining the magnitude relationship of the score data indicating the magnitude as described above, there are also cases where the data is sorted in a predetermined order.

[0139] Specifically, when index data indicating the order of data is associated with each piece of data, the data held in each PE 12 is sorted based on the order indicated by this index data. Note that, hereinafter, data associated with index data will be referred to as input data to distinguish it from the index data. Furthermore, since the index data indicates the order of data, it is numbered consecutively, for example, "0," "1," "2," .... Therefore, no two PEs 12 are assigned the same index data.

[0140] Fig. 20 shows input data associated with index data before and after sorting. In the example of Fig. 20, as shown in (A), input data "a" to "h" are input to each PE 12 of the arithmetic device 10 in the order of "a" to "h", and each of the input data "a" to "h" is associated with one of the index data "7" to "0". The result of sorting the multiple input data thus input in the order of index data "0" to "7" is shown in Fig. 20(B).

[0141] Next, data movement between PEs 12 will be described with reference to Fig. 21. The data movement between PEs 12 shown in Fig. 21 is basically the same as the exchange processing shown in Figs. 17 and 18, but with the addition of the concept of index data. Note that input data associated with index data is held in the register 22 of each PE 12.

[0142] 21A shows the first or odd-numbered processing. The PE 12 exchanges index data with other adjacent PEs 12 based on the order indicated by the index data, and stores destination data indicating the destination of the index data between the adjacent PEs 12.

[0143] For example, the arithmetic circuit 20 of PE 12A performs a magnitude determination between the index data of PE 12A and the index data of PE 12B, and depending on the result of the magnitude determination, the index data with the smaller value is moved from PE 12A to PE 12E in the second row adjacent to PE 12A in the column direction. The index data with the larger value is moved from PE 12A via the selector 24 of PE 12B to PE 12F in the second row adjacent to PE 12B in the column direction. At this time, the arithmetic circuit 20 of PE 12A generates destination data and stores it in the save register 26. Similarly, in PEs 12C and 12D, an index data exchange process is performed between the two adjacent PEs 12, and the destination data is stored in the save register 26. Subsequently, processing is performed for the second and subsequent rows in the same manner as for the first row, and multiple rows are processed at once.

[0144] 21B shows the second or even-numbered processing. The PE 12 moves input data between adjacent PEs 12 based on the destination data of the index data. That is, in the even-numbered processing, the input data is moved based on the destination data indicating the destination of the index data, without determining whether the two pieces of input data are larger or smaller.

[0145] For example, the arithmetic circuit 20 of PE12A reads the destination data from the save register 26 of PE12A, and moves the input data of PE12A and the input data of PE12B based on the read destination data. That is, the input data of PE12A and the input data of PE12B are moved to PE12E or PE12F in the same way as the movement of the index data indicated by the destination data. Processing in the other PEs 12 is carried out in the same way. Subsequently, processing of the second and subsequent rows is carried out in the same way as the processing of the first row, and multiple rows are processed at once.

[0146] As a result, as shown in Fig. 20, the input data associated with index data will be sorted in the order indicated by the index data. Also, if multiple pieces of input data associated with index data are newly input to the calculation device 10 and the input order is the same as the previous time, the input data may be sorted by using the destination data generated previously. In other words, in this case, the process of Fig. 21(B) is performed instead of the process of Fig. 21(A).

[0147] In this way, when input data to a PE 12 is associated with index data indicating the arrangement order of the input data, the PE 12 determines whether the index data moved between it and another adjacent PE 12 is large via the selector 24, and moves the index data to the other PE 12 according to the result of the size determination, while retaining destination data indicating the destination of the index data. The PE 12 then moves the input data between it and another adjacent PE 12 based on the destination data.

[0148] As described above, when the arithmetic device 10 inputs input data associated with index data from the external memory 30 to the PE 12, the PE 12 moves the input data between itself and another adjacent PE 12 based on the destination data.

[0149] (Data Swapping by Selector Settings) In a predetermined process such as a transposition process that swaps row data and column data, the operation of the selector 24 may be set in advance so that data moves from one PE 12 to another PE 12.

[0150] When the distance over which data must be moved between PEs 12 is long, the data may be moved by burst-transferring a plurality of pieces of data from one or more PEs 12 to one or more PEs 12 .

[0151] (Sorting of Relative Addresses for Moving to Relative Address Locations) The arithmetic unit 10 may read data from the external memory 30 to relative address locations by sorting the relative addresses.

[0152] 22 is a schematic diagram showing relative addresses and input data rearranged by the sorting process of the arithmetic unit 10 when moving to a relative address position, with the numbers on the left indicating the processing order. Also, as an example, the number of PEs 12 arranged in the row direction is eight. That is, in the first processing, a state is shown in which relative addresses are input to each of the PEs 12 arranged in the row direction. Specifically, assuming that the PEs 12 are arranged from the left end of the row as PE12A, PE12B, ..., PE12H, a relative address "5" is input to PE12A, a relative address "1" is input to PE12B, a relative address "0" is input to PE12C, a relative address "7" is input to PE12D, a relative address "8" is input to PE12E, a relative address "0" is input to PE12F, a relative address "5" is input to PE12G, and no relative address is input to PE12H, which is set to "-".

[0153] In this way, some PEs 12 in the row direction are input with the same relative address as that input to other PEs 12, some are not input with a relative address, and some are input with a relative address but the relative address is not within the range of the input data.

[0154] 22, the relative address "8" is the ninth relative address, and is not processed at the same timing as "0" to "7", but is a relative address outside the input range. Therefore, in the second processing, the relative address "8" is converted to "+". Note that the "-" input to the PE 12G is also outside the input range, and is converted to "+".

[0155] In the third pass, the relative addresses are sorted in ascending order from the left. Note that the "+" sign, which is outside the input range, is considered to be the largest value and is moved to the right. The data movement information resulting from this sorting is stored in the save register 26 of the PE 12 as destination data 1.

[0156] In the fourth process, if the relative address is the same as the value on the left, the relative address is converted to "-". In this process, "+" is also converted to "-". The conversion information from "+" to "-" is held in the save register 26 as destination data 2.

[0157] In the fifth processing, relative addresses equal to or greater than "0" are moved to the PE 12 in the column corresponding to the same value. That is, PE 12A is in the first column and corresponds to "0", PE 12B is in the second column and corresponds to "1", and similarly, PE 12H is in the eighth column and corresponds to "7". Therefore, relative address "0" is moved to PE 12A, relative address "1" is moved to PE 12B, relative address "5" is moved to PE 12F, and relative address "7" is moved to PE 12G. Furthermore, data movement information for the fifth processing is held in the save register 26 of PE 12 as destination data 3.

[0158] In this way, by the first to fifth processes, the relative addresses are sorted in ascending order for the PEs 12A to 12H.

[0159] In the sixth processing, the input data is read from the external memory 30 and input to the PEs 12A to 12H in order, and is stored in each PE 12. That is, the input data is input from the external memory 30 to the PEs 12 so as to correspond to the relative addresses sorted in ascending order. The input data is then associated with the relative addresses stored in the PEs 12. Note that in this embodiment, the input data is read from the external memory 30, but this is not limiting, and the input data may be stored in the PEs 12 in advance. That is, in the sixth processing, the input data is associated with each of the relative addresses sorted in ascending order in the first to fifth processing.

[0160] In the seventh processing, the destination data 3 is used to perform an inverse transformation, so that the row order of the input data held in each PE 12 is made the same as the order of the relative addresses in the fifth processing.

[0161] In the eighth processing, the destination data 2 is used to perform an inverse conversion, thereby making the input data held in each PE 12 correspond to the relative address in the fourth processing.

[0162] In the ninth processing, the input data held in each PE 12 is made to correspond to the relative address in the third processing by performing an inverse conversion using the destination data 1.

[0163] In this way, in the sixth to ninth processing steps, the input data held by the PE 12 is moved and converted by the reverse order and reverse conversion in which the relative addresses are moved. As a result, the input data held by the PE 12 in the sixth processing step is held in the PE 12 at the original relative address position (the relative address position at the time of the first processing step).

[0164] In this manner, when a relative address is associated with the PE 12 of this embodiment, the PE 12 determines whether the relative address moved between it and another adjacent PE 12 is larger or smaller via the selector 24, and moves the relative address to the other PE 12 according to the result of the determination of the size, while retaining destination data indicating the destination of the relative address. Then, after the input data is associated with the moved relative address, the PE 12 moves the input data between it and another adjacent PE 12 in the reverse order of the movement indicated by the destination data.

[0165] As described above, when the arithmetic device 10 inputs input data associated with a relative address from the external memory 30 to the PE 12, the PE 12 moves the input data between itself and another adjacent PE 12 based on the move destination data.

[0166] 22 is processing for relative addresses from "0" to "7," the arithmetic unit 10 performs similar processing for relative addresses from "8" onwards, while limiting the range to "8" to "15," "16" to "23," etc. Also, if the values ​​and order of the relative addresses input to the arithmetic unit 10 are known in advance, destination data may be created in advance, and only reverse conversion may be performed when performing the processing shown in FIG.

[0167] (Sorting of data with index data in two dimensions) In this embodiment, index data for each PE 12 constituting the arithmetic device 10 is used as position information, and two-dimensional index data is specified for each PE 12 based on this one-dimensional index data.

[0168] For example, two-dimensional index data is specified for each PE 12 using consecutive numbers, with x representing columns and 0, 1, 2, ... from the left, and y representing rows and 0, 1, 2, ... from the top. If the number of columns of the two-dimensionally arranged PEs 12 is 8 and the one-dimensional index data is a, the two-dimensional index data (x, y) will be (the remainder when a is divided by 8, the quotient when a is divided by 8). In other words, if the one-dimensional index data is 21, the two-dimensional index data (x, y) will be (5, 2). In this way, the multiple PEs 12 specified with two-dimensional index data are virtually divided into multiple groups, and the data is sorted among the multiple PEs 12 for each group.

[0169] The following describes the sorting process of data for each group with reference to Fig. 23. In the example of Fig. 23, data is moved between four grouped PEs 12 in one processing run to perform the sorting process, so the wiring 14 between the PEs 12 may be multiplexed or each PE 12 may be provided with a plurality of arithmetic circuits 20 as needed.

[0170] First, in the first (odd-numbered) processing, the plurality of PEs 12 are virtually divided into first groups 40A each consisting of three or more adjacent PEs 12. For example, in the example of Fig. 23, a total of four PEs 12 arranged in two rows and two columns are grouped into one first group 40A.

[0171] Then, a first sorting process is performed in which a magnitude determination is made on the plurality of index data for each first group 40A, and the index data and the input data associated with the index data are moved according to the determination result. The sorting of data among the plurality of PEs 12 constituting a group is similar to the sorting by the exchange process described above. Note that in Figure 23, as an example, in the row-wise exchange process, data with a small value in a column position of the two-dimensional index data is moved to the PE 12 on the left, and in the column-wise exchange process, data with a small value in a row position of the two-dimensional index data is moved to the PE 12 on the upper side.

[0172] In the second (even-numbered) process after the first sorting process, three or more PEs 12 are virtually divided into a plurality of second groups 40B different from the first group 40A. In the example of Figure 23, PEs 12 located at the corners of the matrix do not form a group, PEs 12 in the row direction at the edge form second group 40B with two PEs 12 adjacent to each other on the left and right, and PEs 12 in the column direction at the edge form second group 40B with two PEs 12 adjacent to each other above and below. The inner PEs 12 form second group 40B with a total of four PEs 12 arranged in two rows and two columns.

[0173] Then, in even-numbered processing, a second sorting process is performed in which a magnitude determination is made on the plurality of index data for each second group 40B, and the index data and the input data associated with the index data are moved according to the determination result. The calculation device 10 repeats the first sorting process and the second sorting process the required number of times. In the example of Figure 23, sorting is completed after eight repetitions, which is the square root of the number of data.

[0174] This method of sorting data among multiple PEs 12 for each group can be applied not only to a case where the PEs 12 are arranged two-dimensionally in the row and column directions (x and y directions), but also to a configuration where the PEs 12 are arranged multidimensionally. In this configuration, even-numbered processes are executed by groups of PEs 12 arranged as elements in three or more dimensions (w and z directions). This allows sorting to be completed with fewer processes.

[0175] Furthermore, if it is desired to sort multiple pieces of data input to the calculation device 10 in the same order, destination data for the index data may be generated as described above and stored in the PE 12, and the data may be moved based on the destination data.

[0176] (Sorting Data with Two-Dimensional Index Data When the Number of Data is Greater than the Number of PEs) Next, a case where the number of input data to be sorted is greater than the number of PEs 12 and sorting processing is performed with two-dimensional index data will be described with reference to Figures 24 and 25. Note that Figure 24 shows odd-numbered processing, and Figure 25 shows even-numbered processing, where x represents the column number and y represents the row number.

[0177] 24 and 25, the calculation device 10 has 16 PEs 12, but the number of input data to the calculation device 10 is four times as many, or 64. If the number of input data to be sorted is greater than the number of PEs 12, each PE 12 holds multiple pieces of input data and assigns numbers to them. In the example of Figures 24 and 25, each PE 12 holds four pieces of input data, and each piece of input data is assigned an identification number from 1 to 4.

[0178] Then, a plurality of PE groups 42, which are a set of a plurality of PEs 12 that hold data with the same number, are virtually set. In the example of Fig. 24, the PE group 42A corresponds to the first data, the PE group 42B corresponds to the second data, the PE group 42C corresponds to the third data, and the PE group 42D corresponds to the fourth data.

[0179] Furthermore, the multiple PE groups 42 are set so that the PEs 12 constituting the PE group 42 are arranged in reverse order in at least one of the row and column directions relative to the reference PE group 42. In the example of FIG. 24 , the PE group 42A is the reference, and the PE group 42B is arranged in reverse order relative to the reference. The PE group 42C is arranged in reverse order relative to the reference, and the PE group 42D is arranged in reverse order relative to the reference in the row and column directions. Therefore, the PE groups 42B, 42C, and 42D are arranged such that the PEs 12 are folded up and down, left and right, or both, relative to the PE group 42A. To arrange the PEs in reverse order, a selector setting command is issued so that the data is in reverse order when inputting data. Conversely, a selector setting command is issued so that the reversed data is returned to normal order when outputting data. Furthermore, two wirings 14 may be provided between the PEs 12 so that data can be moved in both the forward and reverse directions simultaneously.

[0180] Then, the calculation device 10 performs a first sorting process for each first group 40A divided within the PE group 42, and then performs a second sorting process for each second group 40B including groups divided across multiple PE groups 42, and repeatedly performs the first sorting process and the second sorting process.

[0181] 24 corresponds to odd-numbered processing of the first sorting process. As shown in Fig. 24, each first group 40A exists in each PE group 42. The first sorting process performs a magnitude determination of a plurality of index data for each first group 40A, and performs an exchange process in which the index data and input data associated with the index data are moved between PEs 12 according to the determination result.

[0182] Figure 25 corresponds to an even-numbered execution of the second sorting process. As shown in Figure 25, some of the second groups 40B exist across multiple PE groups 42. The second sorting process involves determining whether multiple index data are larger or smaller for each second group 40B, and then performing an exchange process in which the index data and input data associated with the index data are moved between PEs 12 based on the determination result. Note that in Figure 25, the dashed line indicating the second group 40B beyond the PE groups 42B, 42C, and 42D represents the second group 40B in the case where a PE group 42 adjacent to the PE groups 42B, 42C, and 42D exists.

[0183] Here, the PE 12 located at the edge of each PE group 42 has the same x and y coordinates as the PE 12 in the other adjacent PE groups 42. That is, the input data of the second group 40B formed across the PE groups 42 is input data with different numbers held in the same actual PE 12. And the PE 12 adjacent to the other PE groups 42 in each PE group 42 is the outer edge PE 12X located at the edge of the actual PE 12. That is, in the second sorting process, the outer edge PE 12X sorts the multiple input data held by itself as the second group 40B.

[0184] For this reason, the outer edge PE 12X needs to sort four pieces of input data using one PE 12. Therefore, as shown in Fig. 26, a first spare PE 50 is provided adjacent to the outer edge PE 12X, which is used to sort the multiple pieces of input data held by the outer edge PE 12X in the second sorting process.

[0185] 26 , the PE 12 adjacent to the outer edge PE 12X surrounded by the dashed line is the first spare PE 50. The first spare PE 50 is not a virtual one, but a PE 12 actually provided in the calculation device 10, and the first spare PE 50 is connected to the adjacent first spare PE 50 and the outer edge PE 12X by wiring 14.

[0186] In the second sorting process, the outer edge PE 12X moves the input data it holds to the save register 26 of the first spare PE 50, and sorts the input data as the second group 40B together with the outer edge PE 12X and the first spare PE 50. Therefore, the first spare PE 50 includes the selector 24, the arithmetic circuit 20, and the save register 26, but does not necessarily include the register 22.

[0187] In the above-described sorting by grouping when the number of input data is greater than the number of PEs 12, even when the PEs 12 are multidimensional, the input data of the even element number in each dimension and the next element number are exchanged at odd-numbered times, totaling 2 times the number of dimensions. Then, the input data of the odd element number in each dimension and the next element number are exchanged at even-numbered times, totaling 2 times the number of dimensions.

[0188] 27 and 28, an example of a convolution operation using the second spare PE 52 will be described. The second spare PE 52 does not have an arithmetic circuit 20, but has a selector 24 and a save register 26 or a register 22. Data transfer between the PE 12 and the second spare PE 52 is performed via the selector 24.

[0189] FIG. 27 is a schematic diagram showing the relationship between the data and the PEs 12 used in the convolution calculation of this embodiment. In the example of FIG. 27 , the calculation device 10 includes 16 PEs 12 (4 rows and 4 columns), and each PE 12 holds multiple (9) pieces of data. That is, in FIG. 27 , multiple PEs 12 indicated by the same x and y coordinates are the same PE 12, and FIG. 27 shows that each PE 12 holds nine different pieces of data in a two-dimensional array. Note that a group of data for each (x, y) = (0,0) to (3,3) is called a data group. For example, the data groups in the upper left of FIG. 27 are "0" to "3," "10" to "13," "20" to "23," and "30" to "33." The data groups in the center, "44" to "47," "54" to "57," "64" to "67," and "74" to "77," are the data of interest that will be subjected to the convolution calculation.

[0190] The hatched data on the periphery of the central data group virtually represents data required to perform a convolution operation on the data of interest (hereinafter referred to as "required data"). The required data is represented by coordinates of x = -2, -1, 4, 5 and y = -2, -1, 4, 5. Of this required data, the data within the outer dashed dotted line is the required data used for a 5x5 convolution operation, and the data within the inner dashed dotted line is the required data used for a 3x3 convolution operation. As shown in Figure 27, the required data is data held as a data group surrounding the data of interest.

[0191] Therefore, in this embodiment, the necessary data is stored in the second spare PE 52 as shown in Figure 28 so that the necessary data can be used as part of the target data. That is, the PE represented by coordinates of x = -2, -1, 4, 5 and y = -2, -1, 4, 5 in Figure 28 is the second spare PE 52, and this second spare PE 52 is an actual PE. The data within the dashed line located at the end of the arrow pointing from PE 12 to the second spare PE 52 in Figure 28 is the necessary data stored in the second spare PE 52. Therefore, the second spare PE 52 obtains the necessary data from the corresponding other PE 12 via the selector 24 and stores it in the save register 26.

[0192] When a convolution operation is performed on the data of interest, the second spare PE 52 outputs the necessary data to the PE 12 (the PE 12 at the center in FIG. 28) via the selector 24. This simplifies the transfer of the necessary data to the PE 12, enabling faster processing.

[0193] 28, the second spare PE 52 is arranged outside each PE 12, but this is not limiting, and for example, the arithmetic device 10 may include one second spare PE 52 equipped with a save register 26 having a large storage capacity, and necessary data may be stored in this second spare PE 52. Furthermore, the wiring 14 between the second spare PE 52 and the PE 12 may be multiplexed as necessary.

[0194] (Sorting in SIMD Processing) In this embodiment, input data is divided into a plurality of data pieces by a predetermined number of bits and stored between a plurality of PEs 12, and processing is performed for each of the data pieces divided by the predetermined number of bits.

[0195] As an example, this embodiment describes a data sorting process among a plurality of PEs 12 that divides input data into a plurality of data pieces each having a predetermined number of bits and holds the data. That is, the sorting process of this embodiment sorts data in units of a predetermined number of bits. Note that the sorting process of this embodiment is performed in parallel using single instruction multiple data (SIMD) processing in order to simultaneously determine the magnitude of data and move the data for a plurality of sets of data within a single PE 12.

[0196] In this embodiment, as an example, 128-bit input data is input to the PE 12, and the PE 12 divides the input data into 32-bit pieces and stores them in the save register 26. That is, the PE 12 stores four pieces of 32-bit data in the save register 26. The example in Fig. 29 shows a state in which one PE 12 stores four pieces of data, with the leftmost PE 12A being the PE 12 in the first row and first column, and the PEs 12 being arranged two-dimensionally in the row and column directions.

[0197] Each piece of data held in each PE 12 is assigned a storage position (hereinafter referred to as a "data bit position") in the save register 26 to distinguish it from other data. That is, "1", "2", ..., "0a", "0b" written in each PE 12 indicate a data bit position. The data bit positions are consecutive across multiple PEs 12.

[0198] Although the register 22, the arithmetic circuit 20, the selector 24, and the save register 26 are not shown in FIG. 29, the PE 12 includes these components as in the other embodiments.

[0199] When the arithmetic device 10 performs a sorting process on a plurality of data, it first determines the size of the data to be paired within one PE 12, and then performs a first exchange process to move the data within the PE 12 depending on the result of the size determination.

[0200] 29 correspond to the first exchange process, and within one PE 12, the arithmetic circuit 20 determines whether the data at an even-numbered data bit position is larger than the data at an odd-numbered data bit position obtained by adding 1 to the even-numbered data bit position. That is, the data bit positions "0" and "1" of PE 12A form one pair, and "2" and "3" form another pair. Similarly, two pairs are generated in PEs 12B and 12C, and the data size relationship is determined between these pairs.

[0201] Then, data is moved within the PE 12 depending on the result of the magnitude determination. For example, if the data at data bit position "0" is larger than the data at data bit position "1", the data at data bit position "0" is moved to data bit position "1", and the data at data bit position "1" is moved to data bit position "0". As a result, the bit position of the data changes depending on the magnitude relationship of the data.

[0202] The magnitude determination of the data on a bit-by-bit basis is performed by outputting the data held in the save register 26 to the arithmetic circuit 20 via the selector 24. The data is then output from the arithmetic circuit 20 to the save register 26 via the save register 26, and is held at a data bit position according to the magnitude relationship.

[0203] In this way, in the first exchange process, the magnitude relationship of the data is determined only within one PE 12, and the data is moved within the PE 12. This data magnitude determination and movement are performed simultaneously for multiple sets of data within one PE 12. Therefore, this data magnitude determination and movement are performed within the PE 12 by SIMD processing.

[0204] 29 corresponds to the second exchange process, in which a different set from the odd-numbered exchanges is generated, the magnitude relationship of the data is determined, and data is moved within the PE 12. In the second exchange process of this embodiment, the magnitude of data to be used in another set is determined within one PE 12, and the magnitude of data moved between adjacent PEs 12 via the selector 24 is determined, and the data is moved according to the result of the magnitude determination. Note that the other set is a combination of multiple data different from the set generated in the first exchange process.

[0205] In the second exchange process, first, within one PE 12, data at an odd-numbered data bit position and data at an even-numbered data bit position obtained by adding 1 to the odd-numbered data bit position are paired (another pair). With reference to Figure 29, data bit positions "1" and "2" of PE 12A form one pair, data bit positions "5" and "6" of PE 12B form one pair, and data bit positions "9" and "0a" of PE 12C form one pair. As a result, in the second exchange process, another pair different from that in the first exchange process is generated.

[0206] Furthermore, in the second exchange process, data pairs are also generated between adjacent PEs 12. For this purpose, data is moved between adjacent PEs 12 via the selector 24. Referring to FIG. 29 , the data bit position "3" of PE 12A and the data bit position "4" of PE 12B form a pair, and the data bit position "7" of PE 12B and the data bit position "8" of PE 12B form a pair. In this way, in the second exchange process, data is also paired between adjacent PEs 12. Note that the data paired between adjacent PEs 12 is, for example, the data at the data bit position with the largest value of one PE 12 and the data at the data bit position with the smallest value of the other PE 12.

[0207] In the second exchange process, the magnitude relationship between these sets of data is determined, and the data is moved according to the result of the magnitude determination.

[0208] The sorting process of this embodiment repeats the first exchange process and the second exchange process. Note that in the sorting process of this embodiment, as described with reference to FIG. 19 , the PEs 12 forming multiple rows are virtually regarded as one row, and data is sorted.

[0209] In this embodiment, when sorting data between multiple PEs 12 that hold input data divided into multiple data pieces each having a predetermined number of bits, a first exchange process is performed in which the size of the multiple data pieces grouped together within one PE 12 is determined, and data is moved within the PE 12 depending on the result of the size determination. Then, as a second exchange process, the size of another multiple data piece grouped together within one PE 12 is determined, and the size of data moved between the PE 12 and another adjacent PE 12 via the selector 24 is determined, and data is moved depending on the result of the size determination. The arithmetic device 10 repeatedly performs the first exchange process and the second exchange process.

[0210] 30 is a schematic diagram showing two-dimensional sorting involving SIMD processing. In the example of FIG. 30, 128-bit input data is divided into eight 16-bit data pieces, and each PE 12 holds the data in two rows and four columns. As shown in FIG. 30, the data bit positions of the divided data are specified by consecutive numbers so that the data can be processed in a matrix across multiple PEs 12.

[0211] 30 , in the odd-numbered iteration of the first exchange process, the magnitude relationship of the data is determined for every two rows and two columns only within one PE 12, and the data is moved within the PE 12. For example, within PE 12A, data bit positions "0", "1", "10", and "11" are grouped into one set, and data bit positions "2", "3", "12", and "13" are grouped into another set. Then, a magnitude determination is made between the four pieces of data in each set generated within PE 12, and the data is moved according to the result of the magnitude determination.

[0212] In the even-numbered rounds, which are the second exchange processes, pairs different from those in the odd-numbered rounds are generated, the magnitude relationship of the data is determined, and data is moved within the PE 12. In the even-numbered rounds in Fig. 30, data pairs are also generated between adjacent PEs 12, as in the even-numbered rounds in Fig. 29. For this purpose, data is moved between adjacent PEs 12 via the selector 24.

[0213] In the example of FIG. 30, for example, data at data bit positions "1" and "2" in the PE 12A are grouped together, and a comparison is made between these two pieces of data to see which is larger, and the data is moved depending on the result of the comparison.

[0214] Furthermore, the data at data bit position "10" of PE12A and the data at data bit position "20" of the adjacent PE12D are grouped together. Furthermore, the data at data bit positions "11" and "12" of PE12A and the data at data bit positions "21" and "22" of PE12D are grouped together. Furthermore, the data at data bit position "3" of PE12A and the data at data bit position "4" of PE12B are grouped together.

[0215] Furthermore, the data at data bit position "13" of PE12A, the data at data bit position "14" of PE12B, the data at data bit position "23" of PE12D, and the data at data bit position "24" of PE12E are grouped together. Note that PE12A and PE12E are not adjacent to each other, but PE12A and PE12E are adjacent to PE12B and PE12C, respectively, and in the second exchange process, data groups are generated between such a plurality of PEs 12.

[0216] Then, in the second exchange process, the magnitude relationship between the multiple data sets within the PE 12 and between the multiple PEs 12 is determined, and the data is moved according to the result of the magnitude determination. Then, in the example of Fig. 30 as well, the first exchange process and the second exchange process are repeated.

[0217] In this embodiment, the number of rows and columns of data in one PE 12 is determined arbitrarily according to the number of bits of input data and the number of divisions of the data, and various circuits are configured according to the determination.

[0218] Furthermore, the method of dividing the data into a plurality of data sets for each predetermined number of bits is not limited to the above-described sorting process, and as shown in other embodiments, a diagonal movement, an arithmetic process via the selector 24, a convolution operation, or the like may be performed on the plurality of data sets divided for each number of bits. Also, the plurality of data sets divided for each number of bits may be returned to one data set and moved or operated on together.

[0219] Although the present disclosure has been described using the above-mentioned embodiments, the technical scope of the present disclosure is not limited to the scope described in the above-mentioned embodiments. Various modifications or improvements can be made to the above-mentioned embodiments without departing from the gist of the disclosure, and such modifications or improvements are also included in the technical scope of the present disclosure.

[0220] Next, the features of the present invention will be described as follows.

[0221] (Aspect 1) An arithmetic device (10) comprising a plurality of processors (12), wherein the processor comprises a selector (24) that outputs input data in a set direction, and the processor moves the data via the selector between non-adjacent processors or moves the data via the selector within the processor by a single processing of an instruction to set the selector and an instruction to input / output the data. (Aspect 2) The arithmetic device according to Aspect 1, wherein the processor comprises a register (22, 26) connected to the selector and holding the data. (Aspect 3) The arithmetic device according to Aspect 1 or Aspect 2, wherein the processor comprises a plurality of the selectors. (Aspect 4) The arithmetic device according to any one of Aspects 1 to 3, wherein the processor comprises an arithmetic circuit (20) connected to the selector and performing arithmetic processing on the data, and wherein data movement between the processor and arithmetic processing by the arithmetic circuit are performed by a single processing of an instruction to set the selector and an instruction to input / output the data. (Aspect 5) The arithmetic device according to Aspect 4, wherein the arithmetic circuit for performing a specific process is provided in some of the processors, and when the specific process is performed, data is moved to some of the processors via the selector. (Aspect 6) The arithmetic device according to any one of Aspects 1 to 5, wherein wiring used for moving data between the processors is provided for each of the processors at a predetermined interval. (Aspect 7) The arithmetic device according to any one of Aspects 1 to 6, wherein when sorting score data indicating sizes held in a plurality of the processors, the processor determines whether the score data moved between the processors via the selector is larger or smaller, and performs an exchange process in which the score data is moved to the other of the processors depending on the result of the size determination, and the exchange process is repeated with different combinations of two adjacent processors.(Aspect 8) The arithmetic device according to aspect 1, wherein the data input to the processor is associated with score data indicating the size of the data or index data indicating an order of arrangement, the processor determines whether the score data or the index data moved between the adjacent processors via the selector is larger or smaller, and moves the score data or the index data to the other processor according to the result of the size determination, and holds destination data indicating a destination of the score data or the index data, the processor moves the data between the adjacent processors based on the destination data. (Aspect 9) The arithmetic device according to aspect 1, wherein a relative address indicating a destination where the data is to be held is associated with the processor, the processor determines whether the relative address moved between the adjacent processors via the selector is larger or smaller, and moves the relative address to the other processor according to the result of the size determination, and holds destination data indicating a destination of the relative address, and after the data is associated with the relative address after movement, the processor moves the data between the adjacent processors based on the reverse order of movement indicated by the destination data. (Aspect 10) The arithmetic device according to aspect 8 or aspect 9, wherein when the score data, the index data, or the data associated with the relative address is input from an external memory (30) to the processor, the processor moves the data between adjacent other processors based on the destination data.(Aspect 11) The arithmetic device according to aspect 8, wherein the processors are virtually divided into first groups consisting of three or more adjacent processors, a first sorting process is performed for each of the first groups to determine whether a plurality of pieces of index data are large or small, and the index data and the data associated with the index data are moved according to the determination result, and then the three or more adjacent processors are virtually divided into second groups different from the first groups, a second sorting process is performed for each of the second groups to determine whether a plurality of pieces of index data are large or small, and the index data and the data associated with the index data are moved according to the determination result, and the first sorting process and the second sorting process are repeatedly performed. (Aspect 12) The arithmetic device according to aspect 11, wherein, when the number of data to be sorted is greater than the number of processors, one of the processors assigns numbers to each of the multiple pieces of data and holds them, and virtually sets multiple processor groups as a collection of multiple processors holding the data assigned the same numbers, the multiple processor groups are set such that the processors constituting the multiple processor groups are in reverse order in at least one of the row direction and the column direction with respect to the reference processor group, and after performing the first sorting process for each of the first groups divided within the processor group, the second sorting process is performed for each of the second groups including groups divided across the multiple processor groups, and the first sorting process and the second sorting process are repeatedly performed. (Aspect 13) The arithmetic device according to aspect 12, wherein, adjacent to the outer edge processors located at the edges of the processors arranged two-dimensionally, a first spare processor is provided as a processor used for sorting the multiple pieces of data held by the outer edge processors in the second sorting process. (Aspect 14) The arithmetic device according to any one of Aspects 1 to 13, wherein input data is divided into a plurality of pieces of data by a predetermined number of bits and stored among a plurality of the processors, and processing is performed for each of the pieces of data divided by the predetermined number of bits.(Aspect 15) The arithmetic device according to any one of Aspects 1 to 14, comprising an auxiliary processor (52) having no arithmetic circuit, and having the selector and a register for holding the data, wherein the processor and the auxiliary processor move data via the selector. (Aspect 16) The arithmetic device according to any one of Aspects 1 to 15, wherein an operation for executing a function required of the arithmetic device is set in advance or by data for each of the processors, and each of the processors performs a different operation in accordance with the requirement of the function. (Aspect 17) A data movement method for an arithmetic device composed of a plurality of processors, wherein each of the processors has a selector that outputs input data in a set direction, and wherein the processor moves the data via the selector between other non-adjacent processors, or moves the data via the selector within the processor, by processing a single instruction to set the selector and an instruction to input / output the data.

Claims

1. An arithmetic device (10) comprising a plurality of processors (12), each of which has a selector (24) that outputs input data in a set direction, and the processor moves the data between non-adjacent processors via the selector, or moves the data within the processor via the selector, by processing a setting command for the selector and an input / output command for the data in a single operation.

2. The arithmetic device according to claim 1, wherein the processor comprises a register (22, 26) connected to the selector for holding the data.

3. The arithmetic device according to claim 1 or 2, wherein the processor comprises a plurality of the selectors.

4. The arithmetic device according to claim 1 or 2, wherein the processor comprises an arithmetic circuit (20) connected to the selector and performing arithmetic processing on the data, and data movement between the processor and the arithmetic processing by the arithmetic circuit are performed in a single processing of a setting command for the selector and an input / output command for the data.

5. The arithmetic device according to claim 4, wherein the arithmetic circuit for performing a specific process is provided in a portion of the processors, and when the specific process is performed, data is moved to the portion of the processors via the selector.

6. The arithmetic device according to claim 1 or 2, wherein wiring used for data transfer between said processors is provided for each of said processors at a predetermined interval.

7. The arithmetic device according to claim 1 or claim 2, wherein when sorting process of score data indicating size held in a plurality of said processors, said processor judges whether the score data moved between said processors via said selector is larger or smaller, and performs an exchange process in which said score data is moved to the other said processor depending on the result of the judgment of the size, and repeats said exchange process with different combinations of two adjacent said processors.

8. The arithmetic device of claim 1, wherein the data input to the processor is associated with score data indicating the size of the data or index data indicating the order of the data, the processor determines whether the score data or the index data moved between the processor and an adjacent processor via the selector is larger or smaller, and moves the score data or the index data to the other processor depending on the result of the size determination, while retaining destination data indicating the destination of the score data or the index data, and the processor moves the data between the processor and an adjacent processor based on the destination data.

9. The arithmetic device of claim 1, wherein the processor is associated with a relative address indicating a destination where the data is to be stored, the processor determines whether the relative address moved between the processor and another adjacent processor via the selector is larger or smaller, and moves the relative address to the other processor depending on the result of the determination of the size while retaining destination data indicating the destination of the relative address, and after the data is associated with the relative address after the move, the processor moves the data between the processor and the other adjacent processor based on the reverse order of the move indicated by the destination data.

10. An arithmetic device as described in claim 8 or claim 9, wherein when the score data, the index data, or the data associated with the relative address is input from an external memory (30) to the processor, the processor moves the data between adjacent other processors based on the destination data.

11. The arithmetic device according to claim 8, further comprising: virtually dividing the plurality of processors into first groups consisting of three or more adjacent processors; performing a first sorting process in which a size determination is made on a plurality of the index data for each of the first groups, and the index data and the data associated with the index data are moved according to the determination result; virtually dividing the three or more adjacent processors into second groups different from the first groups; performing a second sorting process in which a size determination is made on a plurality of the index data for each of the second groups, and the index data and the data associated with the index data are moved according to the determination result; and repeatedly performing the first sorting process and the second sorting process.

12. The arithmetic device according to claim 11, wherein, when the number of data to be sorted is greater than the number of processors, one of the processors holds multiple pieces of data assigned numbers, and multiple processor groups are virtually set as a collection of multiple processors holding the data assigned the same numbers, the multiple processor groups are set such that the processors constituting the processor groups are in reverse order in at least one of the row and column directions relative to a reference processor group, the first sorting process is performed for each of the first groups divided within the processor groups, and then the second sorting process is performed for each of the second groups including groups divided across the multiple processor groups, and the first sorting process and the second sorting process are repeatedly performed.

13. The arithmetic device according to claim 12, further comprising a first spare processor, which is a processor used for sorting the plurality of data held by the outer edge processor in the second sorting process, adjacent to the outer edge processor located at the edge of the two-dimensionally arranged processors.

14. The arithmetic device according to claim 1 or 2, wherein input data is divided into a plurality of data pieces each having a predetermined number of bits and stored between the plurality of processors, and processing is performed for each of the data pieces divided by the predetermined number of bits.

15. The arithmetic device according to claim 1 or 2, further comprising an auxiliary processor (52) having no arithmetic circuit, the auxiliary processor having the selector and a register for holding the data, and data transfer between the processor and the auxiliary processor is performed via the selector.

16. The arithmetic device according to claim 1 or 2, wherein the operation for executing a function required by the arithmetic device is preset or set by data for each of said processors, and each of said processors performs a different operation according to the requirements of that function.

17. A data movement method for an arithmetic device composed of multiple processors, wherein each processor has a selector that outputs input data in a set direction, and the processor moves the data via the selector between non-adjacent processors, or moves the data via the selector within the processor, by processing a setting command for the selector and an input / output command for the data in a single operation.

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