Information processing device, control method for same, and program

Abstract

Provided is an information processing device comprising: a first integrated circuit; a second integrated circuit; and a first bus and a second bus that independently connect the first integrated circuit and the second integrated circuit to each other. The first integrated circuit includes a first bus controller that controls communication via the first bus and a second bus controller that controls communication via the second bus. The first integrated circuit performs data transmission to the second integrated circuit via the second bus using the second bus controller when communication via the first bus is not usable.

Description

Information processing device, control method thereof, and program

[0001] The present invention relates to an information processing device including a plurality of integrated circuits, a control method therefor, and a control program therefor.

[0002] Some information processing devices include multiple integrated circuits that function independently of each other, and such information processing devices include a bus interface for transmitting and receiving data between the multiple integrated circuits.

[0003] The bus controller that controls the bus interface described above may have a function to reduce overall power consumption by transitioning to a low-power (inactive) state when communication between integrated circuits is not required. However, such a function may cause communication delays when returning from a power-saving state, or may not be able to effectively reduce power consumption depending on the frequency of communication that occurs.

[0004] The present invention has been made in consideration of the above-mentioned circumstances, and one of its objects is to provide an information processing device, a control method thereof, and a control program thereof that can efficiently realize communication between integrated circuits.

[0005] An information processing device according to one embodiment of the present invention is an information processing device comprising a first integrated circuit, a second integrated circuit, and a first bus and a second bus that connect the first integrated circuit and the second integrated circuit independently of each other, wherein the first integrated circuit comprises a first bus controller that controls communication via the first bus and a second bus controller that controls communication via the second bus, and when communication via the first bus is unavailable, the first integrated circuit transmits data to the second integrated circuit via the second bus using the second bus controller.

[0006] A control method for an information processing device according to one embodiment of the present invention is a control method for an information processing device comprising a first integrated circuit, a second integrated circuit, and a first bus and a second bus that independently connect the first integrated circuit and the second integrated circuit, wherein the first integrated circuit comprises a first bus controller that controls communication via the first bus and a second bus controller that controls communication via the second bus, and when the first integrated circuit is in a state where communication via the first bus is unavailable, the second bus controller transmits data to the second integrated circuit via the second bus.

[0007] According to one aspect of the present invention, there is provided a program for controlling an information processing device including a first integrated circuit, a second integrated circuit, and a first bus and a second bus that independently connect the first integrated circuit and the second integrated circuit, the first integrated circuit including a first bus controller that controls communication via the first bus and a second bus controller that controls communication via the second bus, the program causing the first integrated circuit to execute a process of transmitting data to the second integrated circuit via the second bus when communication via the first bus is unavailable. The program may be provided by being stored on a computer-readable, non-transitory information storage medium.

[0008] FIG. 1 is a configuration block diagram showing an example of the configuration of an information processing device according to an embodiment of the present invention. FIG. 2 is a timing chart for explaining the content of control executed by the subchip when the high-speed bus controller transitions to a power-saving state. FIG. 3 is a timing chart for explaining the content of control executed by the subchip when the high-speed bus controller is not transitioned to an active state when communication occurs while the high-speed bus controller is transitioned to a power-saving state. FIG. 4 is a diagram for comparing control during data transfer in the information processing device according to an embodiment of the present invention with control during data transfer in a conventional information processing device. FIG. 5 is a timing chart for explaining the content of control executed by the subchip when the high-speed bus controller is transitioned to an active state when communication occurs while the high-speed bus controller is transitioned to a power-saving state. FIG. 6 is a configuration block diagram showing an example of the configuration of an information processing device according to another embodiment of the present invention.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] 1 is a block diagram showing an example of the configuration of an information processing device 10 according to an embodiment of the present invention. Information processing device 10 may be a home game console, a portable information terminal, a personal computer, or the like, and as shown in the figure, includes a main chip 20, a sub-chip 30, a high-speed bus 41, a low-speed bus 42, a main memory 51, a USB interface 52, which is a communication interface based on the USB (registered trademark), and an Ethernet interface 53, which is a communication interface based on the Ethernet (registered trademark). Note that in this embodiment, the sub-chip 30, the main chip 20, the high-speed bus 41, and the low-speed bus 42 are examples of the first integrated circuit, the second integrated circuit, the first bus, and the second bus, respectively, of the present invention.

[0011] The main chip 20 is an integrated circuit incorporating a processor that executes primary information processing to realize the functions of the information processing device 10. The sub-chip 30 is an integrated circuit incorporating a processor that realizes auxiliary functions for the main chip 20, and is implemented as an integrated circuit independent of the main chip 20. The main chip 20 and the sub-chip 30 are connected by two types of buses that are independent of each other, a high-speed bus 41 and a low-speed bus 42, and are capable of transmitting and receiving data to and from each other via these buses. In this embodiment, both the high-speed bus 41 and the low-speed bus 42 are buses that allow bidirectional data communication.

[0012] 1, the main chip 20 incorporates a main processor unit 21, a high-speed bus controller 22, a low-speed bus controller 23, a memory controller 24, and a DMA controller 25. The main chip 20 may incorporate various circuits other than those shown here. It may also be provided with an interface for connecting to other electronic components not shown.

[0013] The main processor unit 21 is a processor that performs various arithmetic operations according to programs stored in the main memory 51 .

[0014] The high-speed bus controller 22 is a control circuit for controlling communication with the sub-chip 30 via the high-speed bus 41. The low-speed bus controller 23 is a control circuit for controlling communication with the sub-chip 30 via the low-speed bus 42.

[0015] The high-speed bus 41 is a bus that can perform data communication at a relatively high speed compared to the low-speed bus 42. Here, the high-speed bus 41 is a bus that performs data communication based on the PCI Express (registered trademark) standard, but the embodiment of the present invention is not limited to this.

[0016] The low-speed bus 42 is a bus that performs data communication at a relatively slower speed than the high-speed bus 41. In other words, the low-speed bus 42 has a smaller data transfer amount per unit time than the high-speed bus 41, and a smaller band (bandwidth) for data transfer than the high-speed bus 41. Specifically, for example, the low-speed bus 42 may be a bus that performs data communication based on an interface standard such as Quad SPI, I3C (registered trademark), or MIPI (registered trademark) M-PHY (registered trademark).

[0017] The memory controller 24 is a control circuit connected to the main memory 51 and controls access to the main memory 51. The DMA controller 25 is a control circuit for realizing direct memory access. These circuits may all be realized by known techniques.

[0018] In this embodiment, the sub-chip 30 incorporates a microcontroller 31, a high-speed bus controller 32, a low-speed bus controller 33, a USB controller 34, an Ethernet controller 35, an internal memory 36, a DMA controller 37, and a timer 38. The sub-chip 30 may incorporate various circuits other than those shown here. It may also be provided with an interface for connecting to other electronic components not shown.

[0019] The microcontroller 31 is a processor for controlling the overall operation of the subchip 30, and performs various arithmetic processing in accordance with programs stored in the internal memory 36, etc. In particular, in this embodiment, the microcontroller 31 controls switching between inter-processor communications using the high-speed bus 41 and the low-speed bus 42. Specific examples of control processing executed by the microcontroller 31 in this embodiment will be described later.

[0020] The high-speed bus controller 32 is a control circuit for controlling communication with the main chip 20 via the high-speed bus 41. As described above, the high-speed bus controller 32 performs communication based on the PCI Express standard. The low-speed bus controller 33 is a control circuit for controlling communication with the main chip 20 via the low-speed bus 42. The high-speed bus controller 32 and the low-speed bus controller 33 in this embodiment are examples of the first bus controller and the second bus controller, respectively, of the present invention.

[0021] In this embodiment, the high-speed bus controller 32 controls its own state transition to reduce power consumption. Specifically, the high-speed bus controller 32 transitions to one of multiple states depending on the situation. These multiple states include an active state in which communication with the main chip 20 is possible, and a power-saving state in which communication is restricted but consumes less power than the active state. If the high-speed bus controller 32 does not communicate with the main chip 20 for a predetermined period of time, it automatically transitions to the power-saving state. This allows for reduced power consumption compared to when the high-speed bus controller 32 always operates in the active state.

[0022] The USB controller 34 is a control circuit connected to the USB interface 52 and performs data communication with a USB device connected to the information processing device 10 via the USB interface 52 .

[0023] The Ethernet controller 35 is a control circuit connected to the Ethernet interface 53 and executes data communication with network devices connected to the information processing device 10 via the Ethernet interface 53 .

[0024] The internal memory 36 stores some of the programs executed by the microcontroller 31 and the main processor unit 21 of the main chip 20. In particular, the microcontroller 31 may execute various control processes in accordance with the programs stored in the internal memory 36.

[0025] The DMA controller 37 is a control circuit for realizing direct memory access. The timer 38 is an electronic circuit for realizing a timekeeping function. These circuits may all be realized by known techniques.

[0026] In this embodiment, the main chip 20 and the sub-chip 30 communicate data with each other via either the high-speed bus 41 or the low-speed bus 42. In particular, when transmitting data from the sub-chip 30 to the main chip 20, the microcontroller 31 controls bus switching to determine which bus to transmit the data through. More specifically, the microcontroller 31 manages status information for each of the high-speed bus 41 and the low-speed bus 42, indicating whether communication is enabled or disabled. When a data transfer request (command) to the main chip 20 is issued, the data to be transmitted is written to either the data buffer for the high-speed bus 41 or the data buffer for the low-speed buffer 42, depending on the status information. The data stored in each data buffer is then transmitted to the main chip 20 by the corresponding bus controller. Therefore, as described in detail below, the microcontroller 31 can stop or start data transfer by each bus controller by changing the status information depending on the status of the high-speed bus controller 32 and the low-speed bus controller 33, thereby switching the bus used for data transmission at any timing.

[0027] Hereinafter, several specific examples of control executed by the microcontroller 31 when data is transmitted from the sub-chip 30 to the main chip 20 will be described.

[0028] First, as a first example, a control when the system startup process of the information processing device 10 is performed, such as when the power of the information processing device 10 is turned on, will be described.

[0029] When the system is started, the main processor unit 21 of the main chip 20 needs to load programs such as boot code and a BIOS program stored in the internal memory 36 of the sub chip 30 or in a flash memory (not shown) connected to the sub chip 30. Therefore, data transfer from the sub chip 30 to the main chip 20 is required.

[0030] On the other hand, to set the high-speed bus controller 32 to the active state, the microcontroller 31 must load firmware for the high-speed bus controller 32 and execute initialization processing. Prior to the initialization processing of the high-speed bus controller 32, the microcontroller 31 itself must load necessary programs from an external flash memory and execute initialization processing such as initializing various hardware. Data cannot be transferred from the subchip 30 to the main chip 20 via the high-speed bus 41 until the initialization processing of the high-speed bus controller 32 is completed.

[0031] Therefore, in this embodiment, at least a part of the data such as the boot code to be transmitted to the main chip 20 at system startup is transmitted via the low-speed bus 42. Here, the low-speed bus controller 33 does not require initialization processing and is capable of transmitting data without being controlled by the microcontroller 31.

[0032] An example of the startup process executed when the information processing device 10 is started will be described below with reference to the timing chart of FIG. 2. As shown in the figure, when the system starts up at time t0, the low-speed bus controller 33 first transmits a boot code to the main chip 20 via the low-speed bus 42 (S1). Note that the low-speed bus controller 33 does not require initialization and can immediately execute data transmission processing after system startup without going through the microcontroller 31. In this figure, the transfer of the boot code via the low-speed bus 42 is completed at time t1. Thereafter, the main processor unit 21 of the main chip 20 executes initialization processing, such as initializing various interfaces, based on the loaded boot code.

[0033] In parallel with the transmission of the boot code in S1, the microcontroller 31 of the sub-chip 30 executes a predetermined initialization process when the system starts up (S2). In the example shown in this figure, the initialization process of the microcontroller 31 is completed at time t2.

[0034] After the initialization process in S2 is completed, the microcontroller 31 then executes initialization process for the high-speed bus controller 32 (S3). Completion of this initialization process enables the subchip 30 to communicate via the high-speed bus 41. Therefore, at time t3 when the process in S3 is completed, the microcontroller 31 changes the low-speed bus 42 from a communication-enabled state to a communication-disabled state, and also changes the high-speed bus 41 from a communication-disabled state to a communication-enabled state (S4). As a result, any subsequent data transmission to the main chip 20 will be performed via the high-speed bus 41.

[0035] If the low-speed bus 42 were not present, the boot code would be transmitted via the high-speed bus 41 after the initialization process of the high-speed bus controller 32 is completed. Therefore, the transmission of the boot code after the start of system startup would be completed at a timing even later than time t3. In contrast, in this embodiment, the low-speed bus controller 33 transmits the boot code via the low-speed bus 42 in parallel with various initialization processes by the microcontroller 31. Therefore, the transmission of the boot code can be completed before time t3, when the initialization process of the high-speed bus controller 32 is completed, thereby shortening the time required for the entire system startup process.

[0036] Next, the control when the high-speed bus controller 32 transitions from the active state to the power-saving state after the system startup is complete will be described with reference to the timing chart of FIG.

[0037] When the data buffer of the high-speed bus 41 becomes empty (when there is no data to be transmitted), the high-speed bus controller 32 generates an interrupt to notify the microcontroller 31 of this (S11). In response to this, the microcontroller 31 switches the high-speed bus 41 from a communication enabled state to a communication disabled state (S12). As a result, no new data is written to the data buffer of the high-speed bus 41. As described above, the high-speed bus controller 32 automatically transitions to the power-saving state when communication ceases. Therefore, even if the microcontroller 31 does not actively control the state of the high-speed bus controller 32, when data is no longer being written to the data buffer of the high-speed bus 41, the high-speed bus controller 32 transitions to the power-saving state after a predetermined time has elapsed (S15).

[0038] On the other hand, when the microcontroller 31 receives a notification of completion of data transfer in response to the command (S13), it switches the low-speed bus 42 to a communication-enabled state and clears the low-speed buffer threshold-reaching interrupt flag (described later) of the low-speed bus controller 33 (S14). As a result, subsequent communication requests are accepted by the low-speed bus controller 33 and are sent to the main chip 20 via the low-speed bus 42.

[0039] Next, control when a data transmission request occurs while the high-speed bus controller 32 is in the power-saving state will be described. If a data transmission request to the main chip 20 occurs while the high-speed bus controller 32 is in the power-saving state, and if the low-speed bus 42 does not exist, the high-speed bus controller 32 will return from the power-saving state to the active state and then transmit the requested data via the high-speed bus 41. In this case, a delay in communication will occur by the time required to return from the power-saving state to the active state. Therefore, in this embodiment, when the high-speed bus controller 32 is in the power-saving state, data transmission via the low-speed bus 42 is prioritized. This makes it possible to reduce communication delays.

[0040] Furthermore, if the microcontroller 31 determines that data can be transmitted more efficiently by returning the high-speed bus controller 32 from the power-saving state to the active state, it controls the high-speed bus controller 32 to transition to the active state. On the other hand, if the required data transfer can be completed via the low-speed bus 42, it does not transition the high-speed bus controller 32 to the active state, but continues data transmission via the low-speed bus controller 33. This makes it possible to minimize the frequency at which the high-speed bus controller 32 transitions to the active state, thereby reducing unnecessary power consumption.

[0041] Below, a specific example of control when data is transmitted via the low-speed bus 42 without transitioning to the active state when the high-speed bus controller 32 is in the power-saving state will be described using the timing chart of Figure 4.

[0042] In this example, the high-speed bus controller 32 has transitioned to the power-saving state, so the microcontroller 31 has the high-speed bus 41 in a communication-disabled state and the low-speed bus 42 in a communication-enabled state. This is the last state in the chart of Figure 3 mentioned above. When a data transmission request occurs in this state, the data to be transmitted to the main chip 20 is written to the data buffer of the low-speed bus 42, which is in a communication-enabled state (S21). Here, it is assumed that 2 KB of data has been written to the buffer.

[0043] When the data to be transmitted is written to the data buffer, the low-speed bus controller 33 transmits the written data to the main chip 20 via the low-speed bus 42 (S22). Here, the size of the data to be transmitted is 2 kilobytes, which does not exceed the predetermined low-speed buffer threshold Th. Therefore, the low-speed bus controller 33 simply transmits the data written to the data buffer as is, and ends transmission control when the data buffer becomes empty. During this time, the high-speed bus controller 32 remains in the power-saving state.

[0044] In particular, when relatively small amounts of data need to be transmitted periodically, without the low-speed bus 42, the high-speed bus controller 32 would return from the power-saving state to the active state each time a data transfer occurs, making it impossible to fully achieve the power consumption reduction effect achieved by transitioning to the power-saving state. As an example, the power-saving effect achieved by the information processing device 10 according to this embodiment in a case where 2 KB of data is required to be transferred at a 200 μs interval will be described with reference to FIG. 5. In this figure, the upper part of FIG. 5(a) shows an example of data transmission via a high-speed bus in a conventional information processing device that does not include a low-speed bus 42, while the lower part of FIG. 5(b) shows an example of data transmission via the low-speed bus 42 in this embodiment.

[0045] As a specific example, assume that the high-speed bus controller 32 transfers data at a data transfer rate of 16 GB / s, takes 70 μs to transition from the power-saving state to the active state, and transitions to the power-saving state after a 32 μs wait period without data transfer. In this case, assuming that the high-speed bus controller 32 is responsible for this data transfer, it takes 0.125 μs to transfer 2 KB of data. Therefore, as shown in FIG. 5A, the high-speed bus controller 32 operates in the active state for 102.125 μs (= 70 μs + 0.125 μs + 32 μs) each time a data transfer is performed (including the time during the transition from the power-saving state to the active state). Since data transfers occur every 200 μs, the remaining 97.875 μs is spent in the power-saving state. Assuming that the power consumption in the active state is 1.5 W and the power consumption in the power-saving state is 10 mW, the power consumption per second of the high-speed bus controller 32 is calculated to be 0.7708 J.

[0046] In contrast, in this embodiment, as shown in FIG. 5B, 2 KB data transfers are always performed by the low-speed bus controller 33, while the high-speed bus controller 32 remains in the power-saving state. Here, the data transfer rate of the low-speed bus 42 is assumed to be 50 MB / s, and the low-speed bus controller 33 operates with 100 mW of power consumption only during data transfer. In this case, since a 2 KB data transfer takes 40 μs, the average power consumption of the low-speed bus controller 33 is calculated to be 20 mW. Furthermore, since the high-speed bus controller 32 remains in the power-saving state during this time, its power consumption is calculated to be 10 mW. Therefore, the combined power consumption per second is calculated to be 0.03 J. In other words, under these conditions, utilizing the low-speed bus 42 is expected to result in an average power reduction of approximately 0.74 J per second.

[0047] Next, an example in which the size of data to be transmitted exceeds the low-speed buffer threshold Th and the high-speed bus controller 32 is caused to transition to the active state will be described with reference to the timing chart of FIG.

[0048] In this example, similarly to the example of Fig. 4, in the initial state, the high-speed bus controller 32 transitions to a power-saving state, the high-speed bus 41 is in a communication-disabled state, and the low-speed bus 42 is in a communication-enabled state. In this state, data to be transmitted to the main chip 20 is written to the data buffer of the low-speed bus 42 (S31), similarly to the example of Fig. 4. However, in this example, unlike the example of Fig. 4, it is assumed that the size of the data to be transmitted exceeds the low-speed buffer threshold Th (here, 3.5 KB).

[0049] In this case, when the size of the data written to the data buffer reaches the low-speed buffer threshold Th, the low-speed bus controller 33 generates a low-speed buffer threshold reached interrupt, thereby notifying the microcontroller 31 that the low-speed buffer threshold Th has been reached (S32). In response to this, the microcontroller 31 generates a return interrupt that transitions the high-speed bus controller 32 to the active state and changes the low-speed bus 42 to a communication disabled state (S33). As a result, no new data will be written to the data buffer of the low-speed bus 42 thereafter. Therefore, the low-speed bus controller 33 transmits only the data that has been written up to that point (i.e., data of a size corresponding to the low-speed buffer threshold Th) via the low-speed bus 42 (S34).

[0050] The high-speed bus controller 32 transitions to the active state in response to the return interrupt from the microcontroller 31 (S35). As a specific example, it is assumed here that the return time Tx required for transition to the active state is approximately 70 μs.

[0051] On the other hand, the microcontroller 31 changes the high-speed bus 41 to a communication enabled state (S38) on the condition that the data buffer of the low-speed bus 42 is empty (S36) and that a notification that the data transfer is complete is received from the low-speed bus controller 33.

[0052] When the high-speed bus 41 becomes available for communication, the unsent data following the data written in the data buffer of the low-speed bus 42 is written to the data buffer of the high-speed bus 41 (S39). When the transition to the active state is completed, the high-speed bus controller 32 transmits the data written in the data buffer to the main chip 20 via the high-speed bus 41 (S40).

[0053] Here, in steps S36-S38, the microcontroller 31 changes the high-speed bus controller 32 to a communication-enabled state after confirming that the low-speed bus controller 33 has completed transmitting the data, in order to ensure that the data to be transmitted requested by the source of transmission is transmitted in the correct order to the main chip 20. With this control, after the microcontroller 31 has completed transmitting the data written to the data buffer of the low-speed bus 42 to the main chip 20, it can transmit subsequent data to the main chip 20 via the high-speed bus 41, and the data transmission order can be kept consistent even when the two buses are used in a switched manner.

[0054] Here, the high-speed bus 41 is changed to a communication-enabled state after the low-speed bus controller 33 completes data transmission. In this case, neither bus controller accepts data transfer during the period from S33 to S38. If this state continues, a command overflow or other problem may occur at the source. To avoid this situation, the microcontroller 31 may change the high-speed bus 41 to a communication-enabled state at the same time as changing the low-speed bus 42 to a communication-disabled state, thereby enabling data to be written to the data buffer of the high-speed bus 41. However, in this case, it is desirable to have the high-speed bus controller 32 wait for data transfer via the low-speed bus 42 to complete, so that the data transmission order is not out of sync. Therefore, the microcontroller 31 may control the wait state of transfer by the high-speed bus controller 32 by setting a register or the like. In this case, the microcontroller 31 changes the setting to release the high-speed bus controller 32 from its standby state upon receiving a data transfer completion notification from the low-speed bus controller 33. The high-speed bus controller 32 references this setting and starts transferring the data that has been written to the data buffer up to that point after the standby state is released. This makes it possible to prevent a situation in which a data transfer request cannot be accepted from the perspective of the data sender while guaranteeing the data transmission order, thereby making it difficult for command overflow to occur.

[0055] In this example, the low-speed buffer threshold Th, which is the criterion for transitioning the high-speed bus controller 32 to the active state, is preferably determined based on the recovery time Tx required to transition the high-speed bus controller 32 to the active state and the data transfer rate of the low-speed bus 42. As a specific example, assume that the data transfer rate of the low-speed bus 42 is 50 MB / s and the recovery time Tx required for the high-speed bus controller 32 to transition from the power-saving state to the active state is 70 μs. In this case, the low-speed bus controller 33 can transmit 3.5 KB of data via the low-speed bus 42 before the recovery time Tx has elapsed. Therefore, if the size of the data to be transmitted is equal to or less than this size, it is better to transmit it via the low-speed bus 42 without returning the high-speed bus controller 32 to the active state, as illustrated in FIG. 4 . Conversely, if data larger than this size needs to be transmitted, the remaining data that could not be transmitted via the low-speed bus 42 can be transmitted via the high-speed bus 41 after the high-speed bus controller 32 returns to the active state, thereby shortening the time required to complete transmission of the entire data.

[0056] Therefore, in this embodiment, the low-speed buffer threshold Th is determined according to the data size that can be transmitted via the low-speed bus 42 before the return time Tx has elapsed, and the high-speed bus controller 32 is returned to the active state when a data transfer of a size exceeding the low-speed buffer threshold Th is requested. This prevents the high-speed bus controller 32 from transitioning to the active state more than necessary. Furthermore, when the high-speed bus controller 32 is returned to the active state, it can be expected that the high-speed bus controller 32 will transition to the active state in time with the completion of transmission of data equivalent to the low-speed buffer threshold Th via the low-speed bus 42, and that the time loss associated with bus switching can be minimized.

[0057] An example of the overall flow of the processing executed by the sub-chip 30 to realize the control described above will now be described with reference to the flowchart in Fig. 7. In this diagram, it is assumed that initially the high-speed bus controller 32 is in a power-saving state, the high-speed bus 41 is set to a communication-disabled state, and the low-speed bus 42 is set to a communication-enabled state.

[0058] First, the data to be transmitted is written from the source to the data buffer of the low-speed bus 42 (S41). The low-speed bus controller 33 continues to transfer the written data until the size of the data written to the data buffer reaches the low-speed buffer threshold Th. When the size of the written data reaches the low-speed buffer threshold Th (S42), the low-speed bus controller 33 generates a low-speed buffer threshold reached interrupt (S43).

[0059] In response to this interrupt in S43, the microcontroller 31 changes the low-speed bus 42 to a communication-disabled state and generates a return interrupt that transitions the high-speed bus controller 32 to an active state (S44).The microcontroller 31 then waits until the data buffer of the low-speed bus 42 is empty and until it receives a notification from the low-speed bus controller 33 that the data transfer is complete (S45).When both conditions are met, the microcontroller 31 changes the high-speed bus 41 to a communication-enabled state (S46).Once the high-speed bus 41 is in a communication-enabled state, subsequent data from the sender is written to the data buffer of the high-speed bus 41 (S47).

[0060] In response to this, the high-speed bus controller 32 performs a transfer process for the data stored in the data buffer. When the data buffer becomes empty (S48), the microcontroller 31 changes the high-speed bus 41 to a communication-disabled state (S49). Furthermore, the microcontroller 31 waits for a data transfer completion notification from the high-speed bus controller 32 (S50), then changes the low-speed bus controller 33 to a communication-enabled state and clears the low-speed buffer threshold-reached interrupt (S51). As a result, the high-speed bus controller 32 automatically transitions to a power-saving state, and the low-speed bus controller 33 returns to a state in which it can accept new data transfers.

[0061] As described above, according to the information processing device 10 of this embodiment, the microcontroller 31 performs bus switching control, so that if the high-speed bus 41 is not immediately available, data transmission is started without delay via the low-speed bus 42, and if it would take a long time to transmit data using only the low-speed bus 42, the high-speed bus controller 32 is transitioned to the active state, allowing communication to continue via the high-speed bus 41. This makes it possible to achieve both reduced power consumption and improved communication efficiency.

[0062] The embodiments of the present invention are not limited to those described above, and various modifications are possible. For example, in the above description, the low-speed bus controller 33 communicates based on a bus interface that does not require initialization. However, the bus interface of the low-speed bus 42 is not limited to this. If initialization is required, transmission of boot code and the like cannot be started immediately after system startup. However, depending on the conditions, it may be possible to transmit data required for system startup in parallel with the initialization of the high-speed bus controller 32. Furthermore, after system startup, the same bus switching control as described above can be used to reduce the number of times the high-speed bus controller 32 transitions to the active state and to transfer data with low latency using the low-speed bus 42.

[0063] In the above description, the microcontroller 31 in the sub-chip 30 executes a prepared control program to control switching between the high-speed bus 41 and the low-speed bus 42. However, in this embodiment, some or all of the control performed by the microcontroller 31 may be realized by a control circuit implemented as hardware. In this case, the control circuit receives signals from the high-speed bus controller 32 indicating switching between operating states such as a power-saving state and a signal indicating the presence or absence of data in the data buffer, and also receives signals from the low-speed bus controller 33 indicating the presence or absence of data in the data buffer and an interrupt signal indicating the low-speed buffer threshold has been reached, and outputs a control signal to switch the bus to be used depending on the signals. As a result, as in the above-described embodiment, data can be efficiently transmitted to the main chip 20 using the low-speed bus 42 when communication via the high-speed bus 41 is unavailable.

[0064] In the above description, both the high-speed bus 41 and the low-speed bus 42 are bus interfaces capable of bidirectional data communication, but two buses capable of unidirectional data transmission may be provided instead of the low-speed bus 42 in the embodiments described so far. In this case, one of the two unidirectional buses is used for transmission from the main chip 20 to the sub-chip 30, and the other is used for transmission from the sub-chip 30 to the main chip 20.

[0065] FIG. 8 is a diagram showing an example of the configuration of such an information processing device. In this example, the main chip 20 and the sub-chip 30 are interconnected by three buses: a high-speed bus 41, a first low-speed bus 42-1, and a second low-speed bus 42-2. The first low-speed bus 42-1 is used for transmission from the main chip 20 to the sub-chip 30, and the second low-speed bus 42-2 is used for transmission from the sub-chip 30 to the main chip 20. The sub-chip 30 also incorporates a first low-speed bus controller 33-1 and a second low-speed bus controller 33-2 corresponding to the two low-speed buses, which control communication via the respective buses. Similarly, the main chip 20 also incorporates a first low-speed bus controller 23-1 and a second low-speed bus controller 23-2. In this embodiment, as in the examples described above, when the sub-chip 30 transmits data to the main chip 20, the microcontroller 31 of the sub-chip 30 controls switching between the high-speed bus 41 and the second low-speed bus 42-2. This allows efficient data transmission without returning the high-speed bus controller 32 to the active state more than necessary when the high-speed bus controller 32 is in the power-saving state. In the example shown in this figure, the high-speed bus 41, the second low-speed bus 42-2, the high-speed bus controller 32, and the second low-speed bus controller 33-2 function as the first bus, the second bus, the first bus controller, and the second bus controller, respectively, in the present invention.

[0066] 10 Information processing device, 20 Main chip, 21 Main processor unit, 22 High-speed bus controller, 23 Low-speed bus controller, 24 Memory controller, 25 DMA controller, 30 Subchip, 31 Microcontroller, 32 High-speed bus controller, 33 Low-speed bus controller, 34 USB controller, 35 Ethernet controller, 36 Internal memory, 37 DMA controller, 38 Timer, 41 High-speed bus, 42 Low-speed bus, 51 Main memory, 52 USB interface, 53 Ethernet interface.

Claims

1. An information processing device comprising a first integrated circuit, a second integrated circuit, and a first bus and a second bus that connect the first integrated circuit and the second integrated circuit independently of each other, wherein the first integrated circuit comprises: a first bus controller that controls communication via the first bus; and a second bus controller that controls communication via the second bus, and when communication via the first bus is unavailable, the first integrated circuit transmits data to the second integrated circuit via the second bus using the second bus controller.

2. An information processing device according to claim 1, wherein the first integrated circuit performs an initialization process of the first bus controller when system startup of the information processing device is initiated, and before the initialization process is completed, transmits data necessary for the system startup process to the second integrated circuit via the second bus using the second bus controller.

3. An information processing device according to claim 1, wherein the first bus controller transitions to a power saving state based on given conditions, and when the first bus controller transitions to the power saving state, the first integrated circuit transmits data to the second integrated circuit via the second bus using the second bus controller.

4. An information processing device according to claim 3, wherein the first integrated circuit transitions the first bus controller from a power saving state to an active state when a size of data to be transmitted via the second bus exceeds a predetermined threshold.

5. An information processing device according to claim 4, wherein the first integrated circuit stops accepting data to be transmitted via the second bus when the size of the data to be transmitted via the second bus reaches a predetermined threshold, and transitions the first bus controller from a power saving state to an active state.

6. An information processing device according to claim 5, wherein the first integrated circuit stops accepting data to be transmitted via the second bus, and then starts transmitting data by the first bus controller after the second bus controller has completed transmitting the accepted data.

7. A method for controlling an information processing device comprising a first integrated circuit, a second integrated circuit, and a first bus and a second bus that independently connect the first integrated circuit and the second integrated circuit to each other, wherein the first integrated circuit comprises: a first bus controller that controls communication via the first bus; and a second bus controller that controls communication via the second bus, wherein when the first integrated circuit is in a state in which communication via the first bus is unavailable, the second bus controller transmits data to the second integrated circuit via the second bus.

8. A program for controlling an information processing device comprising a first integrated circuit, a second integrated circuit, and a first bus and a second bus that independently connect the first integrated circuit and the second integrated circuit, wherein the first integrated circuit comprises: a first bus controller that controls communication via the first bus; and a second bus controller that controls communication via the second bus, the program causing the first integrated circuit to execute a process of transmitting data to the second integrated circuit via the second bus using the second bus controller when communication via the first bus is unavailable.

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