Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises a plurality of sub-pixel regions. A pixel driving circuit is arranged in each sub-pixel region. The plurality of pixel driving circuits are arranged in a plurality of rows and columns, each of the plurality of pixel driving circuits comprises a plurality of first-type transistors and a plurality of second-type transistors, and the plurality of second-type transistors at least include a write transistor. The array substrate comprises a base substrate, a first active film layer arranged on one side of the base substrate, a second active film layer arranged on the side of the first active film layer away from the base substrate, and a third source / drain metal layer arranged on the side of the second active film layer away from the base substrate. The first active film layer comprises active layer patterns of the plurality of first-type transistors. The second active film layer comprises an active layer pattern of the write transistor. The third source / drain metal layer comprises a data signal line, and the active layer pattern of the write transistor is electrically connected to the data signal line.

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby achieving display.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided. The array substrate includes a plurality of sub-pixel regions, each of which is provided with a pixel driving circuit, the plurality of pixel driving circuits being arranged in multiple rows and columns, each of the plurality of pixel driving circuits including a plurality of first-type transistors and a plurality of second-type transistors, the plurality of second-type transistors including at least a write transistor; the array substrate includes a base substrate, a first active film layer, a second active film layer, and a third source-drain metal layer, wherein the first active film layer is provided on one side of the base substrate and includes active layer patterns of the plurality of first-type transistors; the second active film layer is provided on a side of the first active film layer away from the base substrate and includes active layer patterns of the write transistors; the third source-drain metal layer is provided on a side of the second active film layer away from the base substrate and includes data signal lines, and the active layer patterns of the write transistors are electrically connected to the data signal lines.

[0005] In some embodiments, the array substrate also includes: a first source-drain metal layer arranged between the first active film layer and the second active film layer; a second source-drain metal layer arranged between the second active film layer and the third source-drain metal layer; in the sub-pixel area, the second source-drain metal layer includes a data line transfer pattern; the data signal line is connected to the data line transfer pattern through a via, and the data line transfer pattern is connected to the active layer pattern of the write transistor.

[0006] In some embodiments, the pixel driving circuit also includes a storage capacitor; the array substrate also includes: a first gate metal layer and a second gate metal layer sequentially arranged on the side of the first active film layer away from the base substrate; in the sub-pixel area, the first gate metal layer includes the first electrode pattern of the capacitor, and the second gate metal layer also includes the second electrode pattern of the capacitor; the third source-drain metal layer also includes a first voltage signal line; in the sub-pixel area, the second source-drain metal layer also includes a first transfer pattern, and the first source-drain metal layer includes a first bridge pattern; the first voltage signal line is connected to the first transfer pattern of the second source-drain metal layer through a via, and the first transfer pattern is connected to the first bridge pattern of the first source-drain metal layer through a via; the first bridge pattern is connected to the second electrode in the second gate metal layer through a via, so that the first voltage signal line is electrically connected to the second electrode.

[0007] In some embodiments, the second type of transistor also includes a first reset transistor and a compensation transistor, and the first type of transistor includes a driving transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a second reset transistor; the first active film layer includes an active layer pattern of the driving transistor, an active layer pattern of the first light-emitting control transistor, an active layer pattern of the second light-emitting control transistor, and an active layer pattern of the second reset transistor, and the second active film layer also includes an active layer pattern of the first reset transistor and an active layer pattern of the compensation transistor.

[0008] In some embodiments, the array substrate further includes a third gate metal layer disposed between the first source / drain metal layer and the second active film layer; and a fourth gate metal layer disposed on a side of the second active film layer away from the third gate metal layer; wherein the third gate metal layer includes a first branch of a first reset signal line and a first branch of a scan signal line, the first branch of the first reset signal line passes through the active layer pattern of the first reset transistor, and the first branch of the scan signal line passes through the active layer pattern of the compensation transistor and the active layer pattern of the write transistor; the fourth gate metal layer includes a second branch of a first reset signal line and a second branch of a scan signal line, the second branch of the first reset signal line passes through the active layer pattern of the first reset transistor, and the second branch of the scan signal line passes through the active layer pattern of the compensation transistor and the active layer pattern of the write transistor; the first branch of the first reset signal line and the second branch of the first reset signal line are electrically connected; the first branch of the scan signal line and the second branch of the scan signal line are electrically connected.

[0009] In some embodiments, the array substrate further includes a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer; the second gate metal layer further includes a plurality of initialization signal lines; in the sub-pixel area, the first source-drain metal layer further includes a second bridge pattern, and the second source-drain metal layer further includes a second transfer pattern; wherein, the second bridge pattern is electrically connected to the active layer pattern of the second reset transistor and the initialization signal line through two vias, so that the active layer pattern of the second reset transistor is electrically connected to the initialization signal line; the second transfer pattern is connected to the second bridge pattern and the active layer pattern of the first reset transistor through two vias, so that the active layer pattern of the first reset transistor is electrically connected to the initialization signal line.

[0010] In some embodiments, in the sub-pixel area, the first source-drain metal layer further includes a third bridge pattern, and the second source-drain metal layer further includes a third transfer pattern; the third bridge pattern is connected to the first plate of the capacitor in the second gate metal layer through a via, and the third transfer pattern is connected to the third bridge pattern through a via, and the active layer pattern of the compensation transistor of the second active film layer is connected to the third transfer pattern through a via, so that the compensation transistor is electrically connected to the first plate.

[0011] In some embodiments, in the sub-pixel area, the first source-drain metal layer further includes a fourth bridge pattern, and the second source-drain metal layer further includes a fourth transfer pattern; the fourth bridge pattern is connected to the active layer pattern of the second light-emitting transistor of the first active film layer through a via; the fourth transfer pattern is connected to the fourth bridge pattern through a via, and the active layer pattern of the compensation transistor of the second active film layer is connected to the fourth transfer pattern through a via, so that the compensation transistor is electrically connected to the second light-emitting control transistor.

[0012] In some embodiments, in the sub-pixel area, the first source-drain metal layer further includes a fifth bridge pattern, and the second source-drain metal layer further includes a fifth transfer pattern; the fifth bridge pattern is connected to the active layer pattern of the first light-emitting control transistor of the first active film layer through a via; the fifth transfer pattern is connected to the fifth bridge pattern through a via, and the active layer pattern of the write transistor of the second active film layer is connected to the fifth transfer pattern through a via, so that the write transistor is electrically connected to the first light-emitting control transistor.

[0013] In some embodiments, the first source-drain metal layer further includes a sixth bridge pattern, and the second source-drain metal layer further includes a sixth transfer pattern; the sixth bridge pattern is connected to the active layer pattern of the second light-emitting control transistor of the first active film layer through a via; and the sixth transfer pattern is connected to the sixth bridge pattern.

[0014] In some embodiments, four adjacent sub-pixel regions along the row direction are respectively the first sub-pixel region, the second sub-pixel region, the third sub-pixel region and the fourth sub-pixel region, wherein the film layer patterns in every two adjacent sub-pixel regions are mirror-imaged.

[0015] In some embodiments, the active layer pattern of the first light-emitting control transistor in the first sub-pixel area overlaps with the active layer pattern of the first light-emitting control transistor in the second sub-pixel area; the active layer pattern of the second reset transistor in the second sub-pixel area overlaps with the active layer pattern of the second reset transistor in the third sub-pixel area.

[0016] In some embodiments, in the sub-pixel area, the first source-drain metal layer includes a first bridge pattern and a second bridge pattern, the first bridge pattern of the first sub-pixel area overlaps with the first bridge pattern of the second sub-pixel area; the second bridge pattern of the second sub-pixel area overlaps with the second bridge pattern of the third sub-pixel area.

[0017] In some embodiments, the second bridge patterns in a plurality of sub-pixel regions arranged along a column direction are connected in sequence.

[0018] In some embodiments, in the sub-pixel area, the active layer pattern of the first reset transistor is connected to the active layer pattern of the compensation transistor, and the active layer pattern of the write transistor is located on one side of the active layer pattern of the compensation transistor in the row direction; the active layer pattern of the first reset transistor in the second sub-pixel area is connected to the active layer pattern of the first reset transistor in the third sub-pixel area.

[0019] In some embodiments, the second source-drain metal layer includes a first transfer pattern and a second transfer pattern; the first transfer pattern of the first sub-pixel area overlaps with the first transfer pattern of the second sub-pixel area; and the second transfer pattern of the second sub-pixel area overlaps with the second transfer pattern of the third sub-pixel area.

[0020] In some embodiments, the third source-drain metal layer includes a plurality of first voltage signal lines, each first voltage signal line is located in a column of sub-pixel areas; the first voltage signal line includes alternatingly connected voltage patterns and voltage sub-lines, and the size of the voltage pattern in the row direction is larger than the size of the voltage sub-line in the row direction; the first voltage signal line of the second sub-pixel area overlaps with the first voltage signal line of the third sub-pixel area.

[0021] In some embodiments, the array substrate further includes a first planarization layer disposed between the first source / drain metal layer and the third gate metal layer, and the thickness of the first planarization layer ranges from 1.5 μm to 2 μm.

[0022] In some embodiments, the array substrate further includes a second planar layer disposed between the second source / drain metal layer and the third source / drain metal layer, and the third source / drain metal layer is connected to the second source / drain metal layer through a via hole penetrating the second planar layer.

[0023] In some embodiments, the first active film layer is a low-temperature polysilicon layer, and the second active film layer is an oxide layer.

[0024] On the other hand, a display panel is provided, comprising the array substrate as described in any one of the above aspects.

[0025] In some embodiments, the display panel further includes a third flat layer disposed on a side of the third source / drain metal layer away from the base substrate; an anode layer disposed on the third flat layer, the anode layer including a plurality of anodes; a pixel defining layer disposed on a side of the anode layer away from the substrate; and a spacer disposed on a side of the pixel defining layer away from the substrate; wherein the array substrate includes a third source / drain metal layer, and the plurality of anodes are electrically connected to the third source / drain metal layer through vias penetrating the third flat layer.

[0026] In yet another aspect, a display device is provided, comprising the display panel as described in any one of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and do not limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, etc. involved in the embodiments of the present disclosure.

[0028] FIG1 is a planar structural diagram of a display device according to some embodiments of the present disclosure;

[0029] FIG2 is a planar structural diagram of a display panel according to some embodiments of the present disclosure;

[0030] FIG3 is a planar structural diagram of an array substrate provided in some embodiments of the present disclosure;

[0031] FIG4 is a cross-sectional structural diagram of an array substrate provided in some embodiments of the present disclosure;

[0032] FIG5A is an equivalent circuit diagram of a pixel driving circuit provided by some embodiments of the present disclosure;

[0033] FIG5B is a timing signal control diagram of a pixel driving circuit provided by some embodiments of the present disclosure;

[0034] FIG6A is a film layer structure diagram of a first active film layer of an array substrate provided in some embodiments of the present disclosure;

[0035] FIG6B is a film layer structure diagram of a first gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0036] FIG6C is a film layer structure diagram of a second gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0037] FIG6D is a film layer structure diagram of a first interlayer dielectric layer of an array substrate provided in some embodiments of the present disclosure;

[0038] FIG6E is a film structure diagram of a first source / drain metal layer of an array substrate provided in some embodiments of the present disclosure;

[0039] FIG6F is a film layer structure diagram of a third gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0040] FIG6G is a film layer structure diagram of a second active film layer of an array substrate provided in some embodiments of the present disclosure;

[0041] 6H is a film layer structure diagram of the fourth gate metal layer of the array substrate provided in some embodiments of the present disclosure;

[0042] FIG6I is a film layer structure diagram of a second interlayer dielectric layer of an array substrate provided in some embodiments of the present disclosure;

[0043] FIG6J is a diagram of a via structure connecting the first source-drain metal layer and the second source-drain metal layer in an array substrate provided by some embodiments of the present disclosure;

[0044] FIG6K is a film structure diagram of a second source / drain metal layer of an array substrate provided by some embodiments of the present disclosure;

[0045] FIG6L is a film layer structure diagram of a second planar layer of an array substrate provided in some embodiments of the present disclosure;

[0046] FIG6M is a film layer structure diagram of a third source / drain metal layer of an array substrate provided in some embodiments of the present disclosure;

[0047] FIG6N is a structural diagram of a third planar layer of a display panel provided by some embodiments of the present disclosure;

[0048] FIG6O is a structural diagram of an anode layer of a display panel provided by some embodiments of the present disclosure;

[0049] 7A is a diagram illustrating a connection structure between a second source-drain metal layer and a third source-drain metal layer of an array substrate provided by some embodiments of the present disclosure;

[0050] 7B is a diagram illustrating a connection structure between a first source-drain metal layer and a second source-drain metal layer of an array substrate provided by some embodiments of the present disclosure;

[0051] 7C is a diagram illustrating a connection structure between a first source / drain metal layer and a first active film layer of an array substrate provided in some embodiments of the present disclosure;

[0052] 7D is a diagram illustrating a connection structure between a second source / drain metal layer and a second active film layer of an array substrate provided in some embodiments of the present disclosure;

[0053] FIG7E is a diagram of a film layer stacking structure of a display panel provided by some embodiments of the present disclosure;

[0054] FIG8 is a diagram illustrating a film layer stacking arrangement structure of a display panel provided by some embodiments of the present disclosure;

[0055] FIG9A is a diagram illustrating a film layer arrangement structure of a first active film layer of an array substrate provided according to some embodiments of the present disclosure;

[0056] FIG9B is a diagram showing a film layer arrangement structure of a first gate metal layer of an array substrate provided according to some embodiments of the present disclosure;

[0057] FIG9C is a diagram showing a film layer arrangement structure of a second gate metal layer of an array substrate provided according to some embodiments of the present disclosure;

[0058] FIG9D is a diagram showing a film layer arrangement structure of a first interlayer dielectric layer of an array substrate provided according to some embodiments of the present disclosure;

[0059] FIG9E is a diagram showing a film layer arrangement structure of a first source / drain metal layer of an array substrate provided according to some embodiments of the present disclosure;

[0060] FIG9F is a diagram illustrating a film layer arrangement structure of a third gate metal layer of an array substrate provided according to some embodiments of the present disclosure;

[0061] FIG9G is a diagram illustrating a film layer arrangement structure of a second active film layer of an array substrate provided according to some embodiments of the present disclosure;

[0062] 9H is a diagram illustrating a film layer arrangement structure of a fourth gate metal layer of an array substrate provided according to some embodiments of the present disclosure;

[0063] FIG9I is a diagram illustrating a film layer arrangement structure of a second interlayer dielectric layer of an array substrate provided according to some embodiments of the present disclosure;

[0064] 9J is a diagram illustrating a via arrangement structure connecting the first source-drain metal layer and the second source-drain metal layer in an array substrate according to some embodiments of the present disclosure;

[0065] FIG9K is a diagram illustrating a film layer arrangement structure of a second source / drain metal layer of an array substrate provided according to some embodiments of the present disclosure;

[0066] FIG9L is a diagram illustrating a film layer arrangement structure of a second planar layer of an array substrate provided according to some embodiments of the present disclosure;

[0067] FIG9M is a diagram illustrating a film layer arrangement structure of a third source / drain metal layer of an array substrate according to some embodiments of the present disclosure;

[0068] FIG9N is a diagram illustrating a film layer arrangement structure of a third planar layer according to some embodiments of the present disclosure;

[0069] FIG9O is a diagram illustrating a film layer arrangement structure of an anode layer according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0070] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0071] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0072] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0073] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0074] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0075] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0076] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0077] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0078] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0079] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0080] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0081] As shown in FIG1 , some embodiments of the present disclosure provide a display device. The display device provided by the embodiments of the present disclosure can be any device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0082] Specifically, as shown in FIG1 , the embodiment of the present disclosure is exemplified by taking the display device 1000 as a mobile phone.

[0083] As shown in Figures 1 and 2, a display device 1000 includes a display panel 100. The display panel 100 includes a display area AA and a peripheral area BB located on at least one side of the display area AA. The display area AA includes a plurality of sub-pixels 21 and a plurality of signal lines. The plurality of sub-pixels 21 are arranged in the display area AA according to a specified rule. The area where each sub-pixel 21 is located is a sub-pixel area A1. The sub-pixel 21 is the smallest unit for displaying an image in the display panel 100. Each sub-pixel 21 can display a single color, such as red, green, or blue. By adjusting the brightness of different sub-pixels 21, color superposition can achieve the display of multiple colors. As shown in Figure 3, each sub-pixel 21 includes a light-emitting device OLED and a pixel driving circuit 200 for driving the light-emitting device OLED to emit light.

[0084] For example, taking the display panel 100 as an OLED (Organic Light-Emitting Diode) display panel, the display panel 100 includes an array substrate 10, a light-emitting device layer, and an encapsulation layer, which are sequentially stacked. The array substrate 10 includes multiple transistors and capacitors included in a pixel driving circuit, and the light-emitting device layer includes multiple light-emitting devices (OLEDs). As shown in Figures 3 and 4, the array substrate 10 includes a base substrate 101, multiple functional layers sequentially stacked on the base substrate 101, and insulating layers located between adjacent functional layers. The functional layers may include active film layers, gate metal layers, and source / drain metal layers. The active film layers, gate metal layers, and source / drain metal layers are used to form multiple pixel driving circuits 200 in the display panel 100. The multiple pixel driving circuits 200 may be formed in the display area AA of the display panel 100. The light-emitting devices OLED are disposed on a side of the pixel driving circuit 200 away from the base substrate 101.

[0085] Wherein, the pixel driving circuit 200 includes a plurality of transistors, the active layers of the plurality of transistors are located in the active film layer, the active layer of each transistor includes a first polar region, a second polar region and a channel region for connecting the first polar region and the second polar region, and the gates of the plurality of transistors are located in the gate metal layer, wherein the gate metal layer includes, for example, a plurality of signal lines, and the portion of a signal line that passes through the active layer of a certain transistor can serve as the gate of the transistor, where "passing" refers to the portion where the orthographic projections of the two on the substrate overlap. Wherein, when manufacturing a transistor, an active film layer can be first formed on the substrate 101 to obtain the active layer of the transistor, and then a gate metal layer can be formed on the side of the active film layer away from the substrate. The position where the gate metal layer overlaps with the active film layer is the position where the gate metal layer "passes" the active layer. For example, the gate of the transistor is arranged to overlap with the channel region of the transistor.

[0086] The pixel driving circuit 200 is mainly composed of transistors. Therefore, the size of the space occupied by the transistors can determine the size of the space occupied by the pixel driving circuit 200. For example, the space occupied by the transistors includes the lateral area size parallel to the plane of the substrate 101 and the longitudinal area size in the direction perpendicular to the plane of the substrate 101. The longitudinal area size is mainly related to the thickness of the film layer included in the array substrate 10. In this disclosure, the focus is on the lateral area size of the transistors and the pixel driving circuit 200 in the plane parallel to the substrate 101. The lateral area size is the area of ​​the positive projection of the transistor on the substrate 101. Hereinafter, the area of ​​the positive projection of the transistor on the substrate 101 will be collectively referred to as the area of ​​the transistor. The same applies to the area of ​​the pixel driving circuit 200. The area of ​​the active layer of the transistor included in the pixel driving circuit 200 can affect the area of ​​the pixel driving circuit 200.

[0087] The inventors of the present disclosure discovered that in the related art, the area occupied by the pixel driving circuit 200 is relatively large, resulting in a larger space occupied by the sub-pixel 21, which is not conducive to achieving a high PPI (Pixels Per Inch, pixel density) for the display panel. This is because the active layers of all transistors in the pixel driving circuit 200 are arranged in parallel, where "arranged in parallel" means that among all transistors in the pixel driving circuit 200, the orthographic projections of any two transistors on the substrate 101 do not overlap. At this time, the area of ​​the orthographic projection of the pixel driving circuit 200 on the substrate 101 is the sum of the areas of the active layers of multiple transistors in the pixel driving circuit 200, resulting in a larger area of ​​the orthographic projection of the pixel driving circuit 200 on the substrate 101, thereby increasing the area occupied by the pixel driving circuit 200.

[0088] Based on this, some embodiments of the present disclosure provide an array substrate 10, which includes: a plurality of pixel driving circuits 200 and a plurality of signal lines. As shown in FIG3 , the plurality of pixel driving circuits 200 are arranged in an array, and the plurality of signal lines include data signal lines Dt, gate lines, initialization signal lines Vin, voltage signal lines, and the like. The gate lines and initialization signal lines Vin extend along a first direction X, and the data signal lines Dt and power signal lines extend along a second direction Y. Each data signal line Dt is electrically connected to a column of pixel driving circuits 200, and at least one gate line is electrically connected to a row of pixel driving circuits 200. Based on the function of the at least one gate line electrically connected to a row of pixel driving circuits 200, the at least one gate line may include a scan signal line, a reset signal line Rst, an emission control signal line EM, and the like.

[0089] As shown in FIG4 , the array substrate 10 includes a base substrate 101 and two active film layers, wherein the two active film layers include a first active film layer 103 and a second active film layer 114 sequentially disposed on the base substrate 101, and the two active film layers are insulated from each other. The multiple transistors in the pixel driving circuit 200 are divided into multiple first-type transistors and multiple second-type transistors, wherein the active layers of the first-type transistors are disposed in the first active film layer 103, and the active layers of the second-type transistors are disposed in the second active film layer 114. Furthermore, the orthographic projections of the active layers of the multiple first-type transistors on the base substrate 101 at least partially overlap with the orthographic projections of the second-type transistors on the base substrate 101. Thus, by disposing the active layers of the transistors in the pixel driving circuit 200 in different active film layers, and by overlapping the active layers of the transistors in different active film layers, the total orthographic projection area of ​​the multiple transistors in the pixel driving circuit 200 on the base substrate 101 is reduced, thereby reducing the area occupied by the pixel driving circuit 200. The following is a detailed description of the solution of the present invention.

[0090] In some embodiments, the pixel driving circuit 200 in some embodiments of the present disclosure can be a 7T1C, 8T1C or 9T1C circuit, wherein T represents a transistor, and the number before T represents the number of transistors, C represents a capacitor, and the number before C represents the number of capacitors. For example, 7T1C represents 7 transistors and 1 capacitor. The following is an introduction to the pixel driving circuit in 7T1C mode.

[0091] 5A and 5B , the pixel driving circuit 200 may specifically include a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a write transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7 and a capacitor Cst, and the signal lines electrically connected to the pixel driving circuit 200 include a scanning signal line GN, an initialization signal line Vin, a first reset signal line Rst-P, a second reset signal line Rst-N and a light-emitting control signal line EM.

[0092] Among them, the gate of the first reset transistor T1 is electrically connected to the second reset signal line Rst-N, the first electrode region of the first reset transistor T1 is electrically connected to the first node N1, and the second electrode region of the first reset transistor T1 is electrically connected to the initialization signal line Vin; the gate of the compensation transistor T2 is electrically connected to the scanning signal line GN, the first electrode region of the compensation transistor T2 is electrically connected to the second electrode region of the driving transistor T3, and the second electrode region of the compensation transistor T2 is electrically connected to the first node N1; the gate of the driving transistor T3 is electrically connected to the first node N1; the gate of the write transistor T4 is electrically connected to the scanning signal line GN, the first electrode region of the write transistor T4 is electrically connected to the data signal line Dt, and the second electrode region of the write transistor T4 is electrically connected to the first electrode region of the driving transistor T3; the gate of the first light-emitting control transistor T5 and the gate G6 of the second light-emitting control transistor T6 are both electrically connected to the light-emitting control signal line EM, and the first light-emitting control transistor T5 is electrically connected to the first light-emitting control transistor T3. The first electrode region of the first light-emitting control transistor T5 is electrically connected to the first electrode region of the driving transistor T3, the first electrode region of the second light-emitting control transistor T6 is electrically connected to the second electrode region of the driving transistor T3, and the second electrode region of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting device OLED; the gate of the second reset transistor T7 is electrically connected to the first reset signal line Rst-P, the first electrode region of the second reset transistor T7 is electrically connected to the initialization signal line Vin, the second electrode region of the second reset transistor T7 is electrically connected to the anode of the light-emitting device OLED, and the cathode of the light-emitting device OLED is electrically connected to the second voltage signal line VSS.

[0093] Among them, the scanning signal line GN is used to transmit the scanning signal gN, the first reset signal line Rst-P is used to transmit the first reset timing signal rst-P, the second reset signal line Rst-N is used to transmit the second reset timing signal rst-N, the first voltage signal line VDD is used to transmit the first voltage signal, for example, a high-voltage DC signal, the initialization signal line Vin is used to transmit the initialization signal, the data signal line Dt is used to transmit the data signal dt, the light-emitting control signal line EM is used to transmit the light-emitting control timing signal em, and the second voltage signal line VSS is used to transmit the second voltage signal, for example, a low-voltage DC signal.

[0094] As shown in FIG5B , the driving process of the pixel driving circuit 200 is as follows: a frame period includes a reset phase t1, a data refresh and compensation phase t2, and a light-emitting phase t3. During the reset phase t1, the first reset transistor T1 is turned on under the control of the second reset timing signal rst-N, causing the initialization signal to be written to the first node N1, thereby resetting the first node N1. The second reset transistor T7 is turned on under the control of the first reset timing signal rst-P, causing the initialization signal to be written to the anode of the OLED, thereby resetting the anode of the light-emitting device OLED.

[0095] At this time, the driving transistor T3 is turned on, while the compensation transistor T2, the writing transistor T4, the first light emission control transistor T5 and the second light emission control transistor T6 are all in the off state, and the light emitting device OLED does not emit light.

[0096] During the data refresh and compensation phase t2, the write transistor T4 and the compensation transistor T2 are turned on under the control of the scan signal gN, while the drive transistor T3 maintains the on-state of the reset phase t1. Therefore, the data signal dt can be sequentially transmitted through the write transistor T4, the drive transistor T3, and the compensation transistor T2 to the first node N1, causing the voltage of the first node N1 to change until the voltage of the first node N1 reaches the sum of the threshold voltage of the drive transistor T3 and the voltage of the data signal dt, turning off the drive transistor T3. During the data refresh and compensation phase t2, the threshold voltage of the drive transistor T3 can be written to the first node N1 to compensate for threshold voltage drift of the drive transistor T3, thereby preventing changes in the drive signal generated by the drive transistor and preventing an impact on the luminous intensity of the light-emitting device OLED. During this phase, the first and second emission control transistors T5 and T6 are in the off state under the control of the emission control timing signal em.

[0097] In the light-emitting stage t3, the second reset transistor T7 is turned off under the control of the first reset timing signal rst-P, the first reset transistor T1 is turned off under the control of the second reset timing signal rst-N, the write transistor T4 and the compensation transistor T2 are turned off under the control of the scan signal gN, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control timing em, thereby causing the voltage signal of the first voltage signal line VDD to be written into the first electrode region of the driving transistor T3, and the anode AND1 voltage of the light-emitting device OLED can be written into the second electrode region of the driving transistor T3, thereby causing the driving transistor T3 to be turned on, thereby forming a path between the first voltage signal line VDD and the light-emitting device OLED, causing the light-emitting device OLED to emit light.

[0098] It should be noted that the first region of the transistor disclosed herein is one of the source and drain of the transistor, and the second region is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first region and the second region of the transistor in the embodiment of the present disclosure can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first region of the transistor is the source, and the second region is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first region of the transistor is the drain, and the second region is the source.

[0099] In the circuit provided by the embodiments of the present disclosure, nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0100] The above-mentioned pixel driving circuit 200 adopts an LTPO (Low Temperature Polycrystalline Oxide) circuit, that is, a pixel driving circuit 200 includes both a low-temperature polycrystalline silicon (LTPS) thin film transistor and an oxide thin film transistor. The low-temperature polycrystalline silicon thin film transistor has a strong load capacity, and the oxide thin film transistor has a small off-state current and a stronger charge retention ability than the low-temperature polycrystalline silicon thin film transistor. In this way, the pixel driving circuit 200 can achieve higher charge mobility and better stability.

[0101] In some instances, the oxide transistor is an N-type transistor and the LTPS transistor is a P-type transistor, wherein the N-type transistor is turned on when the gate receives a high voltage signal, and the P-type transistor is turned on when the gate receives a low voltage signal. For example, as shown in FIG5A , the first reset transistor T1, the compensation transistor T2, and the write transistor T4 can be oxide thin film transistors, and are N-type transistors, that is, they are turned on at a high level. The driving transistor T3, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are all P-type transistors of low temperature polysilicon thin film transistors (LTPS), which are turned on at a low level. Among them, the setting of the first reset transistor T1 and the compensation transistor T2 using oxide thin film transistors can effectively prevent leakage of the first node N1.

[0102] It should be noted that the "high voltage signal" and "low voltage signal" mentioned above are popular terms. Generally speaking, the turn-on condition of an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. The threshold voltage of the N-type transistor is a positive value, then the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The turn-on condition of a P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage. The threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage, then the gate voltage signal that turns on the P-type transistor is called a low voltage signal. The high and low in "high voltage signal" and "low voltage signal" are relative to a reference voltage (for example, 0V).

[0103] The following describes the film layer structures included in the array substrate 10 and the arrangement of the transistors in the pixel driving circuit.

[0104] Exemplarily, as shown in FIG. 4 , the array substrate 10 includes: a base substrate 101 and a pixel circuit stack 20 , wherein the pixel circuit stack 20 is disposed on the base substrate 101 .

[0105] Exemplarily, the material of the base substrate 101 may include any one of glass, metal or flexible material.

[0106] The pixel circuit stack 20 is formed with multiple pixel driving circuits 200. For example, the pixel circuit stack 20 includes: a first buffer layer 102, a first active film layer 103, a first gate insulating layer 104, a first gate metal layer 105, a second gate insulating layer 106, a second gate metal layer 107, a first interlayer dielectric layer 108, a first source-drain metal layer 109, a first planarizing layer 110, a second buffer layer 111, a third gate metal layer 112, a third gate insulating layer 113, a second active film layer 114, a fourth gate insulating layer 115, a fourth gate metal layer 116, a second interlayer dielectric layer 117, a second source-drain metal layer 118, a second planarizing layer 119 and a third source-drain metal layer 120, which are stacked in sequence.

[0107] For example, the first buffer layer 102 and the second buffer layer 111 are prepared using PECVD (Plasma Enhanced Chemical Vapor Deposition). The materials used may be silicon nitride, silicon oxide, or silicon oxynitride, which have water and gas barrier properties. The thickness of silicon nitride may range from 30 nm to 70 nm, and the thickness of silicon oxide may range from 250 nm to 350 nm.

[0108] Exemplarily, the first active film layer 103 is obtained by an excimer laser annealing process, and its material is low-temperature polycrystalline silicon with a thickness range of 30nm to 50nm; the second active film layer 114 is obtained by a PVD (Physical Vapor Deposition) process, and its thickness range is 30nm to 50nm, and its material can be any one of indium gallium zinc oxide or low-temperature polycrystalline oxide, for example, IGZO (Indium gallium zinc oxide) and IGZTO (Indium gallium zinc tin oxide).

[0109] Illustratively, the first gate insulating layer 104 , the second gate insulating layer 106 , the third gate insulating layer 113 and the fourth gate insulating layer 115 are made of silicon nitride, silicon oxide or silicon oxynitride, and are deposited using a PECVD process, with a thickness ranging from 100 nm to 150 nm.

[0110] Illustratively, the first gate metal layer 105, the second gate metal layer 107, the first source-drain metal layer 109, the third gate metal layer 112, the fourth gate metal layer 116, the second source-drain metal layer 118 and the third source-drain metal layer 120 are mainly obtained by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a PVD process, and their thickness ranges from 300nm to 800nm.

[0111] Exemplarily, the material of the first interlayer dielectric layer 108 and the second interlayer dielectric layer 117 can be any one of silicon nitride, silicon oxide or silicon oxynitride, or a combination of any two of them, and is deposited using a PECVD process with a thickness ranging from 400 nm to 800 nm.

[0112] Illustratively, the first flat layer 110 is obtained by coating PI (Polyimide) using a spin coating process, and its thickness ranges from 1.5 μm to 2 μm; the second flat layer 119 can be obtained by coating PI (Polyimide) using a spin coating process, or by depositing silicon nitride, silicon oxide or silicon oxynitride using a PECVD process, and is mainly used to block water and oxygen and alkaline ions, and its thickness ranges from 400 nm to 800 nm.

[0113] In some embodiments, the material of the first planar layer 110 may be PI. In this case, the thickness of the first planar layer 110 is greater than that of the second planar layer 119. The thicker first planar layer 110 can prevent signal crosstalk between the two active layers.

[0114] In other embodiments, the material of the first planar layer 110 can be an inorganic insulating material such as silicon oxide, silicon nitride, etc. When the first planar layer 110 uses an inorganic material, the film thickness is relatively small (less than 1.5 microns), which can reduce the size of the through hole of the first planar layer 110 and further improve the PPI.

[0115] For example, when the material of the first planar layer 110 is an inorganic insulating material, the surface of the first planar layer 110 on the side close to the second planar layer 119 can be planarized by CMP (Chemical Mechanical Polishing).

[0116] As shown in Figures 2, 3, 4, 5A, 6A, and 6G, the array substrate 10 includes multiple sub-pixel areas A1, each of which is provided with a pixel driving circuit 200. The multiple pixel driving circuits 200 are arranged in multiple rows and columns. Each of the multiple pixel driving circuits 200 includes multiple first-type transistors T0 and multiple second-type transistors T0', wherein the multiple second-type transistors T0' include at least a write transistor T4. The array substrate 10 includes a base substrate 101, a first active film layer 103 disposed on one side of the base substrate 101, a second active film layer 114 disposed on a side of the first active film layer 103 away from the base substrate 101, and a third source / drain metal layer 120 disposed on a side of the second active film layer 114 away from the base substrate 101. Among them, the first active film layer 103 includes active layer patterns of multiple first-type transistors T0, the second active film layer 114 includes active layer patterns of multiple second-type transistors T0', for example, including the active layer pattern of the write transistor T4; the third source-drain metal layer 120 includes a data signal line Dt, and the active layer pattern of the write transistor T4 is electrically connected to the data signal line Dt.

[0117] It should be noted that the aforementioned arrangement of the active layer pattern of the write transistor T4 in the second active film layer 114 and the data signal line Dt in the third source-drain metal layer 120, located away from the transistor, can, on the one hand, avoid parasitic capacitance between the data signal line and the metal transfer pattern in the first source-drain metal layer 109 or the second source-drain metal layer 118, thereby preventing crosstalk. Furthermore, distributing the data signal line in the third source-drain metal layer provides more wiring space, increases the spacing between adjacent data signal lines, and reduces interference between signal lines. Furthermore, the data signal line Dt can directly transmit signals to the second source-drain metal layer 118 through vias penetrating the second planar layer 119, thereby providing data signals to the first electrode region of the write transistor T4. If the active layer pattern of the write transistor T4 is disposed in the first active film layer 103, the data signal line Dt located in the third source / drain metal layer 120 needs to pass through at least two vias in multiple film layers, namely, vias in the first planar layer 110 and the second planar layer 119. Since the number of vias affects the display panel's PPI, and the greater the number of vias, the more likely it is that poor vias will affect the display panel's yield. Therefore, compared to related technologies, the above arrangement not only simplifies the process but also improves the display panel's PPI, thereby enhancing the display quality and yield, while achieving a reasonable layout of the data signal lines, reducing parasitic capacitance, and improving signal transmission stability.

[0118] In some embodiments, as shown in Figures 4 and 6K, the array substrate 10 also includes a first source-drain metal layer 109 arranged between the first active film layer 103 and the second active film layer 114, and a second source-drain metal layer 118 arranged between the second active film layer 114 and the third source-drain metal layer 120; in the sub-pixel area A1, the second source-drain metal layer 118 includes a data line switching pattern SR; the data signal line Dt is connected to the data line switching pattern SR through a via, and the data line switching pattern SR is connected to the active layer pattern of the write transistor T4.

[0119] It can be understood that, referring to Figures 4, 6L, 6K and 6M, according to the aforementioned content, a second flat layer 119 is provided between the second source-drain metal layer 118 and the third source-drain metal layer 120, and a plurality of first-class vias H are provided on the second flat layer 119, specifically including first-class vias H1, first-class vias H2 and first-class vias H3. The data signal line Dt is connected to the data line transfer pattern SR located on the second source-drain metal layer 118 through the first-class via H2 penetrating the second flat layer 119, and a second active film layer 114 is provided between the second source-drain metal layer 118 and the second active film layer 114. There is a second interlayer dielectric layer 117. Referring to Figures 4, 6I, 6K, 6G and 6M, a plurality of second-type vias O are provided on the second interlayer dielectric layer 117, specifically including second-type vias O1, second-type vias O2, second-type vias O3, second-type vias O4 and second-type vias O5. The data line switching pattern SR is connected to the active layer pattern of the write transistor T4 located in the second active film layer 114 through the second-type vias O3 passing through the second interlayer dielectric layer 117 and the vias of the fourth gate insulation layer 115 to ensure that the write transistor T4 receives the data signal transmitted by the data signal line Dt.

[0120] By providing a data line switching pattern SR in the second source-drain metal layer 118 , the data line switching pattern SR connects the third source-drain metal layer and the second active film layer, thereby connecting the data signal line to the write transistor to achieve data signal transmission.

[0121] In some embodiments, referring to FIG. 4 , FIG. 6A to FIG. 6M and FIG. 7E , the pixel driving circuit 200 further includes a capacitor Cst; the array substrate 10 further includes: a first gate metal layer 105 and a second gate metal layer 107 sequentially disposed on a side of the first active film layer 103 away from the base substrate 101; in the sub-pixel area A1, the first gate metal layer 105 includes a first plate pattern Cst1 of the capacitor Cst, and the second gate metal layer 107 further includes a second plate pattern Cst2 of the capacitor Cst; the third source-drain metal layer 120 further includes a first voltage signal line VD D; in the sub-pixel area A1, the second source-drain metal layer 118 also includes a first transfer pattern R1, and the first source-drain metal layer 109 includes a first bridge pattern Q1; the first voltage signal line VDD is connected to the first transfer pattern R1 of the second source-drain metal layer 118 through a via, and the first transfer pattern R1 is connected to the first bridge pattern Q1 of the first source-drain metal layer 109 through a via; the first bridge pattern Q1 is connected to the second electrode pattern Cst2 in the second gate metal layer 107 through a via, so that the first voltage signal line VDD is electrically connected to the second electrode pattern Cst2.

[0122] 6E, 6K, and 6M, FIG. 6E shows a film layer structure diagram of the first source-drain metal layer 109, FIG. 6K shows a film layer structure diagram of the second source-drain metal layer 118, and FIG. 6M shows a film layer structure diagram of the third source-drain metal layer 120. The first source-drain metal layer 109 includes a first bridge pattern Q1, the second source-drain metal layer 118 includes a first transfer pattern R1, and the third source-drain metal layer 120 includes a first voltage signal line VDD. Referring to Figure 7A, Figure 7A is a connection structure diagram of the second source-drain metal layer 118 and the third source-drain metal layer 120, and the first voltage signal line VDD is connected to the first transfer pattern R1 of the second source-drain metal layer 118 through the first type via H1 that penetrates the second flat layer. Continuing to refer to Figures 7B and 6J, Figure 7B is a connection structure diagram of the second source-drain metal layer 118 and the first source-drain metal layer 109, wherein an insulating layer is provided between the second source-drain metal layer 118 and the first source-drain metal layer 109, and the insulating layer may include a first flat layer 110, a second buffer layer 111, a third gate insulating layer 113, a fourth gate insulating layer 115 and a second interlayer dielectric layer 117, and third type vias K are provided inside the insulating layer, including third type vias K1, third type vias K2, third type vias K3, third type vias K4, third type vias K5, third type vias K6 and third type vias K7. The first transfer pattern R1 is connected to the first bridge pattern Q1 of the first source-drain metal layer 109 through the third type via K1 that penetrates the insulating layer; referring to Figures 7C and 6D, a first interlayer dielectric layer 108 is arranged between the first source-drain metal layer 109 and the second gate metal layer 107, and the first interlayer dielectric layer 108 is provided with a fourth type of via L, including a fourth type of via L1, a fourth type of via L2, a fourth type of via L3, a fourth type of via L4, a fourth type of via L5, a fourth type of via L6 and a fourth type of via L7. The first bridge pattern Q1 is connected to the second electrode pattern Cst2 in the second gate metal layer 107 by penetrating the fourth type of via L1, so that the second electrode pattern Cst2 of the capacitor receives the first voltage signal transmitted by the first voltage signal line VDD.

[0123] The above-mentioned setting of the first voltage signal line VDD in the third source-drain metal layer 120 is mainly to increase the wiring space and reduce the resistance of the first voltage signal line VDD to a certain extent. At the same time, it can also avoid the interference of other signal lines on the first voltage signal line VDD, improve the efficiency of the first voltage signal line VDD in transmitting signals, and further realize electrical connection with the capacitor.

[0124] In some embodiments, referring to Figures 4, 6A and 6G, the second type of transistor T0' also includes a first reset transistor T1 and a compensation transistor T2, and the first type of transistor T0 includes a driving transistor T3, a first light-emitting control transistor T5, a second light-emitting control transistor T6 and a second reset transistor T7; the first active film layer 103 includes an active layer pattern of the driving transistor T3, an active layer pattern of the first light-emitting control transistor T5, an active layer pattern of the second light-emitting control transistor T6 and an active layer pattern of the second reset transistor T7, and the second active film layer 114 also includes an active layer pattern of the first reset transistor T1 and an active layer pattern of the compensation transistor T2.

[0125] It can be understood that the active layer pattern of the above-mentioned first type transistor T0 and the active layer pattern of the second type transistor T0' are respectively located in different active film layers. Compared with the related art in which the active layer patterns of the transistors are all set on the same active film layer, the size of the lateral area parallel to the plane where the substrate is located can be reduced, that is, the area occupied by the positive projection of the first type transistor T0 and the second type transistor T0' on the substrate can be reduced, and then the area occupied by the positive projection of the pixel driving circuit 200 on the substrate can be reduced, thereby improving space utilization.

[0126] Exemplarily, the second-type transistors T0' are all oxide thin-film transistors, and are N-type transistors, and the first-type transistors T0 are all P-type transistors of low-temperature polycrystalline silicon thin-film transistors. Since a first flat layer 110 is provided between the first active film layer 103 and the second active film layer 114, it can ensure that the bottom of the second-type transistor T0' is flat, and can play a certain isolation role between the first-type transistor T0 and the second-type transistor T0', thereby reducing the parasitic capacitance between the first-type transistor T0 and the second-type transistor T0', thereby avoiding signal interference between them.

[0127] In some embodiments, referring to Figures 4, 6E, 6F, 6G, 6H, and 7D, the array substrate 10 further includes a third gate metal layer 112 disposed between the first source / drain metal layer 109 and the second active film layer 114, and a fourth gate metal layer 116 disposed on a side of the second active film layer 114 away from the third gate metal layer 112; wherein the third gate metal layer 112 includes a first branch line of a first reset signal line Rst-P1 and a first branch line of a scan signal line G-N1, the first branch line of the first reset signal line Rst-P1 passing through the active layer pattern of the first reset transistor T1, and the first branch line of the scan signal line G-N1 passing through the compensation crystal. The fourth gate metal layer 116 includes the second branch line of the first reset signal line Rst-P2 and the second branch line of the scan signal line G-N2. The second branch line of the first reset signal line Rst-P2 passes through the active layer pattern of the first reset transistor T1, and the second branch line of the scan signal line G-N2 passes through the active layer pattern of the compensation transistor T2 and the active layer pattern of the write transistor T4. The first branch line of the first reset signal line Rst-P1 and the second branch line of the first reset signal line Rst-P2 are electrically connected. The first branch line of the scan signal line G-N1 and the second branch line of the scan signal line G-N2 are electrically connected.

[0128] Exemplarily, referring to Figure 7D, it can be seen from the above setting that the first branch line G-N1 of the scanning signal line passes through the active layer pattern of the compensation transistor T2 and the active layer pattern of the writing transistor T4, and serves as the gate of the compensation transistor T2 and the gate of the writing transistor T4 respectively. That is, the gate of the compensation transistor T2 and the gate of the writing transistor T4 receive the same signal, and since the first branch line G-N1 of the scanning signal line and the second branch line G-N2 of the scanning signal line are electrically connected, it can be obtained that the gate of the compensation transistor T2 and the gate of the writing transistor T4 both receive the same scanning signal gN. Therefore, the compensation transistor T2 and the writing transistor T4 can share a scanning signal line. Compared with the related art, the compensation transistor T2 and the writing transistor T4 are arranged on different layers, the two transistors are of different types and cannot share gate signals, the number of scanning signal lines is reduced, and at the same time, the space of the pixel driving circuit is greatly saved to a certain extent.

[0129] By setting the first branch line G-N1 of the scanning signal line, the second branch line G-N2 of the scanning signal line, the first branch line Rst-P1 of the first reset signal line, and the second branch line Rst-P2 of the first reset signal line, reasonable wiring is achieved to a certain extent, avoiding crosstalk between signal lines due to insufficient wiring space. On the other hand, by setting two branches and applying gate scanning signals to the upper and lower sides of the active layer of the compensation transistor T2 and the write transistor T4 at the same time, the strength of the gate scanning signal received by the transistor can be enhanced, and the conductivity of the channel region of the active layer of the compensation transistor T2 and the write transistor T4 can be enhanced, so that the control of the conduction and cutoff of the compensation transistor T2 and the write transistor T4 is better.

[0130] In some embodiments, continuing to refer to Figures 4, 6C, 6E, 6K, 7C and 7D, the array substrate 10 further includes a second gate metal layer 107, a first source-drain metal layer 109 and a second source-drain metal layer 118; the second gate metal layer 107 further includes a plurality of initialization signal lines Vin; in the sub-pixel area A1, the first source-drain metal layer 109 further includes a second bridge pattern Q2, and the second source-drain metal layer 118 further includes a second transfer pattern R2; wherein the second bridge pattern Q2 is electrically connected to the active layer pattern of the second reset transistor T7 and the initialization signal line Vin through two vias, so that the active layer pattern of the second reset transistor T7 is electrically connected to the initialization signal line Vin; the second transfer pattern R2 is connected to the second bridge pattern Q2 and the active layer pattern of the first reset transistor T1 through two vias, so that the active layer pattern of the first reset transistor T1 is electrically connected to the initialization signal line Vin.

[0131] It should be noted that, referring to Figure 7C, the second bridge pattern Q2 is electrically connected to the initialization signal line Vin through the fourth type of via L21 passing through the first interlayer dielectric layer 108, and is electrically connected to the active layer pattern of the second reset transistor T7 through the fourth type of via L22 passing through the first interlayer dielectric layer 108, wherein the fourth type of via L21 and the fourth type of via L22 are interconnected, so that the second reset transistor T7 can receive the initialization signal of the initialization signal line Vin; referring to Figure 7D, the second transfer pattern R2 is connected to the second bridge pattern Q2 through the third type of via K2, and is connected to the active layer pattern of the first reset transistor T1 located in the second active film layer 114 through the second type of via O1 passing through the second interlayer dielectric layer 117, so that the first reset transistor T1 can receive the initialization signal of the initialization signal line Vin.

[0132] In some embodiments, referring to Figures 6E, 6K, and 7B to 7D, in the sub-pixel area A1, the first source-drain metal layer 109 further includes a third bridge pattern Q3, and the second source-drain metal layer 118 further includes a third transfer pattern R3; the third bridge pattern Q3 is connected to the first plate pattern Cst1 of the capacitor Cst in the second gate metal layer 107 through a via, the third transfer pattern R3 is connected to the third bridge pattern Q3 through a via, and the active layer pattern of the compensation transistor T2 of the second active film layer 114 is connected to the third transfer pattern R3 through a via, so that the compensation transistor T2 is electrically connected to the first plate.

[0133] For example, referring to Figures 6E and 7C, the third bridge pattern Q3 is connected to the first plate pattern Cst1 of the capacitor Cst in the second gate metal layer 107 through the fourth type of via L3 passing through the first interlayer dielectric layer 108; referring to Figure 7B, the third transfer pattern R3 is connected to the third bridge pattern Q3 through the third type of via K3 passing through the second interlayer dielectric layer 117; referring to Figure 7D again, the active layer pattern of the compensation transistor T2 of the second active film layer 114 is connected to the third transfer pattern R3 through the second type of via O2 passing through the second interlayer dielectric layer 117. Through the above connection method, the compensation transistor T2 can be electrically connected to the first plate of the capacitor Cst.

[0134] In some embodiments, referring to Figures 6E, 6K, and 7B to 7D, in the sub-pixel area A1, the first source-drain metal layer 109 further includes a fourth bridge pattern Q4, and the second source-drain metal layer 118 further includes a fourth transfer pattern R4; the fourth bridge pattern Q4 is connected to the active layer pattern of the second light-emitting control transistor T6 of the first active film layer 103 through a via; the fourth transfer pattern R4 is connected to the fourth bridge pattern Q4 through a via, and the active layer pattern of the compensation transistor T2 of the second active film layer 114 is connected to the fourth transfer pattern R4 through a via, so that the compensation transistor T2 is electrically connected to the second light-emitting control transistor T6.

[0135] For example, referring to Figures 6E and 7C, the fourth bridge pattern Q4 is connected to the active layer pattern of the second light-emitting control transistor T6 of the first active film layer 103 through the fourth type of via L4 passing through the first interlayer dielectric layer 108; referring to Figure 7B, the fourth transfer pattern R4 is connected to the fourth bridge pattern Q4 through the third type of via K4; referring to Figure 7D, the active layer pattern of the compensation transistor T2 of the second active film layer 114 is connected to the fourth transfer pattern R4 through the second type of via O4 passing through the second interlayer dielectric layer 117. Through the above connection method, the compensation transistor T2 can be electrically connected to the second light-emitting control transistor T6.

[0136] In some embodiments, referring to Figures 6E, 6K, and 7B to 7D, in the sub-pixel area A1, the first source-drain metal layer 109 further includes a fifth bridge pattern Q5, and the second source-drain metal layer 118 further includes a fifth transfer pattern R5; the fifth bridge pattern Q5 is connected to the active layer pattern of the first light-emitting control transistor T5 of the first active film layer 103 through a via; the fifth transfer pattern R5 is connected to the fifth bridge pattern Q5 through a via, and the active layer pattern of the write transistor T4 of the second active film layer 114 is connected to the fifth transfer pattern R5 through a via, so that the write transistor T4 is electrically connected to the first light-emitting control transistor T5.

[0137] For example, referring to Figures 6E and 7C, the fifth bridge pattern Q5 is connected to the active layer pattern of the first light-emitting control transistor T5 of the first active film layer 103 through the fourth type of via L5 passing through the first interlayer dielectric layer 108; referring to Figure 7B, the fifth transfer pattern R5 is connected to the fifth bridge pattern Q5 through the third type of via K5; referring to Figure 7D, the active layer pattern of the write transistor T4 of the second active film layer 114 is connected to the fifth transfer pattern R5 through the second type of via O5 passing through the second interlayer dielectric layer 117. Through the above connection method, the write transistor T4 can be electrically connected to the first light-emitting control transistor T5.

[0138] In some embodiments, referring to Figures 6E, 6K, 7B and 7C, in the sub-pixel area A1, the first source-drain metal layer 109 further includes a sixth bridge pattern Q6, and the second source-drain metal layer 118 further includes a sixth switching pattern R6; the sixth bridge pattern Q6 is connected to the active layer pattern of the second light-emitting control transistor T6 of the first active film layer 103 through a via; the sixth switching pattern R6 is connected to the sixth bridge pattern Q6.

[0139] For example, referring to Figure 6E and Figure 7C, the sixth bridge pattern Q6 is connected to the active layer pattern of the second light-emitting control transistor T6 of the first active film layer 103 through the fourth type of via L6 passing through the first interlayer dielectric layer 108; referring to Figure 7B, the sixth transfer pattern R6 is connected to the sixth bridge pattern Q6 by passing through the third type of via K6.

[0140] In some embodiments, referring to Figures 8 and 9A to 9O, four adjacent sub-pixel regions A1 along the row direction are respectively the first sub-pixel region A11, the second sub-pixel region A12, the third sub-pixel region A13 and the fourth sub-pixel region A14, wherein the film layer patterns in every two adjacent sub-pixel regions A1 are mirror-imaged.

[0141] For example, referring to FIG8 , FIG8 shows a stacked diagram of the film layer structures of four adjacent sub-pixel regions A1 along the row direction. The film layer patterns in two adjacent sub-pixel regions A1 are mirror images. That is, the film layer patterns in the first sub-pixel region A11 and the second sub-pixel region A12 are mirror images in the row direction, the film layer patterns in the second sub-pixel region A12 and the third sub-pixel region A13 are mirror images in the row direction, and the film layer patterns in the third sub-pixel region A13 and the fourth sub-pixel region A14 are mirror images in the row direction. Furthermore, the film layer patterns in two adjacent sub-pixel regions A1 are mirror images. For example, the first active film layer in the first sub-pixel region A11 and the first active film layer in the second sub-pixel region A12 are mirror images in the row direction, and the first source / drain metal layer in the first sub-pixel region A11 and the first remote metal layer in the second sub-pixel region A12 are mirror images in the row direction. The use of this mirror setting can reduce the total area of ​​the multiple sub-pixel regions A1, further reducing the space occupied by the multiple sub-pixels, which is beneficial for improving the PPI of the display panel and simplifies the pattern design of each film layer.

[0142] In some embodiments, referring to Figure 9A, the active layer pattern of the first light-emitting control transistor T5 in the first sub-pixel area A11 overlaps with the active layer pattern of the first light-emitting control transistor T5 in the second sub-pixel area A12; the active layer pattern of the second reset transistor T7 in the second sub-pixel area A12 overlaps with the active layer pattern of the second reset transistor T7 in the third sub-pixel area A13.

[0143] For example, referring to Figure 9A , the active layer pattern of the first emission control transistor T5 in the first sub-pixel region A11 is configured to overlap with the active layer pattern of the first emission control transistor T5 in the second sub-pixel region A12. This overlapping portion is referred to as the first overlapping portion J1. Simultaneously, the active layer pattern of the second reset transistor T7 in the second sub-pixel region A12 is configured to overlap with the active layer pattern of the second reset transistor T7 in the third sub-pixel region A13. This overlapping portion is referred to as the second overlapping portion J2. It will be understood that any two adjacent sub-pixel regions A1 have an overlapping portion, which is either the first overlapping portion J1 or the second overlapping portion J2. The provision of the first overlapping portion J1 and the second overlapping portion J2 can, on the one hand, reduce the total area of ​​the multiple sub-pixel regions A1, thereby improving the PPI of the display panel. On the other hand, it can simplify the via hole fabrication process, as only a single via hole needs to be drilled in the overlapping portion to connect the active layer patterns of the transistors in the two adjacent sub-pixel regions to the corresponding signal lines.

[0144] In some embodiments, referring to Figure 9E, in the sub-pixel area A1, the first source-drain metal layer 109 includes a first bridge pattern Q1 and a second bridge pattern Q2, and the first bridge pattern Q1 of the first sub-pixel area A11 overlaps with the first bridge pattern Q1 of the second sub-pixel area A12; the second bridge pattern Q2 of the second sub-pixel area A12 overlaps with the second bridge pattern Q2 of the third sub-pixel area A13.

[0145] For example, as shown in FIG9E , the first bridge pattern Q1 of the first sub-pixel area A11 and the first bridge pattern Q1 of the second sub-pixel area A12 are arranged to overlap with each other, that is, the first bridge pattern Q1 can be shared by the first sub-pixel area A11 and the second sub-pixel area A12; similarly, continuing to refer to FIG9E , taking four adjacent sub-pixel areas A1 as an example, it can be seen from the figure that the second bridge pattern Q2 of the second sub-pixel area A12 and the second bridge pattern Q2 of the third sub-pixel area A13 overlap with each other, and the second bridge pattern Q2 can be shared by the second sub-pixel area A12 and the third sub-pixel area A13; accordingly, in a row of sub-pixel areas A1 arranged along the row direction X, except for the first sub-pixel area A1 and the last sub-pixel area A1, any two adjacent sub-pixel areas A1 have an overlapping portion, and the overlapping portion is the first bridge pattern Q1 or the second bridge pattern Q2.

[0146] The configuration of the first bridge pattern Q1 and the second bridge pattern Q2 can simplify the fabrication process of the first source / drain metal layer 109 and reduce the area occupied by two adjacent sub-pixel regions A1, thereby improving the PPI of the display panel.

[0147] In some embodiments, with continued reference to FIG. 9E , the second bridge patterns Q2 in the plurality of sub-pixel regions A1 arranged along the column direction Y are connected in sequence.

[0148] It should be noted that, as shown in FIG9E , taking four adjacent sub-pixel areas A1 as an example, in the first sub-pixel area A11, the second sub-pixel area A12, the third sub-pixel area A13, and the fourth sub-pixel area A14 in the figure, the second bridge patterns Q2 are all arranged along the column direction Y, and in the multiple sub-pixel areas A1 arranged along the column direction Y, the second bridge patterns Q2 of two adjacent sub-pixel areas A1 are connected to each other, that is, the second bridge patterns Q2 in the multiple sub-pixel areas A1 arranged along the column direction Y are connected in sequence to form a plurality of initialization signal bridge lines extending along the column direction Y. This arrangement can simplify the circuit layout of the first source / drain metal layer 109. At the same time, the second bridge pattern Q2 is connected to the initialization signal line. Multiple initialization signal lines are located in the second gate metal layer and extend along the row direction X. Multiple initialization signal bridge lines are located in the first source / drain metal layer and extend along the column direction Y. In this way, multiple lines for transmitting initialization signals form a grid structure, which facilitates signal transmission, improves signal transmission efficiency, reduces transmission voltage drop, improves the uniformity of initialization signals in different sub-pixel areas, and is beneficial to the uniformity of reset of each pixel driving circuit, thereby improving the display effect.

[0149] In some embodiments, as shown in Figure 9G, in the sub-pixel area A1, the active layer pattern of the first reset transistor T1 is connected to the active layer pattern of the compensation transistor T2, and the active layer pattern of the write transistor T4 is located on one side of the active layer pattern of the compensation transistor T2 in the row direction X; the active layer pattern of the first reset transistor T1 of the second sub-pixel area A12 is connected to the active layer pattern of the first reset transistor T1 of the third sub-pixel area A13.

[0150] Exemplarily, referring to Figure 9G, taking the four adjacent sub-pixel areas A1 as an example, in the first sub-pixel area A11, the second sub-pixel area A12, the third sub-pixel area A13 and the fourth sub-pixel area A14, the active layer pattern of the first reset transistor T1 is interconnected with the active layer pattern of the compensation transistor T2 and arranged along the column direction Y, and the active layer pattern of the write transistor T4 is located on one side of the active layer pattern of the compensation transistor T2 in the row direction X. For example, in the first sub-pixel area A11 and the third sub-pixel area A13 shown in Figure 9G, the active layer pattern of the write transistor T4 is located on the first side of the active layer pattern of the compensation transistor T2 in the row direction X. In the second sub-pixel area A12 and the fourth sub-pixel area A14 shown in Figure 9G, the active layer pattern of the write transistor T4 is located on the second side of the active layer pattern of the compensation transistor T2 in the row direction X. Continuing with reference to Figure 9G, the active layer pattern of the first reset transistor T1 in the second sub-pixel area A12 is connected to the active layer pattern of the first reset transistor T1 in the third sub-pixel area A13. This arrangement, on the one hand, can simplify the arrangement of the active layer pattern of the first reset transistor T1 and its corresponding circuit. That is, when setting the circuit connected to the active layer pattern of the first reset transistor T1 in the second sub-pixel area A12 and the third sub-pixel area A13, it is only necessary to connect the active layer pattern of the first reset transistor T1 in the second sub-pixel area A12 or the third sub-pixel area A13. On the other hand, it can reduce the total area of ​​the multiple sub-pixel areas A1, thereby improving the PPI of the display panel.

[0151] In some embodiments, referring to Figure 9K, the second source-drain metal layer 118 includes a first transfer pattern R1 and a second transfer pattern R2; the first transfer pattern R1 of the first sub-pixel area A11 overlaps with the first transfer pattern R1 of the second sub-pixel area A12; and the second transfer pattern R2 of the second sub-pixel area A12 overlaps with the second transfer pattern R2 of the third sub-pixel area A13.

[0152] For example, as shown in FIG9K , the first transfer pattern R1 of the first sub-pixel area A11 and the first transfer pattern R1 of the second sub-pixel area A12 overlap, that is, the first transfer pattern R1 can be shared by the first sub-pixel area A11 and the second sub-pixel area A12. Similarly, referring to FIG9K , taking four adjacent sub-pixel areas A1 as an example, it can be seen from the figure that the second transfer pattern R2 of the second sub-pixel area A12 and the second transfer pattern R2 of the third sub-pixel area A13 overlap, and the second transfer pattern R2 can be shared by the second sub-pixel area A12 and the third sub-pixel area A13. Accordingly, in a row of sub-pixel areas A1 arranged along the row direction X, except for the first sub-pixel area A1 and the last sub-pixel area A1, any two adjacent sub-pixel areas A1 have an overlapping portion, and the overlapping portion is the overlap of the first transfer pattern R1 and the first transfer pattern R1 or the overlap of the second transfer pattern R2 and the second transfer pattern R2.

[0153] Compared with the related art where the first transfer pattern R1 and the second transfer pattern R2 do not overlap, the above-mentioned arrangement of the first transfer pattern R1 and the second transfer pattern R2 simplifies the connection between the first transfer pattern R1 or the second transfer pattern R2 in the second source / drain metal layer 118 and other circuits, and can reduce the area occupied by two adjacent sub-pixel areas A1, thereby improving the PPI of the display panel.

[0154] In some embodiments, referring to Figure 9M, the third source-drain metal layer 120 includes a plurality of first voltage signal lines VDD, each of which is located in a column of sub-pixel areas A1; the first voltage signal line VDD includes alternatingly connected voltage patterns VDD1 and voltage sub-lines VDD2, and a size S1 of the voltage pattern VDD1 in the row direction X is larger than a size S2 of the voltage sub-line VDD2 in the row direction X; the first voltage signal line VDD of the second sub-pixel area A12 overlaps with the first voltage signal line VDD of the third sub-pixel area A13.

[0155] For example, referring to FIG9M , multiple first voltage signal lines VDD are arranged along the column direction Y, and each first voltage signal line VDD is located in a column of sub-pixel areas A1. In the column direction Y, the first voltage signal line VDD includes alternating voltage patterns VDD1 and voltage sub-lines VDD2. The dimension S1 of the voltage pattern VDD1 in the row direction X is larger than the dimension S2 of the voltage sub-line VDD2 in the row direction X. This is primarily based on spatial arrangement requirements and is intended to reduce resistance and improve the transmission efficiency of the first voltage signal line VDD. Furthermore, the block shape of the voltage pattern VDD1 improves the flatness of this area, which is beneficial to the flatness of the film layer pattern (e.g., the anode layer) located above it.

[0156] Continuing with reference to Figure 9M, the first voltage signal line VDD of the second sub-pixel area A12 and the first voltage signal line VDD of the third sub-pixel area A13 are set to overlap. In addition to reducing the area occupied by the sub-pixel area A1 and thereby improving the PPI of the display panel, it also has the function of simplifying the connection between the first voltage signal line VDD in the third source-drain metal layer 120 and other lines. The first voltage signal line VDD in the second sub-pixel area A12 and the third sub-pixel area A13 can both play the role of transmitting the first voltage signal. There is no need to be connected to the first voltage signal line VDD of the second sub-pixel area A12 or the first voltage signal line VDD in the third sub-pixel area A13. Only one of the two can be selected.

[0157] In some embodiments, as shown in FIG. 4 , the array substrate 10 further includes a first planarization layer 110 disposed between the first source / drain metal layer 109 and the third gate metal layer 112 . The thickness of the first planarization layer 110 ranges from 1.5 μm to 2 μm.

[0158] It should be noted that, referring to Figures 4, 5A, 6A and 6G, a first flat layer 110 is provided between the first source / drain metal layer 109 and the third gate metal layer 112, which can ensure that the bottom of the second type transistor T0' is flat, and the thickness of the first flat layer 110 is set to 1.5μm to 2μm, which has a large thickness range. It can play a certain isolation role between the first type transistor T0 and the second type transistor T0', and can reduce the parasitic capacitance between the first type transistor T0 and the second type transistor T0', thereby avoiding signal interference between the transistors.

[0159] In some embodiments, as shown in Figures 4, 6L and 7A, the array substrate 10 also includes a second planar layer 119 arranged between the second source-drain metal layer 118 and the third source-drain metal layer 120, and the third source-drain metal layer 120 is connected to the second source-drain metal layer 118 through a via penetrating the second planar layer 119.

[0160] For example, referring to Figure 6L, a plurality of first-class vias H are provided on the second flat layer 119, specifically including a first-class via H1, a first-class via H2 and a first-class via H3. Referring to Figure 7A, the third source-drain metal layer 120 is connected to the second source-drain metal layer 118 through the first-class via H1 that passes through the second flat layer 119, so as to transmit the first voltage signal transmitted by the first voltage signal line VDD in the third source-drain metal layer 120 to the first transfer pattern R1 of the second source-drain metal layer 118.

[0161] The embodiment of the present disclosure further provides a display panel 100, which includes the array substrate 10 provided by any of the above embodiments. Therefore, the display panel 100 provided by the present invention has all the advantages of the array substrate 10 provided by any of the above embodiments, which will not be described in detail here.

[0162] In some embodiments, referring to Figure 4, the display panel 100 also includes a third flat layer 30, a light-emitting device layer 40 and an encapsulation layer arranged on the array substrate 10, and the array substrate 10 includes: a base substrate 101 and a pixel circuit stack 20, the pixel circuit stack 20 includes a plurality of transistors, and the third flat layer 30, the light-emitting device layer 40 and the encapsulation layer are stacked in sequence on the pixel circuit stack 20.

[0163] The light emitting device layer 40 includes an anode layer 401 , a pixel defining layer 402 , a light emitting layer 403 and a cathode layer, which are arranged on the third planar layer 30 .

[0164] 4 , 6N , and 6O , the array substrate 10 includes a third source / drain metal layer 120. A third planar layer 30 is disposed on a side of the third source / drain metal layer 120 away from the base substrate. An anode layer 401 is disposed on the third planar layer 30. The anode layer 401 includes a plurality of anodes 4011, which are electrically connected to the third source / drain metal layer 120 via vias M1 extending through the third planar layer 30. The light-emitting layer 403 includes a plurality of light-emitting portions, each of which overlaps with an anode 4011. A plurality of pixel openings are formed in the pixel defining layer 402, each of which exposes a portion of an anode 4011. The light-emitting portions in the light-emitting layer 403 are disposed within the pixel openings in a one-to-one correspondence, so that the edges of the light-emitting portions overlap with the edges of the pixel openings.

[0165] The cathode layer is located on a side of the pixel defining layer 402 and the light emitting layer 403 away from the array substrate 10 .

[0166] The light-emitting device OLED shown in Figures 4 and 5A includes an anode, a cathode, and a light-emitting layer sandwiched between the anode and cathode. Applying voltage to the anode and cathode generates an electric field between them, which drives holes in the anode and electrons in the cathode to recombine in the light-emitting layer, causing the light-emitting layer to emit light. Anode 4011 is disposed on array substrate 10 and can be electrically connected to pixel driver circuit 200.

[0167] The display panel 100 may further include spacers PS, which are used to support FMM (Fine Metal Mask) when evaporating the light-emitting layer.

[0168] The encapsulation layer is located on the side of the cathode layer away from the array substrate 10. Exemplarily, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer. The encapsulation layer is used to encapsulate the light-emitting device to protect the light-emitting device OLED and avoid corrosion caused by external water and oxygen.

[0169] Some embodiments of the present disclosure provide a display device 1000, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, a wearable display device, etc. The embodiments of the present disclosure do not impose any particular restrictions on the specific form of the above-mentioned display device. As shown in FIG1 , the display device 1000 includes the display panel 100 provided in any of the above embodiments. Therefore, the display device 1000 provided by the present invention has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be described in detail here.

[0170] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: Multiple sub-pixel regions, each sub-pixel region is provided with a pixel driving circuit, and the multiple pixel driving circuits are arranged in multiple rows and multiple columns. Each pixel driving circuit among the multiple pixel driving circuits includes multiple first-type transistors and multiple second-type transistors, and the multiple second-type transistors at least include a writing transistor; The array substrate includes: A substrate; A first active film layer disposed on one side of the substrate, and the first active film layer includes active layer patterns of the multiple first-type transistors; A second active film layer disposed on the side of the first active film layer away from the substrate, and the second active film layer includes an active layer pattern of the writing transistor; A third source-drain metal layer disposed on the side of the second active film layer away from the substrate, and the third source-drain metal layer includes data signal lines, and the active layer pattern of the writing transistor is electrically connected to the data signal lines.

2. The array substrate according to claim 1, wherein The array substrate further includes: A first source-drain metal layer disposed between the first active film layer and the second active film layer; A second source-drain metal layer disposed between the second active film layer and the third source-drain metal layer; In the sub-pixel region, the second source-drain metal layer includes a data line transfer pattern; the data signal lines are connected to the data line transfer pattern through vias, and the data line transfer pattern is connected to the active layer pattern of the writing transistor.

3. The array substrate according to claim 2, wherein, The pixel driving circuit further includes a storage capacitor; The array substrate further includes: A first gate metal layer and a second gate metal layer sequentially disposed on the side of the first active film layer away from the substrate; In the sub-pixel region, the first gate metal layer includes a first plate pattern of the capacitor, and the second gate metal layer further includes a second plate pattern of the capacitor; The third source-drain metal layer further includes a first voltage signal line; In the sub-pixel region, the second source-drain metal layer further includes a first transfer pattern, and the first source-drain metal layer includes a first bridging pattern; The first voltage signal line is connected to the first transfer pattern of the second source-drain metal layer through a via, the first transfer pattern is connected to the first bridging pattern of the first source-drain metal layer through a via; the first bridging pattern is connected to the second plate in the second gate metal layer through a via, so that the first voltage signal line is electrically connected to the second plate.

4. The array substrate according to any one of claims 1 to 3, wherein, The second-type transistors further include a first reset transistor and a compensation transistor, and the first-type transistors include a driving transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a second reset transistor; The first active film layer includes active layer patterns of the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor, and the second active film layer further includes an active layer pattern of the first reset transistor and an active layer pattern of the compensation transistor.

5. The array substrate according to claim 4, wherein, Further included are: A third gate metal layer disposed between the first source-drain metal layer and the second active film layer; A fourth gate metal layer disposed on the side of the second active film layer away from the third gate metal layer; The third gate metal layer includes a first branch line of a first reset signal line and a first branch line of a scan signal line, the first branch line of the first reset signal line passes through an active layer pattern of a first reset transistor, and the first branch line of the scan signal line passes through an active layer pattern of the compensation transistor and an active layer pattern of the write transistor; The fourth gate metal layer includes a second branch line of a first reset signal line and a second branch line of a scan signal line, the second branch line of the first reset signal line passes through an active layer pattern of the first reset transistor, and the second branch line of the scan signal line passes through an active layer pattern of the compensation transistor and an active layer pattern of the write transistor; The first branch line of the first reset signal line is electrically connected to the second branch line of the first reset signal line; the first branch line of the scan signal line is electrically connected to the second branch line of the scan signal line.

6. The array substrate according to claim 4, wherein The array substrate further includes a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer; The second gate metal layer also includes a plurality of initialization signal lines; In the sub-pixel region, the first source-drain metal layer further includes a second bridge pattern, and the second source-drain metal layer further includes a second transfer pattern; The second bridge pattern is electrically connected to the active layer pattern of the second reset transistor and the initialization signal line through two vias, so that the active layer pattern of the second reset transistor and the initialization signal line are electrically connected; The second transfer pattern is respectively connected to the second bridge pattern and the active layer pattern of the first reset transistor through two via holes, so that the active layer pattern of the first reset transistor is electrically connected to the initialization signal line.

7. The array substrate according to claim 6, wherein In the sub-pixel region, the first source-drain metal layer further includes a third bridge pattern, and the second source-drain metal layer further includes a third transfer pattern; The third bridge pattern is connected to the first electrode plate of the capacitor in the second gate metal layer through a via, the third transfer pattern is connected to the third bridge pattern through a via, and the active layer pattern of the compensation transistor of the second active film layer is connected to the third transfer pattern through a via, so that the compensation transistor is electrically connected to the first electrode plate.

8. The array substrate according to claim 6 or 7, wherein In the sub-pixel region, the first source-drain metal layer further includes a fourth bridge pattern, and the second source-drain metal layer further includes a fourth transfer pattern; The fourth bridge pattern is connected to the active layer pattern of the second light emitting transistor of the first active film layer through a via hole. catch; The fourth transfer pattern is connected to the fourth bridge pattern through a via hole, and the active layer pattern of the compensation transistor of the second active film layer is connected to the fourth transfer pattern through a via hole, so that the compensation transistor is electrically connected to the second light emission control transistor.

9. The array substrate according to any one of claims 6 to 8, wherein, In the sub-pixel region, the first source-drain metal layer further includes a fifth bridge pattern, and the second source-drain metal layer further includes a fifth transfer pattern; The fifth bridge pattern is connected to the active layer pattern of the first light emission control transistor of the first active film layer through a via hole; The fifth transfer pattern is connected to the fifth bridging pattern through a via, and the active layer pattern of the writing transistor in the second active film layer is connected to the fifth transfer pattern through a via, so that the writing transistor is electrically connected to the first light-emitting control transistor.

10. The array substrate according to any one of claims 6 to 9, wherein The first source-drain metal layer further includes a sixth bridging pattern, and the second source-drain metal layer further includes a sixth transfer pattern; The sixth bridging pattern is connected to the active layer pattern of the second light-emitting control transistor in the first active film layer through a via; The sixth transfer pattern is connected to the sixth bridging pattern.

11. The array substrate according to any one of claims 1 to 10, wherein Four adjacent sub-pixel regions in the row direction are a first sub-pixel region, a second sub-pixel region, a third sub-pixel region, and a fourth sub-pixel region respectively. Among them, the film layer patterns in every two adjacent sub-pixel regions are mirror-symmetrically arranged.

12. The array substrate according to claim 11, wherein, The active layer pattern of the first light-emitting control transistor in the first sub-pixel region overlaps with the active layer pattern of the first light-emitting control transistor in the second sub-pixel region; the active layer pattern of the second reset transistor in the second sub-pixel region overlaps with the active layer pattern of the second reset transistor in the third sub-pixel region.

13. The array substrate according to claim 11, wherein, In the sub-pixel region, the first source-drain metal layer includes a first bridging pattern and a second bridging pattern, The first bridging pattern in the first sub-pixel region coincides with the first bridging pattern in the second sub-pixel region; the second bridging pattern in the second sub-pixel region coincides with the second bridging pattern in the third sub-pixel region.

14. The array substrate according to claim 13, wherein, The second bridging patterns in a plurality of sub-pixel regions arranged in the column direction are sequentially connected.

15. The array substrate according to claim 11, wherein, In the sub-pixel region, the active layer pattern of the first reset transistor is connected to the active layer pattern of the compensation transistor, and the active layer pattern of the writing transistor is located on one side of the active layer pattern of the compensation transistor in the row direction; The active layer patterns of the first reset transistors in the second sub-pixel region and the third sub-pixel region are connected.

16. The array substrate according to claim 11, wherein, The second source-drain metal layer includes a first transfer pattern and a second transfer pattern; There is an overlap between the first transfer pattern in the first sub-pixel region and the first transfer pattern in the second sub-pixel region; there is an overlap between the second transfer pattern in the second sub-pixel region and the second transfer pattern in the third sub-pixel region.

17. The array substrate according to claim 11, wherein, The third source-drain metal layer includes a plurality of first voltage signal lines, and each first voltage signal line is located in a column of sub-pixel regions; The first voltage signal line includes alternately connected voltage patterns and voltage sub-lines, and the size of the voltage pattern in the row direction is larger than the size of the voltage sub-line in the row direction; The first voltage signal lines in the second sub-pixel region and the third sub-pixel region overlap.

18. The array substrate according to claim 5, wherein, It further includes a first planarization layer disposed between the first source-drain metal layer and the third gate metal layer, and the thickness range of the first planarization layer is 1.5 μm to 2 μm.

19. The array substrate according to claim 2, wherein, Further included is a second planarization layer disposed between the second source / drain metal layer and the third source / drain metal layer, and the third source / drain metal layer is connected to the second source / drain metal layer through a via hole penetrating through the second planarization layer.

20. The array substrate according to claim 1, wherein, The first active film layer is a low-temperature polysilicon layer, and the second active film layer is an oxide layer.

21. A display panel, comprising: The array substrate according to any one of claims 1 to 20.

22. The display panel according to claim 21, further comprising: A third planarization layer disposed on a side of the third source / drain metal layer away from the substrate; An anode layer disposed on the third planarization layer, the anode layer including a plurality of anodes; A pixel defining layer disposed on a side of the anode layer away from the substrate; A spacer disposed on a side of the pixel defining layer away from the substrate; Wherein, the array substrate includes a third source / drain metal layer, and the plurality of anodes are electrically connected to the third source / drain metal layer through via holes penetrating through the third planarization layer.

23. A display device, comprising: The display panel according to claim 21 or 22.

Images