Liquid crystal display panel and display apparatus

Abstract

A liquid crystal display panel and a display apparatus. The liquid crystal display panel comprises an array substrate and an opposed substrate which are oppositely arranged, and a liquid crystal layer provided between the array substrate and the opposed substrate; the array substrate comprises a first base substrate and a plurality of pixel structures located on the first base substrate; and the opposed substrate comprises a second base substrate and an anti-overflow structure, the anti-overflow structure being arranged on the side of the second base substrate facing the array substrate and being configured to prevent a liquid crystal in the liquid crystal layer from overflowing. The liquid crystal display panel comprises a display area and a peripheral area surrounding the display area; the liquid crystal display panel further comprises a frame sealant located in the peripheral area and arranged between the array substrate and the opposed substrate; and the anti-overflow structure surrounds the display area, and is arranged on the side of the frame sealant close to the display area. After droplets of the liquid crystal drip on the opposed substrate, the anti-overflow structure can prevent the liquid crystal from overflowing, avoiding diffusion of the liquid crystal to the boundary of the frame sealant and avoiding impact on the frame sealant, thus increasing the pass rate of products.

Description

Liquid crystal display panel and display device Technical Field

[0001] Embodiments of the present disclosure relate to a liquid crystal display panel and a display device. Background Art

[0002] In the field of display technology, liquid crystal displays (LCDs) have the advantages of being light, thin, low power consumption, high brightness, and high image quality.

[0003] Typically, a thin-film transistor liquid crystal display (TFT-LCD) consists of an array substrate, an opposing substrate, a liquid crystal layer sandwiched between the array and opposing substrates, and a sealant used to bond the outer edges of the array and opposing substrates. TFT-LCDs utilize variations in the electric field strength across the liquid crystal layer between the array and opposing substrates to alter the orientation of liquid crystal molecules within the layer, thereby controlling the amount of light transmitted to display images.

[0004] In recent years, the trend toward miniaturization of display screens has become increasingly evident. Applications such as scanner pens, e-cigarettes, and knobs have all commonly used small screens under one inch. Thin-film transistor liquid crystal displays (TFT-LCDs) can meet the requirements for upgrading small-screen products while maintaining a low cost, enhancing product display quality.

[0005] Summary of the Invention

[0006] In order to solve the problem of normal box alignment caused by the diffusion of liquid crystal droplets in miniaturized liquid crystal display panels, the embodiments of the present disclosure provide a liquid crystal display panel, on which an anti-overflow structure is provided on the opposing substrate to prevent liquid crystal overflow and avoid liquid crystal diffusion to the boundary of the frame sealing glue. It can also buffer the impact of buffered liquid crystal droplets on the frame sealing glue, improve the puncture problem, and improve the product yield.

[0007] At least one embodiment of the present disclosure provides a liquid crystal display panel, comprising an array substrate and an opposing substrate arranged relative to each other, and a liquid crystal layer arranged between the array substrate and the opposing substrate, the array substrate comprising a first base substrate and a plurality of pixel structures located on the first base substrate, the opposing substrate comprising: a second base substrate; and an anti-overflow structure, arranged on a side of the second base substrate facing the array substrate and configured to prevent liquid crystal in the liquid crystal layer from overflowing, the liquid crystal display panel comprising a display area and a peripheral area surrounding the display area, the liquid crystal display panel further comprising a frame sealing glue located in the peripheral area and arranged between the array substrate and the opposing substrate, the anti-overflow structure surrounding the display area and arranged on a side of the frame sealing glue close to the display area.

[0008] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, the maximum size of the display area of ​​the liquid crystal display panel on a plane parallel to the second base substrate is less than or equal to 30 mm.

[0009] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, on a plane parallel to the second base substrate, the distance between the anti-overflow structure and the display area ranges from 100μm to 300μm, and the distance between the anti-overflow structure and the frame sealing glue ranges from 100μm to 300μm.

[0010] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the opposing substrate further includes a spacer, which is located in the display area and is arranged on the side of the second base substrate facing the array substrate, and the anti-overflow structure is configured to be formed by the same material and the same patterning process as the spacer.

[0011] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the anti-overflow structure includes at least one anti-overflow cofferdam.

[0012] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, the anti-overflow dam includes a polygon on a plane parallel to the second base substrate, and the anti-overflow dam includes a plurality of gaps.

[0013] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the anti-overflow dam includes a notch, the opposing substrate further includes an orientation layer, the orientation layer is arranged on the side of the second base substrate facing the array substrate, and has an orientation direction, and the notch is located at a position of the anti-overflow dam that is farthest from the center line of the display area in the orientation direction.

[0014] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the anti-overflow cofferdam includes: a first anti-overflow cofferdam having a first opening; and a second anti-overflow cofferdam having a second opening, the first opening and the second opening are arranged relative to each other, and the first anti-overflow cofferdam and the second anti-overflow cofferdam have an interlaced area, in which the first anti-overflow cofferdam and the second anti-overflow cofferdam are spaced apart to form a channel.

[0015] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the opposing substrate further includes an orientation layer, which is arranged on the side of the second base substrate facing the array substrate and has an orientation direction, and the staggered area is arranged at a position on the anti-overflow cofferdam that is farthest from the center line of the display area in the orientation direction.

[0016] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the first anti-overflow cofferdam includes a first sub-section and a second sub-section arranged opposite to each other, and a first connecting section connecting the first sub-section and the second sub-section, the second anti-overflow cofferdam includes a third sub-section and a fourth sub-section arranged opposite to each other, and a second connecting section connecting the third sub-section and the fourth sub-section, the first sub-section and the third sub-section have an interlaced area and are arranged at intervals to form a channel, and the second sub-section and the fourth sub-section have an interlaced area and are arranged at intervals to form a channel.

[0017] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the anti-overflow dam includes a plurality of first anti-overflow parts and a plurality of second anti-overflow parts. In the direction perpendicular to the second base substrate, the size of the first anti-overflow part is larger than the size of the second anti-overflow part. In the extension direction of the anti-overflow dam, the first anti-overflow part and the second anti-overflow part are alternately arranged.

[0018] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, in a direction perpendicular to the second base substrate, the difference in height between the first anti-overflow portion and the second anti-overflow portion ranges from 0.5 μm to 0.65 μm.

[0019] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the opposing substrate further includes a planarization layer, which is arranged on the side of the second base substrate facing the array substrate, and the anti-overflow structure includes at least one anti-overflow groove formed in the planarization layer and recessed toward the second base substrate.

[0020] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, the depth of the anti-overflow groove ranges from 0.5 μm to 1.5 μm, and the width of the anti-overflow groove ranges from 200 μm to 400 μm.

[0021] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the opposing substrate further includes: an electrostatic release layer, which is arranged on the side of the second base substrate facing the array substrate, the sealing frame is at least partially connected to the electrostatic release layer, and the sealing frame is configured to have conductivity so that the electrostatic release layer is connected to the array substrate through the sealing frame.

[0022] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the array substrate further includes a common electrode layer, which is arranged on the side of the first base substrate facing the opposing substrate, and the common electrode layer includes a common electrode located in the display area and a conductive structure located in the peripheral area, and the frame sealing glue is at least partially connected to the conductive structure.

[0023] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the array substrate further includes a first common electrode line surrounding the display area and a second common electrode line surrounding the first common electrode line, the first common electrode line is connected to the second common electrode line, the first common electrode line is connected to the common electrode, the second common electrode line is connected to the signal input port of the liquid crystal display panel, and the array substrate further includes a via, and the second common electrode line is connected to the conductive structure through the via.

[0024] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, the orthographic projection of the frame sealant on the first base substrate at least partially overlaps with the orthographic projection of the second common electrode line on the first base substrate, and the second common electrode line includes a metal grid line.

[0025] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the array substrate also includes a first common electrode line surrounding the display area and a second common electrode line surrounding the first common electrode line, the first common electrode line is connected to the second common electrode line, the first common electrode line is connected to the common electrode of the display area, the second common electrode line is connected to the first signal input port of the liquid crystal display panel to be provided with a first voltage signal, and the conductive structure is connected to the second signal input port of the liquid crystal display panel through a lead to be provided with a second voltage signal.

[0026] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, on a plane parallel to the second base substrate, the conductive structure is located on a side of the second common electrode line away from the display area, and on a side of the second common electrode line close to the input port of the liquid crystal display panel.

[0027] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, the difference between the first voltage signal and the second voltage signal ranges from 0 to 3 volts.

[0028] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the plurality of pixel structures are arranged along a first direction and a second direction, the second direction intersecting the first direction, and in the pixel structure, the common electrode includes a plurality of first slits extending along the first direction and arranged along the second direction, and the electrostatic release layer includes a plurality of electrostatic release parts corresponding to the plurality of pixel structures, each of the electrostatic release parts including a plurality of second slits extending along the first direction and arranged along the second direction.

[0029] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, in the pixel structure, the multiple second slits are arranged at equal intervals, and in the second direction, the ratio of the size between two adjacent second slits to the size of the second slit is in the range of 1.0-1.5.

[0030] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, in the pixel structure, the multiple first slits and the multiple second slits are arranged in a one-to-one correspondence, and in the second direction, the first slits and the second slits arranged corresponding to each other have the same size.

[0031] For example, in the liquid crystal display panel provided in an embodiment of the present disclosure, in the pixel structure, the array substrate further includes a block pixel electrode, and the block pixel electrode is located between the second base substrate and the common electrode layer.

[0032] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the opposing substrate further includes: a black matrix layer, arranged on the side of the second base substrate facing the array substrate; a color filter layer, arranged on the side of the second base substrate facing the array substrate; and a planarization layer, arranged on the side of the black matrix layer and the color filter layer facing the array substrate, and the anti-overflow structure is arranged on the side of the planarization layer facing the array substrate.

[0033] At least one embodiment of the present disclosure provides a liquid crystal display panel including any one of the above-mentioned ones. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0035] Figure 1 is a schematic diagram of the diffusion of a 0.2 mg liquid crystal droplet;

[0036] FIG2 is a schematic cross-sectional view of a liquid crystal display panel provided in one embodiment of the present disclosure;

[0037] FIG3 is a schematic diagram of an anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0038] FIG4 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0039] FIG5 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0040] FIG6 is a schematic cross-sectional view of the liquid crystal display panel shown in FIG5 ;

[0041] FIG7 is a schematic diagram of another anti-overflow cofferdam for an opposing substrate provided in one embodiment of the present disclosure;

[0042] FIG8 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0043] FIG9 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0044] FIG10 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0045] FIG11A is a schematic diagram of another anti-overflow cofferdam provided by an embodiment of the present disclosure;

[0046] FIG11B is a partial schematic diagram of the anti-overflow cofferdam shown in FIG11A ;

[0047] FIG12 is a schematic diagram of another anti-overflow cofferdam provided by an embodiment of the present disclosure;

[0048] FIG13 is a schematic diagram of another anti-overflow structure of an opposing substrate provided in one embodiment of the present disclosure;

[0049] FIG14 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0050] FIG15 is a schematic diagram of static electricity on an opposing substrate of a liquid crystal display panel;

[0051] FIG16 is a cross-sectional schematic diagram of a liquid crystal display panel provided in one embodiment of the present disclosure;

[0052] FIG17 is a schematic diagram of a partial structure of a liquid crystal display panel in FIG16;

[0053] FIG18 is a partial enlarged view of FIG17 at position A and position B;

[0054] FIG19 is a partial enlarged view of FIG17 at position C and position D;

[0055] FIG20 is a partial enlarged view of FIG17;

[0056] FIG21 is a schematic cross-sectional view of the conductive layers of FIG17 being connected;

[0057] FIG22 is a partial enlarged view of FIG17 at position E;

[0058] FIG23 is a schematic cross-sectional view of FIG22 ;

[0059] FIG24 is a schematic diagram of an electric field of a liquid crystal display panel;

[0060] FIG25 is a schematic diagram of a partial structure of another liquid crystal display panel of FIG16;

[0061] FIG26 is a partial enlarged schematic diagram of FIG25;

[0062] FIG27 is a partial enlarged view of FIG25 at positions F and G;

[0063] FIG28 is a partial enlarged view of FIG25 at position J;

[0064] FIG29 is a partial enlarged view of FIG25 at position K;

[0065] FIG30 is a schematic cross-sectional view of FIG28;

[0066] FIG31 is a partial cross-sectional schematic diagram of another liquid crystal display panel provided by an embodiment of the present disclosure;

[0067] FIG32 is a schematic top view of a portion of a pixel structure corresponding to FIG31 ;

[0068] FIG33 is a partial cross-sectional schematic diagram of another liquid crystal display panel 100 provided in one embodiment of the present disclosure;

[0069] FIG34 is a schematic top view of a portion of a pixel structure corresponding to FIG33 ;

[0070] FIG35 is a partial cross-sectional schematic diagram of another liquid crystal display panel provided by an embodiment of the present disclosure;

[0071] FIG36 is a schematic partial top view of a pixel structure corresponding to FIG35 ;

[0072] FIG37 is a light effect diagram of two solutions according to an embodiment of the present disclosure at grayscale L255;

[0073] FIG38 is a schematic diagram of a liquid crystal deflection simulation of the liquid crystal display panel shown in FIG31 at grayscale L0;

[0074] FIG39 is a light effect diagram of the liquid crystal display panel shown in FIG35 at grayscale L255;

[0075] FIG40 is a schematic diagram showing a simulation of liquid crystal deflection of the liquid crystal display panel shown in FIG at grayscale L255;

[0076] FIG41 is a schematic diagram of a display device provided by an embodiment of the present disclosure; and

[0077] FIG42 is a flow chart of a method for manufacturing a liquid crystal display panel provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0079] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0080] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present disclosure include the cases of "parallel", "perpendicular", "same" in a strict sense, as well as the cases of "approximately parallel", "approximately perpendicular", "approximately the same" and the like which contain certain errors. For example, the above-mentioned "approximately" may mean that the difference between the compared objects is 10% of the average value of the compared objects, or within 5%. When the number of a component or element is not specifically indicated below in the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer arrangement" in the embodiments of the present disclosure refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0081] Currently, there are very few miniaturized thin-film transistor liquid crystal displays of 1 inch or less on the market, and the market for thin-film transistor liquid crystal displays between 0.4 and 0.8 inches is in a blank stage, with no product channels available.

[0082] The production process of miniaturized LCDs requires overcoming numerous challenges. During the one-drop filling (ODF) stage, the small amount of liquid crystal in the product prevents the liquid crystal dispenser from accurately dripping, and liquid tension also limits the dripping speed. Extensive testing and verification are required to determine the positional accuracy of the liquid crystal droplets, the upper limit of the number of sections that can be stably dripped, the accuracy of the dripping amount, and the dripping time.

[0083] Typically, the liquid crystal droplet process for miniaturized thin-film transistor liquid crystal displays involves dripping liquid crystal onto the array substrate, applying sealant to the opposing substrate, and then performing vacuum cell alignment. Finally, the process is released to atmospheric pressure for cutting. For example, Figure 1 shows the spread of a 0.2mg liquid crystal droplet, using a 0.42-inch product as an example. As shown in Figure 1, the spread diameter D01 of the liquid crystal droplet (approximately 0.2mg) on ​​the array substrate before cell alignment is approximately 9mm, exceeding the minimum inter-interval spacing D02 (approximately 6.4mm) of the sealant frame within the liquid crystal cell.

[0084] During the liquid crystal deposition phase, for example, if the liquid crystal droplet size is 0.2mg / dot, a sheet of glass measuring 1300mm*1100mm requires over 10,000 cuts. By the time all the liquid crystal has been deposited, the first droplet has already spread beyond the area of ​​the panel's sealant frame, preventing proper assembly. Furthermore, the smaller the size of the TFT-LCD display, the greater the impact of the liquid crystal droplets on the sealant during assembly of the array substrate and counter substrate, resulting in the risk of poor penetration and even fracture of the sealant.

[0085] To this end, embodiments of the present disclosure provide a liquid crystal display panel and a display device. The liquid crystal display panel includes an array substrate and an opposing substrate disposed oppositely, and a liquid crystal layer disposed between the array substrate and the opposing substrate. The array substrate includes a first base substrate and a plurality of pixel structures disposed on the first base substrate. The opposing substrate includes a second base substrate and an anti-overflow structure. The anti-overflow structure is disposed on a side of the second base substrate facing the array substrate and is configured to prevent liquid crystal in the liquid crystal layer from overflowing. The liquid crystal display panel includes a display area and a peripheral area surrounding the display area. The liquid crystal display panel also includes a frame sealant disposed in the peripheral area and disposed between the array substrate and the opposing substrate. The anti-overflow structure surrounds the display area and is disposed on the side of the frame sealant closest to the display area.

[0086] In the liquid crystal display panel provided in the disclosed embodiments, an anti-overflow structure is provided on the opposing substrate. This anti-overflow structure is located on the side of the frame sealant near the display area. After liquid crystal droplets are deposited on the opposing substrate, the anti-overflow structure prevents the liquid crystal from overflowing, preventing it from diffusing to the boundary of the frame sealant and thus affecting the alignment of the array substrate and opposing substrate. Furthermore, the anti-overflow structure buffers the impact of liquid crystal droplets on the frame sealant, improving puncture issues and increasing product yield.

[0087] The liquid crystal display panel and the display device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0088] An embodiment of the present disclosure provides a liquid crystal display panel. FIG2 is a schematic cross-sectional view of a liquid crystal display panel provided by an embodiment of the present disclosure. As shown in FIG2 , the liquid crystal display panel 100 includes an array substrate 110 and an opposing substrate 120 disposed opposite each other, and a liquid crystal layer 130 disposed between the array substrate 110 and the opposing substrate 120. The array substrate 110 includes a first base substrate 111 and a plurality of pixel structures disposed on the first base substrate 111. The opposing substrate 120 includes a second base substrate 121 and an anti-overflow structure 122. The anti-overflow structure 122 is disposed on the side of the second base substrate 121 facing the array substrate 110 and is configured to prevent liquid crystal in the liquid crystal layer 130 from overflowing. The liquid crystal display panel 100 includes a display area AA and a peripheral area BB surrounding the display area AA. The liquid crystal display panel 100 also includes a frame sealant 140 located in the peripheral area BB and disposed between the array substrate 110 and the opposing substrate 120. The anti-overflow structure 122 surrounds the display area AA and is disposed on the side of the frame sealant 140 near the display area AA.

[0089] In the liquid crystal display panel 100 provided in the embodiment of the present disclosure, an anti-overflow structure 122 is provided on the opposing substrate 120. The anti-overflow structure 122 is provided on the side of the frame-sealing glue 140 close to the display area AA. After the liquid crystal droplets are dripped onto the opposing substrate 120, the anti-overflow structure 122 can prevent the liquid crystal from overflowing, prevent the liquid crystal from diffusing to the boundary of the frame-sealing glue 140, and prevent the diffusion of the liquid crystal from affecting the alignment of the array substrate 110 and the opposing substrate 120. In addition, the anti-overflow structure 122 can also buffer the impact of the liquid crystal droplets on the frame-sealing glue 140, improve the puncture problem, and improve the yield rate of the product. It should be noted that the anti-overflow structure 122 is used to prevent the liquid crystal from overflowing during the liquid crystal dripping (ODF, One Drop Filling) stage, so that the array substrate 110 and the opposing substrate 120 can be aligned normally.

[0090] In the present disclosure, the pixel structure on the array substrate 110 includes a pixel driving circuit and a pixel electrode. For example, the pixel driving circuit can be connected to the pixel electrode to apply a pixel driving signal, thereby controlling the deflection of the liquid crystal. For example, multiple pixel structures correspond to multiple sub-pixels to achieve different color luminous displays. In some examples, the pixel structure also includes a common electrode for generating an electric field with the pixel electrode.

[0091] In some examples, the maximum dimension of the display area AA of the LCD panel 100, measured on a plane parallel to the second base substrate 121, is less than or equal to 30 mm. The smaller the display area AA of the LCD panel 100, the smaller the distance between the liquid crystal and the sealant 140, due to the size of the entire LCD panel 100. This makes it easier for the liquid crystal to overflow into the sealant 140. Furthermore, the smaller the display area AA, the smaller the number of liquid crystal droplets. For example, there may be only one or two liquid crystal droplets. By the time the liquid crystal droplet injection phase is complete, the first droplet injected may have already spread to the sealant 140. Therefore, for smaller LCD panels 100, the anti-overflow structure 122 is even more necessary to prevent liquid crystal from overflowing and spreading to the boundaries of the sealant 140. Furthermore, the smaller the size of the LCD panel 100, the greater the impact of liquid crystal droplets on the sealant 140. Therefore, the anti-overflow structure 122 is even more necessary to reduce the impact of liquid crystal droplets on the sealant 140 and alleviate puncture problems.

[0092] For example, the display area AA of the LCD panel 100 may be rectangular, with a diagonal length less than or equal to 30 mm. For example, the display area AA of the LCD panel 100 may be circular, with a diameter less than or equal to 30 mm.

[0093] In some examples, as shown in FIG2 , on a plane parallel to the second base substrate 121 , the distance D1 between the anti-overflow structure 122 and the display area AA ranges from 100 μm to 300 μm. This can prevent the alignment layer from accumulating on the anti-overflow structure 122 due to the small distance between the two, and prevent the anti-overflow structure 122 from affecting the alignment layer, thereby avoiding the resulting uneven display.

[0094] In some examples, as shown in FIG2 , the distance D2 between the anti-overflow structure 122 and the sealant 140 on a plane parallel to the second base substrate 121 ranges from 100 μm to 300 μm. This prevents the sealant 140 from accumulating on the anti-overflow structure 122 due to a small distance between the two due to fluctuations in the coating accuracy of the sealant 140, thereby preventing the sealant 140 from increasing in thickness in the peripheral area BB of the liquid crystal display panel 100 and preventing problems such as yellowing of the display.

[0095] In some examples, as shown in FIG2 , the counter substrate 120 further includes a spacer 123 . The spacer 123 is located in the display area AA and disposed on the side of the second base substrate 121 facing the array substrate 110 . The anti-overflow structure 122 is configured to be formed from the same material and through the same patterning process as the spacer 123 . The anti-overflow structure 122 and the spacer 123 are formed from the same material and through the same patterning process, so that the formation of the anti-overflow structure 122 does not require additional process steps and production costs. For example, as shown in the figure, the anti-overflow structure 122 and the spacer 123, formed from the same material and through the same patterning process, have the same cross-section.

[0096] In some examples, as shown in FIG2 , the spacer 123 includes a main spacer 1231 and a supplementary spacer 1232. In a direction perpendicular to the second base substrate 121, the main spacer 1231 is taller than the supplementary spacer 1232. When the anti-overflow structure 122 and the spacer 123 are formed from the same material and through the same patterning process, the height of the anti-overflow structure 122 can be the same as that of the main spacer 1231 or the supplementary spacer 1232.

[0097] In some examples, as shown in FIG2 , the anti-overflow structure 122 includes an anti-overflow weir 1221. The anti-overflow structure 122 is configured as a weir to more effectively prevent liquid crystal from overflowing. Of course, the disclosed embodiments do not limit the height of the anti-overflow weir 1221 in a direction perpendicular to the second base substrate 121 and can be designed based on product size and process requirements.

[0098] In some examples, when the total volume of the liquid crystal in the liquid crystal layer 130 accounts for a large portion of the volume of the display area, for example, when the inner spacing of the sealant 140 is less than 6 mm, the height of the anti-overflow dam 1221 can be set higher in the direction perpendicular to the second base substrate 121. A higher anti-overflow dam 1221 can prevent liquid crystal from overflowing and provide greater puncture resistance. For example, the anti-overflow dam 1221 can be the same height as the main spacer 1231. When the total volume of the liquid crystal in the liquid crystal layer 130 accounts for a moderate portion of the volume of the display area, for example, when the inner spacing of the sealant 140 is greater than 6 mm, the height of the anti-overflow dam 1221 can be set at a moderate height in the direction perpendicular to the second base substrate 121. For example, the anti-overflow dam 1221 can be the same height as the auxiliary spacer 1232. This can minimize the increase in the peripheral BB gap caused by the accumulation of sealant 140 on the anti-overflow structure 122, thereby avoiding problems such as yellowing of the display. The display area volume component refers to the product of the area of ​​the display area AA and the cell thickness after the array substrate 110 and the counter substrate 120 are assembled.

[0099] In addition, the height of the anti-overflow cofferdam 1221 is moderate or the same as the height of the auxiliary spacer 1232, which can also make the liquid crystal droplets have better fluidity after dripping onto the opposing substrate 120, so that the liquid crystal is more evenly filled in the display area AA, avoiding the formation of vacuum bubbles after the array substrate 110 and the opposing substrate 120 are assembled.

[0100] Figure 3 is a schematic diagram of an anti-overflow structure for a counter substrate according to one embodiment of the present disclosure. As shown in Figure 3 , the anti-overflow structure 122 comprises a closed structure surrounding the display area AA. Thus, the anti-overflow structure 122 effectively prevents liquid crystal from overflowing. In this example, the display area AA of the liquid crystal display panel 100 is rectangular.

[0101] In some examples, as shown in FIG3 , the LCD panel 100 is rectangular, the inner spacing of the frame sealant 140 of the LCD panel 100 is 6.4 mm and 10.2 mm, respectively, and the liquid crystal droplet dripping onto the opposing substrate 120 of the LCD panel 100 is 0.2 mg. Therefore, the anti-overflow structure 122 in any of the above embodiments can effectively prevent the overflow of liquid crystal and the impact on the frame sealant 140.

[0102] FIG4 is a schematic diagram of another anti-overflow structure for an opposing substrate provided in an embodiment of the present disclosure. As shown in FIG4 , the anti-overflow structure 122 includes a closed structure surrounding the display area AA, thereby effectively preventing the overflow of liquid crystal. In this example, the display area AA of the liquid crystal display panel 100 is circular. Of course, the embodiment of the present disclosure does not limit the shape of the display area AA of the liquid crystal display panel 100. For example, the display area AA may also be elliptical, polygonal, or irregularly shaped, and the shape of the anti-overflow structure 122 may follow the shape of the display area AA.

[0103] Figure 5 is a schematic diagram of another anti-overflow structure for an opposing substrate according to an embodiment of the present disclosure; Figure 6 is a cross-sectional schematic diagram of the liquid crystal display panel shown in Figure 5 . As shown in Figures 5 and 6 , the liquid crystal display panel 100 includes two circles of anti-overflow structure 122, which are closed structures. Of course, the present embodiment does not limit the number of circles of anti-overflow structure 122.

[0104] 5 and 6 , the dimensions of the multi-ring anti-overflow structure 122 may be the same in a direction perpendicular to the second base substrate 121. Of course, the dimensions of the multi-ring anti-overflow structure 122 may also be different in a direction perpendicular to the second base substrate 121.

[0105] In some examples, as shown in FIG6 , the width D3 of the multi-ring anti-overflow structure 122 ranges from 50 μm to 150 μm.

[0106] FIG7 is a schematic diagram of another anti-overflow dam for an opposing substrate provided in accordance with an embodiment of the present disclosure. As shown in FIG7 , the display area AA of the liquid crystal display panel 100 is rectangular. The anti-overflow dam 1221 is roughly rectangular surrounding the display area AA on a plane parallel to the second base substrate 121. The display area AA includes two oppositely disposed long sides and two oppositely disposed short sides. The anti-overflow dam 1221 includes two notches 1222. The two notches 1222 of the anti-overflow structure 122 are disposed on the side where the short sides of the display area AA are located. The notches 1222 on the short sides of the anti-overflow dam 1221 are relatively far from the center of the display area AA. Providing the notches 1222 on the short sides can not only effectively prevent the overflow of liquid crystal, but also improve the fluidity of the liquid crystal toward the short sides that are farther from the center of the display area, allowing the liquid crystal to be more evenly filled in the display area AA, thereby avoiding the formation of vacuum bubbles after the array substrate 110 and the opposing substrate 120 are assembled.

[0107] For example, as shown in FIG7 , the two notches 1222 of the anti-overflow structure 122 can be located at the center of the side where the short side of the display area AA is located. When the array substrate 110 and the counter substrate 120 are aligned, the liquid crystal is squeezed and diffuses toward the periphery. Compared to arranging the notches 1222 at the edge of the side where the short side is located, arranging the notches 1222 at the center of the side where the short side is located is more conducive to uniform diffusion of the liquid crystal and avoids the formation of vacuum bubbles after alignment.

[0108] For example, the notch 1222 shown in FIG. 7 passes through the anti-overflow cofferdam 1221 in a direction perpendicular to the second base substrate 121 . However, the notch 1222 may not pass through the anti-overflow cofferdam 1221 in a direction perpendicular to the second base substrate 121 .

[0109] For example, as shown in FIG7 , the location where the liquid crystal droplets flow toward the opposing substrate 120 is at the center of the display area AA. This location is farther from the short side than from the long side. Providing a notch 1222 at the center of the side where the short side is located effectively prevents liquid crystal overflow and improves the fluidity of the liquid crystal droplets spreading toward the short side. Of course, the disclosed embodiments do not limit the location and number of notches 1222. The optimal location and number of notches 1222 can be determined based on the actual product size, the number of droplets, and the location.

[0110] For example, the liquid crystal droplets may be directed toward the opposing substrate 120 at multiple locations, at least one of which is not at the center of the display area AA. This location is farther from the long side than from the short side. Thus, the notch 1222 may be provided on the long side of the display area AA. For example, multiple notches 1222 may be provided on the long side to increase the fluidity of the liquid crystal droplets.

[0111] The disclosed embodiments do not limit the number, shape, or location of the notches 1222 in the anti-overflow cofferdam 1221. For example, the anti-overflow cofferdam 1221 may include multiple notches 1222, and the anti-overflow cofferdam 1221 may comprise a polygon in a plane parallel to the second base substrate 121, with the multiple notches 1222 positioned at the centers of multiple sides of the anti-overflow cofferdam 1221. For example, the number of notches 1222 in the anti-overflow cofferdam 1221 may be half the number of sides of the anti-overflow cofferdam 1221. For example, the multiple notches 1222 may be positioned in opposite directions.

[0112] In some examples, as shown in Figure 7, the dimension D4 of the notch 1222 in the extension direction of the anti-overflow cofferdam 1221 can be 15% to 25% of the length of the side where the notch 1222 is located. Of course, the embodiments of the present disclosure are not limited to this, and the optimal value can be obtained through testing and verification based on actual products.

[0113] Figure 8 is a schematic diagram of another anti-overflow structure for a counter substrate according to an embodiment of the present disclosure. As shown in Figure 8 , the anti-overflow weir 1221 includes a plurality of notches 1222 . These notches 1222 are disposed on the long sides of the display area AA of the anti-overflow weir 1221 . The notches 1222 are also disposed at the four corners of the display area AA, thereby further improving the fluidity of the liquid crystal droplets.

[0114] FIG9 is a schematic diagram of another anti-overflow structure of an opposing substrate provided in an embodiment of the present disclosure. As shown in FIG9 , the opposing substrate 120 further includes an alignment layer, which is disposed on the side of the second base substrate 121 facing the array substrate 110 and has an alignment direction a1. The display area AA has a centerline a2 passing through the center in the alignment direction a1, and the notch 1222 is located at the position of the anti-overflow cofferdam 1221 that is farthest from the centerline a2. In the figure, the anti-overflow cofferdam 1221 is rectangular in shape, and the notch 1222 is located at the center of the side of the anti-overflow cofferdam 1221 that is farthest from the centerline a2. For example, when the anti-overflow cofferdam 1221 is circular in shape, the notch 1222 is located at the position of the anti-overflow cofferdam 1221 that is farthest from the centerline a2. In this example, the fluidity of the liquid crystal is related to the orientation direction a1 of the orientation layer. The fluidity of the liquid crystal along the orientation direction a1 is better than the fluidity of the liquid crystal perpendicular to the orientation direction a1. Setting the gap 1222 at the position farthest from the center line a2 on the orientation direction a1 can improve the fluidity of the liquid crystal perpendicular to the orientation direction a1.

[0115] The embodiment of the present disclosure does not limit the position of the alignment layer. The alignment layer may be located on the side of the spacer 123 facing the array substrate 110 , or between the spacer 123 and the second base substrate 121 .

[0116] Figure 10 is a schematic diagram of another anti-overflow structure for an opposing substrate provided in an embodiment of the present disclosure. As shown in Figure 10 , the anti-overflow cofferdam 1221 includes a first anti-overflow cofferdam 1223 and a second anti-overflow cofferdam 1224. The first anti-overflow cofferdam 1223 has a first opening 1223a, and the second anti-overflow cofferdam 1224 has a second opening 1224a. The first opening 1223a and the second opening 1224a are positioned opposite each other. The first anti-overflow cofferdam 1223 and the second anti-overflow cofferdam 1224 have an intersecting region. In the intersecting region, the first anti-overflow cofferdam 1223 and the second anti-overflow cofferdam 1224 are spaced apart to form a channel a3. When the liquid crystal display panel 100 is relatively small, for example, when the inner spacing of the frame sealant 140 is less than 9 mm, referring to Figure 1, the diffusion range of the liquid crystal droplets is greater than the inner spacing of the frame sealant 140. In this case, there is a risk of overflow even if the gap 1222 on the anti-overflow cofferdam 1221 is set at the position farthest from the center. By providing the first anti-overflow cofferdam 1223 and the second anti-overflow cofferdam 1224, the two have an interlaced area and are spaced apart to form a channel a3, thereby improving the fluidity of the liquid crystal through the channel a3 and avoiding the overflow of the liquid crystal through the interlaced area, thereby avoiding the diffusion problem of the liquid crystal as much as possible.

[0117] In some examples, as shown in FIG10 , the display area AA has a center line a2 passing through the center in the orientation direction a1, and the staggered area is provided at the position of the anti-overflow dam 1221 that is farthest from the center line a2. The shape of the anti-overflow dam 1221 in the figure is roughly rectangular, and the staggered area is located at the center of the side of the anti-overflow dam 1221 that is farthest from the center line a2. For example, when the shape of the anti-overflow dam 1221 is circular, the staggered area is located at the position of the anti-overflow dam 1221 that is farthest from the center line a2. In this example, the fluidity of the liquid crystal is related to the orientation direction a1 of the orientation layer. The fluidity of the liquid crystal along the orientation direction a1 is better than the fluidity of the liquid crystal perpendicular to the orientation direction a1. Providing a staggered area at the position farthest from the center line a2 on the orientation direction a1 can improve the fluidity of the liquid crystal perpendicular to the orientation direction a1.

[0118] In some examples, as shown in FIG10 , the first anti-overflow weir 1223 includes a first sub-portion 1223b and a second sub-portion 1223c disposed opposite each other, and a first connecting portion 1223d connecting the first sub-portion 1223b and the second sub-portion 1223c. The second anti-overflow weir 1224 includes a third sub-portion 1224b and a fourth sub-portion 1224c disposed opposite each other, and a second connecting portion 1224d connecting the third sub-portion 1224b and the fourth sub-portion 1224c. The first sub-portion 1223b and the third sub-portion 1224b have an intersecting region and are spaced apart to form a channel a3. The second sub-portion 1223c and the fourth sub-portion 1224c have an intersecting region and are spaced apart to form a channel a3.

[0119] Figure 11A is a schematic diagram of another anti-overflow weir provided in one embodiment of the present disclosure; Figure 11B is a partial schematic diagram of the anti-overflow weir shown in Figure 11A. As shown in Figures 11A and 11B, the anti-overflow weir 1221 includes multiple first anti-overflow sections 1225 and multiple second anti-overflow sections 1226. In a direction perpendicular to the second base substrate 121, the first anti-overflow sections 1225 are larger than the second anti-overflow sections 1226. In the extension direction a4 of the anti-overflow weir 1221, the first anti-overflow sections 1225 and the second anti-overflow sections 1226 are alternately arranged. This alternating arrangement of the first anti-overflow sections 1225 and the second anti-overflow sections 1226 prevents liquid crystal from overflowing and improves its fluidity. The present embodiment does not impose any restrictions on the number, height, or length of the first and second anti-overflow sections 1225, 1226 along the extension direction a4 of the anti-overflow weir 1221; these sections can be designed to match the size of the liquid crystal display panel 100 and the alignment direction a1 of the alignment layer.

[0120] For example, the height of the first anti-overflow portion 1225 may be the same as the height of the main spacer 1231 , and the height of the second anti-overflow portion 1226 may be the same as the height of the auxiliary spacer 1232 .

[0121] In some examples, as shown in FIG. 12 , in a direction Z perpendicular to the second base substrate 121 , a difference D5 between the height of the first anti-overflow portion 1225 and the height of the second anti-overflow portion 1226 ranges from 0.5 μm to 0.65 μm.

[0122] In some examples, along the extension direction a4 of the anti-overflow dam 1221, the length of the first anti-overflow portion 1225 is greater than 15 μm, and the length of the second anti-overflow portion 1226 is greater than 15 μm, so that the first anti-overflow portion 1225 and the second anti-overflow portion 1226 that are staggered with each other can have more obvious size characteristics, can better avoid the overflow of liquid crystal, and can also better improve the fluidity of liquid crystal.

[0123] Figure 12 is a schematic diagram of another anti-overflow weir provided in one embodiment of the present disclosure. As shown in Figure 12, one set of opposing sides of the anti-overflow weir 1221 is a first anti-overflow portion 1225, and the other set of opposing sides is a second anti-overflow portion 1226. Two adjacent sides of the anti-overflow weir 1221 are the first anti-overflow portion 1225 and the second anti-overflow portion 1226, respectively. The multiple sides of the anti-overflow weir 1221 can be set to different heights based on the size of the LCD panel 100, the position of the liquid crystal droplets, and the alignment direction a1 of the alignment layer, thereby preventing liquid crystal overflow and improving liquid crystal fluidity.

[0124] For example, as shown in FIG12 , the edge of the anti-overflow dam 1221 perpendicular to the alignment direction a1 is a first anti-overflow portion 1225, and the edge of the anti-overflow dam 1221 parallel to the alignment direction a1 is a second anti-overflow portion 1226. This ensures liquid crystal fluidity while preventing liquid crystal overflow. For example, the edge of the anti-overflow dam 1221 perpendicular to the alignment direction a1 can be the same height as the main spacer 1231, and the edge of the anti-overflow dam 1221 parallel to the alignment direction a1 can be the same height as the auxiliary spacer 1232.

[0125] In some examples, as shown in FIG2 , the counter substrate 120 further includes a black matrix layer 124, a color filter layer 125, and a planarization layer 126. The black matrix layer 124 is disposed on the side of the second base substrate 121 facing the array substrate 110, the color filter layer 125 is disposed on the side of the second base substrate 121 facing the array substrate 110, and the planarization layer 126 is disposed on the sides of the black matrix layer 124 and the color filter layer 125 facing the array substrate 110. Spacers 123 and anti-overflow dams 1221 are disposed on the side of the planarization layer 126 closer to the array substrate 110.

[0126] In some examples, as shown in FIG2 , the counter substrate 120 may further include a peripheral spacer 1233 located in the peripheral area BB and surrounding the display area AA. The peripheral spacer 1233 is a columnar structure and is disposed on the side of the planarization layer 126 facing the array substrate 110. For example, the peripheral spacer 1233 may be configured to be formed from the same material and patterned as the spacer 123 using the same process. Thus, the formation of the peripheral spacer 1233 does not require additional process steps or production costs. For example, in a direction perpendicular to the second base substrate 121, the height of the peripheral spacer 1233 may be the same as that of the main spacer 1231.

[0127] In some examples, as shown in FIG2 , the color filter layer 125 is located on the side of the anti-overflow structure 122 that is close to the display area AA. For example, the color filter layer 125 is also located on the side of the peripheral spacer 1233 that is close to the display area AA. This prevents the thickness of the peripheral area BB from increasing due to the overlay of the color filter layer 125, thereby preventing problems such as yellowing of the display.

[0128] In some examples, the material of the planarization layer 126 may be photoresist. Of course, the present disclosure does not limit the material of the planarization layer 126. For example, the planarization layer 126 may also be other functional layers on the opposing substrate 120.

[0129] In some examples, as shown in FIG2 , the counter substrate 120 may be formed by sequentially forming a black matrix layer 124, a color filter layer 125, and a planarization layer 126 on a second base substrate 121, and then forming spacers 123 and anti-overflow dams 1221 using the same material and undergoing the same patterning process. For example, a conductive layer may be formed on the side of the second base substrate 121 away from the array substrate 110 to discharge static electricity on the side of the counter substrate 120 away from the array substrate 110.

[0130] Figure 13 is a schematic diagram of an anti-overflow structure of another opposing substrate provided in an embodiment of the present disclosure. As shown in Figure 13, the opposing substrate 120 also includes a planarization layer 126, and the planarization layer 126 is arranged on the side of the second base substrate 121 facing the array substrate 110. The anti-overflow structure 122 includes an anti-overflow groove 1227 formed in the planarization layer 126 and recessed toward the second base substrate 121. The anti-overflow groove 1227 can carry a certain volume of liquid crystal, effectively prevent the liquid crystal from diffusing into the sealant 140, and prevent the liquid crystal from impacting the sealant 140, thereby improving the puncture problem and improving the yield rate of the product. In addition, the design of the anti-overflow groove 1227 can make the liquid crystal droplets have good fluidity, so that the liquid crystal is better filled in the display area AA. For example, the planarization layer 126 can be the outermost layer of the opposing substrate 120 facing the array substrate 110.

[0131] In some examples, as shown in FIG. 13 , the anti-overflow groove 1227 may be a closed structure surrounding the display area AA, thereby more effectively preventing the liquid crystal from diffusing into the sealant 140 and better preventing the liquid crystal from impacting the sealant 140 .

[0132] In some examples, as shown in FIG13 , the depth D6 of the anti-overflow groove 1227 ranges from 0.5 μm to 1.5 μm, and the width D7 of the anti-overflow groove 1227 ranges from 200 μm to 400 μm. By properly setting the depth D6 and width D7 of the anti-overflow groove 1227, the anti-overflow groove 1227 can have a larger carrying volume.

[0133] In some examples, as shown in FIG13 , the depth D6 of the anti-overflow groove 1227 can be 40% to 60% of the thickness of the planarization layer 126. Depending on the actual product and the material and thickness of the planarization layer 126, the depth D6 of the anti-overflow groove 1227 can be properly designed and verified to provide a larger carrying volume for the anti-overflow groove 1227.

[0134] In some examples, as shown in FIG13 , the counter substrate 120 further includes a black matrix layer 124 and a color filter layer 125, and the black matrix layer 124 and the color filter layer 125 are located between the second base substrate 121 and the planarization layer 126. For example, the counter substrate 120 may further include peripheral spacers, as shown in FIG2 , which will not be described in detail here.

[0135] In some examples, as shown in FIG13 , the color filter layer 125 is located on a side of the anti-overflow structure 122 close to the display area AA, thereby allowing the anti-overflow groove 1227 to have a larger carrying volume.

[0136] In some examples, as shown in FIG13 , the material of the planarization layer 126 can be photoresist. Of course, the present disclosure does not limit the material of the planarization layer 126. For example, the planarization layer 126 can also be another functional layer on the opposing substrate 120, which also has a planarization function.

[0137] The embodiment of the present disclosure does not limit the material of the anti-overflow structure 122. For example, the material of the anti-overflow structure 122 can be the same as the material of the color filter layer 125, the same as the material of the planarization layer 126, or the same as the material of the conductive layer on the opposing substrate 120.

[0138] It is worth noting that although the above embodiments respectively show the cases where the anti-overflow structure is an anti-overflow cofferdam and an anti-overflow groove, the embodiments of the present disclosure include but are not limited to this, and the anti-overflow structure may include an anti-overflow cofferdam and an anti-overflow groove at the same time. Figure 14 is a schematic diagram of an anti-overflow structure of another opposing substrate provided by an embodiment of the present disclosure. As shown in Figure 14, the anti-overflow structure of the opposing substrate of the liquid crystal display panel includes an anti-overflow cofferdam and an anti-overflow groove. For example, the anti-overflow groove is arranged on the side of the anti-overflow cofferdam close to the display area. Thus, the liquid crystal display panel can have the beneficial technical effects of the anti-overflow groove and the beneficial technical effects of the anti-overflow cofferdam at the same time, which will not be repeated here. The anti-overflow cofferdam of the liquid crystal display panel can be any of the anti-overflow cofferdams described above, and the anti-overflow groove of the liquid crystal display panel can be any of the anti-overflow grooves shown above.

[0139] Figure 15 is a schematic diagram of static electricity on the opposing substrate of a liquid crystal display panel. As shown in Figure 15, if there is no metal on the side of the opposing substrate 12 facing the array substrate 11, static electricity on the opposing substrate 12 cannot be dispersed and is easily accumulated, as indicated by the arrows circled in the figure. Especially in miniaturized liquid crystal display panels with smaller display areas, the liquid crystal between the opposing substrate 12 and the array substrate 11 is more susceptible to static electricity, causing abnormal initial alignment of the liquid crystal, resulting in uneven display, and also reducing the contrast and transmittance of the liquid crystal display panel.

[0140] Figure 16 is a schematic cross-sectional view of a liquid crystal display panel provided in accordance with an embodiment of the present disclosure. As shown in Figure 16 , the opposing substrate 120 of the liquid crystal display panel 100 further includes an electrostatic release layer 127 disposed on the side of the second base substrate 121 facing the array substrate 110. A sealant 140 is at least partially connected to the electrostatic release layer 127 and is configured to be conductive, thereby connecting the electrostatic release layer 127 to the array substrate 110 through the sealant 140.

[0141] In the liquid crystal display panel 100 of the disclosed embodiment, liquid crystal droplets are deposited onto the counter substrate 120. The counter substrate 120 is provided with an anti-overflow structure 122 to prevent liquid crystal from overflowing and impacting the frame sealant 140. An electrostatic release layer 127 is formed on the counter substrate 120 and connected to the array substrate 110 via the conductive frame sealant 140. This allows static electricity on the counter substrate 120 to be released via the electrostatic release layer 127, preventing static electricity on the counter substrate 120 from affecting the liquid crystal deposited thereon and causing abnormal liquid crystal orientation, thereby improving the display performance of the liquid crystal display panel 100.

[0142] It should be noted that the embodiment of the present disclosure does not limit the form of the anti-overflow structure 122, which can be any of the anti-overflow structures 122 described above. The embodiment of the present disclosure does not limit the structure or film layer setting of the opposing substrate 120, which can be any of the opposing substrates 120 described above.

[0143] In some examples, as shown in FIG16 , the electrostatic release layer 127 can be a conductive layer disposed entirely on the counter substrate 120. For example, in a plane parallel to the second base substrate 121, the size of the electrostatic release layer 127 can be the same as that of the second base substrate 121. A large electrostatic release layer 127 can diffuse static electricity on the counter substrate 120, preventing it from accumulating in large quantities and causing display defects. Furthermore, a full layer of electrostatic release layer 127 eliminates the need for masking, further reducing costs. Of course, the disclosed embodiments do not limit the shape of the electrostatic release layer 127; it can be disposed entirely as a layer, or it can be provided with cutouts at locations corresponding to pixel structures, and the design can be tailored to the performance requirements of the actual product.

[0144] For example, the material of the electrostatic release layer 127 may be a transparent conductive material, for example, the material of the electrostatic release layer 127 may be indium tin oxide.

[0145] For example, the thickness of the electrostatic release layer 127 ranges from

[0146] For example, the frame sealant 140 may contain conductive gold balls or silver balls to provide electrical conductivity.

[0147] In some examples, as shown in FIG16 , the array substrate 110 of the liquid crystal display panel 100 further includes a common electrode layer 116, which is disposed on a side of the first base substrate 111 facing the counter substrate 120. The common electrode layer 116 includes a common electrode 1161 located in the display area AA and a conductive structure 1162 located in the peripheral area BB. The sealant 140 is at least partially connected to the conductive structure 1162. Thus, the electrostatic release layer 127 can be connected to the conductive structure 1162 of the common electrode layer 116 via the conductive sealant 140 to discharge static electricity from the counter substrate 120.

[0148] In this embodiment, the pixel structure on the array substrate 110 includes a common electrode 1161, a pixel electrode 117, and a driving transistor TFT. For example, the driving transistor TFT may be connected to the pixel electrode 117 to achieve deflection of liquid crystal.

[0149] FIG17 is a schematic diagram of a partial structure of the liquid crystal display panel of FIG16. As shown in FIG16 and FIG17, the array substrate 110 of the liquid crystal display panel 100 further includes a first common electrode line 118 surrounding the display area AA and a second common electrode line 119 surrounding the first common electrode line 118. The first common electrode line 118 is connected to the second common electrode line 119. The first common electrode line 119 is connected to the common electrode 1161 of the display area AA, and the second common electrode line 119 is connected to the signal input port 190 of the liquid crystal display panel 100. The array substrate 110 further includes a via hole, and the second common electrode line 119 is connected to the conductive structure 1162 through the via hole. In this example, the electrostatic release layer 127 is sequentially connected to the second common electrode line 119 via the conductive sealant 140 and the conductive structure 1162 of the common electrode layer 116. The second common electrode line 119, the first common electrode line 118, and the common electrode 1161 of the display area AA are connected. As a result, the electrostatic release layer 127 and the common electrode 1161 of the display area AA have the same voltage signal, and there is no vertical electric field between the electrostatic release layer 127 and the common electrode 1161 of the display area AA. This further prevents the potential difference between the electrostatic release layer 127 and the common electrode 1161 from affecting the deflection of the liquid crystal. Moreover, connecting the electrostatic release layer 127 to the second common electrode line 119 does not require additional circuit design. The liquid crystal display panel shown in Figure 17 is described in detail below.

[0150] Figure 18 is a partial enlarged view of Figure 17 at positions A and B; Figure 19 is a partial enlarged view of Figure 17 at positions C and D; Figure 20 is a partial enlarged view of Figure 17; and Figure 21 is a cross-sectional schematic diagram of the conductive layers connected in Figure 17. As shown in Figures 17 to 21, the first common electrode line 118 and the second common electrode line 119 are connected at positions A, B, C, and D.

[0151] In some examples, as shown in Figures 16 and 21, the array substrate 110 of the liquid crystal display panel 100 includes a first conductive layer 112 disposed on the side of the first base substrate 111 facing the opposing substrate 120, and a second conductive layer 114 disposed on the side of the first conductive layer 112 facing the opposing substrate 120. The first conductive layer 112 and the second conductive layer 114 are located between the first base substrate 111 and the common electrode layer 116. A first insulating layer 113 is disposed between the first conductive layer 112 and the second conductive layer 114, and a second insulating layer 115 is disposed between the second conductive layer 114 and the common electrode layer 116. For example, the first conductive layer 112 is disposed on the same layer as the gate layer in the pixel structure of the display area AA, and the second conductive layer 114 is disposed on the same layer as the source and drain conductive layers in the pixel structure. The first insulating layer 113 can be a gate insulating layer, and the second insulating layer 115 can be a passivation layer.

[0152] In some examples, as shown in Figures 17, 18, 20, and 21, at positions A and B, the second common electrode line 119 is connected to the first common electrode line 118 via a lead line L1. The second common electrode line 119 and the lead line L1 are located in the first conductive layer 112. The upper side 1183 and the lower side 1184 of the first common electrode line 118 are located in the first conductive layer 112, and the left side 1181 and the right side 1182 of the first common electrode line 118 are located in the second conductive layer 114. The upper side 1183 and the lower side 1184 of the first common electrode line 118 are connected to the common electrode layer 116 via a via H1, and the left side 1181 and the right side 1182 of the first common electrode line 118 are connected to the common electrode layer 116 via a via H2. As a result, the first common electrode line 118 is connected to the common electrode 1161 of the display area AA. The lead L1 of the second common electrode line 119 is connected to the common electrode layer 116 through the via H1. Thus, the first common electrode line 118 and the second common electrode line 119 are connected. The first common electrode line 118, the second common electrode line 119, and the common electrode 1161 of the display area AA have the same voltage signal. Of course, the present embodiment does not limit the conductive layer where the first common electrode line 118 and the second common electrode line 119 are located.

[0153] It should be noted that Figure 21 only schematically shows that the first conductive layer 112 and the common electrode layer 116 are connected through the via H1, and the second conductive layer 114 and the common electrode layer 116 are connected through the via H2. It does not limit the position and number of the via H1 and the via H2, nor does it limit the routing on the first conductive layer 112 and the second conductive layer 114. The required number of vias are set at the corresponding positions according to different routings, connection positions and the size of the positions.

[0154] In some examples, as shown in Figures 17, 19, and 21, the first common electrode line 118 further includes a connecting line 1180 extending from the display area AA, and the connecting line 1180 can be located in the first conductive layer 112. At positions C and D, because there are other signal lines between the first common electrode line 118 and the second common electrode line 119, to avoid other signal lines, the second common electrode line 119 is connected to the first common electrode line 118 through the common electrode layer 116. The second common electrode line 119 located in the first conductive layer 112 is connected to the common electrode layer 116 through the via H1, and the first common electrode line 118 located in the first conductive layer 112 is connected to the common electrode layer 116 through the via H1. Thus, the first common electrode line 118 and the second common electrode line 119 are connected.

[0155] In some examples, as shown in FIG. 17 , the second common electrode line 119 is connected to the signal input port 190 of the liquid crystal display panel 100 in the binding region CC, thereby providing a common voltage signal to the common electrode 1161 and the electrostatic release layer 127 through the second common electrode 1161 .

[0156] Figure 22 is a partial enlarged view at position E in Figure 17 , and Figure 23 is a schematic cross-sectional view of Figure 22 . As shown in Figures 17 , 22 , and 23 , the second common electrode line 119 located in the first conductive layer 112 is connected to the conductive structure 1162 of the common electrode layer 116 via the via H1. As a result, the electrostatic release layer 127 is connected to the second common electrode line 119 , and further, the electrostatic release layer 127 and the common electrode 1161 in the display area AA have the same voltage signal.

[0157] In some examples, as shown in FIG17 , within the region enclosed by the outermost boundary of the frame sealant 140, the shape of the conductive structure 1162 can be the same as the shape of the second common electrode line 119, thereby enabling the second common electrode line 119 to be better connected to the conductive structure 1162 and the frame sealant 140. Of course, the embodiments of the present disclosure do not limit the shape of the conductive structure 1162, as long as the conductive structure 1162 can achieve connection between the second common electrode line 119 and the frame sealant 140.

[0158] In some examples, as shown in Figures 17, 18, and 22, the second common electrode lines 119 may be metal grid lines. Thus, the area where the orthographic projection of the sealant 140 on the first base substrate 111 overlaps with the orthographic projection of the metal grid lines on the first base substrate 111 has better transmittance, facilitating the curing of the sealant 140. Of course, the present disclosure does not limit the form of the second common electrode lines 119.

[0159] In the embodiment of the present disclosure, the first common electrode line 118 and the second common electrode line 119 are connected. However, the first common electrode line 118 and the second common electrode line 119 may also be disconnected. The first common electrode line 118 may be independently connected to the signal port of the liquid crystal display panel 100 to provide a common voltage signal to the first common electrode line 118. The common voltage signal may be the same as the voltage signal of the second common electrode line 119, thereby also achieving the same voltage signal for the electrostatic release layer 127 and the common electrode 1161. The embodiment of the present disclosure does not limit the connection form and connection position of the first common electrode line 118 and the second common electrode line 119.

[0160] Figure 24 is a schematic diagram of the electric field in a liquid crystal display panel. As shown in Figure 24, the conductive layer 13 on the inner side of the counter substrate 120 forms a vertical electric field ② and other coupled electric fields with the pixel electrodes 14 on the array substrate 11. These fields interfere with the electric field ① between the common electrode 15 and the pixel electrodes 14, which drives the liquid crystal deflection, ultimately causing a decrease in pixel transmittance.

[0161] FIG25 is a schematic diagram of a partial structure of another liquid crystal display panel of FIG16 ; FIG26 is a schematic diagram of an enlarged portion of FIG25 . As shown in FIG16 , FIG25 and FIG26 , the array substrate 110 further includes a first common electrode line 118 surrounding the display area AA and a second common electrode line 119 surrounding the first common electrode line 118 . The first common electrode line 118 is connected to the second common electrode line 119 . The first common electrode line 118 is connected to the common electrode 1161 of the display area AA. The second common electrode line 119 is connected to the first signal input port 1901 of the liquid crystal display panel 100 to be provided with a first voltage signal. The conductive structure 1162 is connected to the second signal input port 1902 of the liquid crystal display panel 100 via a lead line L2 to be provided with a second voltage signal.

[0162] In this example, the electrostatic release layer 127 is sequentially connected to the second signal input port 1902 via the conductive sealant 140, the conductive structure 1162 of the common electrode layer 116, and the lead L2 to be provided with a second voltage signal. The common electrode 1161 of the display area AA is sequentially connected to the first signal input port 1901 via the first common electrode line 118 and the second common electrode line 119 to be provided with a first voltage signal. Thus, voltage signals can be provided to the electrostatic release layer 127 and the common electrode 1161 respectively to independently control the electrostatic release layer 127 and the common electrode 1161. For example, different or the same voltage signals can be set through software simulation to improve performance such as transmittance or contrast.

[0163] For example, the difference between the first voltage signal and the second voltage signal ranges from 0 to 3 V. Of course, the embodiments of the present disclosure do not limit the first voltage signal, the second voltage signal, and the difference between them. Different voltage signals can be matched based on factors such as the size, structural design, cost, and user needs of the actual product to meet the requirements.

[0164] FIG27 is a partial enlarged view of FIG25 at positions F and G. As shown in FIG25 and FIG27, the first common electrode line 118 and the second common electrode line 119 are connected at positions F, G, H, and I. The connection method at these four positions is the same as that in the embodiment of FIG17. The partial enlarged views of positions H and I are the same as those in FIG19 and will not be repeated. In addition, the connection method between the first common electrode line 118 and the common electrode 1161 of the display area AA is also the same as that in the embodiment of FIG17 and will not be repeated. Of course, the embodiments of the present disclosure are not limited to the above-mentioned connection method and can be adaptively adjusted according to actual wiring conditions.

[0165] FIG28 is a partial enlarged view of FIG25 at position J. As shown in FIG25 and FIG28 , unlike the partial enlarged view at position E in FIG22 , the second common electrode line 119 located in the first conductive layer 112 of this embodiment is not connected to the conductive structure 1162 of the common electrode layer 116 through the via H1, and thus the second common electrode line 119 is not connected to the electrostatic release layer 127.

[0166] In some examples, as shown in Figures 25, 27, and 28, the second common electrode lines 119 may be metal grid lines. Thus, the area where the orthographic projection of the sealant 140 on the first base substrate 111 overlaps with the orthographic projection of the second common electrode lines 119 on the first base substrate 111 has better transmittance, facilitating the curing of the sealant 140. Of course, the present disclosure does not limit the form of the second common electrode lines 119.

[0167] Figure 29 is a partial enlarged view of Figure 25 at position K; Figure 30 is a schematic cross-sectional view of Figure 28. As shown in Figures 25, 26, 29, and 30, the conductive structure 1162 located in the common electrode layer 116 is connected to the first conductive layer 112 via via H1. The first conductive layer 112 is provided with a lead L2 and a second signal input port 1902 of the liquid crystal display panel 100. The electrostatic release layer 127 is connected to the second signal input port 1902 in sequence via the conductive sealant 140, the conductive structure 1162, and the lead L2 of the first conductive layer 112 to provide a second voltage signal, thereby enabling independent control of the electrostatic release layer 127. Of course, the embodiments of the present disclosure do not limit the conductive layer where the lead L2 is located, nor do they limit the shape of the conductive structure 1162 or the number of vias H2.

[0168] In some examples, as shown in Figures 25 and 26, on a plane parallel to the second base substrate 121, the conductive structure 1162 is located on the side of the second common electrode line 119 away from the display area AA, and on the side of the second common electrode line 119 close to the signal input port of the liquid crystal display panel 100, thereby making it easier to arrange the conductive structure 1162 and the lead L2. Of course, the embodiments of the present disclosure do not limit the location and extension trend of the conductive structure 1162 and the lead L2, and can be reasonably arranged and designed according to the actual product. For example, as shown in Figures 25 and 26, the lead L2 can extend roughly along the second common electrode line 119 to the second signal input port 1902.

[0169] 25 and 26 , the second signal input port 1902 is closer to the end of the binding region CC than the first signal input port 1901. Of course, the embodiments of the present disclosure do not limit the positions of the first signal input port 1901 and the second signal input port 1902, and they can be reasonably arranged and designed according to the actual product.

[0170] Figure 31 is a partial cross-sectional schematic diagram of another liquid crystal display panel provided in one embodiment of the present disclosure; Figure 32 is a partial top-down schematic diagram of a pixel structure in Figure 31 . As shown in Figures 31 and 32 , the opposing substrate 120 of this liquid crystal display panel is provided with a full-layer electrostatic release layer 127. This electrostatic release layer 127 can have the same voltage signal as the common electrode 1161 on the array substrate 110, or it can have a different voltage signal from the common electrode 1161 on the array substrate 110. In this embodiment, the full-layer electrostatic release layer 127 can disperse and conduct charges to the greatest extent possible, thereby preventing them from affecting the liquid crystal.

[0171] In some examples, as shown in FIG. 31 , the array substrate 110 further includes a plurality of pixel electrodes 117 , the plurality of pixel electrodes 117 corresponding to the plurality of common electrodes 1161 , and the pixel electrodes 117 of the pixel structure may be block-shaped pixel electrodes.

[0172] A simulation analysis of the display performance of a liquid crystal display panel 0 equipped with a full electrostatic release layer and a liquid crystal display panel without such a layer was conducted. For the liquid crystal display panel without the electrostatic release layer, when simulating the L255 transmittance, the pixel electrode voltage V3 was 98% of the operating voltage, or 4.1V. When simulating the L0 transmittance, the pixel electrode voltage V3 was 0% of the operating voltage, or 0V. When simulating the L127 grayscale, the pixel electrode voltage V3 was 2.36V. In this embodiment, the electrostatic release layer and the common electrode have the same voltage signal.

[0173] According to simulation verification, at the L0 grayscale, the transmittance of the LCD panel is reduced by 0.56% after the electrostatic release layer is added, compared with the case without the electrostatic release layer. As a result, the LCD panel is darker in the normally black mode after the static release layer is added. At the L127 grayscale, the voltage of the pixel electrode is reduced from 2.36V to 2.12V, thereby reducing power consumption. At the L255 grayscale, the transmittance of the LCD panel has a relatively large loss, reducing by 40.4%. Therefore, setting up a whole layer of electrostatic release layer can be used in products that do not require high transmittance but have high requirements on appearance and energy consumption.

[0174] Figure 33 is a partial cross-sectional schematic diagram of another liquid crystal display panel 100 provided in one embodiment of the present disclosure; Figure 34 is a partial top view schematic diagram corresponding to a pixel structure in Figure 33 . As shown in Figures 33 and 34 , multiple pixel structures are arranged along a first direction X and a second direction Y, with the second direction Y intersecting the first direction X. In a pixel structure, the common electrode 1161 includes multiple first slits 1161a extending along the first direction X and arranged along the second direction Y. The electrostatic discharge layer 127 includes multiple electrostatic discharge portions 1271 corresponding to the multiple pixel structures, each of which includes multiple second slits 1271a extending along the first direction X and arranged along the second direction Y. Providing the second slits 1271a in the electrostatic discharge layer 127 at locations corresponding to the pixel structures effectively disperses and guides static electricity from the counter substrate 120 and improves the transmittance of the liquid crystal display panel 100. In this example, the electrostatic release layer 127 may have the same voltage signal as the common electrode 1161 on the array substrate 110 , or may have a different voltage signal from the common electrode 1161 on the array substrate 110 .

[0175] In some examples, as shown in Figures 33 and 34 , in a pixel structure, multiple second slits 1271a are arranged at equal intervals. In the second direction Y, the ratio of the dimension D8 between two adjacent second slits 1271a to the dimension D9 of each second slit 1271a ranges from 1.0 to 1.5. Consequently, the dimension D9 of each second slit 1271a in the second direction Y can be appropriately reduced, allowing the ratio of the conductive area of ​​the electrostatic discharge portion 1271 to the total area enclosed by the electrostatic discharge portion 1271 to be greater than 50%. This improves transmittance and allows for better dispersion and removal of static electricity from the counter substrate 120. It should be noted that the total area enclosed by the electrostatic discharge portion 1271 refers to the sum of the conductive area of ​​the electrostatic discharge portion 1271 and the area of ​​all second slits 1271a in the electrostatic discharge portion 1271, i.e., the total area enclosed by the outermost boundary of the electrostatic discharge portion 1271.

[0176] For example, by setting the size between the second slits 1271a and the size of the second slits 1271a, the ratio of the conductive area of ​​the electrostatic release part 1271 to the total area surrounded by the electrostatic release part 1271 can be between 50% and 65%, so that the electrostatic release layer 127 can better disperse and conduct static electricity on the opposing substrate 120 on the basis of improving transmittance.

[0177] In some examples, as shown in FIG34 , the dimension D8 between the two second slits 1271 a in the second direction Y may be in the range of 2 μm to 3 μm. For example, the dimension D10 at the edge of the electrostatic discharge portion 1271 in the second direction Y is half the dimension D8 between the two second slits 1271 a.

[0178] In some examples, as shown in FIG. 34 , the slits on the electrostatic discharge portion 1271 are arranged symmetrically about the center line of the electrostatic discharge portion 1271 along the first direction X and aligned with the center line of the electrostatic discharge portion 1271 along the second direction Y.

[0179] In some examples, as shown in FIG34 , in the first direction X, the second slit 1271 a does not penetrate the electrostatic discharge portion 1271 , and a minimum distance D11 between the end of the second slit 1271 a and the boundary of the electrostatic discharge portion 1271 is greater than or equal to 1 μm. For example, the distance D11 may be in the range of 1 μm to 1.5 μm.

[0180] In some examples, as shown in FIG. 33 , the array substrate 110 further includes a plurality of pixel electrodes 117 , the plurality of pixel electrodes 117 corresponding to the plurality of common electrodes 1161 , and the pixel electrodes 117 of the pixel structure may be block-shaped pixel electrodes.

[0181] A simulation analysis of the display performance of a liquid crystal display panel equipped with the electrostatic release layer shown in Figure 33 and a liquid crystal display panel without such a layer was conducted. The voltage magnitude of the pixel electrode of the liquid crystal display panel without the electrostatic release layer is the same as described above and will not be repeated here. In this embodiment, the electrostatic release layer and the common electrode have the same voltage signal.

[0182] According to simulation verification, at the L127 grayscale, compared with not providing an electrostatic release layer, the voltage of the pixel electrode of the liquid crystal display panel is reduced from 2.36V to 2.16V after the electrostatic release layer is added, thereby reducing power consumption. At the L0 grayscale, the transmittance of the liquid crystal display panel is reduced by 3.18%. Therefore, after adding the static release layer, the liquid crystal display panel is darker in the normally black mode. At the L255 grayscale, the transmittance of the liquid crystal display panel is also lost, decreasing by 34.54%. Compared with providing a whole layer of electrostatic release layer, this embodiment is darker in the normally black mode, and the reduction in transmittance is also improved at the L255 grayscale.

[0183] Figure 35 is a partial cross-sectional schematic diagram of another liquid crystal display panel provided in one embodiment of the present disclosure; Figure 36 is a partial top view schematic diagram corresponding to a pixel structure in Figure 35 . As shown in Figures 35 and 36 , in a pixel structure, a plurality of first slits 1161a are arranged in a one-to-one correspondence with a plurality of second slits 1271a. In the second direction Y, the corresponding first slits 1161a and second slits 1271a have the same dimensions. By arranging the dimensions of the first slits 1161a and second slits 1271a in the second direction Y to be the same, the ratio of the conductive area of ​​the electrostatic discharge portion 1271 to the total area enclosed by the electrostatic discharge portion 1271 can be reduced to less than 50%. Appropriately reducing the ratio of the conductive area of ​​the electrostatic discharge portion 1271 to the total panel area enclosed by the electrostatic discharge portion 1271 can improve the pixel's light efficiency and transmittance. In this example, the electrostatic release layer 127 may have the same voltage signal as the common electrode 1161 on the array substrate 110 , or may have a different voltage signal from the common electrode 1161 on the array substrate 110 .

[0184] In some examples, as shown in FIG. 35 and FIG. 36 , the array substrate 110 further includes a plurality of pixel electrodes 117 , the plurality of pixel electrodes 117 corresponding to the plurality of common electrodes 1161 , and the pixel electrodes 117 of the pixel structure may be block-shaped pixel electrodes.

[0185] A simulation analysis of the display performance of a liquid crystal display panel equipped with the electrostatic release layer shown in Figure 35 and a liquid crystal display panel without such a layer was conducted. The voltage levels of the pixel electrodes of the liquid crystal display panel without the electrostatic release layer are the same as those described above and will not be repeated here. In this embodiment, the electrostatic release layer and the common electrode have the same voltage signal.

[0186] According to simulation verification, at the L127 grayscale, compared with the case where the electrostatic release layer is not provided, the voltage of the pixel electrode of the LCD panel is reduced from 2.36V to 2.17V after the electrostatic release layer is added, thereby reducing power consumption. At the L0 grayscale, the transmittance of the LCD panel is reduced by 0.58%. Therefore, after the static release layer is added, the LCD panel is darker in the normally black mode. At the L255 grayscale, the transmittance loss of the LCD panel is very small, reduced by 8.44%. Compared with the corresponding solutions of Figures 31 and 33 in the previous text, the transmittance has been greatly improved. Therefore, this embodiment can be used not only for products with high requirements on appearance and energy consumption, but also for products with higher requirements on transmittance.

[0187] Figure 37 shows the light effect diagrams of two solutions of the present disclosure at grayscale L255. As shown in Figure 37, (a) corresponds to the light effect diagram of Figure 33, and (b) corresponds to the light effect diagram of Figure 35. (b) has a higher transmittance than (a) at grayscale L255.

[0188] In the liquid crystal display panel shown in Figure 31, the electrostatic release layer 127 can be connected to a separate signal input port through a lead, and the common electrode 1161 is connected to another signal input port through a first common electrode line or a second common electrode line, so that the voltage signals of the electrostatic release layer 127 and the common electrode 1161 can be controlled separately.

[0189] A simulation analysis was conducted on the display performance of a liquid crystal display panel equipped with the electrostatic release layer shown in Figure 31 and a liquid crystal display panel without such a layer. The voltage levels of the pixel electrodes of the liquid crystal display panel without the electrostatic release layer are the same as described above and will not be repeated here. In this example, the voltage of the electrostatic release layer is V1, the voltage of the common electrode is V2, and the voltage of the pixel electrode is V3. V1-V2 represents the difference between voltages V1 and V2. In this embodiment, the voltage signals of the electrostatic release layer and the common electrode are controlled independently.

[0190] At the L0 grayscale, the value range of V1-V2 can be 1.7V to 1.9V, or the value range of V1-V2 can be -1.8V to -1.6V. For example, the value of V1-V2 can be 1.8V or -1.8V. The voltage V3 of the pixel electrode is set to 0V. At this time, the transmittance of the liquid crystal display panel is reduced by 72.2%, so that the liquid crystal display panel is darker in the normally black mode, and has a more obvious reduction compared to the aforementioned embodiment. Compared with the case without an electrostatic release layer, the contrast has been greatly improved. For example, it can be used in products with high requirements for the L0 grayscale and high requirements for contrast.

[0191] At the L255 grayscale, the value of V1-V2 can range from 1.8 V to 2.0 V. For example, the value of V1-V2 can be 1.8 V. When the voltage V3 of the pixel electrode is set to 98% of the operating voltage, the transmittance of the liquid crystal display panel is only lost by 6.48%, which is a significant improvement.

[0192] Figure 38 is a schematic diagram simulating liquid crystal deflection at grayscale L0 for the LCD panel shown in Figure 31. As shown in Figure 38, at grayscale L0, referring to the aforementioned voltage settings, the difference between voltages V1 and V2 is set to 1.8V. The LCD substrate exhibits no deflection, and the liquid crystals are essentially perpendicular to the paper. The LCD panel displays a darker image in normally black mode, and the transmittance curve shows that the transmittance is essentially zero in this state. Consequently, the contrast of the LCD panel is significantly improved.

[0193] In the liquid crystal display panel shown in Figure 33, the electrostatic release layer 127 can be connected to a separate signal input port through a lead, and the common electrode 1161 is connected to another signal input port through a first common electrode line or a second common electrode line, so that the voltage signals of the electrostatic release layer 127 and the common electrode 1161 can be controlled separately.

[0194] A simulation analysis of the display performance of a liquid crystal display panel equipped with the electrostatic release layer shown in Figure 33 and a liquid crystal display panel without such a layer was conducted. The voltage levels of the pixel electrodes of the liquid crystal display panel without the electrostatic release layer are the same as described above and will not be repeated here. In this example, the voltage of the electrostatic release layer is V1, the voltage of the common electrode is V2, and the voltage of the pixel electrode is V3. V1-V2 represents the difference between voltages V1 and V2. In this embodiment, the voltage signals of the electrostatic release layer and the common electrode are controlled independently.

[0195] At grayscale L0, the value of V1-V2 can range from -0.1V to 0.1V. For example, the value of V1-V2 can be 0V, and the voltage of the electrostatic release layer is the same as the voltage of the common electrode. Setting the voltage V3 of the pixel electrode to 0V reduces the transmittance of the LCD panel by 3.18%, resulting in a darker LCD panel in normally black mode.

[0196] At the L255 grayscale, the value range of V1-V2 can be 1.9 V to 2.1 V. For example, the value of V1-V2 can be 2 V. When the voltage V3 of the pixel electrode is set to 98% of the operating voltage, the transmittance of the liquid crystal display panel is only lost by 3.88%.

[0197] In this embodiment, the electrostatic release layer can improve the transmittance in the L0 state and minimize the impact on the transmittance of L255 and the impact on the contrast.

[0198] In the liquid crystal display panel shown in Figure 35, the electrostatic release layer 127 can be connected to a separate signal input port 0 through a lead, and the common electrode is connected to another signal input port through a first common electrode line or a second common electrode line, so that the voltage signals of the electrostatic release layer 127 and the common electrode 1161 can be controlled separately.

[0199] A simulation analysis of the display performance of a liquid crystal display panel equipped with the electrostatic release layer shown in Figure 35 and a liquid crystal display panel without such a layer was conducted. The voltage levels of the pixel electrodes of the liquid crystal display panel without the electrostatic release layer are the same as described above and will not be repeated here. In this example, the voltage of the electrostatic release layer is V1, the voltage of the common electrode is V2, and the voltage of the pixel electrode is V3. V1-V2 represents the difference between voltages V1 and V2. In this embodiment, the voltage signals of the electrostatic release layer and the common electrode are controlled independently.

[0200] At grayscale L0, the value range of V1-V2 can be 1.0 V to 1.2 V, or the value range of V1-V2 can be -1.0 V to -1.2 V. For example, the value of V1-V2 can be 1.1 V or -1.1 V. When the voltage V3 of the pixel electrode is set to 0 V, the transmittance of the liquid crystal display panel is reduced by 22.1%, thereby making the liquid crystal display panel darker in the normally black mode.

[0201] At the L255 grayscale, the value of V1-V2 can range from 1.0 V to 1.3 V. For example, the value of V1-V2 can be 1.1 V. When the pixel electrode voltage V3 is set to 98% of the operating voltage, the transmittance of the liquid crystal display panel is only reduced by 2.59%, which is a significant improvement.

[0202] Figure 39 shows a light effect diagram of the liquid crystal display panel shown in Figure 35 at grayscale L255. As shown in Figure 39, (b) shows a light effect diagram of the liquid crystal display panel shown in Figure 35 at grayscale L255, while (a) shows a light effect diagram of (b) at grayscale L255 without the electrostatic release layer. As shown by the dotted line in the figure, (b) shows a significant reduction in dark areas compared to (a), thereby improving contrast.

[0203] Figure 40 is a schematic diagram of a simulated liquid crystal deflection of the liquid crystal display panel shown in the figure at grayscale L255. As shown in the figure, (b) is a schematic diagram of a simulated liquid crystal deflection of the liquid crystal display panel shown in Figure 35 at grayscale L255, and (a) is a schematic diagram of a simulated liquid crystal deflection of (b) at grayscale L255 without the electrostatic release layer 127. As indicated by the dotted line in the figure, (b) has improved transmittance compared to (a), thereby enhancing contrast.

[0204] An embodiment of the present disclosure further provides a display device. FIG41 is a schematic diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG41 , the display device 200 includes the aforementioned liquid crystal display panel 100.

[0205] For example, the display device 200 may be a display device 200 having a display function, such as a television, a computer monitor, a laptop computer, a tablet computer, a smart phone, a navigation system, an electronic picture frame, or a car display.

[0206] An embodiment of the present disclosure further provides a method for manufacturing a liquid crystal display panel. FIG42 is a flow chart of a method for manufacturing a liquid crystal display panel provided by an embodiment of the present disclosure. As shown in FIG42 , the method for manufacturing a liquid crystal display panel includes the following steps:

[0207] S110: Providing an array substrate, including a first base substrate and a plurality of pixel structures and a sealing adhesive on the first base substrate;

[0208] S120: Providing an opposing substrate, including a second base substrate and an anti-overflow structure, wherein the anti-overflow structure is disposed on a side of the second base substrate facing the array substrate and is configured to prevent liquid crystal in the liquid crystal layer from overflowing;

[0209] S130: dripping liquid crystal droplets on the opposite substrate; and

[0210] S140: Aligning the array substrate with the opposing substrate to form a liquid crystal display panel. The liquid crystal display panel includes a display area and a peripheral area surrounding the display area. The anti-overflow structure surrounds the display area and is disposed on the side of the frame sealant close to the display area. The opposing substrate is provided with an anti-overflow structure, which is disposed on the side of the frame sealant close to the display area. After liquid crystal droplets are injected onto the opposing substrate, the anti-overflow structure can prevent the liquid crystal from overflowing, preventing the liquid crystal from diffusing to the boundary of the frame sealant, and preventing the diffusion of the liquid crystal from affecting the alignment of the array substrate and the opposing substrate. In addition, the anti-overflow structure can also buffer the impact of the liquid crystal droplets on the frame sealant, improve puncture problems, and improve the product yield.

[0211] There are a few points to note:

[0212] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0213] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0214] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A liquid crystal display panel, comprising an array substrate and an opposing substrate arranged opposite to each other, and a liquid crystal layer arranged between the array substrate and the opposing substrate, wherein the array substrate comprises a first base substrate and a plurality of pixel structures located on the first base substrate, and the opposing substrate comprises: a second substrate base plate; as well as an anti-overflow structure, which is disposed on a side of the second base substrate facing the array substrate and is configured to prevent liquid crystal in the liquid crystal layer from overflowing, Among them, the liquid crystal display panel includes a display area and a peripheral area surrounding the display area. The liquid crystal display panel also includes a frame sealing glue located in the peripheral area and arranged between the array substrate and the opposing substrate. The anti-overflow structure surrounds the display area and is arranged on a side of the frame sealing glue close to the display area.

2. The liquid crystal display panel according to claim 1, wherein: The maximum size of the display area of ​​the liquid crystal display panel on a plane parallel to the second base substrate is less than or equal to 30 mm.

3. The liquid crystal display panel according to claim 1, wherein: On a plane parallel to the second base substrate, the distance between the anti-overflow structure and the display area ranges from 100 μm to 300 μm, and the distance between the anti-overflow structure and the frame sealing glue ranges from 100 μm to 300 μm.

4. The liquid crystal display panel according to claim 1, wherein: The counter substrate further includes a spacer, which is located in the display area and arranged on a side of the second base substrate facing the array substrate. The anti-overflow structure is configured to be formed with the spacer through the same material and the same patterning process.

5. The liquid crystal display panel according to any one of claims 1 to 4, wherein: The anti-overflow structure includes at least one anti-overflow cofferdam.

6. The liquid crystal display panel according to claim 5, wherein: The anti-overflow cofferdam includes a polygon on a plane parallel to the second substrate, and the anti-overflow cofferdam includes a plurality of notches.

7. The liquid crystal display panel according to claim 5, wherein: The anti-overflow dam includes a notch, the counter substrate further includes an alignment layer, the alignment layer is arranged on a side of the second base substrate facing the array substrate, and has an alignment direction, The notch is located at a position of the anti-overflow cofferdam that is farthest from a center line of the display area in the orientation direction.

8. The liquid crystal display panel according to claim 5, wherein: The anti-overflow cofferdam comprises: a first overflow prevention weir having a first opening; and A second overflow prevention cofferdam has a second opening, The first opening and the second opening are arranged opposite to each other, the first anti-overflow cofferdam and the second anti-overflow cofferdam have an interlaced area, and in the interlaced area, the first anti-overflow cofferdam and the second anti-overflow cofferdam are arranged at intervals to form a channel.

9. The liquid crystal display panel according to claim 8, wherein: The counter substrate further comprises an alignment layer, which is arranged on a side of the second base substrate facing the array substrate and has an alignment direction. The staggered area is arranged at a position of the anti-overflow cofferdam that is farthest from a center line of the display area in the orientation direction.

10. The liquid crystal display panel according to claim 8, wherein: The first anti-overflow cofferdam includes a first sub-section and a second sub-section arranged opposite to each other, and a first connecting section connecting the first sub-section and the second sub-section, and the second anti-overflow cofferdam includes a third sub-section and a fourth sub-section arranged opposite to each other, and a second connecting section connecting the third sub-section and the fourth sub-section, The first subsection and the third subsection have staggered areas and are spaced apart to form a channel, and the second subsection and the fourth subsection have staggered areas and are spaced apart to form a channel.

11. The liquid crystal display panel according to claim 5, wherein: The anti-overflow cofferdam includes a plurality of first anti-overflow parts and a plurality of second anti-overflow parts, and in a direction perpendicular to the second substrate, the size of the first anti-overflow part is larger than the size of the second anti-overflow part. In the extending direction of the anti-overflow cofferdam, the first anti-overflow parts and the second anti-overflow parts are arranged alternately.

12. The liquid crystal display panel according to claim 11, wherein: In a direction perpendicular to the second base substrate, a height difference between the first anti-overflow portion and the second anti-overflow portion ranges from 0.5 μm to 0.65 μm.

13. The liquid crystal display panel according to any one of claims 1 to 3, wherein: The counter substrate further comprises a planarization layer, and the planarization layer is arranged on a side of the second base substrate facing the array substrate. The anti-overflow structure includes at least one anti-overflow groove formed in the planarization layer and recessed toward the second base substrate.

14. The liquid crystal display panel according to claim 13, wherein: The depth of the anti-overflow groove ranges from 0.5 μm to 1.5 μm, and the width of the anti-overflow groove ranges from 200 μm to 400 μm.

15. The liquid crystal display panel according to any one of claims 1 to 14, wherein: The counter substrate further comprises: an electrostatic release layer, arranged on a side of the second base substrate facing the array substrate, The sealing frame is at least partially connected to the electrostatic release layer, and the sealing frame is configured to have conductivity so that the electrostatic release layer is connected to the array substrate through the sealing frame.

16. The liquid crystal display panel according to claim 15, wherein: The array substrate further comprises a common electrode layer, which is arranged on a side of the first base substrate facing the counter substrate. The common electrode layer includes a common electrode located in the display area and a conductive structure located in the peripheral area, and the frame sealing glue is at least partially connected to the conductive structure.

17. The liquid crystal display panel according to claim 16, wherein: The array substrate also includes a first common electrode line surrounding the display area and a second common electrode line surrounding the first common electrode line, the first common electrode line is connected to the second common electrode line, the first common electrode line is connected to the common electrode, the second common electrode line is connected to the signal input port of the liquid crystal display panel, and the array substrate also includes a via hole, and the second common electrode line is connected to the conductive structure through the via hole.

18. The liquid crystal display panel according to claim 17, wherein: The orthographic projection of the frame sealing adhesive on the first base substrate at least partially overlaps with the orthographic projection of the second common electrode line on the first base substrate, and the second common electrode line includes a metal grid line.

19. The liquid crystal display panel according to claim 16, wherein: The array substrate further comprises a first common electrode line surrounding the display area and a second common electrode line surrounding the first common electrode line, the first common electrode line is connected to the second common electrode line, the first common electrode line is connected to the common electrode of the display area, and the second common electrode line is connected to a first signal input port of the liquid crystal display panel to be provided with a first voltage signal. The conductive structure is connected to the second signal input port of the liquid crystal display panel through a lead wire to be provided with a second voltage signal.

20. The liquid crystal display panel according to claim 19, wherein: On a plane parallel to the second base substrate, the conductive structure is located on a side of the second common electrode line away from the display area and on a side of the second common electrode line close to an input port of the liquid crystal display panel.

21. The liquid crystal display panel according to claim 19, wherein: The difference between the first voltage signal and the second voltage signal has a value range of 0-3 volts.

22. The liquid crystal display panel according to any one of claims 1 to 21, wherein: The plurality of pixel structures are arranged along a first direction and a second direction, wherein the second direction intersects the first direction. In the pixel structure, the common electrode includes a plurality of first slits extending along the first direction and arranged along the second direction. The electrostatic release layer includes a plurality of electrostatic release portions corresponding to the plurality of pixel structures, and each of the electrostatic release portions includes a plurality of second slits extending along the first direction and arranged along the second direction.

23. The liquid crystal display panel according to claim 22, wherein: In the pixel structure, the plurality of second slits are arranged at equal intervals. In the second direction, a ratio of a size between two adjacent second slits to a size of the second slit is in a range of 1.0-1.

5.

24. The liquid crystal display panel according to claim 22, wherein: In the pixel structure, the plurality of first slits and the plurality of second slits are arranged in one-to-one correspondence, In the second direction, the first slits and the second slits corresponding to each other have the same size.

25. The liquid crystal display panel according to claim 22, wherein: In the pixel structure, the array substrate further includes a block pixel electrode, and the block pixel electrode is located between the second base substrate and the common electrode layer.

26. The liquid crystal display panel according to any one of claims 1 to 25, wherein: The counter substrate further comprises: A black matrix layer, arranged on a side of the second base substrate facing the array substrate; a color filter layer, arranged on a side of the second base substrate facing the array substrate; and A planarization layer is arranged on a side of the black matrix layer and the color filter layer facing the array substrate, Wherein, the anti-overflow structure is arranged on a side of the planarization layer facing the array substrate.

27. A display device comprising a liquid crystal display panel according to any one of claims 1 to 26.

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