Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of circuit units; each circuit unit comprises a pixel driving circuit, a first scanning signal line (31), a second scanning signal line (32), a third scanning signal line (33), and a light-emitting signal line (35); the pixel driving circuit comprises at least an eighth transistor (T8) and a ninth transistor (T9); the orthographic projection of the first scanning signal line (31) on the plane of the display substrate is at least partially overlapped with the orthographic projection of the second scanning signal line (32) on the plane of the display substrate; the orthographic projection of the third scanning signal line (33) on the plane of the display substrate is at least partially overlapped with the orthographic projection of the light-emitting signal line (35) on the plane of the display substrate; and the orthographic projection of the eighth transistor (T8) on the plane of the display substrate is at least partially overlapped with the orthographic projection of the ninth transistor (T9) on the plane of the display substrate.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Light-emitting diode (LED) technology has developed over the past three decades, from initial solid-state lighting power supplies to display backlights and finally LED displays, laying a solid foundation for its wider application. With the advancement of chip manufacturing and packaging technologies, sub-millimeter light-emitting diode (Mini LED) and micro LED (Micro LED) displays have gradually become a hot topic in display panels, with applications in AR / VR, TV, and outdoor displays.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, a first scanning signal line, a second scanning signal line, a third scanning signal line, and a light-emitting signal line, the pixel driving circuit comprising at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; a gate electrode of the first transistor, a gate electrode of the seventh transistor, and a gate electrode of the tenth transistor are electrically connected to the third scanning signal line, a gate electrode of the second transistor is electrically connected to the second scanning signal line, and a gate electrode of the second transistor is electrically connected to the second scanning signal line. The orthographic projection of the first scanning signal line on the display substrate at least partially overlaps with the orthographic projection of the second scanning signal line on the display substrate plane, the orthographic projection of the third scanning signal line on the display substrate plane at least partially overlaps with the orthographic projection of the light emitting signal line on the display substrate plane, and the orthographic projection of the eighth transistor on the display substrate plane at least partially overlaps with the orthographic projection of the ninth transistor on the display substrate plane.

[0006] In an exemplary embodiment, the first transistor, the second transistor, the seventh transistor, the ninth transistor, and the tenth transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor are polysilicon transistors.

[0007] In an exemplary embodiment, an orthographic projection of the gate electrode of the eighth transistor on the plane of the display substrate at least partially overlaps with an orthographic projection of the gate electrode of the ninth transistor on the plane of the display substrate.

[0008] In an exemplary embodiment, an orthographic projection of the active layer of the eighth transistor on the plane of the display substrate at least partially overlaps with an orthographic projection of the active layer of the ninth transistor on the plane of the display substrate.

[0009] In an exemplary embodiment, an orthographic projection of the channel region of the eighth transistor on the plane of the display substrate at least partially overlaps with an orthographic projection of the channel region of the ninth transistor on the plane of the display substrate.

[0010] In an exemplary embodiment, in at least one unit row, pixel driving circuits in two adjacent circuit units are mirror-symmetrical with respect to a column boundary line, which is a straight line located between adjacent unit columns and extending along the pixel column direction.

[0011] In an exemplary embodiment, in at least one unit column, pixel driving circuits in two adjacent circuit units are mirror-symmetrical with respect to a row boundary line, which is a straight line located between adjacent unit rows and extending along the pixel row direction.

[0012] In an exemplary embodiment, in at least one cell column, the first electrodes of the first transistors in two adjacent circuit cells are connected to the same initial signal line, and the first electrodes of the seventh transistors in two adjacent circuit cells are connected to the same initial signal line.

[0013] In an exemplary embodiment, in at least one unit column, the active layers of the first transistors in two adjacent circuit units are connected as an integrated structure, and the active layers of the seventh transistors in two adjacent circuit units are connected as an integrated structure.

[0014] In an exemplary embodiment, in at least one cell row, first electrodes of the eighth transistors in two adjacent circuit cells are connected to the same high-frequency signal line.

[0015] In an exemplary embodiment, in at least one unit row, active layers of the eighth transistors in two adjacent circuit units are connected to each other in an integrated structure.

[0016] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer and a third conductive layer arranged in sequence on a base; the active layer of the third transistor, the active layer of the fourth transistor, the active layer of the fifth transistor, the active layer of the sixth transistor and the active layer of the eighth transistor are arranged in the first semiconductor layer, the first scan signal line, the light emitting signal line and the gate electrode of the eighth transistor are arranged in the first conductive layer, the active layer of the first transistor, the active layer of the second transistor, the active layer of the seventh transistor, the active layer of the ninth transistor and the active layer of the tenth transistor are arranged in the second semiconductor layer, and the second scan signal line, the third scan signal line and the gate electrode of the ninth transistor are arranged in the third conductive layer.

[0017] In an exemplary embodiment, the display substrate further includes a first shielding line, which is arranged between the third scanning signal line and the light-emitting signal line in a direction perpendicular to the display substrate, and the orthographic projection of the first shielding line on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line on the substrate, and the orthographic projection of the first shielding line on the substrate at least partially overlaps with the orthographic projection of the third scanning signal line on the substrate.

[0018] In an exemplary embodiment, the display substrate further includes a second shielding line, which is arranged between the first scanning signal line and the second scanning signal line in a direction perpendicular to the display substrate, and the orthographic projection of the second shielding line on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line on the substrate, and the orthographic projection of the second shielding line on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line on the substrate.

[0019] In an exemplary embodiment, the display substrate further includes a fourth conductive layer disposed on a side of the third conductive layer away from the base; the fourth conductive layer includes at least an interconnection electrode, which is respectively connected to the active layer of the eighth transistor and the active layer of the ninth transistor.

[0020] In an exemplary embodiment, one end of the interconnection electrode is connected to the active layer of the eighth transistor through a via hole, and the other end of the interconnection electrode is connected to the active layer of the ninth transistor through another via hole.

[0021] In an exemplary embodiment, the interconnect electrode overlaps the first surface of the active layer of the eighth transistor through a overlapping hole, and overlaps the second surface of the active layer of the ninth transistor through the overlapping hole, the first surface is a surface parallel to the substrate, and the second surface is a surface intersecting the substrate.

[0022] In an exemplary embodiment, the third conductive layer further includes a transfer electrode; the transfer electrode is connected to the active layer of the eighth transistor through a transfer hole, one end of the interconnection electrode is connected to the first transfer electrode through a via hole, and the other end of the interconnection electrode is connected to the active layer of the ninth transistor through another via hole.

[0023] In an exemplary embodiment, the display substrate further includes a shielding layer, which is arranged between the first conductive layer and the second conductive layer, and the shielding layer includes a transfer electrode; the transfer electrode is connected to the active layer of the eighth transistor through a transfer hole, one end of the interconnection electrode is connected to the transfer electrode through a via hole, and the other end of the interconnection electrode is connected to the active layer of the ninth transistor through another via hole.

[0024] In an exemplary embodiment, the second conductive layer includes a switching electrode; the switching electrode is connected to the active layer of the eighth transistor through a switching hole, and the active layer of the ninth transistor is connected to the switching electrode through another switching hole.

[0025] In an exemplary embodiment, the display substrate further includes a shielding layer, which is disposed between the first conductive layer and the second conductive layer, and the shielding layer includes a transfer electrode; the transfer electrode is connected to the active layer of the eighth transistor through a transfer hole, and the active layer of the ninth transistor is connected to the transfer electrode through another transfer hole.

[0026] On the other hand, the present disclosure further provides a display device comprising the display substrate as described above.

[0027] In another aspect, the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the method comprising:

[0028] A pixel driving circuit, a first scan signal line, a second scan signal line, a third scan signal line and a light-emitting signal line are formed in at least one circuit unit, wherein the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the gate electrode of the first transistor, the gate electrode of the seventh transistor and the gate electrode of the tenth transistor are electrically connected to the third scan signal line, the gate electrode of the second transistor is electrically connected to the second scan signal line, the gate electrode of the fourth transistor is electrically connected to the first scan signal line, the gate electrode of the fifth transistor is electrically connected to the light-emitting signal line, and the gate electrode of the eighth transistor is electrically connected to the gate electrode of the ninth transistor; the orthographic projection of the first scan signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second scan signal line on the display substrate plane, the orthographic projection of the third scan signal line on the display substrate plane at least partially overlaps with the orthographic projection of the light-emitting signal line on the display substrate plane, and the orthographic projection of the eighth transistor on the display substrate plane at least partially overlaps with the orthographic projection of the ninth transistor on the display substrate plane.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0031] FIG1 is a schematic diagram of a planar structure of a display substrate;

[0032] FIG2 is a schematic diagram of a cross-sectional structure of a display substrate;

[0033] FIG3 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0034] FIG4 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG5 is a schematic diagram of a display substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0036] 6A and 6B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0037] 7A and 7B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0038] 8A and 8B are schematic diagrams of a display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0039] 9A and 9B are schematic diagrams of a display substrate after a third conductive layer pattern is formed according to the present disclosure;

[0040] FIG10 is a schematic diagram of a display substrate after a sixth insulating layer pattern is formed according to the present disclosure;

[0041] 11A and 11B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0042] FIG12 is a cross-sectional view taken along line AA in FIG11A;

[0043] 13A and 13B are schematic structural diagrams of another display substrate according to an exemplary embodiment of the present disclosure;

[0044] FIG14 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0045] 15A to 15E are schematic diagrams showing a process for preparing the display substrate shown in FIG. 14 ;

[0046] FIG16 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0047] 17A to 17D are schematic diagrams showing a process for preparing the display substrate shown in FIG. 16 ;

[0048] FIG18 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0049] 19A to 19F are schematic diagrams illustrating a process of preparing the display substrate shown in FIG. 18 .

[0050] DESCRIPTION OF NUMERALS: 10—substrate; 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 19—ninth active layer; 20—tenth active layer; 26—sixth gate electrode; 28—eighth gate electrode; 29—ninth gate electrode; 31—first scan signal line; 32—second scan signal line; 33—third scan signal line; 34—fourth scan signal line; 35—light-emitting signal line; 36—first power line; 37—second power line; 38—first shielding line; 39—second shielding line; 41—first shielding line; 42—second shielding line; 43—third shielding line; 44—shielding block; 45—initial signal line; 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode; 57—seventh connecting electrode; 58—eighth connecting electrode; 61—data signal line; 62—high-frequency signal line; 71—first transfer electrode; 72—second transfer electrode; 73—third transfer electrode; 74—fourth transfer electrode; 81—first electrode plate; 82—second electrode plate; 83—third electrode plate; 84—fourth electrode plate; 91—first insulating layer; 92—second insulating layer; 93—third insulating layer; 94—fourth insulating layer; 95—fifth insulating layer; 96—sixth insulating layer; 97—shielding insulating layer; 102—driving circuit layer; 103—light-emitting structure layer. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0052] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0053] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0054] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0055] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0056] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0057] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0058] In this specification, "connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0059] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0060] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0061] In the present disclosure, “thickness” and “height” refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer close to the substrate.

[0062] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0063] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0064] Micro LED displays / Mini LED displays are a new display technology that miniaturizes LEDs to less than 100μm and solders them to a separate driver backplane to achieve addressable active drive. Due to the advantages of LEDs, such as high brightness, long life, fast response time, and low energy consumption, Micro LED displays / Mini LED displays offer advantages such as high resolution and wide viewing angles, making them a potential next-generation display technology that could replace LCDs and OLEDs.

[0065] Figure 1 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 1, the display substrate may include a plurality of pixel units P in a direction parallel to the display substrate. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line and a data signal line, respectively. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0066] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the three subpixels in the pixel unit P may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure.

[0067] In an exemplary embodiment, the pixel unit P may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square arrangement, a diamond arrangement, or the like, which is not limited in the present disclosure.

[0068] Figure 2 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels in the display area. As shown in Figure 2, in a plane perpendicular to the display substrate, the display substrate may include at least a drive circuit layer 102 disposed on a substrate 10 and a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as an encapsulation structure layer and a touch structure layer, but this disclosure does not limit this.

[0069] In an exemplary embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting diode. The light-emitting diodes in the plurality of light-emitting units are connected to the pixel driving circuits in the plurality of circuit units, and the light-emitting diodes are configured to emit light of corresponding brightness when driven by the output current of the corresponding pixel driving circuit.

[0070] The display substrate of the present disclosure is illustrated below through multiple examples.

[0071] Figure 3 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure, illustrating a 10T2C pixel driving circuit structure. As shown in Figure 3, the pixel driving circuit provided by the exemplary embodiment of the present disclosure may include at least a current control subcircuit DK and a duration control subcircuit SK. The current control subcircuit DK may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. The duration control subcircuit SK may include at least an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a first capacitor C1.

[0072] In an exemplary embodiment, the pixel driving circuit may include at least a first node N1, a second node N2, a third node N3, a fourth node N4, a fifth node N5, and a sixth node N6. The first node N1 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor Cst, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively. The fifth node N5 is connected to the gate electrode of the sixth transistor T6, the second electrode of the eighth transistor T8, and the second electrode of the ninth transistor T9, respectively. The sixth node N6 is connected to the gate electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9, the second electrode of the tenth transistor T10, and the first end of the first capacitor C1, respectively.

[0073] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the third scan signal line S3 , a first electrode of the first transistor T1 is connected to the initial signal line Vint, and a second electrode of the first transistor T1 is connected to the first node N1 .

[0074] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the second scan signal line S2 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0075] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0076] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line Data, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0077] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0078] In an exemplary embodiment, a gate electrode of the sixth transistor T6 is connected to the fifth node N5 , a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0079] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the third scan signal line S3 , a first electrode of the seventh transistor T7 is connected to the initial signal line Vint, and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0080] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the sixth node N6 , a first electrode of the eighth transistor T8 is connected to the high-frequency signal line Hf, and a second electrode of the eighth transistor T8 is connected to the fifth node N5 .

[0081] In an exemplary embodiment, a gate electrode of the ninth transistor T9 is connected to the sixth node N6 , a first electrode of the ninth transistor T9 is connected to the light emitting signal line EM, and a second electrode of the ninth transistor T9 is connected to the fifth node N5 .

[0082] In an exemplary embodiment, a gate electrode of the tenth transistor T10 is connected to the third scan signal line S3 , a first electrode of the tenth transistor T10 is connected to the data signal line Data, and a second electrode of the tenth transistor T10 is connected to the sixth node N6 .

[0083] In an exemplary embodiment, the eighth transistor T8 , the ninth transistor T9 , and the tenth transistor T10 constitute an inverter structure.

[0084] In an exemplary embodiment, a first end of the storage capacitor Cst is connected to the first node N1 , and a second end of the storage capacitor Cst is connected to the first power line VDD.

[0085] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the sixth node N6 , and a second end of the first capacitor C1 is connected to the second power line VSS.

[0086] In an exemplary embodiment, the first transistor T1 , the second transistor T2 , and the fourth to tenth transistors T4 to T10 may be switching transistors, and the third transistor T3 may be a driving transistor.

[0087] In an exemplary embodiment, the light emitting diode EL may be a Mini LED or a Micro LED. A first electrode of the light emitting diode EL is connected to the fourth node N4, and a second electrode of the light emitting diode EL is connected to the second power line VSS.

[0088] In an exemplary embodiment, the signal on the first power line VDD is a continuously provided high-level signal, such as a DC high voltage. The signal on the second power line VSS is a continuously provided low-level signal, such as a DC low voltage. The signal on the high-frequency signal line Hf is a pulse signal, and within an image frame, the signal on the high-frequency signal line Hf has multiple pulses. In an exemplary embodiment, the frequency of the signal on the high-frequency signal line Hf can be greater than the frequency of the signal on the light-emitting signal line EM. For example, the frequency of the signal on the high-frequency signal line Hf can be between 3000 Hz and 60000 Hz, while the frequency of the light-emitting signal line EM can be between 60 Hz and 120 Hz.

[0089] In an exemplary embodiment, multiple light-emitting diodes in the display substrate can be driven by current mode. The pixel driving circuit shown in Figure 3 adopts a pulse amplitude modulation (PAM) + pulse width modulation (PWM) operating mode. The PAM mode is used at low current density to reduce power consumption, and the PWM mode is used at high current density to reduce the high current driving state.

[0090] In an exemplary embodiment, the first to tenth transistors T1 to T10 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to tenth transistors T1 to T10 may include P-type transistors and N-type transistors.

[0091] In an exemplary embodiment, the first transistor T1 to the tenth transistor T10 may be low-temperature polysilicon transistors, or oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is made of a metal oxide first semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, achieving low-frequency driving, reducing power consumption, and improving display quality.

[0092] In an exemplary embodiment, in the pixel driving circuit provided by the present disclosure, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are low-temperature polysilicon transistors, and the first transistor T1, the second transistor T2, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are oxide transistors. This not only effectively reduces the leakage current of the switching transistor and the size of the storage capacitor, but also the inverter circuit composed of low-temperature polysilicon transistors and oxide transistors can effectively reduce the number of transistors in the PWM module and effectively improve the resolution.

[0093] The present disclosure provides a display substrate. The display substrate may include, on a plane perpendicular to the display substrate, at least a drive circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the drive circuit layer away from the base. The drive circuit layer may include a plurality of circuit units, each of which may include a pixel drive circuit. The light-emitting structure layer may include a plurality of light-emitting units, each of which may include a light-emitting diode. The light-emitting diodes in the plurality of light-emitting units are connected to the pixel drive circuits in the plurality of circuit units, and the light-emitting diodes are configured to emit light of corresponding brightness when driven by the output current of the corresponding pixel drive circuit.

[0094] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting diode. In exemplary embodiments, the positions of the light-emitting unit and the circuit unit may correspond, or they may not correspond, and this disclosure does not limit this.

[0095] In an exemplary embodiment, the light emitting diode mentioned in the present disclosure may be a sub-millimeter light emitting diode Mini LED or a micro light emitting diode Micro LED.

[0096] An exemplary embodiment of the present disclosure provides a display substrate, including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit, a first scanning signal line, a second scanning signal line, a third scanning signal line, and a light emitting signal line, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; a gate electrode of the first transistor, a gate electrode of the seventh transistor, and a gate electrode of the tenth transistor are electrically connected to the third scanning signal line, a gate electrode of the second transistor is electrically connected to the second scanning signal line, and a gate electrode of the second transistor is electrically connected to the second scanning signal line. The orthographic projection of the first scanning signal line on the display substrate at least partially overlaps with the orthographic projection of the second scanning signal line on the display substrate plane, the orthographic projection of the third scanning signal line on the display substrate plane at least partially overlaps with the orthographic projection of the light emitting signal line on the display substrate plane, and the orthographic projection of the eighth transistor on the display substrate plane at least partially overlaps with the orthographic projection of the ninth transistor on the display substrate plane.

[0097] In an exemplary embodiment, the first transistor, the second transistor, the seventh transistor, the ninth transistor, and the tenth transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor are polysilicon transistors.

[0098] In an exemplary embodiment, an orthographic projection of the gate electrode of the eighth transistor on the plane of the display substrate at least partially overlaps with an orthographic projection of the gate electrode of the ninth transistor on the plane of the display substrate.

[0099] In an exemplary embodiment, an orthographic projection of the active layer of the eighth transistor on the plane of the display substrate at least partially overlaps with an orthographic projection of the active layer of the ninth transistor on the plane of the display substrate.

[0100] In an exemplary embodiment, an orthographic projection of the channel region of the eighth transistor on the plane of the display substrate at least partially overlaps with an orthographic projection of the channel region of the ninth transistor on the plane of the display substrate.

[0101] In an exemplary embodiment, in at least one unit row, pixel driving circuits in two adjacent circuit units are mirror-symmetrical with respect to a column boundary line, which is a straight line located between adjacent unit columns and extending along the pixel column direction.

[0102] In an exemplary embodiment, in at least one unit column, pixel driving circuits in two adjacent circuit units are mirror-symmetrical with respect to a row boundary line, which is a straight line located between adjacent unit rows and extending along the pixel row direction.

[0103] Figure 4 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate may include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. The plurality of circuit units in each unit row may be arranged sequentially along a first direction X, and the plurality of circuit units in each unit column may be arranged sequentially along a second direction Y, forming an array of circuit units arranged in an array, where the first direction X intersects the second direction Y. Figure 4 illustrates the structure of four circuit units in two unit rows (the Mth unit row and the M+1th unit row) and two unit columns (the Nth unit column and the N+1th unit column).

[0104] As shown in Figure 4, at least one circuit unit may include a pixel driving circuit, and a first scanning signal line 31, a second scanning signal line 32, a third scanning signal line 33, a light-emitting signal line 35, a first power line 36, a second power line 37, an initial signal line 45, a data signal line 61 and a high-frequency signal line 62 respectively connected to the pixel driving circuit. The shapes of the first scanning signal line 31, the second scanning signal line 32, the third scanning signal line 33, the light-emitting signal line 35, the first power line 36, the second power line 37 and the initial signal line 45 can be a line shape whose main part extends along the first direction X, and the shapes of the data signal line 61 and the high-frequency signal line 62 can be a line shape whose main part extends along the second direction Y.

[0105] In this disclosure, "structure A extends along direction B" means that structure A can include a main portion and a secondary portion connected to the main portion. The main portion is generally strip-shaped and extends in a particular direction. The secondary portion can be of any shape, and the main portion comprises at least 60% of structure A. The main portion extends along direction B, and the main portion's dimension along direction B is greater than that of the secondary portion extending in other directions. In the following description, "structure A extends along direction B" refers to "the main portion of structure A extending along direction B."

[0106] In an exemplary embodiment, the pixel driving circuit of at least one circuit unit may include a storage capacitor, a first capacitor, and a plurality of transistors, the plurality of transistors may include: a first transistor T1 and a seventh transistor T7 as initialization transistors, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 and a tenth transistor T10 as data writing transistors, a fifth transistor T5 and a sixth transistor T6 as light emitting control transistors, an eighth transistor T8 as a first control transistor, and a ninth transistor T9 as a second control transistor.

[0107] In example embodiments, the first transistor T1 , the second transistor T2 , the seventh transistor T7 , the ninth transistor T9 , and the tenth transistor T10 may be oxide transistors, and the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the eighth transistor T8 may be polysilicon transistors.

[0108] In an exemplary embodiment, the storage capacitor may include a stacked first plate and a third plate, the first plate may serve as the gate electrode of the third transistor T3, and the third plate is connected to the first power line 36. The first capacitor may include a stacked second plate and a fourth plate, the second plate being connected to the gate electrode of the eighth transistor T8 and the gate electrode of the ninth transistor T9, respectively, and the fourth plate being connected to the second power line 37.

[0109] In an exemplary embodiment, the gate electrode of the first transistor T1, the gate electrode of the seventh transistor T7, and the gate electrode of the tenth transistor T10 are all connected to the third scan signal line 33, which is configured to control the on and off of the first transistor T1, the seventh transistor T7, and the tenth transistor T10. The first electrode of the first transistor T1 and the first electrode of the seventh transistor T7 are both connected to the initial signal line 45, which is configured to provide an initial signal to the first transistor T1 and the seventh transistor T7. The first electrode of the tenth transistor T10 is connected to the data signal line 61, which is configured to provide a data signal to the tenth transistor T10. The gate electrode of the second transistor T2 is connected to the second scan signal line 32, which is configured to control the on and off of the second transistor T2. The first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1 and the gate electrode of the third transistor T3, respectively. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 31, which is configured to control the on / off state of the fourth transistor T4. The first electrode of the fourth transistor T4 is connected to the data signal line 61, which is configured to provide a data signal to the fourth transistor T4. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 35, which is configured to control the on / off state of the fifth transistor T5. The first electrode of the fifth transistor T5 is connected to the first power supply line 36, which is configured to provide a first power supply signal to the fifth transistor T5. The gate electrode of the eighth transistor T8 and the gate electrode of the ninth transistor T9 are connected to each other. The first electrode of the eighth transistor T8 is connected to the high-frequency signal line 62, which is configured to provide a high-frequency signal to the eighth transistor T8. The first electrode of the ninth transistor T9 is connected to the light emission signal line 35, which is configured to provide a light emission signal to the ninth transistor T9.

[0110] In an exemplary embodiment, the position of the first scan signal line 31 in the circuit unit corresponds to the position of the second scan signal line 32 in the circuit unit, and the orthographic projection of the first scan signal line 31 on the display substrate plane at least partially overlaps with the orthographic projection of the second scan signal line 32 on the display substrate plane.

[0111] In an exemplary embodiment, the position of the third scan signal line 33 in the circuit unit corresponds to the position of the light emitting signal line 35 in the circuit unit, and the orthographic projection of the third scan signal line 33 on the display substrate plane at least partially overlaps with the orthographic projection of the light emitting signal line 35 on the display substrate plane.

[0112] In an exemplary embodiment, the position of the eighth transistor T8 in the circuit unit corresponds to the position of the ninth transistor T9 in the circuit unit, and the orthographic projection of the eighth transistor T8 on the display substrate plane at least partially overlaps with the orthographic projection of the ninth transistor T9 on the display substrate plane.

[0113] In an exemplary embodiment, the eighth transistor T8 and the ninth transistor T9 may both include a gate electrode and an active layer, and the orthographic projection of the eighth transistor T8 on the display substrate plane at least partially overlaps with the orthographic projection of the ninth transistor T9 on the display substrate plane, which may include any one or more of the following: the orthographic projection of the gate electrode 28 of the eighth transistor on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode 29 of the ninth transistor on the display substrate plane, the orthographic projection of the active layer 18 of the eighth transistor on the display substrate plane at least partially overlaps with the orthographic projection of the active layer 19 of the ninth transistor on the display substrate plane, and the orthographic projection of the channel region of the eighth transistor T8 on the display substrate plane at least partially overlaps with the orthographic projection of the channel region of the ninth transistor T9 on the display substrate plane.

[0114] In an exemplary embodiment, in at least one unit row, the pixel driving circuits in two adjacent circuit units may be mirror-symmetric with respect to a column boundary, and the column boundary may be a straight line located between adjacent unit columns and extending along the pixel column direction. For example, the pixel driving circuit in the Nth unit column and the pixel driving circuit in the N+1th unit column may be mirror-symmetric with respect to the column boundary. For another example, the pixel driving circuit in the N+1th unit column and the pixel driving circuit in the N+2th unit column may be mirror-symmetric with respect to the column boundary. For another example, the pixel driving circuit in the N-1th unit column and the pixel driving circuit in the Nth unit column may be mirror-symmetric with respect to the column boundary.

[0115] In an exemplary embodiment, in at least one unit column, the pixel driving circuits in two adjacent circuit units may be mirror-symmetrical with respect to a row boundary, and the row boundary may be a straight line located between adjacent unit rows and extending along the direction of the pixel rows. For example, the pixel driving circuit in the Mth unit row and the pixel driving circuit in the M+1th unit row may be mirror-symmetrical with respect to the row boundary. For another example, the pixel driving circuit in the M+1th unit row and the pixel driving circuit in the M+2th unit row may be mirror-symmetrical with respect to the row boundary. For another example, the pixel driving circuit in the M-1th unit row and the pixel driving circuit in the Mth unit row may be mirror-symmetrical with respect to the column boundary.

[0116] In an exemplary embodiment, in at least one unit column, the first electrodes of the first transistors T1 in two adjacent circuit units can be connected to the same initial signal line 45, that is, the initial signal line 45 can be set between two adjacent unit rows, and the pixel driving circuits of the two adjacent unit rows share one initial signal line 45.

[0117] In an exemplary embodiment, in at least one cell column, the active layers of the first transistors T1 in two adjacent circuit cells are connected to each other in an integrated structure.

[0118] In an exemplary embodiment, in at least one unit row, the first electrodes of the eighth transistors T8 in two adjacent circuit units are connected to the same high-frequency signal line 62, that is, the high-frequency signal line 62 can be arranged between two adjacent unit columns, and the pixel driving circuits of the two adjacent unit columns share one high-frequency signal line 62.

[0119] In an exemplary embodiment, in at least one unit row, the active layers of the eighth transistors T8 in two adjacent circuit units are connected to each other in an integrated structure.

[0120] In an exemplary embodiment, the display substrate may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a base in a direction perpendicular to the display substrate.

[0121] In an exemplary embodiment, the active layers of the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may be disposed in the first semiconductor layer, and the active layers of the first transistor T1, the second transistor T2, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 may be disposed in the second semiconductor layer.

[0122] In an exemplary embodiment, the first scan signal line 31, the light emitting signal line 35, the first power line 36, the gate electrode, the first plate, and the second plate of the eighth transistor T8 can be set in the first conductive layer, the second power line 37, the third plate, and the fourth plate can be set in the second conductive layer, the second scan signal line 32, the third scan signal line 33, and the gate electrode of the ninth transistor T9 can be set in the third conductive layer, and the data signal line 61 and the high-frequency signal line 62 can be set in the fourth conductive layer.

[0123] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0124] In an exemplary embodiment, taking four circuit cells in two cell rows (Mth cell row and M+1th cell row) and two cell columns (Nth cell column and N+1th cell column) as an example, the preparation process of the display substrate may include the following operations.

[0125] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer disposed on the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 5 .

[0126] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least: a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, and an eighth active layer 18 of an eighth transistor T8, and the third active layer 13 to the sixth active layer 16 are an integral structure connected to each other, and the eighth active layer 18 is provided separately.

[0127] In an exemplary embodiment, the third active layer 13 may be shaped like a strip extending along the first direction X, the fourth active layer 14, the fifth active layer 15, and the sixth active layer 16 may be shaped like a strip extending along the second direction Y, and the eighth active layer 18 may be shaped like a broken line.

[0128] In an exemplary embodiment, in the first direction X, the fourth active layer 14 in the Nth unit column may be located on a side of the third active layer 13 in the present circuit unit opposite to the first direction X, and the fourth active layer 14 in the N+1th unit column may be located on a side of the third active layer 13 in the present circuit unit in the first direction X. The sixth active layer 16 in the Nth unit column may be located on a side of the third active layer 13 in the present circuit unit in the first direction X, and the sixth active layer 16 in the N+1th unit column may be located on a side of the third active layer 13 in the present circuit unit opposite to the first direction X.

[0129] In an exemplary embodiment, in the second direction Y, the fourth active layer 14 in the Mth cell row may be located on one side of the third active layer 13 in the present circuit unit in the second direction Y, and the fourth active layer 14 in the M+1th cell row may be located on a side of the third active layer 13 in the present circuit unit in the opposite direction of the second direction Y. The fifth active layer 15, the sixth active layer 16, and the eighth active layer 18 in the Mth cell row may be located on a side of the third active layer 13 in the present circuit unit in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, and the eighth active layer 18 in the M+1th cell row may be located on one side of the third active layer 13 in the present circuit unit in the second direction Y.

[0130] In example embodiments, the third to sixth active layers 13 to 16 and the eighth active layer 18 may each include a first region, a second region, and a channel region between the first and second regions.

[0131] In an exemplary embodiment, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the second region 16-2 of the sixth active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be separately provided, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer may be connected to each other, that is, the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer, and the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer.

[0132] In an exemplary embodiment, within a cell row, the first regions 16-1 of the eighth active layer in two adjacent circuit cells may be interconnected, such that the eighth active layers in the two adjacent circuit cells form an interconnected, integrated structure. For example, the first region of the eighth active layer in the Nth cell column and the first region 18-1 of the eighth active layer in the N+1th cell column may be interconnected. For another example, the first region of the eighth active layer in the N+2th cell column and the first region of the eighth active layer in the N+3th cell column may be interconnected. For another example, the first region of the eighth active layer in the N-2th cell column and the first region of the eighth active layer in the N-1th cell column may be interconnected. Since the first region of the eighth active layer in each circuit unit is configured to be connected to a subsequently formed high-frequency signal line, by forming the first regions of the eighth active layers of adjacent circuit units into an interconnected integrated structure, two unit columns can share a high-frequency signal line. This not only reduces one high-frequency signal line and the corresponding via, reducing the occupied area of ​​the pixel driving circuit and improving the resolution, but also ensures that the first electrodes of the eighth transistors T8 in adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0133] In an exemplary embodiment, the eighth active layer 18 may include a first subsegment 18A and a second subsegment 18B connected to each other. The first subsegment 18A may be in the shape of a strip extending along the second direction Y, and the second subsegment 18B may be in the shape of a strip extending along the first direction X. The first end of the first subsegment 18A is located on a side of the third active layer 13 away from the fourth active layer 14. The second end of the first subsegment 18A extends away from the third active layer 13 along the second direction Y and is connected to the first end of the second subsegment 18B. The second end of the second subsegment 18B extends away from the first subsegment 18A along the first direction X and is connected to the eighth active layer 18 in an adjacent circuit unit in the first direction X. In an exemplary embodiment, the first end of the first subsegment 18A may serve as the second region of the eighth active layer, and the second end of the second subsegment 18B may serve as the first region of the eighth active layer. The channel region of the eighth active layer may be located in the second subsegment 18B.

[0134] In an exemplary embodiment, the first semiconductor layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the first semiconductor layer in the Nth cell column and the first semiconductor layer in the N+1th cell column may be mirror-symmetric with respect to a column boundary. For another example, the first semiconductor layer in the N+1th cell column and the first semiconductor layer in the N+2th cell column may be mirror-symmetric with respect to a column boundary. For another example, the first semiconductor layer in the N-1th cell column and the first semiconductor layer in the Nth cell column may be mirror-symmetric with respect to a column boundary.

[0135] In an exemplary embodiment, the first semiconductor layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the first semiconductor layer in the Mth cell row and the first semiconductor layer in the M+1th cell row may be mirror-symmetric with respect to a row boundary. For another example, the first semiconductor layer in the M+1th cell row and the first semiconductor layer in the M+2th cell row may be mirror-symmetric with respect to a row boundary. For another example, the first semiconductor layer in the M-1th cell row and the first semiconductor layer in the Mth cell row may be mirror-symmetric with respect to a column boundary.

[0136] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), i.e., the third to sixth transistors T6 and the eighth transistor T8 are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the second insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0137] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG6A and FIG6B , where FIG6B is a plan view schematic diagram of the first conductive layer in FIG6A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0138] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a sixth gate electrode 26 , an eighth gate electrode 28 , a first scan signal line 31 , a light emitting signal line 35 , a first power line 36 , a first plate 81 , and a second plate 82 .

[0139] In an exemplary embodiment, the sixth gate electrode 26 may be in the shape of a strip extending along the first direction X. The orthographic projection of the sixth gate electrode 26 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer on the substrate. The overlapping region of the sixth gate electrode 26 and the sixth active layer may serve as the gate electrode of the sixth transistor T6. In an exemplary embodiment, the sixth gate electrode 26 is configured to be connected to a sixth connection electrode formed subsequently.

[0140] In an exemplary embodiment, the eighth gate electrode 28 may be in the shape of a strip extending along the second direction Y. The orthographic projection of the eighth gate electrode 28 on the substrate at least partially overlaps with the orthographic projection of the eighth active layer on the substrate. The overlapping region of the eighth gate electrode 28 and the eighth active layer may serve as the gate electrode of the eighth transistor T8. In an exemplary embodiment, the eighth gate electrode 28 is configured to be connected to a seventh connection electrode formed subsequently.

[0141] In an exemplary embodiment, the first electrode plate 81 may be rectangular, with chamfered corners. The first electrode plate 81 may be disposed on a side of the sixth gate electrode 26 away from the eighth gate electrode 28, with the orthographic projection of the first electrode plate 81 on the substrate at least partially overlapping the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 81 may serve as both the lower plate of the storage capacitor and the gate electrode of the third transistor T3.

[0142] In an exemplary embodiment, a first opening 81-1 may be provided on the first electrode plate 81. The first opening 81-1 may be rectangular and located on a side of the first electrode plate 81 away from the first scan signal line, forming a "U" shape or an inverted "U" shape. The first opening 81-1 exposes the second insulating layer covering the first semiconductor layer, and the orthographic projection of the first opening 81-1 on the substrate at least partially overlaps the orthographic projection of the second region of the third active layer on the substrate. In an exemplary embodiment, the first opening 81-1 is configured to accommodate a subsequently formed fourth via V4. The fourth via V4 is located within the first opening 81-1 and exposes the second region of the third active layer (also the first region of the sixth active layer), allowing a subsequently formed second connecting electrode to connect to the second region of the third active layer (also the first region of the sixth active layer).

[0143] In an exemplary embodiment, the shape of the second electrode 82 can be rectangular, and the corners of the rectangle can be chamfered. The second electrode 82 can be set on the side of the eighth gate electrode 28 away from the sixth gate electrode 26. The second electrode 82 can serve as the lower plate of the first capacitor.

[0144] In an exemplary embodiment, the second plate 82 may be connected to the eighth gate electrode 28 so that the lower plate of the first capacitor (the first end of the first capacitor) and the gate electrode of the eighth transistor T8 have the same potential.

[0145] In an exemplary embodiment, the eighth gate electrode 28 and the second plate 82 may be an integral structure connected to each other.

[0146] In an exemplary embodiment, the shape of the first scan signal line 31 can be a straight line or a zigzag line with the main portion extending along the first direction X. The region where the first scan signal line 31 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4. In an exemplary embodiment, the first scan signal line 31 in the Mth unit row can be located on one side of the first electrode plate 81 in the circuit unit in the second direction Y, and the first scan signal line 31 in the M+1th unit row can be located on the side of the first electrode plate 81 in the circuit unit opposite to the second direction Y.

[0147] In an exemplary embodiment, the shape of the light-emitting signal line 35 can be a straight line or a broken line, with the main portion extending along the first direction X. The region where the light-emitting signal line 35 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5. In an exemplary embodiment, the light-emitting signal line 35 in the Mth unit row can be located on the side of the second electrode plate 82 in the circuit unit opposite to the second direction Y. The light-emitting signal line 35 in the M+1th unit row can be located on the side of the second electrode plate 82 in the circuit unit in the second direction Y.

[0148] In an exemplary embodiment, a light-emitting connection block 35-1 is connected to the light-emitting signal line 35 of each circuit unit. The light-emitting connection block 35-1 may be in the shape of a bar extending along the second direction Y. A first end of the light-emitting connection block 35-1 is connected to the light-emitting signal line 35, and a second end of the light-emitting connection block 35-1 extends in a direction away from the second electrode plate 82. The light-emitting connection block 35-1 is configured to be connected to an eighth connection electrode formed subsequently.

[0149] In an exemplary embodiment, in the second direction Y, the sixth gate electrode 26 , the eighth gate electrode 28 , the first electrode plate 81 , and the second electrode plate 82 may be disposed between the first scan signal line 31 and the light emitting signal line 35 .

[0150] In an exemplary embodiment, the first power line 36 may be in a straight line or a broken line shape with its main portion extending along the first direction X. The first power line 36 may be located on a side of the light emitting signal line 35 away from the first scanning signal line 31 in the circuit unit.

[0151] In an exemplary embodiment, the first conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the first conductive layer in the Nth cell column and the first conductive layer in the N+1th cell column may be mirror-symmetric with respect to a column boundary. For another example, the first conductive layer in the N+1th cell column and the first conductive layer in the N+2th cell column may be mirror-symmetric with respect to a column boundary. For another example, the first conductive layer in the N-1th cell column and the first conductive layer in the Nth cell column may be mirror-symmetric with respect to a column boundary.

[0152] In an exemplary embodiment, the first conductive layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the first conductive layer in the Mth cell row and the first conductive layer in the M+1th cell row may be mirror-symmetric with respect to a row boundary. For another example, the first conductive layer in the M+1th cell row and the first conductive layer in the M+2th cell row may be mirror-symmetric with respect to a row boundary. For another example, the first conductive layer in the M-1th cell row and the first conductive layer in the Mth cell row may be mirror-symmetric with respect to a column boundary.

[0153] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the sixth transistor T6 and the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the third transistor T3 to the sixth transistor T6 and the eighth transistor T8 are both conductorized.

[0154] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG7A and FIG7B , where FIG7B is a plan view schematic diagram of the second conductive layer in FIG7A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0155] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: a second power line 37 , a first shielding line 41 , a second shielding line 42 , a third shielding line 43 , a shielding block 44 , an initial signal line 45 , a third electrode plate 83 , and a fourth electrode plate 84 .

[0156] In an exemplary embodiment, the second power line 37 may be in a straight line or a zigzag shape with a main portion extending along the first direction X. The second power line 37 may be located between the sixth gate electrode 26 and the eighth gate electrode 28 in the circuit unit.

[0157] In an exemplary embodiment, the first shielding line 41 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The first shielding line 41 in the Mth unit row may be located on one side of the first scanning signal line 31 in the circuit unit in the second direction Y, and the first shielding line 41 in the M+1th unit row may be located on the side opposite to the first scanning signal line 31 in the circuit unit in the second direction Y. In an exemplary embodiment, the first shielding line 41 is configured as a shielding layer for the first transistor T1 and the seventh transistor T7, shielding the channel regions of the first transistor T1 and the seventh transistor T7 to ensure the electrical performance of the oxide of the first transistor T1 and the seventh transistor T7, and is also configured as the bottom gate electrode of the first transistor T1 and the seventh transistor T7.

[0158] In an exemplary embodiment, the second shielding line 42 may be in the shape of a straight line or a broken line, with the main portion extending along the first direction X. It may be located between the first electrode 81 and the first shielding line 41 in this circuit unit. The orthographic projection of the second shielding line 42 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 31 on the substrate. In an exemplary embodiment, the second shielding line 42 serves as a shielding layer for the second transistor T2, shielding the channel region of the second transistor T2 to ensure the electrical performance of the oxide-based second transistor T2. It also serves as the bottom gate electrode of the second transistor T2.

[0159] In an exemplary embodiment, the third shielding line 43 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. It may be located on a side of the second electrode plate 82 in this circuit unit that is away from the first scanning signal line 31. The orthographic projection of the third shielding line 43 on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line 35 on the substrate. In an exemplary embodiment, the third shielding line 43 serves as a shielding layer for the tenth transistor T10, shielding the channel region of the tenth transistor T10 to ensure the electrical performance of the oxide-containing tenth transistor T10. It also serves as the bottom gate electrode of the tenth transistor T10.

[0160] In an exemplary embodiment, the blocking block 44 may be in the shape of a strip extending along the second direction Y, and an orthographic projection of the blocking block 44 on the substrate at least partially overlaps with an orthographic projection of the eighth gate electrode 28 on the substrate. In an exemplary embodiment, the blocking block 44 is configured as a blocking layer for the ninth transistor T9, shielding the channel region of the ninth transistor T9 to ensure the electrical performance of the oxide-containing ninth transistor T9, and is also configured as a bottom gate electrode of the ninth transistor T9.

[0161] In an exemplary embodiment, the initial signal line 45 may be in the shape of a straight line or a broken line with its main portion extending along the first direction X. The initial signal line 45 may be located on a side of the first shielding line 41 away from the second shielding line 42 in the circuit unit.

[0162] In an exemplary embodiment, the initial signal line 45 can be arranged between the Mth unit row and the M+1th unit row, so that the pixel driving circuit in the Mth unit row and the pixel driving circuit in the M+1th unit row share an initial signal line 45, that is, the initial signal line 45 in the Mth unit row and the initial signal line 45 in the M+1th unit row can be the same signal line.

[0163] The present disclosure provides a common initial signal line for two adjacent unit rows, thereby not only eliminating one initial signal line and corresponding vias, reducing the area occupied by the pixel driving circuit, and improving resolution, but also ensuring that the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7 in the adjacent unit rows have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0164] In an exemplary embodiment, the contour shape of the third electrode plate 83 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the third electrode plate 83 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 81 on the substrate. The third electrode plate 83 can serve as the upper plate of the storage capacitor, and the first electrode plate 81 and the third electrode plate 83 constitute the storage capacitor of the pixel driving circuit.

[0165] In an exemplary embodiment, a second opening 83-1 is provided on the third plate 83. The second opening 83-1 can be rectangular and located on a side of the third plate 83 away from the first scan signal line, forming a ring-shaped structure with an opening. The second opening 83-1 not only exposes the third insulating layer covering the first plate 81, but also exposes the second and third insulating layers covering the first semiconductor layer. The orthographic projection of the second opening 83-1 on the substrate at least partially overlaps with the orthographic projection of the first plate 81 on the substrate. The orthographic projection of the second opening 83-1 on the substrate at least partially overlaps with the orthographic projection of the second region of the third active layer on the substrate. In an exemplary embodiment, the second opening 83-1 is configured to accommodate a fourth via hole and a fifteenth via hole to be formed subsequently. The fourth via hole is located within the second opening 83-1 and exposes the second region of the third active layer, allowing a second connecting electrode to be formed subsequently to be connected to the second region of the third active layer. The fifteenth via hole is located within the second opening 83-1 and exposes the first plate 81, allowing a first connecting electrode to be formed subsequently to be connected to the first plate 81.

[0166] In an exemplary embodiment, the third plates 83 in two adjacent circuit units in a unit row can be interconnected integral structures. For example, the third plate 83 in the Nth column and the third plate 83 in the N+1th unit column can be interconnected. For another example, the third plate 83 in the N+2th column and the third plate 83 in the N+3th unit column can be interconnected. For another example, the third plate 83 in the N-2th column and the third plate 83 in the N-1th unit column can be interconnected. In an exemplary embodiment, the third plate of the integral structure can extend to the frame area and be connected to the first power line in the frame area. The present disclosure forms an integral structure in which the third plates of adjacent circuit units are interconnected, and the third plates of the integral structure can be reused as a horizontal power signal line, which can ensure that multiple third plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0167] In an exemplary embodiment, the contour shape of the fourth plate 84 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the fourth plate 84 on the substrate at least partially overlaps with the orthographic projection of the second plate 82 on the substrate. The fourth plate 84 can serve as the upper plate of the first capacitor, and the second plate 82 and the fourth plate 84 constitute the first capacitor of the pixel driving circuit.

[0168] In an exemplary embodiment, a first plate connecting bar 84-1 may be provided on the fourth plate 84 in each circuit unit, wherein the first end of the first plate connecting bar 84-1 is connected to the fourth plate 84 of the circuit unit, and the second end of the first plate connecting bar 84-1 extends toward the adjacent circuit unit and is connected to the first plate connecting bar 84-1 of the adjacent circuit unit, so that the fourth plates 84 of some adjacent circuit units in a unit row are connected to each other.

[0169] In an exemplary embodiment, the fourth electrode plate 84 and the first electrode plate connecting bar 84-1 in each circuit unit can be interconnected as an integral structure. The fourth electrode plates 84 of some adjacent circuit units in a unit row are interconnected as an integral structure via the electrode plate connecting bar 84-1. By interconnecting the fourth electrode plates of adjacent circuit units as an integral structure, the present disclosure not only reduces the footprint of the pixel driving circuit and improves resolution, but also ensures that the fourth electrode plates of adjacent circuit units have the same potential, which helps improve panel uniformity, avoids display defects on the display substrate, and ensures the display quality of the display substrate.

[0170] In an exemplary embodiment, each circuit unit may further include a second plate connecting bar 84-2. The second plate connecting bar 84-2 may be in the shape of a bar extending along the second direction Y and disposed between the first plate connecting bar 84-1 and the second power line 37. A first end of the second plate connecting bar 84-2 is connected to the first plate connecting bar 84-1, and a second end of the second plate connecting bar 84-2 is connected to the second power line 37. Since the first plate connecting bar 84-1 is connected to the fourth plate 84, the fourth plate 84 is connected to the second power line 37, and the fourth plate 84 has the potential of the second power line 37.

[0171] In an exemplary embodiment, in at least one circuit unit, the second power line 37 , the fourth electrode plate 84 , the first electrode plate connecting bar 84 - 1 , and the second electrode plate connecting bar 84 - 2 may be an integrated structure connected to each other.

[0172] In an exemplary embodiment, the second conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the second conductive layer in the Nth cell column and the second conductive layer in the N+1th cell column may be mirror-symmetric with respect to a column boundary. For another example, the second conductive layer in the N+1th cell column and the second conductive layer in the N+2th cell column may be mirror-symmetric with respect to a column boundary. For another example, the second conductive layer in the N-1th cell column and the second conductive layer in the Nth cell column may be mirror-symmetric with respect to a column boundary.

[0173] In an exemplary embodiment, the second conductive layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the second conductive layer in the Mth cell row and the second conductive layer in the M+1th cell row may be mirror-symmetric with respect to a row boundary. For another example, the second conductive layer in the M+1th cell row and the second conductive layer in the M+2th cell row may be mirror-symmetric with respect to a row boundary. For another example, the second conductive layer in the M-1th cell row and the second conductive layer in the Mth cell row may be mirror-symmetric with respect to a column boundary.

[0174] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the second conductive layer, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the second semiconductor layer in FIG8A .

[0175] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least: a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a seventh active layer 17 of a seventh transistor T7, a ninth active layer 19 of a ninth transistor T9, and a tenth active layer 20 of a tenth transistor T10. The first active layer 11, the second active layer 12, and the seventh active layer 17 may be an integral structure connected to each other, and the ninth active layer 19 and the tenth active layer 20 are separately provided.

[0176] In exemplary embodiments, the first active layer 11 , the second active layer 12 , the seventh active layer 17 , and the tenth active layer 20 may have stripe shapes extending along the second direction Y, and the ninth active layer 19 may have a zigzag shape.

[0177] In an exemplary embodiment, in the first direction X, the seventh active layer 17 in the Nth unit column can be located on one side of the first active layer 11 in the present circuit unit in the first direction X, and the seventh active layer 17 in the N+1th unit column can be located on the side opposite to the first direction X of the first active layer 11 in the present circuit unit.

[0178] In an exemplary embodiment, in the second direction Y, the second active layer 12, the ninth active layer 19, and the tenth active layer 20 in the Mth cell row may be located on a side of the first active layer 11 in the circuit unit opposite to the second direction Y, and the second active layer 12, the ninth active layer 19, and the tenth active layer 20 in the M+1th cell row may be located on a side of the first active layer 11 in the circuit unit in the second direction Y. The ninth active layer 19 may be located on a side of the second active layer 12 away from the first active layer 11, and the tenth active layer 20 may be located on a side of the ninth active layer 19 away from the first active layer 11.

[0179] In example embodiments, the first active layer 11 , the second active layer 12 , the seventh active layer 17 , the ninth active layer 19 , and the tenth active layer 20 may each include a first region, a second region, and a channel region between the first and second regions.

[0180] In an exemplary embodiment, the second region 12-2 of the second active layer, the second region 17-2 of the seventh active layer, the first region 19-1 of the ninth active layer, the second region 19-2 of the ninth active layer, the first region 20-1 of the tenth active layer, and the second region 20-2 of the tenth active layer may be separately provided, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the first region 11-2 of the first active layer and the first region 17-1 of the seventh active layer may be connected to each other, that is, the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer, and the first region 11-2 of the first active layer may serve as the first region 17-1 of the seventh active layer.

[0181] In an exemplary embodiment, in a cell column, the first active layers of two partially adjacent circuit cells may be interconnected as an integrated structure, and the seventh active layers of two partially adjacent circuit cells may be interconnected as an integrated structure. For example, the first region of the first active layer and the seventh active layer of the Mth cell row may be interconnected with the first region of the first active layer and the seventh active layer of the Mth cell row. For another example, the first region of the first active layer and the seventh active layer of the M+2th cell row may be interconnected with the first region of the first active layer and the seventh active layer of the M+3th cell row. The first region of the first active layer and the seventh active layer of the M-2th cell row may be interconnected with the first region of the first active layer and the seventh active layer of the M-1th cell row. Since the first regions of the first active layer and the seventh active layer in each circuit unit are configured to be connected to the initial signal line, by forming the first active layers and the seventh active layers of adjacent circuit units into an integrated structure that is interconnected, two unit rows can share one initial signal line. This not only reduces one initial signal line and the corresponding via, thus reducing the area occupied by the pixel driving circuit and improving resolution, but also ensures that the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7 in adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0182] In an exemplary embodiment, the orthographic projection of the ninth active layer 19 on the substrate at least partially overlaps with the orthographic projection of the blocking block 44 on the substrate, so that the blocking block 44 can block the channel region of the ninth active layer 19 and at the same time serve as the bottom gate electrode of the ninth transistor T9.

[0183] In an exemplary embodiment, the orthographic projection of the ninth active layer 19 on the substrate at least partially overlaps with the orthographic projection of the eighth active layer 18 on the substrate, so that the eighth transistor T8 and the ninth transistor T9 form a transistor stack structure, and the ninth transistor T9 is located on the side of the eighth transistor T8 away from the substrate, which can effectively reduce the occupied area of ​​the pixel driving circuit and is conducive to improving the resolution.

[0184] In an exemplary embodiment, the ninth active layer 19 may include a third subsegment 19A, a fourth subsegment 19B, and a fifth subsegment 19C connected in sequence. The third subsegment 19A and the fifth subsegment 19C may be strip-shaped extending along the second direction Y, and the fourth subsegment 19B may be strip-shaped extending along the first direction X. A first end of the third subsegment 19A is located on a side of the first electrode plate 81 away from the first scan line 31. A second end of the third subsegment 19A extends away from the first electrode plate 81 along the second direction Y and is connected to a first end of the fourth subsegment 19B. A second end of the fourth subsegment 19B extends away from the third subsegment 19A along the first direction X and is connected to a first end of the fifth subsegment 19C. A second end of the fifth subsegment 19C extends away from the first electrode plate 81 along the second direction Y. In an exemplary embodiment, the first end of the third subsegment 19A may serve as the second region of the ninth active layer, the second end of the fifth subsegment 19C may serve as the first region of the ninth active layer, and the channel region of the ninth active layer may be located in the fourth subsegment 19B.

[0185] In an exemplary embodiment, the orthographic projection of the third subsegment 19A of the ninth active layer 19 on the substrate at least partially overlaps with the orthographic projection of the first subsegment 18A of the eighth active layer 18 on the substrate, and the orthographic projection of the fourth subsegment 19B of the ninth active layer 19 on the substrate at least partially overlaps with the orthographic projection of the second subsegment 18B of the eighth active layer 18 on the substrate.

[0186] In an exemplary embodiment, the orthographic projection of the third subsegment 19A of the ninth active layer 19 on the substrate may be within the range of the orthographic projection of the first subsegment 18A of the eighth active layer 18 on the substrate, and the orthographic projection of the fourth subsegment 19B of the ninth active layer 19 on the substrate may be within the range of the orthographic projection of the second subsegment 18B of the eighth active layer 18 on the substrate.

[0187] In example embodiments, a first width of the third subsegment 19A of the ninth active layer 19 may be substantially the same as a first width of the first subsegment 18A of the eighth active layer 18 , and the first width may be a dimension in the first direction X.

[0188] In example embodiments, a first extension length of the third subsegment 19A of the ninth active layer 19 may be smaller than a first extension length of the first subsegment 18A of the eighth active layer 18 , and the first extension length may be a dimension in the second direction Y.

[0189] In example embodiments, the second width of the fourth subsegment 19B of the ninth active layer 19 may be substantially the same as the second width of the second subsegment 18B of the eighth active layer 18 , and the second width may be a dimension in the second direction Y.

[0190] In example embodiments, the second extension length of the fourth subsegment 19B of the ninth active layer 19 may be smaller than the second extension length of the second subsegment 18B of the eighth active layer 18 , and the second extension length may be a dimension in the first direction X.

[0191] In an exemplary embodiment, the second semiconductor layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the second semiconductor layer in the Nth cell column and the second semiconductor layer in the N+1th cell column may be mirror-symmetric with respect to a column boundary. For another example, the second semiconductor layer in the N+1th cell column and the second semiconductor layer in the N+2th cell column may be mirror-symmetric with respect to a column boundary. For another example, the second semiconductor layer in the N-1th cell column and the second semiconductor layer in the Nth cell column may be mirror-symmetric with respect to a column boundary.

[0192] In an exemplary embodiment, the second semiconductor layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the second semiconductor layer in the Mth cell row and the second semiconductor layer in the M+1th cell row may be mirror-symmetric with respect to a row boundary. For another example, the second semiconductor layer in the M+1th cell row and the second semiconductor layer in the M+2th cell row may be mirror-symmetric with respect to a row boundary. For another example, the second semiconductor layer in the M-1th cell row and the second semiconductor layer in the Mth cell row may be mirror-symmetric with respect to a column boundary.

[0193] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the eighth transistor T8 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0194] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a plan view schematic diagram of the third conductive layer in FIG9A . In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0195] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a ninth gate electrode 29 , a second scan signal line 32 , a third scan signal line 33 , and a fourth scan signal line 34 .

[0196] In an exemplary embodiment, the ninth gate electrode 29 may be in the shape of a strip extending along the second direction Y. The orthographic projection of the ninth gate electrode 29 on the substrate at least partially overlaps with the orthographic projection of the ninth active layer on the substrate. The overlapping region of the ninth gate electrode 29 and the ninth active layer may serve as the gate electrode of the ninth transistor T9. In an exemplary embodiment, the ninth gate electrode 29 is configured to be connected to a seventh connection electrode formed subsequently.

[0197] In an exemplary embodiment, the orthographic projection of the ninth gate electrode 29 on the substrate at least partially overlaps with the orthographic projection of the shielding block 44 on the substrate. In an exemplary embodiment, the ninth gate electrode 29 can be connected to the shielding block 44 via a seventh connecting electrode formed subsequently, so that the shielding block 44 can serve as the bottom gate electrode of the ninth transistor T9, and the ninth gate electrode 29 can serve as the top gate electrode of the ninth transistor T9, forming the ninth transistor T9 with a top-gate and bottom-gate structure.

[0198] In an exemplary embodiment, the orthographic projection of the ninth gate electrode 29 on the substrate at least partially overlaps with the orthographic projection of the eighth gate electrode 28 on the substrate, and the orthographic projection of the channel region of the ninth transistor T9 on the substrate at least partially overlaps with the orthographic projection of the channel region of the eighth transistor T8 on the substrate, so that the eighth transistor T8 and the ninth transistor T9 form a transistor stack structure, and the ninth transistor T9 is located on the side of the eighth transistor T8 away from the substrate, which effectively reduces the occupied area of ​​the pixel driving circuit and is conducive to improving the resolution.

[0199] In an exemplary embodiment, the second scan signal line 32 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The region where the second scan signal line 32 overlaps with the second active layer may serve as the gate electrode of the second transistor T2. In an exemplary embodiment, the position of the second scan signal line 32 corresponds to the position of the second shielding line 42, and the orthographic projection of the second scan signal line 32 on the substrate at least partially overlaps the orthographic projection of the second shielding line 42 on the substrate.

[0200] In an exemplary embodiment, the second scanning signal line 32 and the second shielding line 42 can be connected to the same signal source, so that the second shielding line 42 can serve as the bottom gate electrode of the second transistor T2, and the second scanning signal line 32 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.

[0201] In an exemplary embodiment, the position of the second scan signal line 32 corresponds to the position of the first scan signal line 31, and the orthographic projection of the second scan signal line 32 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 31 on the substrate, so that the first scan signal line 31 and the second scan signal line 32 form a signal line stack structure. The second scan signal line 32 is located on the side of the first scan signal line 31 away from the substrate, which can effectively reduce the occupied area of ​​the pixel driving circuit and is conducive to improving the resolution.

[0202] In an exemplary embodiment, the third scan signal line 33 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The region where the third scan signal line 33 overlaps with the tenth active layer may serve as the gate electrode of the tenth transistor T10. In an exemplary embodiment, the position of the third scan signal line 33 corresponds to the position of the third shielding line 43, and the orthographic projection of the third scan signal line 33 on the substrate at least partially overlaps the orthographic projection of the third shielding line 43 on the substrate.

[0203] In an exemplary embodiment, the third scanning signal line 33 and the third shielding line 43 can be connected to the same signal source, so that the third shielding line 43 can serve as the bottom gate electrode of the tenth transistor T10, and the third scanning signal line 33 can serve as the top gate electrode of the tenth transistor T10, forming the tenth transistor T10 with a top-gate and bottom-gate structure.

[0204] In an exemplary embodiment, the position of the third scanning signal line 33 corresponds to the position of the light-emitting signal line 35, and the orthographic projection of the third scanning signal line 33 on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line 35 on the substrate, so that the third scanning signal line 33 and the light-emitting signal line 35 form a signal line stack structure. The third scanning signal line 33 is located on the side of the light-emitting signal line 35 away from the substrate, which can effectively reduce the occupied area of ​​the pixel driving circuit and is conducive to improving the resolution.

[0205] In an exemplary embodiment, the fourth scan signal line 34 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The regions where the fourth scan signal line 34 overlaps with the first active layer and the seventh active layer may serve as the gate electrode of the first transistor T1 and the gate electrode of the seventh transistor T7, respectively. In an exemplary embodiment, the position of the fourth scan signal line 34 corresponds to the position of the first shielding line 41, and the orthographic projection of the fourth scan signal line 34 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 41 on the substrate.

[0206] In an exemplary embodiment, the fourth scanning signal line 34 and the first shielding line 41 can be connected to the same signal source, so that the first shielding line 41 can serve as the bottom gate electrode of the first transistor T1 and the bottom gate electrode of the seventh transistor T7, respectively, and the fourth scanning signal line 34 can serve as the top gate electrode of the first transistor T1 and the top gate electrode of the seventh transistor T7, respectively, forming the first transistor T1 and the seventh transistor T7 with a top-gate and bottom-gate structure.

[0207] In an exemplary embodiment, the third scan signal line 33 and the fourth scan signal line 34 may be connected to the same signal source and may synchronously control the on and off of the first transistor T1 , the seventh transistor T7 , and the tenth transistor T10 .

[0208] In an exemplary embodiment, the third conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the third conductive layer in the Nth cell column and the third conductive layer in the N+1th cell column may be mirror-symmetric with respect to a column boundary. For another example, the third conductive layer in the N+1th cell column and the third conductive layer in the N+2th cell column may be mirror-symmetric with respect to a column boundary. For another example, the third conductive layer in the N-1th cell column and the third conductive layer in the Nth cell column may be mirror-symmetric with respect to a column boundary.

[0209] In an exemplary embodiment, the third conductive layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the third conductive layer in the Mth cell row and the third conductive layer in the M+1th cell row may be mirror-symmetric with respect to a row boundary. For another example, the third conductive layer in the M+1th cell row and the third conductive layer in the M+2th cell row may be mirror-symmetric with respect to a row boundary. For another example, the third conductive layer in the M-1th cell row and the third conductive layer in the Mth cell row may be mirror-symmetric with respect to a column boundary.

[0210] (6) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 10 .

[0211] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21 and a twenty-second via V22.

[0212] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer (also the first region of the seventh active layer) on the substrate, the sixth insulating layer and the fifth insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed third connecting electrode to the first region of the first active layer (also the first region of the seventh active layer) through the via hole.

[0213] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the sixth insulating layer and the fifth insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect the subsequently formed first connecting electrode to the second region of the first active layer (also the first region of the second active layer) through the via hole.

[0214] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the second region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0215] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first opening 81-1 of the first electrode 81 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fourth via hole V4 are etched away to expose the surface of the second region of the third active layer (which is also the first region of the sixth active layer). The fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the third active layer (which is also the first region of the sixth active layer) through the via hole.

[0216] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of ​​the fourth active layer. The fifth via hole V5 is configured to connect a subsequently formed data signal line to the first area of ​​the fourth active layer through the via hole.

[0217] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via hole V6 are etched away to expose the surface of the first region of the fifth active layer. The sixth via hole V6 is configured to connect a subsequently formed fourth connecting electrode to the first region of the fifth active layer through the via hole.

[0218] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second region of the sixth active layer, and the seventh via hole V7 is configured to connect the subsequently formed fifth connecting electrode to the second region of the sixth active layer through the via hole.

[0219] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second region of the seventh active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the eighth via V8 are etched away to expose the surface of the second region of the seventh active layer, and the eighth via V8 is configured to connect a subsequently formed fifth connecting electrode to the second region of the seventh active layer through the via.

[0220] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first region of the eighth active layer. The ninth via V9 is configured to connect a subsequently formed high-frequency signal line to the first region of the eighth active layer through the via.

[0221] In an exemplary embodiment, since the first regions of the eighth active layers of some adjacent circuit units in one cell row are connected to each other, some adjacent circuit units in one cell row may share one ninth via hole V9 .

[0222] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via hole V10 are etched away to expose the surface of the second region of the eighth active layer, and the tenth via hole V10 is configured to connect a subsequently formed sixth connecting electrode to the second region of the eighth active layer through the via hole.

[0223] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the eleventh via hole V11 are etched away to expose the surface of the first region of the ninth active layer, and the eleventh via hole V11 is configured to connect the subsequently formed eighth connecting electrode to the first region of the ninth active layer through the via hole.

[0224] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the ninth active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the ninth active layer, and the twelfth via hole V12 is configured to connect the subsequently formed sixth connecting electrode to the second region of the ninth active layer through the via hole.

[0225] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first region of the tenth active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first region of the tenth active layer, and the thirteenth via hole V13 is configured to connect a subsequently formed data signal line to the first region of the tenth active layer through the via hole.

[0226] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second region of the tenth active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the second region of the tenth active layer, and the fourteenth via hole V14 is configured to connect the subsequently formed seventh connecting electrode to the second region of the tenth active layer through the via hole.

[0227] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second opening 83-1 of the third electrode 83 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first electrode 81. The fifteenth via hole V15 is configured to connect the subsequently formed first connecting electrode to the first electrode 81 through the via hole.

[0228] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the sixth gate electrode 26, and the sixteenth via hole V16 is configured to connect the subsequently formed sixth connecting electrode to the sixth gate electrode 26 through the via hole.

[0229] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the eighth gate electrode 28 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the eighth gate electrode 28, and the seventeenth via hole V17 is configured to connect the subsequently formed seventh connecting electrode to the eighth gate electrode 28 through the via hole.

[0230] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the initial signal line 45 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the initial signal line 45, and the eighteenth via hole V18 is configured to connect the subsequently formed third connecting electrode to the initial signal line 45 through the via hole.

[0231] In an exemplary embodiment, since adjacent circuit units in one unit column share one initial signal line 45 , adjacent circuit units in one unit column may share one first via hole V1 and one eighteenth via hole V18 .

[0232] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the first power line 36 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the nineteenth via V19 are etched away to expose the surface of the first power line 36, and the nineteenth via V19 is configured to connect the subsequently formed fourth connecting electrode to the first power line 36 through the via.

[0233] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the light-emitting connection block 35-1 of the light-emitting signal line 35 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the twentieth via hole V20 are etched away to expose the surface of the light-emitting connection block 35-1, and the twentieth via hole V20 is configured to connect the subsequently formed eighth connection electrode to the light-emitting connection block 35-1 through the via hole.

[0234] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the ninth gate electrode 29 on the substrate, the sixth insulating layer in the twenty-first via V21 is etched away to expose the surface of the ninth gate electrode 29, and the twenty-first via V21 is configured to connect the subsequently formed seventh connecting electrode to the ninth gate electrode 29 through the via.

[0235] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the blocking block 44 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the twenty-second via hole V22 are etched away to expose the surface of the blocking block 44, and the twenty-second via hole V22 is configured to connect the subsequently formed seventh connecting electrode to the blocking block 44 through the via hole.

[0236] In an exemplary embodiment, this patterning process may include two patterning processes, and the two patterning processes may be an ILD-L MASK and an ILD-O MASK, respectively.

[0237] In an exemplary embodiment, the vias in adjacent unit columns may be mirror-symmetric with respect to the column boundary. For example, the vias in the Nth unit column and the vias in the N+1th unit column may be mirror-symmetric with respect to the column boundary. For another example, the vias in the N+1th unit column and the vias in the N+2th unit column may be mirror-symmetric with respect to the column boundary. For another example, the vias in the N-1th unit column and the vias in the Nth unit column may be mirror-symmetric with respect to the column boundary.

[0238] In an exemplary embodiment, the vias in adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the vias in the Mth cell row and the vias in the M+1th cell row may be mirror-symmetric with respect to a row boundary. For another example, the vias in the M+1th cell row and the vias in the M+2th cell row may be mirror-symmetric with respect to a row boundary. For another example, the vias in the M-1th cell row and the vias in the Mth cell row may be mirror-symmetric with respect to a column boundary.

[0239] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 11A and FIG. 11B , where FIG. 11B is a plan view schematic diagram of the fourth conductive layer in FIG. 11A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0240] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58, a data signal line 61 and a high-frequency signal line 62.

[0241] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the first connection electrode 51 is connected to the first region of the second active layer (also the second region of the first active layer) via a second via hole V1, and a second end of the first connection electrode 51 is connected to the first electrode plate 81 via a fifteenth via hole V15. In an exemplary embodiment, because the first electrode plate 81 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 81 to have the same potential, thereby forming a first node N1 of the pixel driving circuit.

[0242] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the second connection electrode 52 is connected to the second region of the second active layer via a third via hole V3, and a second end of the second connection electrode 52 is connected to the second region of the third active layer (also the first region of the sixth active layer) via a fourth via hole V4. In an exemplary embodiment, the second connection electrode 52 causes the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0243] In an exemplary embodiment, the third connection electrode 53 may be in the shape of a strip with a main portion extending along the first direction X. A first end of the third connection electrode 53 is connected to the first region of the first active layer (also the first region of the seventh active layer) via a first via hole V1, and a second end of the third connection electrode 53 is connected to the initial signal line 45 via an eighteenth via hole V18. In an exemplary embodiment, the third connection electrode 53 enables the initial signal line 45 to simultaneously write the initial signal into the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7.

[0244] In an exemplary embodiment, the fourth connection electrode 54 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer via a sixth via hole V6, and a second end of the fourth connection electrode 54 is connected to the first power line 36 via a nineteenth via hole V19. In an exemplary embodiment, the fourth connection electrode 54 enables the first power line 36 to write the first power signal to the first electrode of the fifth transistor T5.

[0245] In an exemplary embodiment, the fifth connection electrode 55 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the fifth connection electrode 55 is connected to the second region of the sixth active layer via a seventh via hole V7, and a second end of the fifth connection electrode 55 is connected to the second region of the seventh active layer via an eighth via hole V8. In an exemplary embodiment, the fifth connection electrode 55 ensures that the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 have the same potential, forming a fourth node N4 of the pixel driving circuit.

[0246] In an exemplary embodiment, the sixth connection electrode 56 may be L-shaped. A first end of the sixth connection electrode 56 is connected to the second region of the ninth active layer via a twelfth via hole V12. A second end of the sixth connection electrode 56 is connected to the sixth gate electrode 26 via a sixteenth via hole V16. The region between the first and second ends is connected to the second region of the eighth active layer via a tenth via hole V10. In an exemplary embodiment, the sixth connection electrode 56 connects the gate electrode of the sixth transistor T6, the second electrode of the eighth transistor T8, and the second electrode of the ninth transistor T9, forming the fifth node N5 of the pixel driving circuit. In this disclosure, the sixth connection electrode 56 may be referred to as an interconnection electrode.

[0247] In an exemplary embodiment, the seventh connection electrode 57 may be in a block shape (e.g., a rectangle). A first end of the seventh connection electrode 57 is connected to the second region of the tenth active layer via a fourteenth via hole V14. A second end of the seventh connection electrode 57 is connected to the eighth gate electrode 28 via a seventeenth via hole V17. A third end of the seventh connection electrode 57 is connected to the ninth gate electrode 29 via a twenty-first via hole V21. A fourth end of the seventh connection electrode 57 is connected to the shielding block 44 via a twenty-second via hole V22. In an exemplary embodiment, because the eighth gate electrode 28 is connected to the second electrode plate 82, the seventh connection electrode 57 interconnects the gate electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9 (including the top gate electrode and the bottom gate electrode), the second electrode of the tenth transistor T10, and the second electrode plate 82 of the first capacitor, thereby forming a sixth node N6 of the pixel driving circuit.

[0248] In an exemplary embodiment, the eighth connection electrode 58 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the eighth connection electrode 58 is connected to the first region of the ninth active layer via an eleventh via hole V11, and a second end of the eighth connection electrode 58 is connected to the light-emitting connection block 35-1 via a twentieth via hole V20. In an exemplary embodiment, since the light-emitting connection block 35-1 is connected to the light-emitting signal line 35, the eighth connection electrode 58 enables the light-emitting signal line 35 to write a light-emitting signal to the first electrode of the ninth transistor T9. In this disclosure, the eighth connection electrode 58 may be referred to as an interconnection electrode.

[0249] In an exemplary embodiment, the shape of the data signal line 61 can be a straight line or a broken line with the main part extending along the second direction Y. On the one hand, the data signal line 61 is connected to the first area of ​​the fourth active layer through the fifth via V5, and on the other hand, it is connected to the first area of ​​the tenth active layer through the thirteenth via V13, so that the data signal line 61 can write the data signal into the first electrode of the fourth transistor T4 and the first electrode of the tenth transistor T10 respectively.

[0250] In an exemplary embodiment, the shape of the high-frequency signal line 62 can be a straight line or a broken line with the main part extending along the second direction Y. The high-frequency signal line 62 is connected to the first area of ​​the eighth active layer through the ninth via V9, so that the high-frequency signal line 62 can write the high-frequency signal into the first electrode of the eighth transistor T8.

[0251] In an exemplary embodiment, since the first regions of the eighth active layers of some adjacent circuit units in a unit row are interconnected, some adjacent circuit units can share a high-frequency signal line 62. One high-frequency signal line 62 can simultaneously provide high-frequency signals to pixel driving circuits in two unit columns, thereby reducing one high-frequency signal line and the corresponding via, reducing the occupied area of ​​the pixel driving circuit, and improving the resolution.

[0252] In an exemplary embodiment, the first connection electrode 51 allows the first plate 81 to have the potential of the first node N1 of the pixel driving circuit, and the third plate 83 to have the potential of the first power line 36, so that the first plate 81 and the third plate 83 constitute a storage capacitor of the pixel driving circuit.

[0253] In an exemplary embodiment, the seventh connection electrode 57 allows the second plate 82 to have the potential of the sixth node N6 of the pixel driving circuit and the fourth plate 84 to have the potential of the second power line 37 , so that the second plate 82 and the fourth plate 84 constitute a first capacitor of the pixel driving circuit.

[0254] In an exemplary embodiment, the fourth conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the fourth conductive layer in the Nth cell column and the fourth conductive layer in the N+1th cell column may be mirror-symmetric with respect to a column boundary. For another example, the fourth conductive layer in the N+1th cell column and the fourth conductive layer in the N+2th cell column may be mirror-symmetric with respect to a column boundary. For another example, the fourth conductive layer in the N-1th cell column and the fourth conductive layer in the Nth cell column may be mirror-symmetric with respect to a column boundary.

[0255] In an exemplary embodiment, the fourth conductive layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the fourth conductive layer in the Mth cell row and the fourth conductive layer in the M+1th cell row may be mirror-symmetric with respect to a row boundary. For another example, the fourth conductive layer in the M+1th cell row and the fourth conductive layer in the M+2th cell row may be mirror-symmetric with respect to a row boundary. For another example, the fourth conductive layer in the M-1th cell row and the fourth conductive layer in the Mth cell row may be mirror-symmetric with respect to a column boundary.

[0256] In an exemplary embodiment, the subsequent fabrication process may include: forming a first planar layer and a seventh insulating layer, each provided with a plurality of vias; forming a fifth conductive layer, which may be referred to as a second source / drain metal (SD2) layer, wherein the fifth conductive layer of each circuit unit may include at least a first pad electrode and a second pad electrode; forming a second planar layer and an eighth insulating layer, each provided with a first binding hole and a second binding hole, wherein the first binding hole exposes the first pad electrode, and the second binding hole exposes the second pad electrode.

[0257] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a light-emitting signal line, an initial signal line, a data signal line, a high-frequency signal line, a first power line, and a second power line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planar layer, a seventh insulating layer, a fifth conductive layer, a second planar layer, and an eighth insulating layer, which are sequentially arranged on the substrate. The first semiconductor layer may include at least an active layer of multiple polysilicon transistors, the first conductive layer may include at least a first scanning signal line, a light-emitting signal line, a first plate of a storage capacitor and a second plate of a first capacitor, the second conductive layer may include at least a third plate of a storage capacitor, a fourth plate of a first capacitor, a second power line, an initial signal line and multiple shielding lines, the second semiconductor layer may include at least an active layer of multiple oxide transistors, the third conductive layer may include at least a second scanning signal line, a third scanning signal line and a fourth scanning signal line, the fourth conductive layer may include at least a data signal line, a high-frequency signal line and multiple connecting electrodes, and the fifth conductive layer may include at least a first pad electrode and a second pad electrode.

[0258] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0259] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, the seventh insulating layer, and the eighth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The first planarizing layer and the second planarizing layer can be made of an organic material, such as a resin.

[0260] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in a unit row may be substantially mirror-symmetrical with respect to a column boundary. For example, the pixel driving circuit in the Nth unit column and the pixel driving circuit in the N+1th unit column may be mirror-symmetrical with respect to a column boundary.

[0261] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in a unit column may be substantially mirror-symmetrical with respect to a row boundary. For example, the pixel driving circuit in the Mth unit row and the pixel driving circuit in the M+1th unit row may be mirror-symmetrical with respect to the row boundary.

[0262] In an exemplary embodiment, after the driving circuit layer is prepared, a light-emitting structure layer is prepared on the driving circuit layer. In an exemplary embodiment, the preparation process of the light-emitting structure layer may include: first using a dispensing machine to add binding material (such as solder paste) into multiple first binding holes and multiple second binding holes, and then using a transfer die bonding process to bind the first poles of the multiple light-emitting diodes to the first pad electrodes through the first binding holes, and to bind the second poles of the multiple light-emitting diodes to the second pad electrodes through the second binding holes, thereby completing the connection between the light-emitting diodes and the corresponding pixel driving circuits. Subsequently, a covering film is coated on the substrate forming the aforementioned structure to form a covering layer, and the covering layer covers the multiple light-emitting diodes. In an exemplary embodiment, the multiple light-emitting diodes and the covering layer may constitute the light-emitting structure layer.

[0263] FIG12 is a cross-sectional view taken along the AA line in FIG11A, illustrating the film layer structure of the region where the eighth transistor T8 and the ninth transistor T9 are located. As shown in FIG12 , in a plane perpendicular to the display substrate, the display substrate may include:

[0264] A first insulating layer 91 is provided on the substrate 10;

[0265] A first semiconductor layer provided on a side of the first insulating layer 91 away from the substrate 10 , wherein the first semiconductor layer may include at least an eighth active layer 18 of the eighth transistor T8 ;

[0266] A second insulating layer 92 disposed on a side of the first semiconductor layer away from the substrate 10;

[0267] A first conductive layer (GATE1) provided on a side of the second insulating layer 92 away from the substrate 10, the first conductive layer may include at least the eighth gate electrode 28 of the eighth transistor T8, the light emitting signal line 35 and the second plate 82;

[0268] A third insulating layer 93 provided on a side of the first conductive layer away from the substrate 10;

[0269] A second conductive layer (GATE2) is provided on a side of the third insulating layer 93 away from the substrate 10. The second conductive layer may include at least a second power line 37, a third shielding line 43, a shielding block 44, and a fourth electrode plate 84. The orthographic projection of the fourth electrode plate 84 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 82 on the substrate. The second electrode plate 82 and the fourth electrode plate 84 constitute a first capacitor of the pixel driving circuit.

[0270] A fourth insulating layer 94 provided on a side of the second conductive layer away from the substrate 10;

[0271] a second semiconductor layer disposed on a side of the fourth insulating layer 94 away from the substrate 10 , the second semiconductor layer may include at least a ninth active layer 19 of the ninth transistor T9 , an orthographic projection of the ninth active layer 19 on the substrate at least partially overlapping with an orthographic projection of the eighth active layer 18 on the substrate;

[0272] A fifth insulating layer 95 disposed on a side of the second semiconductor layer away from the substrate 10;

[0273] a third conductive layer (GATE3) disposed on a side of the fifth insulating layer 95 away from the substrate 10, the third conductive layer may include at least a ninth gate electrode 29 of the ninth transistor T9 and a third scan signal line 33, an orthographic projection of the ninth gate electrode 29 on the substrate at least partially overlapping with an orthographic projection of the eighth gate electrode 28 on the substrate, and an orthographic projection of the third scan signal line 33 on the substrate at least partially overlapping with an orthographic projection of the light-emitting signal line 35 on the substrate;

[0274] a sixth insulating layer 96 disposed on a side of the third conductive layer away from the substrate 10;

[0275] The fourth conductive layer (SD1) is disposed on the side of the sixth insulating layer 96 away from the substrate 10. The fourth conductive layer may include at least a sixth connecting electrode 56 and an eighth connecting electrode 58 serving as interconnect electrodes. One end of the sixth connecting electrode 56 is connected to the eighth active layer 18 via a tenth via V10, and the other end of the sixth connecting electrode 56 is connected to the ninth active layer 19 via a twelfth via V12, forming the fifth node of the interconnect structure. One end of the eighth connecting electrode 58 is connected to the ninth active layer via an eleventh via V11, and the other end of the eighth connecting electrode 58 is connected to the light-emitting signal line 35 via a twentieth via V20, enabling the light-emitting signal line 35 to write the light-emitting signal to the ninth transistor T9.

[0276] At present, due to the complexity of the pixel driving circuit of Micro LED display / Mini LED display, more transistors occupy a larger area, which limits the improvement of resolution (Pixels Per Inch, referred to as PPI). The display substrate provided by the exemplary embodiment of the present disclosure effectively reduces the occupied area of ​​the pixel driving circuit and effectively improves the resolution by setting the eighth transistor and the ninth transistor into a transistor stacking structure, setting the first scan signal line and the second scan signal line into a signal line stacking structure, and setting the third scan signal line and the light-emitting signal line into a signal line stacking structure. The ninth transistor is set on the side of the eighth transistor away from the substrate, which not only overlaps the gate electrodes of the two transistors and saves the area of ​​the gate electrode, but also facilitates the connection and sharing of the two transistors, reducing the area of ​​the connecting electrode. The display substrate provided by the present disclosure effectively improves the resolution under the same pixel driving circuit. Compared with the existing structure of about 240PPI, the display substrate of the present disclosure can be improved to about 326PPI.

[0277] The exemplary embodiment of the present disclosure adopts a horizontal mirror image and a vertical mirror image structure of the pixel driving circuit, so that two adjacent unit rows share an initial signal line and two adjacent unit columns share a high-frequency signal line. This not only reduces the number of signal lines, but also reduces the corresponding via connection structure, effectively reducing the occupied area of ​​the pixel driving circuit and maximizing the resolution.

[0278] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0279] It should be noted that the structure and preparation process shown in the exemplary embodiment of the present disclosure are merely exemplary. The corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the fourth transistor and the second transistor can be arranged into a transistor stack structure, and the second transistor can be arranged on the side of the fourth transistor away from the substrate. For another example, the fifth transistor and the tenth transistor can be arranged into a transistor stack structure, and the tenth transistor can be arranged on the side of the fifth transistor away from the substrate. The embodiments of the present disclosure are not specifically limited here.

[0280] Figures 13A and 13B are schematic diagrams of another display substrate structure according to an exemplary embodiment of the present disclosure. Figure 13A is a cross-sectional view taken along line AA in Figure 11A, illustrating the film structure in the region where the eighth transistor T8 and the ninth transistor T9 are located. Figure 13B is a cross-sectional view taken along line BB in Figure 11A, illustrating the film structure in the region where the first scan signal line 31 and the second scan signal line 32 are located. The main structure of the display substrate in this embodiment is substantially the same as that in the embodiment shown in Figure 12, except that the display substrate in this embodiment further includes a shielding layer and a shielding insulating layer.

[0281] As shown in Figures 13A and 13B, in a plane perpendicular to the display substrate, the display substrate may include a first insulating layer 91, a first semiconductor layer, a second insulating layer 92, a first conductive layer, a third insulating layer 93, a shielding layer, a shielding insulating layer 97, a second conductive layer, a fourth insulating layer 94, a second semiconductor layer, a fifth insulating layer 95, a third conductive layer, a sixth insulating layer 96 and a fourth conductive layer arranged in sequence on a base, wherein the structures of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer and the fourth conductive layer are substantially the same as those in the aforementioned embodiment.

[0282] In an exemplary embodiment, the shielding layer may be disposed between the first conductive layer and the second conductive layer.

[0283] In an exemplary embodiment, the shielding layer may be disposed on a side of the third insulating layer 93 away from the substrate 10, and the shielding layer may include at least a first shielding line 38 and a second shielding line 39. The shielding insulating layer 97 may be disposed on a side of the shielding layer away from the substrate 10, and the second conductive layer may be disposed on a side of the shielding insulating layer away from the substrate 10.

[0284] As shown in Figure 13A, in an exemplary embodiment, in a direction perpendicular to the display substrate, the first shielding line 38 can be arranged between the third scanning signal line 33 and the light-emitting signal line 35, and the shape of the first shielding line 38 can be a straight line or a broken line with the main part extending along the first direction X. The position of the first shielding line 38 can correspond to the position of the light-emitting signal line 35 and the third scanning signal line 33, and the orthographic projection of the first shielding line 38 on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line 35 on the substrate, and the orthographic projection of the first shielding line 38 on the substrate at least partially overlaps with the orthographic projection of the third scanning signal line 33 on the substrate.

[0285] In an exemplary embodiment, the orthographic projection of the light-emitting signal line 35 (excluding the light-emitting connection block portion) on the substrate can be within the range of the orthographic projection of the first shielding line 38 on the substrate, and the orthographic projection of the third scanning signal line 33 on the substrate can be within the range of the orthographic projection of the first shielding line 38 on the substrate.

[0286] As shown in Figure 13B, in an exemplary embodiment, in a direction perpendicular to the display substrate, the second shielding line 39 can be arranged between the first scanning signal line 31 and the second scanning signal line 32, and the shape of the second shielding line 39 can be a straight line or a broken line with the main part extending along the first direction X. The position of the second shielding line 39 can correspond to the position of the first scanning signal line 31 and the second scanning signal line 32, and the orthographic projection of the second shielding line 39 on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line 31 on the substrate, and the orthographic projection of the second shielding line 39 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 32 on the substrate.

[0287] In an exemplary embodiment, the orthographic projection of the first scan signal line 31 on the substrate may be within the range of the orthographic projection of the second shielding line 39 on the substrate, and the orthographic projection of the second scan signal line 32 on the substrate may be within the range of the orthographic projection of the second shielding line 39 on the substrate.

[0288] In an exemplary embodiment, the first shielding line and the second shielding line 39 may be connected to the first power line, or may be connected to the second power line, or may be connected to a ground signal, which is not limited in the present disclosure.

[0289] In an exemplary embodiment, the shielding layer may further be provided with other shielding structures, which is not limited in the present disclosure.

[0290] In an exemplary embodiment, the manufacturing process of the display substrate of this embodiment may include the following operations: a first insulating layer 91, a first semiconductor layer, a second insulating layer 92, and a first conductive layer (GATE1) are sequentially formed, and the manufacturing process is substantially the same as that of the previous embodiment. Subsequently, a third insulating film and a shielding film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The shielding film is patterned using a patterning process to form a third insulating layer covering the first conductive layer, and a shielding layer pattern disposed on the third insulating layer. Subsequently, a shielding insulating layer 97, a second conductive layer, a fourth insulating layer 94, a second semiconductor layer, a fifth insulating layer 95, a third conductive layer, a sixth insulating layer 96, and a fourth conductive layer are sequentially formed, and the manufacturing process is substantially the same as that of the previous embodiment.

[0291] The display substrate provided by this embodiment not only has the technical effects of the aforementioned embodiments, namely, effectively reducing the occupied area of ​​the pixel driving circuit, which is conducive to improving the resolution, but also, by providing a shielding layer, can improve the working performance of the pixel driving circuit and improve the display quality. This embodiment effectively avoids coupling between the light-emitting signal line and the third scanning signal line by providing the first shielding line between the stacked light-emitting signal line and the third scanning signal line, and reduces the mutual influence between the light-emitting signal line and the third scanning signal line. This embodiment effectively avoids coupling between the first scanning signal line and the second scanning signal line by providing the second shielding line between the stacked first scanning signal line and the second scanning signal line, and reduces the mutual influence between the first scanning signal line and the second scanning signal line. The display substrate of this embodiment can reduce the occupied area of ​​the pixel driving circuit and improve the resolution while ensuring the working performance of the pixel driving circuit and the display quality.

[0292] Figure 14 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the film layer structure in the region where the eighth transistor T8 and the ninth transistor T9 are located. The main structure of the display substrate of this embodiment is substantially the same as that of the embodiment shown in Figure 12 , except that the sixth connection electrode 56, serving as an interconnect electrode, is connected to both the eighth active layer 18 and the ninth active layer 19 through a single overlapping hole.

[0293] As shown in Figure 14, in a plane perpendicular to the display substrate, the display substrate may include a first insulating layer 91, a first semiconductor layer, a second insulating layer 92, a first conductive layer, a third insulating layer 93, a second conductive layer, a fourth insulating layer 94, a second semiconductor layer, a fifth insulating layer 95, a third conductive layer, a sixth insulating layer 96 and a fourth conductive layer arranged in sequence on a base, and the main structure of the above film layers is basically the same as that of the aforementioned embodiment.

[0294] In an exemplary embodiment, the sixth connection electrode 56 serving as an interconnecting electrode is overlapped with the first surface of the eighth active layer 18 through the overlap hole KA on the one hand, and is overlapped with the second surface of the ninth active layer 19 through the overlap hole KA on the other hand. The first surface is the surface of the eighth active layer 18 parallel to the substrate 10, and the second surface is the surface of the ninth active layer 19 intersecting with the substrate 10.

[0295] In exemplary embodiments, an angle between the second surface of the ninth active layer 19 and the substrate plane may be 50 degrees to 70 degrees.

[0296] In an exemplary embodiment, the overlapping hole KA can be set in multiple insulating layers and the second semiconductor layer, and the overlapping hole KA can penetrate the stacked second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, the second semiconductor layer, the fifth insulating layer 95 and the sixth insulating layer 96. The overlapping hole KA exposes the first surface of the eighth active layer 18 on the one hand and exposes the second surface of the ninth active layer 19 on the other hand.

[0297] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0298] (11) A first insulating layer 91, a first semiconductor layer, a second insulating layer 92, a first conductive layer (GATE1), a third insulating layer 93, a second conductive layer (GATE2), a fourth insulating layer 94, a second semiconductor layer, a fifth insulating layer 95, and a third conductive layer (GATE3) are sequentially formed, and the preparation process is substantially the same as that of the aforementioned embodiment. The first semiconductor layer may include at least the eighth active layer 18, the first conductive layer may include at least the eighth gate electrode 28, the light-emitting signal line 35, and the second electrode 82, the second conductive layer may include at least the second power line 37, the third shielding line 43, the shielding block 44, and the fourth electrode 84, the second semiconductor layer may include at least the ninth active layer 19, and the third conductive layer may include at least the ninth gate electrode 29 and the third scanning signal line 33, as shown in FIG15A.

[0299] (12) A sixth insulating film is deposited and patterned by a patterning process to form a sixth insulating layer 96 covering the third conductive layer. At least a lap hole KA and a twentieth via hole V20 are formed on the sixth insulating layer 96. The sixth insulating layer 96 and the fifth insulating layer 95 in the lap hole KA and the twentieth via hole V20 are etched away. The lap hole KA exposes the surface of the ninth active layer 19 away from the substrate, and the twentieth via hole V20 exposes the surface of the fourth insulating layer 94 away from the substrate, as shown in FIG15B.

[0300] In an exemplary embodiment, the overlapping hole etching in this patterning process may be performed by inductively coupled plasma (ICP) dry etching.

[0301] (13) The display substrate is placed in a buffered oxide etchant (BOE). The BOE etches the ninth active layer 19 exposed in the overlap hole KA, removing the ninth active layer 19 from the overlap hole KA. The overlap hole KA exposes the second surface of the ninth active layer 19 and the surface of the fourth insulating layer 94 away from the substrate. Since the BOE cannot etch the inorganic layer, the twentieth via hole V20 remains unchanged, as shown in FIG15C.

[0302] In an exemplary embodiment, the overlapping hole KA forms a ring-shaped overlapping sidewall in the ninth active layer 19 , and an angle between the overlapping sidewall and the substrate plane may be approximately 50 degrees to 70 degrees.

[0303] The present disclosure improves the surface quality of the second surface by etching the ninth active layer 19 with an oxide etching solution (wet etching method), so that the overlapping resistance of the subsequently formed sixth connecting electrode in contact with the side surface of the ninth active layer 19 has the same or similar resistance value as the overlapping resistance in contact with the front surface.

[0304] (14) The display substrate after wet etching is subjected to ICP dry etching again to remove the fourth insulating layer 94, the third insulating layer 93 and the second insulating layer 92 in the overlap hole KA, and the fourth insulating layer 94 and the third insulating layer 93 in the twentieth via hole V20, so that the overlap hole KA exposes the surface (first surface) of the eighth active layer 18 away from the substrate, and the twentieth via hole V20 exposes the surface of the light-emitting signal line 35 away from the substrate, as shown in FIG15D.

[0305] (15) The sixth insulating layer 96 and the fifth insulating layer 95 are patterned by a patterning process to form an eleventh via hole V11. The sixth insulating layer 96 and the fifth insulating layer 95 in the eleventh via hole V11 are etched away to expose the surface of the ninth active layer 19 away from the substrate, as shown in FIG15E .

[0306] (16) A fourth conductive film is deposited and patterned by a patterning process to form a fourth conductive layer (SD1) on the sixth insulating layer 96. The fourth conductive layer may include at least a sixth connecting electrode 56 and an eighth connecting electrode 58 as interconnecting electrodes. The sixth connecting electrode 56 is overlapped with the first surface of the eighth active layer 18 on one hand and with the second surface of the ninth active layer 19 on the other hand through the overlapping hole KA, thereby achieving simultaneous connection with the eighth active layer 18 and the ninth active layer 19 through a single overlapping hole, forming the fifth node of the interconnection structure. One end of the eighth connecting electrode 58 is connected to the ninth active layer 19 through the eleventh via hole V11, and the other end of the eighth connecting electrode 58 is connected to the light-emitting signal line 35 through the twentieth via hole V20, thereby achieving the light-emitting signal line 35 writing the light-emitting signal into the ninth transistor T9, as shown in FIG14 .

[0307] The preparation process shown in this embodiment is merely an exemplary description, and the corresponding structure can be changed according to the actual connection relationship. For example, in step (15), a via hole exposing the surface of the third conductive layer can also be formed simultaneously, and this disclosure does not make specific limitations here.

[0308] Based on current process capabilities, the size of a via is approximately 2.5μm. Taking into account exposure alignment accuracy, etching deviation, and etching-induced non-uniformity, each via requires an additional 1.5μm of edge wrapping around the outside. Therefore, each additional via in a circuit unit increases the size of the circuit unit by approximately 5.5μm (2.5μm + 2*1.5μm), significantly impacting resolution improvement.

[0309] In the display substrate provided by the embodiments of the present disclosure, the fourth conductive layer can be connected to both the oxide active layer and the polysilicon active layer via a single overlapping hole, effectively reducing the number of vias and the space occupied by the pixel drive circuit, thereby facilitating high resolution. By providing overlapping holes that simultaneously expose the side surfaces of the ninth oxide active layer and the front surface of the eighth polysilicon active layer, the present disclosure allows the interconnect electrode to overlap with the side surfaces of the eighth active layer through the overlapping hole and overlap with the front surface of the ninth active layer through the overlapping hole, optimizing the two-hole interconnect structure into a single-hole interconnect structure. This not only reduces the number of vias but also reduces the complexity of the drilling process, effectively improving yield.

[0310] In an exemplary embodiment, there are multiple two-hole interconnect structures or three-hole interconnect structures in the circuit unit. For example, the second connection electrode in the structure of Figure 4 is a two-hole interconnect structure, and the second connection electrode is connected to the second area of ​​the second active layer through a via, and is connected to the second area of ​​the third active layer through another via. For another example, the seventh connection electrode in the structure of Figure 4 is a three-hole interconnect structure, and the seventh connection electrode is connected to the second area of ​​the tenth active layer through a via, connected to the eighth gate electrode through another via, and connected to the ninth gate electrode through another via. These two-hole or three-hole interconnect structures not only put a lot of pressure on the layout space, but also greatly affect the yield due to the complexity of the punching process. The single-hole interconnect structure provided in the embodiment of the present disclosure can be adaptively applied to the above-mentioned interconnect structure, optimizing the two-hole interconnect structure into a single-hole interconnect structure, and optimizing the three-hole interconnect structure into a two-hole interconnect structure or a single-hole interconnect structure. Not only can the layout space be greatly saved in a complex layout and the resolution can be maximized, but the complexity of the punching process can also be reduced, which can effectively improve the product yield.

[0311] In an exemplary embodiment, the single-hole interconnect structure provided by the embodiment of the present disclosure can be applied to the scheme of setting a shielding layer as shown in FIG. 13 , which will not be described in detail here.

[0312] Figure 16 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the film layer structure in the region where the eighth transistor T8 and the ninth transistor T9 are located. The main structure of the display substrate in this embodiment is substantially the same as that in the embodiment shown in Figure 12, except that the third conductive layer (GATE3) is configured as a transfer structure layer in this embodiment.

[0313] As shown in Figure 16, in a plane perpendicular to the display substrate, the display substrate may include a first insulating layer 91, a first semiconductor layer, a second insulating layer 92, a first conductive layer, a third insulating layer 93, a second conductive layer, a fourth insulating layer 94, a second semiconductor layer, a fifth insulating layer 95, a third conductive layer, a sixth insulating layer 96 and a fourth conductive layer arranged in sequence on the base.

[0314] In an exemplary embodiment, the third conductive layer is further provided with a first transfer electrode 71 and a second transfer electrode 72 as a transfer structure. The first transfer electrode 71 is connected to the eighth active layer 18 through a first transfer hole, and the second transfer electrode 72 is connected to the light-emitting signal line 35 through a second transfer hole. The fourth conductive layer may include at least a sixth connection electrode 56 and an eighth connection electrode 58. One end of the sixth connection electrode 56 is connected to the ninth active layer 19 through a via hole, and the other end of the sixth connection electrode 56 is connected to the first transfer electrode 71 through another via hole. One end of the eighth connection electrode 58 is connected to the ninth active layer through a via hole, and the other end of the eighth connection electrode 58 is connected to the second transfer electrode 72 through another via hole.

[0315] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0316] (21) A first insulating layer 91, a first semiconductor layer, a second insulating layer 92, a first conductive layer (GATE1), a third insulating layer 93, a second conductive layer (GATE2), a fourth insulating layer 94, and a second semiconductor layer are sequentially formed, and the preparation process is substantially the same as that of the aforementioned embodiment. The first semiconductor layer may include at least the eighth active layer 18, the first conductive layer may include at least the eighth gate electrode 28, the light-emitting signal line 35, and the second electrode plate 82, the second conductive layer may include at least the second power line 37, the third shielding line 43, the shielding block 44, and the fourth electrode plate 84, and the second semiconductor layer may include at least the ninth active layer 19, as shown in FIG17A.

[0317] (22) A fifth insulating film is deposited and patterned through a patterning process to form a fifth insulating layer 95 covering the second semiconductor layer. A first transfer hole KB1 and a second transfer hole KB2 are formed on the fifth insulating layer 95. The fifth insulating layer 95, the fourth insulating layer 94, the third insulating layer 93, and the second insulating layer 92 within the first transfer hole KB1 are removed to expose the surface of the eighth active layer 18. The fifth insulating layer 95, the fourth insulating layer 94, and the third insulating layer 93 within the second transfer hole KB2 are removed to expose the surface of the light-emitting signal line 35, as shown in FIG17B.

[0318] In an exemplary embodiment, the patterning process may not provide a via hole in the region where the second semiconductor layer is located, so as to prevent the subsequently formed third conductive layer from being connected to the second semiconductor layer.

[0319] (23) A third conductive film is deposited and patterned by a patterning process to form a third conductive layer (GATE3) on the fifth insulating layer 95. The third conductive layer may include at least a ninth gate electrode 29, a third scanning signal line 33, a first transfer electrode 71, and a second transfer electrode 72. The first transfer electrode 71 is connected to the eighth active layer 18 through a first transfer hole KB1, and the second transfer electrode 72 is connected to the light-emitting signal line 35 through a second transfer hole KB2, as shown in FIG17C.

[0320] (24) A sixth insulating film is deposited and patterned by a patterning process to form a sixth insulating layer 96 covering the third conductive layer. The sixth insulating layer 96 is provided with a tenth via hole V10, an eleventh via hole V11, a twelfth via hole V12, and a twentieth via hole V20. The sixth insulating film in the tenth via hole V10 is removed to expose the surface of the first transfer electrode 71. The sixth insulating film and the fifth insulating film in the eleventh via hole V11 are removed to expose the surface of the ninth active layer 19. The sixth insulating film and the fifth insulating film in the twelfth via hole V12 are removed to expose the surface of the ninth active layer 19. The sixth insulating film in the twentieth via hole V20 is removed to expose the surface of the second transfer electrode 72, as shown in FIG17D.

[0321] In this exemplary embodiment, since all film layers below the second semiconductor layer have already been transferred through multiple transfer electrodes in the third conductive layer, this patterning process only requires one mask, and the formed via only needs to expose the second semiconductor layer and the third conductive layer. Compared to the embodiment shown in Figure 4, which uses an ILD-L mask and an ILD-O mask process, this embodiment does not add a mask.

[0322] (25) A fourth conductive film is deposited and patterned by a patterning process to form a fourth conductive layer (SD1) on the sixth insulating layer 96. The fourth conductive layer may include at least a sixth connecting electrode 56 and an eighth connecting electrode 58. The sixth connecting electrode 56 is connected to the first transfer electrode 71 through the tenth via hole V10 and to the ninth active layer 19 through the twelfth via hole V12. Since the first transfer electrode 71 is connected to the eighth active layer 18 through the via hole, the sixth connecting electrode 56 is simultaneously connected to the eighth active layer 18 and the ninth active layer 19, forming the fifth node of the interconnection structure. The eighth connecting electrode 58 is connected to the second transfer electrode 72 through the twentieth via hole V20 and to the ninth active layer 19 through the eleventh via hole V11. Since the second transfer electrode 72 is connected to the light-emitting signal line 35, the eighth connecting electrode 58 is simultaneously connected to the light-emitting signal line 35 and the ninth active layer 19. The light-emitting signal line 35 can write the light-emitting signal into the ninth transistor T9, as shown in FIG16.

[0323] The preparation process shown in this embodiment is merely an example, and the corresponding structure can be modified according to the actual connection relationship. For example, in step (22), a connection hole exposing the surface of the second conductive layer can also be formed simultaneously. For another example, in step (24), a connection hole exposing the surface of the third conductive layer can also be formed simultaneously. This disclosure does not make specific limitations here.

[0324] The display substrate provided by the embodiment of the present disclosure utilizes the third conductive layer with a relatively ample layout space as a transfer structure layer, which can not only effectively alleviate the layout pressure of multiple connection electrodes in the fourth conductive layer, which is beneficial to the optimization of the layout structure and can effectively improve the resolution, but also can reduce the via depth, reduce the process difficulty, improve the connection reliability, and effectively improve the product yield.

[0325] In an exemplary embodiment, there are multiple deep hole connection structures in the circuit unit. For example, the multiple vias exposing the first semiconductor layer and the multiple vias exposing the first conductive layer in the structure of Figure 4 are all deeper vias. These deep hole connection structures not only put a lot of pressure on the arrangement of the multiple connection electrodes in the fourth conductive layer, but also greatly affect the yield due to the complexity of the deep hole preparation process and connection. The use of the third conductive layer as a transfer structure layer provided by the embodiment of the present disclosure can be adaptively applied to the above-mentioned deep hole connection structure, which can not only effectively alleviate the layout pressure of the multiple connection electrodes in the fourth conductive layer, which is beneficial to the optimization of the layout structure and can effectively improve the resolution, but also can reduce the via depth, reduce the process difficulty, improve the connection reliability, and effectively improve the product yield.

[0326] In an exemplary embodiment, the use of the third conductive layer as the transition structure layer provided in the embodiment of the present disclosure can be applied to the scheme of providing the shielding layer as shown in FIG. 13 , which will not be described in detail here.

[0327] Figure 18 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the film layer structure in the region where the eighth transistor T8 and the ninth transistor T9 are located. The main structure of the display substrate in this embodiment is substantially the same as that shown in Figure 13 , except that the shielding layer is provided as a transition structure layer, and the second semiconductor layer is connected to the transition structure layer through vias.

[0328] As shown in Figure 18, in a plane perpendicular to the display substrate, the display substrate may include a first insulating layer 91, a first semiconductor layer, a second insulating layer 92, a first conductive layer, a third insulating layer 93, a shielding layer, a shielding insulating layer 97, a second conductive layer, a fourth insulating layer 94, a second semiconductor layer, a fifth insulating layer 95, a third conductive layer, a sixth insulating layer 96 and a fourth conductive layer arranged in sequence on the base.

[0329] In an exemplary embodiment, the shielding layer is further provided with a third transfer electrode 73 and a fourth transfer electrode 74 as a transfer structure. The third transfer electrode 73 is connected to the eighth active layer 18 via a third transfer hole, and the fourth transfer electrode 74 is connected to the light-emitting signal line 35 via a fourth transfer hole. The second semiconductor layer may include at least a ninth active layer 19, which is connected to the third transfer electrode 73 via a fifth transfer hole and to the fourth transfer electrode 74 via a sixth transfer hole.

[0330] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0331] (31) A first insulating layer 91, a first semiconductor layer, a second insulating layer 92, and a first conductive layer (GATE1) are sequentially formed, and the preparation process is substantially the same as that of the previous embodiment. The first semiconductor layer may include at least the eighth active layer 18, and the first conductive layer may include at least the eighth gate electrode 28, the light-emitting signal line 35, and the second electrode plate 82, as shown in FIG19A.

[0332] (32) A third insulating film is deposited and patterned through a patterning process to form a third insulating layer 93 covering the first conductive layer. A third transfer hole KB3 and a fourth transfer hole KB4 are formed on the third insulating layer 93. The third insulating layer 93 and the second insulating layer 92 within the third transfer hole KB3 are removed, exposing the surface of the eighth active layer 18. The third insulating layer 93 within the fourth transfer hole KB4 is removed, exposing the surface of the light-emitting signal line 35, as shown in FIG19B.

[0333] In an exemplary embodiment, after the third via hole KB3 and the fourth via hole KB4 are formed, the via holes may be cleaned with a buffered oxide etching solution to improve the contact quality between the first semiconductor layer and the via electrode.

[0334] (33) Depositing a shielding film and patterning the shielding film through a patterning process to form a shielding layer on the third insulating layer 93. The shielding layer may include at least a third transfer electrode 73, a fourth transfer electrode 74, a first shielding line 38, and a second shielding line (not shown). The shape, position, and structure of the first and second shielding lines may be substantially the same as those in the aforementioned embodiment. In an exemplary embodiment, the third transfer electrode 73 is connected to the eighth active layer 18 via a third transfer hole KB3, and the fourth transfer electrode 74 is connected to the light-emitting signal line 35 via a fourth transfer hole KB4, as shown in FIG. 19C .

[0335] (34) A shielding insulating layer 97 covering the shielding layer and a second conductive layer (GATE2) arranged on the shielding insulating layer 97 are formed in sequence. The second conductive layer may include at least a second power line 37, a third shielding line 43, a shielding block 44 and a fourth electrode 84, as shown in FIG19D.

[0336] (35) A fourth insulating film is deposited and patterned through a patterning process to form a fourth insulating layer 94 covering the first conductive layer. A fifth transfer hole KB5 and a sixth transfer hole KB6 are formed on the fourth insulating layer 94. The fourth insulating layer 94 and the shielding insulating layer 97 within the fifth transfer hole KB5 are removed, exposing the surface of the third transfer electrode 73. The fourth insulating layer 94 and the shielding insulating layer 97 within the sixth transfer hole KB6 are removed, exposing the surface of the fourth transfer electrode 74, as shown in FIG19E.

[0337] (36) A second semiconductor film is deposited and patterned by a patterning process to form a second semiconductor layer on the fourth insulating layer 94. The second semiconductor layer may include at least a ninth active layer 19. The ninth active layer 19 is connected to the third transfer electrode 73 through the fifth transfer hole KB5 on the one hand, and to the fourth transfer electrode 74 through the sixth transfer hole KB6 on the other hand, as shown in FIG19F.

[0338] In this exemplary embodiment, the third switching electrode 73 is connected to the eighth active layer 18 through a via, thereby connecting the ninth active layer 19 to the eighth active layer 18, forming a fifth node of the interconnect structure. The fourth switching electrode 74 is connected to the light emitting signal line 35, thereby connecting the light emitting signal line 35 to the ninth active layer 19. The light emitting signal line 35 can write a light emitting signal to the ninth transistor T9.

[0339] (37) A fifth insulating layer 95 covering the second semiconductor layer, a third conductive layer (GATE3) arranged on the fifth insulating layer 95, a sixth insulating layer 96 covering the third conductive layer, and a fourth conductive layer arranged on the sixth insulating layer 96 are formed in sequence. The third conductive layer may include at least a ninth gate electrode 29 and a third scanning signal line 33, and the fourth conductive layer may include at least a data signal line and a high-frequency signal line, as shown in FIG. 18 .

[0340] The preparation process shown in this embodiment is merely an example, and the corresponding structure can be modified according to the actual connection relationship. For example, in step (32), a connection hole exposing the surface of the first conductive layer can also be formed simultaneously. For another example, in step (35), a connection hole exposing the surface of the second conductive layer can also be formed simultaneously. This disclosure does not make specific limitations here.

[0341] The display substrate provided in the embodiment of the present disclosure utilizes a shielding layer with a relatively ample layout space as a transfer structure layer, and the second semiconductor layer is connected to the transfer structure layer through vias. This can not only effectively alleviate the layout pressure of multiple connection electrodes in the fourth conductive layer, which is beneficial to layout structure optimization and resolution improvement, but also reduce the via depth, reduce process difficulty, improve connection reliability, and effectively improve product yield.

[0342] In an exemplary embodiment, the scheme of using the shielding layer as the transition structure layer and the scheme of using the third conductive layer as the transition structure layer provided in the embodiment of the present disclosure can be used in combination. A part of the transition electrodes can be set on the shielding layer, and another part of the transition electrodes can be set on the third conductive layer. No further details are given here.

[0343] In a possible exemplary embodiment, this embodiment shows that the substrate can only be provided with a shielding layer without providing a second conductive layer, and structures such as the second power line 37, the initial signal line 45, the third electrode 83, the fourth electrode 84 and the shielding line can be provided on the shielding layer, which will not be repeated here.

[0344] The display substrate provided by the exemplary embodiments of the present disclosure can be applicable to any LED driving pixel circuit, including P-type PAM, P-type PAM+PWM, N-type PAM, N-type PAM+PWM, and LTPO-type PAM and PAM+PWM circuits.

[0345] The exemplary embodiments of the present disclosure further provide a method for preparing a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the preparation method includes:

[0346] A pixel driving circuit, a first scan signal line, a second scan signal line, a third scan signal line and a light-emitting signal line are formed in at least one circuit unit, wherein the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the gate electrode of the first transistor, the gate electrode of the seventh transistor and the gate electrode of the tenth transistor are electrically connected to the third scan signal line, the gate electrode of the second transistor is electrically connected to the second scan signal line, the gate electrode of the fourth transistor is electrically connected to the first scan signal line, the gate electrode of the fifth transistor is electrically connected to the light-emitting signal line, and the gate electrode of the eighth transistor is electrically connected to the gate electrode of the ninth transistor; the orthographic projection of the first scan signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second scan signal line on the display substrate plane, the orthographic projection of the third scan signal line on the display substrate plane at least partially overlaps with the orthographic projection of the light-emitting signal line on the display substrate plane, and the orthographic projection of the eighth transistor on the display substrate plane at least partially overlaps with the orthographic projection of the ninth transistor on the display substrate plane.

[0347] The exemplary embodiments of the present disclosure further provide a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0348] While the embodiments disclosed herein are as described above, it should be noted that the embodiments described above are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, a first scanning signal line, a second scanning signal line, a third scanning signal line and a light emitting signal line, the pixel driving circuit comprising at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; a gate electrode of the first transistor, a gate electrode of the seventh transistor and a gate electrode of the tenth transistor are electrically connected to the third scanning signal line, a gate electrode of the second transistor is electrically connected to the second scanning signal line The gate electrode of the fourth transistor is electrically connected to the first scanning signal line, the gate electrode of the fifth transistor is electrically connected to the light-emitting signal line, and the gate electrode of the eighth transistor is electrically connected to the gate electrode of the ninth transistor; the orthographic projection of the first scanning signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second scanning signal line on the display substrate plane, the orthographic projection of the third scanning signal line on the display substrate plane at least partially overlaps with the orthographic projection of the light-emitting signal line on the display substrate plane, and the orthographic projection of the eighth transistor on the display substrate plane at least partially overlaps with the orthographic projection of the ninth transistor on the display substrate plane.

2. The display substrate according to claim 1, in, The first transistor, the second transistor, the seventh transistor, the ninth transistor, and the tenth transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor are polysilicon transistors.

3. The display substrate according to claim 1, in, The orthographic projection of the gate electrode of the eighth transistor on the plane of the display substrate at least partially overlaps with the orthographic projection of the gate electrode of the ninth transistor on the plane of the display substrate.

4. The display substrate according to claim 1, in, An orthographic projection of the active layer of the eighth transistor on the plane of the display substrate at least partially overlaps with an orthographic projection of the active layer of the ninth transistor on the plane of the display substrate.

5. The display substrate according to claim 1, in, An orthographic projection of the channel region of the eighth transistor on the plane of the display substrate at least partially overlaps with an orthographic projection of the channel region of the ninth transistor on the plane of the display substrate.

6. The display substrate according to claim 1, in, In at least one unit row, the pixel driving circuits in two adjacent circuit units are mirror-symmetric with respect to a column boundary line, and the column boundary line is a straight line located between adjacent unit columns and extending along the pixel column direction.

7. The display substrate according to claim 1, in, In at least one unit column, the pixel driving circuits in two adjacent circuit units are mirror-symmetric with respect to a row boundary line, and the row boundary line is a straight line located between adjacent unit rows and extending along the pixel row direction.

8. The display substrate according to claim 1, in, In at least one unit column, the first electrodes of the first transistors in two adjacent circuit units are connected to the same initial signal line, and the first electrodes of the seventh transistors in two adjacent circuit units are connected to the same initial signal line.

9. The display substrate according to claim 1, in, In at least one unit column, the active layers of the first transistors in two adjacent circuit units are interconnected as an integrated structure, and the active layers of the seventh transistors in two adjacent circuit units are interconnected as an integrated structure.

10. The display substrate according to claim 1, in, In at least one unit row, first electrodes of the eighth transistors in two adjacent circuit units are connected to the same high-frequency signal line.

11. The display substrate according to claim 1, in, In at least one unit row, active layers of the eighth transistors in two adjacent circuit units are interconnected as an integrated structure.

12. The display substrate according to any one of claims 1 to 11, in, In a direction perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer and a third conductive layer which are sequentially arranged on a base; the active layer of the third transistor, the active layer of the fourth transistor, the active layer of the fifth transistor, the active layer of the sixth transistor and the active layer of the eighth transistor are arranged in the first semiconductor layer, the first scan signal line, the light emitting signal line and the gate electrode of the eighth transistor are arranged in the first conductive layer, the active layer of the first transistor, the active layer of the second transistor, the active layer of the seventh transistor, the active layer of the ninth transistor and the active layer of the tenth transistor are arranged in the second semiconductor layer, and the second scan signal line, the third scan signal line and the gate electrode of the ninth transistor are arranged in the third conductive layer.

13. The display substrate according to claim 12, in, The display substrate also includes a first shielding line. In a direction perpendicular to the display substrate, the first shielding line is arranged between the third scanning signal line and the luminous signal line. The orthographic projection of the first shielding line on the substrate at least partially overlaps with the orthographic projection of the luminous signal line on the substrate. The orthographic projection of the first shielding line on the substrate at least partially overlaps with the orthographic projection of the third scanning signal line on the substrate.

14. The display substrate according to claim 12, in, The display substrate also includes a second shielding line, which is arranged between the first scanning signal line and the second scanning signal line in a direction perpendicular to the display substrate, and the orthographic projection of the second shielding line on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line on the substrate, and the orthographic projection of the second shielding line on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line on the substrate.

15. The display substrate according to claim 12, in, The display substrate further comprises a fourth conductive layer disposed on a side of the third conductive layer away from the base; the fourth conductive layer at least comprises interconnecting electrodes, and the interconnecting electrodes are respectively connected to the active layer of the eighth transistor and the active layer of the ninth transistor.

16. The display substrate according to claim 15, in, One end of the interconnect electrode is connected to the active layer of the eighth transistor through a via hole, and the other end of the interconnect electrode is connected to the active layer of the ninth transistor through another via hole.

17. The display substrate according to claim 15, in, The interconnect electrode overlaps the first surface of the active layer of the eighth transistor through a overlap hole, and overlaps the second surface of the active layer of the ninth transistor through the overlap hole, the first surface is a surface parallel to the substrate, and the second surface is a surface intersecting the substrate.

18. The display substrate according to claim 15, in, The third conductive layer also includes a transfer electrode; the transfer electrode is connected to the active layer of the eighth transistor through a transfer hole, one end of the interconnection electrode is connected to the first transfer electrode through a via hole, and the other end of the interconnection electrode is connected to the active layer of the ninth transistor through another via hole.

19. The display substrate according to claim 15, in, The display substrate further comprises a shielding layer, the shielding layer is arranged between the first conductive layer and the second conductive layer, and the shielding layer comprises a switching electrode; The switching electrode is connected to the active layer of the eighth transistor through a switching hole, one end of the interconnection electrode is connected to the switching electrode through a via hole, and the other end of the interconnection electrode is connected to the active layer of the ninth transistor through another via hole.

20. The display substrate according to claim 12, in, The second conductive layer includes a switching electrode; The switching electrode is connected to the active layer of the eighth transistor through a switching hole, and the active layer of the ninth transistor is connected to the switching electrode through another switching hole.

21. The display substrate according to claim 12, in, The display substrate further comprises a shielding layer, the shielding layer is arranged between the first conductive layer and the second conductive layer, and the shielding layer comprises a switching electrode; The switching electrode is connected to the active layer of the eighth transistor through a switching hole, and the active layer of the ninth transistor is connected to the switching electrode through another switching hole.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

23. A method for preparing a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the method include: A pixel driving circuit, a first scanning signal line, a second scanning signal line, a third scanning signal line and a light emitting signal line are formed in at least one circuit unit, wherein the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor a body tube, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; a gate electrode of the first transistor, a gate electrode of the seventh transistor and a gate electrode of the tenth transistor are electrically connected to the third scan signal line, a gate electrode of the second transistor is electrically connected to the second scan signal line, a gate electrode of the fourth transistor is electrically connected to the first scan signal line, a gate electrode of the fifth transistor is electrically connected to the light-emitting signal line, and a gate electrode of the eighth transistor is electrically connected to the gate electrode of the ninth transistor; an orthographic projection of the first scan signal line on a display substrate plane at least partially overlaps with an orthographic projection of the second scan signal line on a display substrate plane, an orthographic projection of the third scan signal line on a display substrate plane at least partially overlaps with an orthographic projection of the light-emitting signal line on a display substrate plane, and an orthographic projection of the eighth transistor on a display substrate plane at least partially overlaps with an orthographic projection of the ninth transistor on a display substrate plane.

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