Pixel circuit and driving method therefor, and display apparatus

Abstract

A pixel circuit (50) and a driving method therefor, and a display apparatus. The pixel circuit (50) comprises a drive circuit (100) and a data writing circuit (200), wherein the drive circuit (100) is configured to control the magnitude of a drive current flowing through a first end (100a) and a second end (100b); and a first end (200a) of the data writing circuit (200) is electrically connected to the second end (100b) of the drive circuit (100), a second end (200b) of the data writing circuit (200) is configured to receive a data signal, the data writing circuit (200) is configured to write the data signal into the second end (100b) of the drive circuit (100) in response to a data scanning signal and comprises a data writing transistor (T1) and a first compensation capacitor (Cst1), a gate electrode of the data writing transistor (T1) is configured to receive the data scanning signal, and a first electrode of the first compensation capacitor (Cst1) is electrically connected to a first electrode of the data writing transistor (T1). The pixel circuit (50) can reduce the influence of a fluctuation in the data signal and a change in the state of the data writing transistor (T1) on the voltage of the second end (100b) of a drive transistor, which is conducive to maintaining the stability of a gate-source voltage of the drive transistor, so that a light-emitting element has a stable light-emitting state.

Description

Pixel circuit, driving method thereof and display device TECHNICAL FIELD

[0001] At least one embodiment of the present disclosure relates to a pixel circuit, a driving method thereof and a display device. BACKGROUND

[0002] With the continuous development of display technology, pixel circuits with low temperature polycrystalline oxide (LTPO) are increasingly applied in display devices. The pixel circuits with LTPO have high refresh rate, low leakage, and high uniformity of brightness of display panels. In addition, internal compensation circuits are widely used due to their low requirements for driving integrated circuits (ICs), low cost and simple control algorithm.

[0003] SUMMARY

[0004] At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof and a display device.

[0005] At least one embodiment of the present disclosure provides a pixel circuit, which includes a driving circuit and a data writing circuit. The driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control the size of a driving current flowing through the first terminal and the second terminal. The data writing circuit includes a first terminal and a second terminal, wherein the first terminal of the data writing circuit is electrically connected to the second terminal of the driving circuit, the second terminal of the data writing circuit is configured to receive a data signal, the data writing circuit is configured to write the data signal to the second terminal of the driving circuit in response to a data scanning signal, and includes a data writing transistor and a first compensation capacitor, wherein the gate of the data writing transistor is configured to receive the data scanning signal, and the first pole of the first compensation capacitor is electrically connected to the first pole of the data writing transistor.

[0006] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second pole of the first compensation capacitor is electrically connected to the second terminal of the driving circuit, and the second pole of the data writing transistor is electrically connected to a data signal terminal to receive the data signal.

[0007] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the capacitance value of the first compensation capacitor is 30 to 100 times the capacitance value of the parasitic capacitance between the gate of the data writing transistor and the first pole of the data writing transistor.

[0008] For example, the pixel circuit provided by at least one embodiment of the present disclosure has a first compensation capacitor, and a capacitance value of the first compensation capacitor is 100 fF to 300 fF.

[0009] For example, the pixel circuit provided by at least one embodiment of the present disclosure has a first compensation capacitor, and a capacitance value of the first compensation capacitor is 100 fF to 300 fF.

[0010] For example, the pixel circuit provided by at least one embodiment of the present disclosure further includes a first reset circuit, a control end of the first reset circuit is configured to receive a first reset control signal, a first end of the first reset circuit is electrically connected to a first pole of the first compensation capacitor, and a second end of the first reset circuit is electrically connected to a reference signal end to receive a reference signal, and the first reset circuit is configured to write the reference signal to the second end of the driving circuit with the first compensation capacitor in response to the first reset control signal.

[0011] For example, the pixel circuit provided by at least one embodiment of the present disclosure has a first compensation capacitor, and a capacitance value of the first compensation capacitor is 100 fF to 300 fF.

[0012] For example, the pixel circuit provided by at least one embodiment of the present disclosure has a first compensation capacitor, and a capacitance value of the first compensation capacitor is 100 fF to 300 fF.

[0013] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the first reset circuit includes a first reset transistor, a gate of the first reset transistor is electrically connected with a first reset control end to receive the first reset control signal, a first pole of the first reset transistor is electrically connected with a first pole of the first compensation capacitor, and a second pole of the first reset transistor is electrically connected with the reference signal end to receive the reference signal; the data write transistor and the first reset transistor are respectively independently controlled transistors, a gate of the data write transistor is electrically connected with a data control end, a gate of the first reset transistor is electrically connected with the first reset control end, the data control end and the first reset control end are respectively independent and different signal ends, and the data signal end and the reference signal end are respectively independent and different signal ends.

[0014] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit further includes a light emitting element and a second reset circuit, the light emitting element is configured to emit light under the driving of the driving current, a second end of the driving circuit is electrically connected with a first electrode of the light emitting element, the driving circuit is configured to control the size of the driving current flowing through the light emitting element, a second electrode of the light emitting element is electrically connected with a first voltage end to receive a first power voltage, a control end of the second reset circuit is configured to receive a second reset control signal, a first end of the second reset circuit is electrically connected with the first electrode of the light emitting element, and a second end of the second reset circuit is electrically connected with a first reset signal end to receive a first reset signal, and the second reset circuit is configured to apply the first reset signal to the first electrode of the light emitting element in response to the second reset control signal.

[0015] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second reset circuit includes a second reset transistor, a gate of the second reset transistor is electrically connected with a second reset control end to receive the second reset control signal, a first pole of the second reset transistor is electrically connected with the first electrode of the light emitting element, and a second pole of the second reset transistor is electrically connected with the first reset signal end to receive the first reset signal; a gate of the data write transistor is electrically connected with a gate of the second reset transistor, the data write transistor and the second reset transistor share the gate, the data scanning signal serves as the second reset control signal, the type of the data transistor is the same as the type of the second reset transistor, or the gate of the data transistor and the gate of the second reset transistor are independent of each other and are not electrically connected.

[0016] For example, the pixel circuit provided by at least one embodiment of the present disclosure further includes: a first light-emitting control circuit and a second light-emitting control circuit, a control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first end of the first light-emitting control circuit is electrically connected with the first end of the driving circuit, a second end of the first light-emitting control circuit is electrically connected with a second voltage end to receive a second power voltage, and the first light-emitting control circuit is configured to apply the second power voltage to the first end of the driving circuit in response to the first light-emitting control signal; a control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the second light-emitting control signal being different from the first light-emitting control signal, a first end of the second light-emitting control circuit is electrically connected with the second end of the driving circuit, and a second end of the second light-emitting control circuit is electrically connected with the first electrode of the light-emitting element, and the second light-emitting control circuit is configured to apply the driving current to the light-emitting element in response to the second light-emitting control signal.

[0017] For example, the pixel circuit provided by at least one embodiment of the present disclosure further includes a direct reset circuit, a control end of the direct reset circuit is configured to receive a direct reset control signal, a first end of the direct reset circuit is electrically connected with the second end of the driving circuit, and a second end of the direct reset circuit is electrically connected with a second reset signal end to receive a second reset signal, and the direct reset circuit is configured to directly apply the second reset signal to the second end of the driving circuit in response to the direct reset control signal.

[0018] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the value of the first reset signal is equal to the value of the second reset signal.

[0019] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the first light-emitting control circuit includes a first light-emitting control transistor, a gate of the first light-emitting control transistor is electrically connected to the first light-emitting control terminal to receive the first light-emitting control signal, a first electrode of the first light-emitting control transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the first light-emitting control transistor is electrically connected to the second voltage terminal to receive the second power supply voltage; and the second light-emitting control circuit includes a second light-emitting control transistor, a gate of the second light-emitting control transistor is electrically connected to the second light-emitting control terminal to receive the second light-emitting control signal, a first electrode of the second light-emitting control transistor is electrically connected to the second terminal of the driving circuit, and a second electrode of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting element.

[0020] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit further includes an auxiliary compensation circuit, the auxiliary compensation circuit includes a second compensation capacitor, a first electrode of the second compensation capacitor is electrically connected to the second terminal of the driving circuit, and a second electrode of the second compensation capacitor is configured to receive a first constant signal.

[0021] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second electrode of the second compensation capacitor is electrically connected to the second voltage terminal, and the second power supply voltage serves as the first constant signal; or the second electrode of the second compensation capacitor is electrically connected to the first reset signal terminal, and the first reset signal serves as the first constant signal; or the second electrode of the second compensation capacitor is electrically connected to an external constant signal terminal outside the pixel circuit to receive the first constant signal from the external constant signal terminal.

[0022] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit further includes an auxiliary circuit, the auxiliary circuit includes an auxiliary capacitor, a first electrode of the auxiliary capacitor is electrically connected to the gate of the data writing transistor, and a second electrode of the auxiliary capacitor is configured to receive a second constant signal.

[0023] For example, the pixel circuit provided by at least one embodiment of the present disclosure further includes a third reset circuit and a compensation control circuit, a control end of the third reset circuit is configured to receive a third reset control signal, a first end of the third reset circuit is electrically connected with the first end of the driving circuit, a second end of the third reset circuit is electrically connected with the control end of the driving circuit, and the third reset circuit is configured to allow the second power supply voltage to be applied to the control end of the driving circuit in response to the third reset control signal; the compensation control circuit includes a compensation control capacitor, a first pole of the compensation control capacitor is electrically connected with the control end of the driving circuit, and a second pole of the compensation control capacitor is electrically connected with the first electrode of the light emitting element.

[0024] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes a driving transistor, a gate of the driving transistor serves as the control end of the driving circuit, a first pole of the driving transistor serves as the first end of the driving circuit, and a second pole of the driving transistor serves as the second end of the driving circuit; the third reset circuit includes a third reset transistor, a gate of the third reset transistor is electrically connected with the third reset control end to receive the third reset control signal, a first pole of the third reset transistor is electrically connected with the first pole of the driving transistor, and a second pole of the third reset transistor is electrically connected with the gate of the driving transistor.

[0025] At least one embodiment of the present disclosure further provides a display device, which includes the pixel circuit of any of the above embodiments.

[0026] At least one embodiment of the present disclosure further provides a driving method of a pixel circuit, which is applicable to the pixel circuit of any of the above embodiments, and includes: in a data writing and compensation phase, allowing the data scanning signal to be an open signal to open the data writing transistor, and writing the data signal to the second end of the driving circuit through the data writing transistor and the first compensation capacitor.

[0027] For example, the driving method of the pixel circuit provided by at least one embodiment of the present disclosure also includes a data writing circuit, a control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected with a second end of the driving circuit, and a second end of the data writing circuit is electrically connected with a data signal end to receive the data signal; the driving method further includes: in the data writing and compensation phase, the data scanning signal is an open signal to write the data signal into the second end of the driving circuit; and when entering the light emitting phase from the data writing and compensation phase, the data scanning signal is changed from the open signal to a closed signal to close the data writing transistor, and in the light emitting phase, the data scanning signal remains as the closed signal.

[0028] For example, in the step of writing the data signal into the second end of the driving circuit through the data writing transistor and the first compensation capacitor, a difference between an initial voltage value Vc11 of the first pole of the first compensation capacitor before entering the data writing and compensation phase and a stable voltage value Vc12 of the first pole of the first compensation capacitor in the data writing and compensation phase is a first change amount AVc1, and a difference between an initial voltage value Vc13 of the second pole of the first compensation capacitor before entering the data writing and compensation phase and a stable voltage value Vc14 of the second pole of the first compensation capacitor in the data writing and compensation phase is a second change amount AVc2, and the first change amount AVc1 is equal to the second change amount AVc2.

[0029] For example, the driving method of the pixel circuit provided by at least one embodiment of the present disclosure also includes an auxiliary compensation circuit, the auxiliary compensation circuit includes a second compensation capacitor, a first pole of the second compensation capacitor is electrically connected with the second end of the driving circuit, and a second pole of the second compensation capacitor is configured to receive a first constant signal; in the step of writing the data signal into the second end of the driving circuit through the data writing transistor and the first compensation capacitor, the first compensation capacitor and the second compensation capacitor are connected in series, and in the data writing and compensation phase, a voltage Vc3 of the second end of the driving circuit is Vc3=(Vdata-Vref)×[C1 / (C1+C2)]+Vini1, Vdata represents a value of the data signal, Vref represents an initial voltage value of the first pole of the first compensation capacitor before entering the data writing and compensation phase, C1 represents a capacitance value of the first compensation capacitor, C2 represents a capacitance value of the second compensation capacitor, and Vini1 represents an initial voltage value of the second end of the driving circuit before entering the data writing and compensation phase.

[0030] For example, the driving method of the pixel circuit provided by at least one embodiment of the present disclosure also includes: a light emitting element, a first reset circuit, a second reset circuit, a third reset circuit, a first light emitting control circuit, and a second light emitting control circuit, a second end of the driving circuit is electrically connected with a first electrode of the light emitting element, and the driving circuit is configured to control the size of the driving current flowing through the light emitting element; the control end of the first reset circuit is configured to receive a first reset control signal, the first end of the first reset circuit is electrically connected with the first pole of the first compensation capacitor, and the second end of the first reset circuit is electrically connected with a reference signal end to receive a reference signal; the control end of the second reset circuit is configured to receive a second reset control signal, the first end of the second reset circuit is electrically connected with the first electrode of the light emitting element, and the second end of the second reset circuit is electrically connected with a first reset signal end to receive a first reset signal; the control end of the third reset circuit is configured to receive a third reset control signal, the first end of the third reset circuit is electrically connected with the first end of the driving circuit, and the second end of the third reset circuit is electrically connected with the control end of the driving circuit; the control end of the first light emitting control circuit is configured to receive a first light emitting control signal, the first end of the first light emitting control circuit is electrically connected with the first end of the driving circuit, and the second end of the first light emitting control circuit is electrically connected with a second voltage end to receive a second power voltage; the control end of the second light emitting control circuit is configured to receive a second light emitting control signal, the first end of the second light emitting control circuit is electrically connected with the second end of the driving circuit, and the second end of the second light emitting control circuit is electrically connected with the first electrode of the light emitting element; the driving method further includes: in a reset stage before the compensation stage, the first reset control signal is an open signal to open the first reset circuit, wherein the first reset circuit applies the reference signal to the first pole of the first compensation capacitor; the first light emitting control signal is an open signal to open the first light emitting control circuit, wherein the first light emitting control circuit applies the second power voltage to the first end of the driving circuit; the third reset control signal is an open signal to open the third reset circuit, wherein the third reset circuit applies the second power voltage to the control end of the driving circuit; the second reset control signal is an open signal to open the second reset circuit, wherein the second reset circuit applies the first reset signal to the first electrode of the light emitting element; and the second light emitting control signal is an open signal to open the second light emitting control circuit; the first reset signal is applied to the second end of the driving circuit through the second light emitting control circuit, and the value of the first reset signal is Vini1, so that the initial voltage value of the second end of the driving circuit before entering the data writing and compensation stage is Vini1.Or the pixel circuit further comprises a direct reset circuit, a control end of the direct reset circuit is configured to receive a direct reset control signal, a first end of the direct reset circuit is electrically connected with the second end of the drive circuit, and a second end of the direct reset circuit is electrically connected with the second reset signal end to receive a second reset signal; in the light-emitting stage, the driving method further comprises: taking the direct reset control signal as an opening signal to open the direct reset circuit, applying the second reset signal to the second end of the drive circuit, and taking the value of the second reset signal as Vini2, so that the initial voltage value of the second end of the drive circuit before entering the data writing and compensation stage is Vini2.

[0031] For example, the driving method of the pixel circuit provided by at least one embodiment of the present disclosure further comprises a compensation control circuit, and the compensation control circuit comprises a compensation control capacitor, wherein a first pole of the compensation control capacitor is electrically connected with the gate of the drive transistor, and a second pole of the compensation control capacitor is electrically connected with the first electrode of the light-emitting element; the driving method further comprises: in the data writing and compensation stage, taking the second reset control signal as an opening signal to open the second reset circuit, wherein the second reset circuit applies the first reset signal to the first electrode of the light-emitting element and the second pole of the compensation control capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure, but not limit the present disclosure.

[0033] FIG. 1 is a schematic block diagram of a pixel circuit according to at least one embodiment of the present disclosure.

[0034] FIG. 2A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 1.

[0035] FIG. 2B is a schematic diagram of the pixel circuit shown in FIG. 2A in a data writing and compensation stage.

[0036] FIG. 2C is a schematic diagram of the pixel circuit shown in FIG. 2A in a light-emitting stage.

[0037] FIG. 3 is a signal timing diagram of a driving method according to at least one embodiment of the present disclosure.

[0038] FIG. 4 is a schematic block diagram of another pixel circuit according to at least one embodiment of the present disclosure.

[0039] FIG. 5A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 4.

[0040] FIG. 5B is a schematic diagram of the pixel circuit shown in FIG. 5A in a data writing and compensation phase.

[0041] FIG. 5C is a schematic diagram of the pixel circuit shown in FIG. 5A in a light emitting phase.

[0042] FIG. 6 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0043] FIG. 7 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0044] FIG. 8A is a circuit diagram of one implementation of the pixel circuit shown in FIG. 7.

[0045] FIG. 8B is a schematic diagram of the pixel circuit shown in FIG. 8A in a reset phase.

[0046] FIG. 8C is a schematic diagram of the pixel circuit shown in FIG. 8A in a data writing and compensation phase.

[0047] FIG. 8D is a schematic diagram of the pixel circuit shown in FIG. 8A in a light emitting phase.

[0048] FIG. 9 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0049] FIG. 10 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0050] FIG. 11A is a circuit diagram of one implementation of the pixel circuit shown in FIG. 10.

[0051] FIG. 11B is a schematic diagram of the pixel circuit shown in FIG. 11A in a reset phase.

[0052] FIG. 11C is a schematic diagram of the pixel circuit shown in FIG. 11A in a data writing and compensation phase.

[0053] FIG. 11D is a schematic diagram of the pixel circuit shown in FIG. 11A in a light emitting phase.

[0054] FIG. 12 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0055] FIG. 13 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0056] FIG. 14A is a circuit diagram of one implementation of the pixel circuit shown in FIG. 13.

[0057] FIG. 14B is a schematic diagram of the pixel circuit shown in FIG. 13 in a data writing and compensation phase.

[0058] FIG. 14C is a schematic diagram of the pixel circuit of FIG. 13 in a light emission phase.

[0059] FIG. 15 is a schematic block diagram of yet another pixel circuit, according to at least one embodiment of the present disclosure.

[0060] FIG. 16 is a circuit diagram of one implementation of the pixel circuit of FIG. 15.

[0061] FIG. 17 is a schematic block diagram of yet another pixel circuit, according to at least one embodiment of the present disclosure.

[0062] FIG. 18 is a circuit diagram of one implementation of the pixel circuit of FIG. 17.

[0063] FIG. 19 is a circuit diagram of another implementation of the pixel circuit of FIG. 1.

[0064] FIG. 20 is a schematic block diagram of a display device, according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] So that the purposes, technical solutions and superiorities of the embodiments of the present disclosure can be more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some of the embodiments of the present disclosure, but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0066] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second”, and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms “include”, “contain”, and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects.

[0067] The terms “vertical”, “parallel”, and “same” and the like used in the embodiments of the present disclosure include the strict “vertical”, “parallel”, “same” and the like, and “approximately vertical”, “approximately parallel”, “approximately same” and the like with a certain error, which, considering the measurement and the error related to the measurement of a specific value (that is, the limitation of the measurement system), means within the acceptable deviation range for the specific value determined by those of ordinary skill in the art. The “center” in the embodiments of the present disclosure can include a position strictly at the geometric center and a position approximately at the center within a small area around the geometric center.

[0068] Generally, in the pixel circuit, the first electrode of the data writing transistor can be electrically connected with the first electrode of the driving transistor, so that the data signal can be written to the first electrode of the driving transistor. In the driving process of the pixel circuit, when the pixel circuit enters the light emitting stage, the data writing transistor will be switched from the open state to the closed state. However, due to the parasitic capacitance between the gate electrode and the first electrode of the data writing transistor, the voltage of the first electrode of the data writing transistor can be reduced at the moment when the data writing transistor is closed, thereby reducing the voltage of the first electrode of the driving transistor, and further reducing the gate-source voltage Vgs of the driving transistor in the light emitting stage, affecting the size of the driving current.

[0069] For example, when the gate-source voltage Vgs of the driving transistor of each of a plurality of sub-pixels in the display panel is reduced to different degrees when entering the light emitting stage, the brightness of the plurality of sub-pixels will be different, and the brightness uniformity of the entire display panel will be affected. In addition, due to the fact that the pixel circuit includes a plurality of transistors, a plurality of capacitors and a plurality of signal lines, the internal compensation structure of the pixel circuit is complex. For example, there can be parasitic capacitance between some signal lines and the first electrode of the driving transistor. When the voltage signal of these signal lines changes, the voltage of the first electrode of the driving transistor can fluctuate, which can cause crosstalk, for example, the light emitting element can suddenly emit light, thereby causing the display panel to have abnormal images and affecting the display effect.

[0070] At the same time, some display devices can have short-term residual images when displaying. That is, after the display device displays the same image for a period of time, the original image can be partially retained and appear in the next image when the current display image is switched to the next image, and then the residual image disappears after a period of time. The reason for the short-term residual image can be that the driving transistor in the pixel circuit has a hysteresis effect, which is mainly caused by the threshold voltage (Vth) offset caused by the movable ions remaining in the holes. When the display device performs image switching, the gate-source voltage Vgs (the voltage difference between the gate electrode and the source electrode of the driving transistor) of the driving transistor can be different, so the threshold voltage of the driving transistor can be offset. For example, when the display device displays an initial image for a period of time, the initial image can still be partially retained within a few hours when the display device switches to a new image, thereby affecting the display. For example, in the low gray scale driving process, the gate-source voltage Vgs of the driving transistor is more likely to fluctuate due to the offset of the threshold voltage (Vth) of the driving transistor.

[0071] At least one embodiment of the present disclosure provides a pixel circuit and a driving method thereof, and a display device.

[0072] The pixel circuit provided by at least one embodiment of the present disclosure includes a driving circuit and a data writing circuit. The driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control the size of a driving current flowing through the first terminal and the second terminal. The data writing circuit includes a first terminal and a second terminal. The first terminal of the data writing circuit is electrically connected to the second terminal of the driving circuit. The second terminal of the data writing circuit is configured to receive a data signal. The data writing circuit is configured to write the data signal to the second terminal of the driving circuit in response to a data scanning signal, and includes a data writing transistor and a first compensation capacitor. A gate of the data writing transistor is configured to receive the data scanning signal. A first pole of the first compensation capacitor is electrically connected to a first pole of the data writing transistor.

[0073] The pixel circuit provided by at least one embodiment of the present disclosure can reduce the influence of the data writing transistor on the voltage of the second terminal of the driving circuit when the pixel circuit switches to the light emitting stage, so that the fluctuation of the gate-source voltage Vgs of the driving transistor in the light emitting stage is small, thereby improving the uniformity of the brightness of the display panel. At the same time, the influence of the fluctuation of the data writing signal on the voltage of the second terminal of the driving circuit can also be reduced. Therefore, the pixel circuit provided by the embodiments of the present disclosure is of great significance to stabilize the gate-source voltage Vgs of the driving circuit and improve the display effect of the display device.

[0074] The pixel circuit, the driving method thereof and the display device provided by the embodiments of the present disclosure will be described below in combination with the drawings.

[0075] FIG. 1 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

[0076] As shown in FIG. 1, the pixel circuit 10 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light emitting element 400, a second reset circuit 500, a first light emitting control circuit 600, a second light emitting control circuit 700, a third reset circuit 800 and a compensation control circuit 900.

[0077] As shown in FIG. 1, the driving circuit 100 includes a control terminal 100m, a first terminal 100a and a second terminal 100b. The first terminal 100a of the driving circuit 100 is electrically connected to a first node N1. The control terminal 100m of the driving circuit 100 is electrically connected to a second node N2. The second terminal 100b of the driving circuit 100 is electrically connected to a third node N3. The driving circuit 100 is configured to control the size of a driving current flowing through the first terminal 100a and the second terminal 100b. For example, the driving current can be used to drive the light emitting element 400 to emit light. For example, in the light emitting stage, the driving circuit 100 can provide a driving current to the light emitting element 400 to drive the light emitting element 400 to emit light, and can emit light according to the required “gray scale”.

[0078] As shown in FIG. 1, the data writing circuit 200 includes a control terminal 200m, a first terminal 200a, and a second terminal 200b. The control terminal 200m of the data writing circuit 200 is configured to receive a data scanning signal G1, the first terminal 200a of the data writing circuit 200 is electrically connected with the second terminal 100b of the driving circuit 100, and the second terminal 200b of the data writing circuit 200 is electrically connected with the data signal terminal DATA to receive a data signal DATA. The data writing circuit 200 includes a data writing transistor T1 and a first compensation capacitor Cst1 (see FIG. 2A), and the gate of the data writing transistor T1 is configured to receive the data scanning signal G1, and the first pole of the first compensation capacitor Cst1 is electrically connected with the first pole of the data writing transistor T1. For example, in the data writing and compensation phase, the data writing circuit 200 is turned on in response to the data scanning signal G1, and the data writing transistor T1 and the first compensation capacitor Cst1 cooperate to write the data signal DATA to the second terminal 100m of the driving circuit 100.

[0079] As shown in FIG. 1, the first reset circuit 300 includes a control terminal 300m, a first terminal 300a, and a second terminal 300b. The control terminal 300m of the first reset circuit 300 is configured to receive a first reset control signal RST1, the first terminal 300a of the first reset circuit 300 is electrically connected with the second terminal 100b of the driving circuit 100; the first reset circuit 300 includes a first reset transistor T2, here, the data transistor T1 is multiplexed as the first reset transistor T2, and the first pole of the first reset transistor T2 is electrically connected with the first pole of the first compensation capacitor Cst1; the second terminal 300b of the first reset circuit 300 is electrically connected with the reference signal terminal REF to receive a reference signal REF, and the first reset circuit 300 is configured to write the reference signal REF to the second terminal 100b of the driving circuit 100 in cooperation with the first compensation capacitor Cst1 in response to the first reset control signal RST1. For example, the reference signal REF can be a reference voltage. For example, in some embodiments of the present disclosure, as shown in FIG. 1, the first reset circuit 300 includes a first reset transistor T2 (see FIG. 2A), and the data writing transistor T1 can be multiplexed as the first reset transistor T2 to simplify the structure of the pixel circuit. For example, in some embodiments, the data writing circuit 200 and the first reset circuit 300 can also be independent of each other for separate control, which can be set according to design requirements, and the embodiments of the present disclosure are not limited thereto.

[0080] As shown in FIG. 1, the light emitting element 400 includes a first electrode 400a and a second electrode 400b, and is configured to emit light under the driving of a driving current. The second end 100b of the driving circuit 100 is electrically connected to the first electrode 400a of the light emitting element 400, and the driving circuit 100 is configured to control the magnitude of the driving current flowing through the light emitting element 400. For example, in one example, as shown in FIG. 1, the first electrode 400a of the light emitting element 400 is electrically connected to the fourth node N4, and the light emitting element 400 can be electrically connected to the second end 100b of the driving circuit 100 through the second light emitting control circuit 700, and embodiments of the present disclosure include but are not limited to this case. The second electrode 400b of the light emitting element 400 is electrically connected to the first voltage terminal VSS to receive the first power voltage VSS. For example, the first voltage terminal VSS can be grounded, i.e., the first power voltage VSS can be 0V. For example, the first power voltage VSS can be a negative voltage. For example, the light emitting element can be implemented as a light emitting diode (LED), which can be an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or an inorganic light emitting diode, which can be a micro light emitting diode (Micro LED) or a micro OLED, and embodiments of the present disclosure are not limited to the type of light emitting element.

[0081] The second reset circuit 500 includes a control end 500m, a first end 500a and a second end 500b. The control end 500m of the second reset circuit 500 is configured to receive a second reset control signal RST2, the first end 500a of the second reset circuit 500 is electrically connected to the first electrode 400a of the light emitting element 400, and the second end 500b of the second reset circuit 500 is electrically connected to the first reset signal terminal VINI1 to receive the first reset signal VINI1. The second reset circuit 500 is configured to apply the first reset signal VINI1 to the first electrode 400a of the light emitting element 400 and the second end 100b of the driving circuit 100 in response to the second reset control signal RST2, thereby implementing a reset operation.

[0082] The first light-emitting control circuit 600 includes a control terminal 600m, a first terminal 600a, and a second terminal 600b. The control terminal 600m of the first light-emitting control circuit 600 is configured to receive the first light-emitting control signal EM1, the first terminal 600a of the first light-emitting control circuit 600 is electrically connected with the first terminal 100a of the driving circuit 100, and the second terminal 600b of the first light-emitting control circuit 600 is electrically connected with the second voltage terminal ELVDD to receive the second power voltage ELVDD. The first light-emitting control circuit 600 is configured to apply the second power voltage ELVDD to the first terminal 100a of the driving circuit 100 in response to the first light-emitting control signal EM1. For example, in the reset phase, the first light-emitting control circuit 600 can be turned on in response to the first light-emitting control signal EM1, so that the second power voltage ELVDD can be applied to the first terminal 100a of the driving circuit 100. For example, in the light-emitting phase, the first light-emitting control circuit 600 can also be turned on in response to the first light-emitting control signal EM1, so that the second power voltage ELVDD can be applied to the first terminal 100a of the driving circuit 100. When the driving circuit 100 is turned on, the second power voltage ELVDD is written to the second terminal 100b of the driving circuit 100. The second terminal 400b of the light-emitting element 400 receives the first power voltage VSS, and the light-emitting element 400 emits light under the action of the second power voltage ELVDD and the first power voltage VSS. For example, the second power voltage ELVDD can be a high voltage, and the first power voltage VSS is a low voltage, but embodiments of the present disclosure are not limited thereto.

[0083] As shown in FIG. 1, the second light emitting control circuit 700 includes a control terminal 700m, a first terminal 700a and a second terminal 700b. The control terminal 700m of the second light emitting control circuit 700 is configured to receive the second light emitting control signal EM2, the first terminal 700a of the second light emitting control circuit 700 is electrically connected with the second terminal 100b of the driving circuit 100, and the second terminal 700b of the second light emitting control circuit 700 is electrically connected with the first electrode 400a of the light emitting element 400. The second light emitting control circuit 700 is configured to apply a driving current to the light emitting element 400 in response to the second light emitting control signal EM2 and allow the first reset signal VINI1 to be applied to the second terminal 100b of the driving circuit 100 through the second light emitting control circuit 700. For example, in the light emitting stage, the second light emitting control circuit 700 is turned on in response to the second light emitting control signal EM2, so that the driving circuit 100 can apply a driving current to the light emitting element 400 through the second light emitting control circuit 700 to make it emit light. For example, in the reset stage, the second light emitting control circuit 700 can also be turned on in response to the second light emitting control signal EM2, so that the first reset signal VINI1 can be applied to the second terminal 100b of the driving circuit 100 in combination with other circuit elements (for example, the second reset circuit 500), so as to realize the reset operation of the driving circuit 100 and the light emitting element 400. For example, in the data writing and compensation stage, the second light emitting control circuit 700 is turned off in response to the second light emitting control signal EM2, so as to avoid the light emitting element 400 from emitting light, so as to improve the contrast of the corresponding display device. For example, the first reset signal VINI1 can be a first reset voltage.

[0084] For example, as shown in FIG. 1, the second light emitting control signal EM2 is different from the first light emitting control signal EM1, for example, the two can be electrically connected to different signal output terminals. For example, in the reset stage and the light emitting stage, the first light emitting control signal EM1 and the second light emitting control signal EM2 are both open signals. For example, in the data writing and compensation stage, the first light emitting control signal EM1 and the second light emitting control signal EM2 are both closed signals to avoid the light emitting element 400 from emitting light. For example, in some embodiments of the present disclosure, the first light emitting control circuit 600 can share the same control terminal with the second light emitting control circuit 700, so as to simplify the structure of the pixel circuit and the control method, and the embodiments of the present disclosure are not limited thereto.

[0085] As shown in FIG. 1, the third reset circuit 800 includes a control terminal 800m, a first terminal 800a and a second terminal 800b. The control terminal 800m of the third reset circuit 800 is configured to receive a third reset control signal RST3, the first terminal 800a of the third reset circuit 800 is electrically connected with the first terminal 100a of the driving circuit 100, and the second terminal 800b of the third reset circuit 800 is electrically connected with the control terminal 100m of the driving circuit 100. The third reset circuit 800 is configured to allow the second power supply voltage ELVDD to be applied to the control terminal 100m of the driving circuit 100 in response to the third reset control signal RST3. For example, in the reset phase, the third reset circuit 800 is turned on in response to the third reset control signal RST3, so that the second power supply voltage ELVDD can be applied to the control terminal 100m of the driving circuit 100, thereby realizing the reset of the driving circuit 100.

[0086] As shown in FIG. 1, the compensation control circuit 900 includes a first terminal 900a and a second terminal 900b. The first terminal 900a of the compensation control circuit 900 is electrically connected with the control terminal 100m of the driving circuit 100, and the second terminal 900b of the compensation control circuit 900 is electrically connected with the first electrode 400a of the light emitting element 400. For example, the compensation control circuit 900 can include a compensation control capacitor Ca (as shown in FIG. 2A). The first pole of the compensation control capacitor Ca is electrically connected with the control terminal 100m of the driving circuit 100, and the second pole of the compensation control capacitor Ca is electrically connected with the first electrode 400a of the light emitting element 400. For example, when the light emitting stage is entered from the data writing and compensation stage, the compensation control capacitor Ca can play a bootstrap role when the voltage of the first electrode 400a of the light emitting element 400 rises, so that the voltage of the control terminal 100m of the driving circuit 100 rises, which is conducive to making the driving circuit 100 in an open state, and thus making the light emitting element 400 emit light.

[0087] FIG. 2A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 1; and FIG. 3 is a signal timing diagram of a driving method provided by at least one embodiment of the present disclosure.

[0088] For example, the pixel circuit shown in FIG. 1 can be implemented as the pixel circuit structure shown in FIG. 2A. As shown in FIG. 2A, the pixel circuit 101 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light-emitting element OLED. For example, the data writing transistor T1 (the first reset transistor T2), the first reset transistor T2, the second reset transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, and the third reset transistor T6 are used as switching transistors. For example, embodiments of the present disclosure take the light-emitting element as OLED for illustration, but are not limited thereto. For example, the light-emitting element can also adopt other light-emitting devices, and embodiments of the present disclosure do not limit this. For example, when the light-emitting element is OLED, the light-emitting element can be various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., and embodiments of the present disclosure do not limit this.

[0089] For example, as shown in FIG. 1 and FIG. 2A, the driving circuit 100 includes a driving transistor DT, a first electrode of the driving transistor DT as a first end 100a of the driving circuit 100, and electrically connected to the first node N1; a gate electrode of the driving transistor DT as a control end 100m of the driving circuit 100, and electrically connected to the second node N2; and a second electrode of the driving transistor DT as a second end 100b of the driving circuit 100, and electrically connected to the third node N3.

[0090] For example, as shown in FIG. 1 and FIG. 2A, the data writing circuit 200 includes a data writing transistor T1 and a first compensation capacitor Cst1, a gate electrode of the data writing transistor T1 electrically connected to a data scanning signal end G1 to receive a data scanning signal G1, a first electrode of the data writing transistor T1 electrically connected to a first electrode of the first compensation capacitor Cst1, a second electrode of the data writing transistor T1 electrically connected to a data signal end DATA to receive a data signal DATA, and a second electrode of the first compensation capacitor Cst1 electrically connected to a second electrode of the driving transistor DT.

[0091] For example, as shown in FIG. 1 and FIG. 2A, the first reset circuit 300 includes a first reset transistor T2, a gate electrode of the first reset transistor T2 electrically connected to a first reset control end RST1 to receive a first reset control signal RST1, a first electrode of the first reset transistor T2 electrically connected to a first electrode of the first compensation capacitor Cst1, and a second electrode of the first reset transistor T2 electrically connected to a reference signal end REF to receive a reference signal REF.

[0092] For example, as shown in FIG. 1 and FIG. 2A, the data write transistor T1 is multiplexed as the first reset transistor T2, and the data scanning signal G1 is multiplexed as the first reset control signal RST1. The second electrode of the data write transistor T1 is also electrically connected to the reference signal end REF to receive the reference signal REF, and is configured to apply the reference signal REF to the second end 100b of the driving circuit 100 together with the first compensation capacitor Cst1. For example, in the pixel circuit 101 shown in FIG. 2A, the data signal end DATA is multiplexed as the reference signal end REF, and the data signal end DATA is configured to receive the data signal DATA and the reference signal REF in different time periods, respectively, so that the data signal end DATA can receive different signals in different time periods according to the working needs of the pixel circuit, thereby simplifying the structure of the pixel circuit.

[0093] For example, in some embodiments of the present disclosure, as shown in FIG. 1 and FIG. 2A, the data signal end DATA and the reference signal end REF can also be different signal ends independent of each other, and the data signal end DATA and the reference signal end REF are both electrically connected to the second electrode of the data write transistor T1. For example, in different time periods, the data signal end DATA can apply the data signal DATA to the second electrode of the data write transistor T1, and the reference signal end REF can apply the reference signal REF to the second electrode of the data write transistor T1, thereby making the control method of the pixel circuit more flexible.

[0094] For example, as shown in FIG. 1 and FIG. 2A, the second reset circuit 500 includes a second reset transistor T3, the gate electrode of the second reset transistor T3 is electrically connected to the second reset control end RST2 to receive the second reset control signal RST2, the first electrode of the second reset transistor T3 is electrically connected to the first electrode of the light emitting element OLED, and the second electrode of the second reset transistor T3 is electrically connected to the first reset signal end VINI1 to receive the first reset signal VINI1.

[0095] For example, as shown in FIG. 1 and FIG. 2A, the first light emitting control circuit 600 includes a first light emitting control transistor T4, the gate electrode of the first light emitting control transistor T4 is electrically connected to the first light emitting control end EM1 to receive the first light emitting control signal EM1, the first electrode of the first light emitting control transistor T4 is electrically connected to the first end 100a (the first electrode of the driving transistor DT) of the driving circuit 100, and the second electrode of the first light emitting control transistor T4 is electrically connected to the second voltage end ELVDD to receive the second power voltage ELVDD.

[0096] For example, as shown in FIG. 1 and FIG. 2A, the second light-emitting control circuit 700 includes a second light-emitting control transistor T5, a gate of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control terminal EM2 to receive the second light-emitting control signal EM2, a first electrode of the second light-emitting control transistor T5 is electrically connected to the second terminal 100b (a second electrode of the driving transistor DT) of the driving circuit 100, and a second electrode of the second light-emitting control transistor T5 is electrically connected to the first electrode of the light-emitting element OLED.

[0097] For example, as shown in FIG. 1 and FIG. 2A, the third reset circuit 800 includes a third reset transistor T6, a gate of the third reset transistor T6 is electrically connected to the third reset control terminal RST3 to receive the third reset control signal RST3, a first electrode of the third reset transistor T6 is electrically connected to the first electrode (the first node N1) of the driving transistor DT, and a second electrode of the third reset transistor T6 is electrically connected to the gate (the second node N2) of the driving transistor DT.

[0098] For example, as shown in FIG. 1 and FIG. 2A, the compensation control capacitor Ca is electrically connected to the gate (the second node N2) of the driving transistor DT at a first electrode, and is electrically connected to the first electrode (the fourth node N4) of the light-emitting element OLED at a second electrode.

[0099] For example, as shown in FIG. 1 and FIG. 2A, the light-emitting element 400 can be implemented as an organic light-emitting diode (OLED). In the embodiments described below, the light-emitting element is taken as an OLED as an example, and the embodiments of the present disclosure include but are not limited to this, the light-emitting element can also be other types of electroluminescent devices such as inorganic light-emitting diodes, etc., and the embodiments of the present disclosure do not limit the type of light-emitting element.

[0100] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3 and the fourth node N4 do not necessarily represent actual components, but represent the convergence points of the relevant circuit connections in the circuit diagram. In the description of the embodiments of the present disclosure, the symbol DATA can represent both a data signal end and a data signal; similarly, the symbol G1 can represent both a data scanning signal end and a data scanning signal; the symbol REF can represent both a reference signal end and a reference signal; the symbol RST1 can represent both a first reset control signal end and a first reset control signal; the symbol RST2 can represent both a second reset control signal end and a second reset control signal; the symbol RST3 can represent both a third reset control signal end and a third reset control signal; the symbol VSS can represent both a first voltage end and a first power voltage; the symbol ELVDD can represent both a second voltage end and a second power voltage; the symbol EM1 can represent both a first light-emitting control end and a first light-emitting control signal; the symbol EM2 can represent both a second light-emitting control end and a second light-emitting control signal; the symbol VINI1 can represent both a first reset signal end and a first reset signal; the symbol VINI2 can represent both a second reset signal end and a second reset signal, and the same applies to the following embodiments, which will not be described again.

[0101] It should be noted that the transistors used in the embodiments of the present disclosure can be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as an example. The source and drain of the transistor used here can be symmetrical in structure, so that the source and drain can be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other is the second pole.

[0102] In addition, the transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). However, the type of the transistor is not limited in the embodiments of the present disclosure, and the connection relationship in the circuit can be adjusted accordingly when the type of the transistor changes.

[0103] The working principle of the pixel circuit 101 shown in FIG. 2A is described below in combination with a signal timing diagram shown in FIG. 3. As shown in FIG. 3, the display process of each frame of image includes three stages, namely, a reset stage 1, a data writing and compensation stage 2, and an emission stage 3.

[0104] It should be noted that FIG. 2A is a schematic diagram of the pixel circuit 101 in the reset stage; FIG. 2B is a schematic diagram of the pixel circuit 101 shown in FIG. 2A in the data writing and compensation stage; and FIG. 2C is a schematic diagram of the pixel circuit 101 shown in FIG. 2A in the emission stage. In addition, the transistors identified by dashed lines in FIGS. 2B and 2C are all in the off state in the corresponding stage.

[0105] For example, in the pixel circuit 101 shown in FIG. 2A, the driving transistor DT, the data writing transistor T1 (the first reset transistor T2), the second reset transistor T3, the first emission control transistor T4, the second emission control transistor T5, and the third reset transistor T6 are all N-type transistors, that is, each transistor is turned on when a high-level signal is input to the gate thereof, and is turned off when a low-level signal is input to the gate thereof.

[0106] As shown in FIGS. 2B and 3, the embodiment of the present disclosure provides a driving method, which includes: in the data writing and compensation stage, making the data scanning signal G1 an on signal to turn on the data writing transistor T1, and writing the data signal DATA into the second end 100b (i.e., the second electrode of the driving transistor DT) of the driving circuit 100 through the data writing transistor T1 and the first compensation capacitor Cst1. For the pixel circuit 101, when the data writing transistor T1 is turned on, the data signal DATA is first applied to the first electrode of the first compensation capacitor Cst1, so that the voltage change of the second electrode of the first compensation capacitor Cst1 changes the voltage of the second electrode of the driving transistor DT, and then the voltage of the second electrode of the driving transistor DT reaches a specific value. For example, when the data writing transistor T1 is switched from the on state to the off state when entering the emission stage 3 from the data writing and compensation stage 2, due to the parasitic capacitance between the gate of the data writing transistor T1 and the first electrode thereof, and under the voltage division effect of the parasitic capacitance and the first compensation capacitor Cst1, the voltage change of the first electrode of the first compensation capacitor Cst1 is small, and then the voltage change of the second electrode of the first compensation capacitor Cst1 is also small, so that the influence of the data writing transistor T1 on the voltage of the second electrode of the driving transistor DT when the data writing transistor T1 is turned off can be reduced, and the stability of the driving current flowing through the driving transistor DT can be maintained, so as to improve the uniformity of the brightness of the display panel.

[0107] Specifically, for example, as shown in FIG. 1 and FIG. 3, in the reset stage 1, the driving method comprises: taking the first reset control signal RST1 as an opening signal to open the first reset circuit 300, the first reset circuit 300 applies the reference signal REF to the first pole of the first compensation capacitor Cst1; and taking the first light-emitting control signal EM1 as an opening signal to open the first light-emitting control circuit 600, the first light-emitting control circuit 600 applies the second power supply voltage ELVDD to the first end 100a of the driving circuit 100; taking the third reset control signal RST3 as an opening signal to open the third reset circuit 800, the third reset circuit 800 applies the second power supply voltage ELVDD to the control end 100m of the driving circuit 100; taking the second light-emitting control signal EM2 as an opening signal to open the second light-emitting control circuit 700; and taking the second reset control signal RST2 as an opening signal to open the second reset circuit 500, the second reset circuit 500 applies the first reset signal VINI1 to the first electrode 400a of the light-emitting element 400, the first reset signal VINI1 is applied to the second end 100b of the driving circuit 100 through the second light-emitting control circuit 700, and the value of the first reset signal VINI1 is Vini1, so that the initial voltage value of the second end 100b of the driving circuit 100 before entering the data writing and compensation stage is Vini1.

[0108] Correspondingly, for example, as shown in FIG. 2A and FIG. 3, in the reset stage 1, in the pixel circuit 101, since the data writing transistor T1 is multiplexed as the first reset transistor T2 and the data scanning signal G1 is multiplexed as the first reset control signal RST1, the data scanning signal G1 is taken as a high-level signal to open the data writing transistor T1, the reference signal REF can be applied to the first pole of the data writing transistor T1, and then applied to the first pole of the first compensation capacitor Cst1. And the first light-emitting control signal EM1 is taken as a high-level signal to open the first light-emitting control transistor T4, and the third reset control signal RST3 is taken as a high-level signal to open the third reset transistor T6, so that the second power supply voltage ELVDD can be applied to the first pole of the driving transistor DT and applied to the gate of the driving transistor DT through the third reset transistor T6. At the same time, the second light-emitting control signal EM2 is taken as a high-level signal to open the second light-emitting control transistor T5, and the second reset control signal RST2 is taken as a high-level signal to open the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (the fourth node N4) of the light-emitting element OLED and applied to the second pole (the third node N3) of the driving transistor DT through the second light-emitting control transistor T5, so that the voltage value of the second pole of the driving transistor DT and the voltage value of the first electrode of the light-emitting element OLED are both equal to the value Vini1 of the first reset signal VINI1.

[0109] For example, as shown in FIG. 1 and FIG. 3, the driving method further comprises: in the data writing and compensation phase 2, the data scanning signal G1 is a high signal to turn on the data writing transistor T1, and the data signal DATA is written to the second end 100b (i.e. the second electrode of the driving transistor DT) of the driving circuit 100 through the data writing transistor T1 and the first compensation capacitor Cst1, and the second reset control signal RST2 is a high signal to turn on the second reset circuit 500, and the second reset circuit 500 applies the first reset signal VINI1 to the first electrode 400a of the light emitting element 400 and the second electrode of the compensation control capacitor Ca.

[0110] Specifically, as shown in FIG. 2B and FIG. 3, in the data writing and compensation phase 2, the second reset control signal RST2 is a high signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (the fourth node N4) of the light emitting element OLED and the second electrode of the compensation control capacitor Ca, so that the voltage value of the first electrode (the fourth node N4) of the light emitting element OLED is equal to the value Vini1 of the first reset signal VINI1, thereby avoiding the light emitting element OLED emitting light in the data writing and compensation phase 2. At the same time, the data scanning signal G1 is a high signal to turn on the data writing transistor T1, so that the data signal DATA is applied to the first electrode of the first compensation capacitor Cst1.

[0111] For example, as shown in FIG. 2B and FIG. 3, in the data writing and compensation phase 2, the difference between the initial voltage value Vc11 of the first electrode of the first compensation capacitor Cst1 before entering the data writing and compensation phase and the stable voltage value Vc12 thereof in the data writing and compensation phase is the first change amount AVc1; the difference between the initial voltage value Vc13 of the second electrode of the first compensation capacitor Cst1 before entering the data writing and compensation phase and the stable voltage value Vc14 thereof in the data writing and compensation phase is the second change amount AVc2, and the first change amount AVc1 is equal to the second change amount AVc2.

[0112] For example, as shown in FIG. 2B and FIG. 3, the initial voltage value Vc11 of the first pole of the first compensation capacitor Cst1 before entering the data writing and compensation stage is the value Vref of the reference signal REF, and the stable voltage value Vc12 of the first compensation capacitor Cst1 in the data writing and compensation stage is the value Vdata of the data signal DATA, so the first variation amount AVc1 = Vdata - Vref. The initial voltage value Vc13 of the second pole of the first compensation capacitor Cst1 before entering the data writing and compensation stage is the value Vini1 of the first reset signal VINI1, and according to the characteristic that the voltage of the first pole and the second pole of the first compensation capacitor Cst1 cannot be abrupt, the voltage of the second pole of the first compensation capacitor Cst1 also has the first variation amount AVc1, that is, the second variation amount AVc2 is equal to the first variation amount AVc1. Therefore, the voltage variation amount of the second end of the driving transistor DT is also equal to the first variation amount AVc1. The initial voltage value of the second end of the driving transistor DT before entering the data writing and compensation stage is the value Vini1 of the first reset signal VINI1, so the stable voltage value of the second end of the driving transistor DT in the data writing and compensation stage is Vini1 + AVc1 (AVc2) = Vini1 + Vdata - Vref.

[0113] For example, as shown in FIG. 2B and FIG. 3, before entering the data writing and compensation stage, the initial voltage of the gate of the driving transistor DT is the second power supply voltage ELVDD, and the difference (Vgs) between the second power supply voltage ELVDD and the value Vini1 of the first reset signal VINI1 is greater than the threshold voltage Vth of the driving transistor DT, that is, Vgs = ELVDD - Vini1 > Vth, so the driving transistor DT is in the on state, the first pole of the driving transistor DT charges to the second pole of the driving transistor DT until the driving transistor DT is turned off (turned off), so that the gate-source voltage Vgs of the driving transistor DT is Vth, at this time the voltage value of the gate of the driving transistor DT (the voltage value of the first pole of the compensation control capacitor Ca) is Vini1 + Vdata - Vref + Vth, so that the charging process can make the threshold voltage Vth information of the driving transistor DT be stored in the compensation control capacitor Ca, thereby completing the data writing and compensation process.

[0114] For example, as shown in FIG. 1 and FIG. 3, in the light emitting stage 3, the first light emitting control signal EM1 is an on signal to turn on the first light emitting control circuit 600, and the first light emitting control circuit 600 applies the second power supply voltage ELVDD to the first end 100a of the driving circuit 100; the second light emitting control signal EM2 is an on signal to turn on the second light emitting control circuit 700, and the second light emitting control circuit 700 applies a driving current to the first electrode 400a of the light emitting element 400 to drive it to emit light.

[0115] Correspondingly, as shown in FIG. 2C and FIG. 3, in the light emitting stage 3, the first light emitting control signal EM1 is a high level signal to turn on the first light emitting control transistor T4, and the second power voltage ELVDD is applied to the first electrode of the driving transistor DT. Meanwhile, the second light emitting control signal EM2 is a high level signal to turn on the second light emitting control transistor T5, and the driving current is applied to the light emitting element OLED via the second light emitting control transistor T5 to make the light emitting element OLED emit light.

[0116] For example, as shown in FIG. 2C and FIG. 3, in the light emitting stage 3, since the light emitting element OLED is in the light emitting state, the voltage value of the first electrode of the light emitting element OLED (the voltage value of the fourth node N4) and the voltage value of the second electrode of the driving transistor DT both correspond to the voltage value Voled of the light emitting element OLED when it emits light, so the variation amount AV of the voltage value of the first electrode of the light emitting element OLED is AV = Voled-Vini1. Accordingly, the compensation control capacitor Ca can play a bootstrap role to make the first electrode of the compensation control capacitor Ca also have the variation amount AV, so that the voltage value of the gate of the driving transistor DT (the voltage value of the second node N2) has the variation amount AV, so that the voltage value of the gate of the driving transistor DT is Vini1+Vdata-Vref+Vth+AV = Vini1+Vdata-Vref+Vth+Voled-Vini1. The driving transistor DT is in the on state, and the gate-source voltage Vgs of the driving transistor DT is Vini1+Vdata-Vref+Vth+Voled-Vini1-Voled = Vdata-Vref+Vth.

[0117] The value I of the driving current flowing through the light emitting element can be obtained according to the following formula:

[0118] I = K x (Vgs-Vth) 2 , K is the conductive coefficient of the driving transistor DT. That is:

[0119] I = K x (Vdata-Vref) 2

[0120] According to the above formula, the value I of the driving current flowing through the light emitting element is no longer related to the threshold voltage Vth of the driving transistor DT, so that the compensation of the pixel circuit can be realized, the problem of threshold voltage Vth drift of the driving transistor DT caused by process and long time operation is solved, and the influence of the threshold voltage Vth on the driving current is eliminated, so that the display effect of the display device using the pixel circuit can be improved.

[0121] For example, as shown in FIG. 2B, FIG. 2C and FIG. 3, when entering from the data writing and compensation stage 2 to the light emitting stage 3, the data writing transistor T1 is switched from the open state to the closed state, and in this process, due to the parasitic capacitance between the gate of the data writing transistor T1 and the first electrode thereof, and the fact that the parasitic capacitance is in series with the first storage capacitor Cst1, when the voltage of the gate of the data writing transistor T1 decreases, the parasitic capacitance between the gate of the data writing transistor T1 and the first electrode thereof and the first storage capacitor Cst1 can perform voltage division, so that the change amount of the voltage value of the first electrode of the first storage capacitor Cst1 is small. For example, the voltage value of the parasitic capacitance between the gate of the data writing transistor T1 and the first electrode thereof can be C0, and the voltage value of the first storage capacitor Cst1 can be C1, so when the voltage value of the gate of the data writing transistor T1 decreases by △V1, the change amount of the voltage value of the first storage capacitor Cst1 is △V1×C0 / (C0+C1), and since the voltage value C0 of the parasitic capacitance between the gate of the data writing transistor T1 and the first electrode thereof is usually much smaller than the voltage value C1 of the first storage capacitor Cst1, the change amount of the voltage value of the first storage capacitor Cst1 will also be correspondingly small. Therefore, by electrically connecting the first electrode of the data writing transistor T1 and the first electrode of the first storage capacitor Cst1, and electrically connecting the second electrode of the first storage capacitor Cst1 and the second electrode of the driving transistor DT, the influence of the data writing transistor T1 being switched from the open state to the closed state on the voltage of the second electrode of the driving transistor DT can be reduced, so that the change amount of the voltage value of the second electrode of the driving transistor DT is small, so that the difference between the gate voltage of the driving transistor DT and the voltage of the second electrode of the driving transistor DT (i.e. the gate-source voltage Vgs of the driving transistor DT) is basically unchanged or fluctuates little, so as to make the driving current flowing through the light emitting element more stable, and make the brightness of the display panel more uniform.

[0122] In the pixel circuit provided by the embodiments of the present application, by combining the data writing transistor T1 with the first storage capacitor Cst1 and other elements, not only the technical problem of how to compensate the threshold voltage Vth of the driving transistor DT is solved to eliminate its influence on the driving current, but also when entering from the data writing and compensation stage to the light emitting stage, the influence of the data writing transistor T1 being switched to the closed state on the gate-source voltage Vgs of the driving transistor DT is small, so that the driving current is more stable, and the display effect of the display panel is improved.

[0123] For example, as shown in FIG. 2A, the capacitance value C1 of the first compensation capacitor Cst1 can be 30 times to 100 times, for example, at least one of 30 times to 50 times, 40 times to 80 times, 50 times to 70 times, and 60 times to 90 times, of the capacitance value C0 of the parasitic capacitance between the gate of the data write transistor T1 and the first electrode of the data write transistor T1, but embodiments of the present disclosure are not limited thereto. In this way, when the voltage value of the gate of the data write transistor T1 decreases by AV1, the change amount AV1xC0 / (C0+C1) of the voltage value of the first storage capacitor Cst1 is small, so that the influence on the gate-source voltage Vgs of the drive transistor DT when the data write transistor T1 turns to the off state can be reduced.

[0124] For example, as shown in FIG. 2A, the capacitance value C1 of the first compensation capacitor Cst1 can be 100 fF to 300 fF, for example, at least one of 100 fF to 150 fF, 120 fF to 180 fF, 200 fF to 250 fF, 230 fF to 250 fF, and 240 fF to 280 fF, but embodiments of the present disclosure are not limited thereto. For example, the capacitance value C0 of the parasitic capacitance between the gate of the data write transistor T1 and the first electrode thereof can be 3 fF to 5 fF, for example, 3 fF, 3.5 fF, 4 fF, and 4.5 fF, but embodiments of the present disclosure are not limited thereto.

[0125] FIG. 4 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0126] For example, as shown in FIG. 4, the pixel circuit 20 includes a drive circuit 100, a data write circuit 200 (a first reset circuit 300), a light emitting element 400, a second reset circuit 500, a first light emitting control circuit 600, a second light emitting control circuit 700, a third reset circuit 800, and a compensation control circuit 900. Compared with the pixel circuit 10 shown in FIG. 1, the difference of the pixel circuit 20 is that the control end 200m of the data write circuit 200 is electrically connected with the control end 500m of the second reset circuit 500. For example, the data scanning signal G1 and the second reset control signal RST2 can be the same control signal to simultaneously control the opening and closing of the data write circuit 200 and the second reset circuit 500, so that the structure of the pixel circuit can be simplified. For the other structures in the pixel circuit 20, refer to the related description of FIG. 1 in the above embodiments, which will not be repeated here.

[0127] FIG. 5A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 4; FIG. 6 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure. It should be noted that FIG. 5A is a schematic diagram of the pixel circuit 102 in a reset stage; FIG. 5B is a schematic diagram of the pixel circuit 102 shown in FIG. 5A in a data writing and compensation stage; FIG. 5C is a schematic diagram of the pixel circuit 102 shown in FIG. 5A in a light emitting stage. In addition, the transistors identified by dashed lines in FIG. 5B and FIG. 5C are all in an off state in the corresponding stage.

[0128] For example, the pixel circuit shown in FIG. 4 can be implemented as the pixel circuit structure shown in FIG. 5A.

[0129] For example, as shown in FIG. 5A, the pixel circuit 102 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light emitting control transistor T4, a second light emitting control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light emitting element OLED. For example, the pixel circuit 102 is different from the pixel circuit 101 (as shown in FIG. 2A) in that the gate of the data writing transistor T1 is electrically connected to the gate of the second reset transistor T3, the data writing transistor T1 and the second reset transistor T3 share a gate, the data scanning signal G1 is used as the second reset control signal RST2, and the type of the data writing transistor T1 is the same as the type of the second reset transistor T3.

[0130] For example, as shown in FIG. 5A, the timing diagram corresponding to the pixel circuit 102 can be referred to FIG. 6. For example, in the driving process of the pixel circuit 102, the working state (for example, an on state or an off state) of each transistor is the same as that of the pixel circuit 101 shown in FIG. 2A. Compared with the timing diagram shown in FIG. 3, the timing states of the data signal DATA, the first reset control signal RST1, the second reset control signal RST2, the third reset control signal RST3, the data scanning signal G1, the first light emitting control signal EM1, and the second light emitting control signal EM2 in the timing diagram of FIG. 6 are unchanged, and the difference is that the data scanning signal G1 is multiplexed as the second reset control signal RST2.

[0131] For example, as shown in FIG. 5A and FIG. 6, the data writing transistor T1 and the second reset transistor T3 are both N-type transistors. For example, in the reset stage 1, the data scanning signal G1 is a high-level signal, the data writing transistor T1 is the second reset transistor T2, and the data scanning signal G1 can be used as the first reset control signal RST1 to turn on the second reset transistor T2, so that the reference signal REF is applied to the first electrode of the data writing transistor T1. Meanwhile, the data scanning signal G1 is also used as the second reset control signal RST2 to turn on the second reset transistor T3, and the first reset signal VINI1 is applied to the first electrode of the light emitting element OLED.

[0132] For example, as shown in FIG. 5B and FIG. 6, in the data writing and compensation stage 2, the data scanning signal G1 is a high-level signal, and the data writing transistor T1 is turned on in response to the data scanning signal G1, so that the data signal DATA is applied to the first electrode of the first compensation capacitor Cst1. Meanwhile, the data scanning signal G1 is also used as the second reset control signal RST2 to turn on the second reset transistor T3, and the first reset signal VINI1 is applied to the first electrode of the light emitting element OLED.

[0133] For example, as shown in FIG. 5C and FIG. 6, in the light emitting stage 3, the data scanning signal G1 is a low-level signal, and the data writing transistor T1 and the second reset transistor T3 are both turned off in response to the data scanning signal G1. For the working process of the pixel circuit 102 in the reset stage 1, the data writing and compensation stage 2, and the light emitting stage 3 shown in FIG. 5A and the corresponding technical effects, reference can be made to the related descriptions about FIG. 2A-FIG. 2C in the above-mentioned embodiments, which will not be repeated here.

[0134] For example, as shown in FIG. 5A, by making the data writing transistor T1 and the second reset transistor T3 in the pixel circuit 102 share the same gate electrode, the opening and closing states of the data writing transistor T1 and the second reset transistor T3 can be controlled simultaneously by the same control signal (i.e., the data scanning signal G1), so that the structure of the pixel circuit 102 is simplified, and the control method of the pixel circuit 102 is also more convenient.

[0135] For example, referring to FIG. 5A, the gate of the data writing transistor T1 and the gate of the second reset transistor T3 can also be independent of each other and not electrically connected. For example, as shown in FIG. 2A, the data scanning signal G1 and the second reset control signal RST2 can be different signals, for example, the two can be electrically connected to different signal output terminals to control the on and off states of the data writing transistor T1 and the second reset transistor T3, respectively. For example, in some embodiments of the present disclosure, the gate of the data writing transistor T1 and the gate of the reset control signal RST2 can be independent of each other, the data scanning signal G1 and the second reset control signal RST2 can be electrically connected to the same signal output terminal, and the data scanning signal G1 is applied to the gate of the data writing transistor T1, and the second reset control signal RST2 is applied to the gate of the second reset transistor T3. The embodiments of the present disclosure do not limit whether the gate of the data writing transistor T1 and the gate of the reset control signal RST2 are electrically connected, and can be flexibly adjusted according to design requirements.

[0136] FIG. 7 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0137] For example, as shown in FIG. 7, the pixel circuit 30 includes a driving circuit 100, a data writing circuit 200, a first reset circuit 300, a light emitting element 400, a second reset circuit 500, a first light emitting control circuit 600, a second light emitting control circuit 700, a third reset circuit 800, and a compensation control circuit 900. Compared with the pixel circuit 10 shown in FIG. 1, the difference of the pixel circuit 30 is that the control end 200m of the data writing circuit 200 and the control end 300m of the first reset circuit 300 are independent of each other. The control end 200m of the data writing circuit 200 is configured to receive a data scanning signal G1, and the control end 300m of the first reset circuit 300 is configured to receive a first reset control signal RST1. The data scanning signal G1 and the first reset control signal RST1 can be different signals, and the two can come from different signal terminals, respectively.

[0138] For the other structures in the pixel circuit 30, refer to the related descriptions about FIG. 1 in the above embodiments, which will not be repeated here.

[0139] FIG. 8A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 7; FIG. 9 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure. It should be noted that FIG. 8B is a schematic diagram of the pixel circuit 103 shown in FIG. 8A in a reset stage; FIG. 8C is a schematic diagram of the pixel circuit 103 shown in FIG. 8A in a data writing and compensation stage; and FIG. 8D is a schematic diagram of the pixel circuit 103 shown in FIG. 8A in a light emitting stage. In addition, the transistors identified by the dashed lines in FIGS. 8B-8D are all in the off state in the corresponding stage.

[0140] For example, the pixel circuit shown in FIG. 7 can be implemented as the pixel circuit structure shown in FIG. 8A.

[0141] For example, as shown in FIG. 8A, the pixel circuit 103 includes a driving transistor DT, a data writing transistor T1, a first reset transistor T2, a second reset transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light-emitting element OLED. For example, the pixel circuit 103 is different from the pixel circuit 101 (as shown in FIG. 2A) in that the data writing transistor T1 and the first reset transistor T2 are respectively transistors controlled independently of each other, the gate of the data writing transistor T1 is electrically connected to the data control end G1, the gate of the first reset transistor T2 is electrically connected to the first reset control end RST1, and the data control end G1 and the first reset control end RST1 are respectively different signal ends independent of each other, and the data signal end DATA and the reference signal end REF are respectively different signal ends independent of each other. In this way, the data writing transistor T1 and the first reset transistor T2 can be independently controlled, so that the pixel circuit 103 has a more flexible control mode.

[0142] For example, the timing diagram corresponding to the pixel circuit 103 can be referred to FIG. 9. For example, as shown in FIG. 8A and FIG. 9, in the driving process of the pixel circuit 103, the working state (for example, the open state or the closed state) of each transistor is different from that of the pixel circuit 101 shown in FIG. 2A in that the working state of the data writing transistor T1 and the first reset transistor T2 is not the same. For example, compared with the timing diagram shown in FIG. 3, the timing state of the data signal DATA, the second reset control signal RST2, the third reset control signal RST3, the first light-emitting control signal EM1, and the second light-emitting control signal EM2 in the timing diagram of FIG. 9 is unchanged, and the difference is that the timing state of the data scanning signal G1 and the first reset control signal RST1 is different.

[0143] For example, as shown in FIG. 8B and FIG. 9, in the reset phase 1, the data scanning signal G1 is a low-level signal, so that the data writing transistor T1 is in the closed state. The first reset control signal RST1 is a high-level signal, so that the first reset transistor T2 is in the open state, and the reference signal REF is applied to the first pole of the first compensation capacitor Cst1 via the first reset transistor T2.

[0144] For example, as shown in FIG. 8C and FIG. 9, in the data writing and compensation phase 2, the data scanning signal G1 is a high-level signal, so that the data writing transistor T1 is in an open state, and the data signal DATA is applied to the first pole of the first compensation capacitor Cst1 via the data writing transistor T1, and then written to the second pole of the driving transistor DT. The first reset control signal RST1 is a low-level signal, so that the first reset transistor T2 is in a closed state.

[0145] For example, as shown in FIG. 8D and FIG. 9, in the light emitting phase 3, the data scanning signal G1 and the first reset control signal RST1 are both low-level signals, so that the data writing transistor T1 and the first reset transistor T2 are both in a closed state. The working process and the corresponding technical effects of the pixel circuit 103 shown in FIG. 8A in the reset phase 1, the data writing and compensation phase 2, and the light emitting phase 3 can be referred to the related description of FIG. 2A-FIG. 2C in the above-mentioned embodiments, which will not be repeated here.

[0146] For example, as shown in FIG. 8A, by making the data writing transistor T1 and the first reset transistor T2 be transistors independently controlled by each other, the control method of the pixel circuit 103 can be more flexible to adapt to different design requirements.

[0147] For example, referring to FIG. 8A, in some embodiments of the present disclosure, when the data writing transistor T1 and the first reset transistor T2 are transistors independently controlled by each other, and the data control end G1 and the first reset control end RST1 are different signal ends independently from each other, the data signal end DATA and the reference signal end REF are different signal ends independently from each other, the type of the data writing transistor T1 can also be different from the type of the first reset transistor T2. For example, the data writing transistor T1 can be an N-type transistor, and the first reset transistor T2 can be a P-type transistor; or the data writing transistor T1 can be a P-type transistor, and the first reset transistor T2 can be an N-type transistor, as long as the data writing transistor T1 and the first reset transistor T2 are in specific states in different control phases, that is, the data writing transistor T1 is in a closed state in the reset phase 1 and the light emitting phase 3, and in an open state in the data writing and compensation phase 2; the first reset transistor T2 is in an open state in the reset phase 1, and in a closed state in the data writing and compensation phase 2 and the light emitting phase 3, so as to adapt to more flexible design requirements.

[0148] FIG. 10 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0149] For example, as shown in FIG. 10, the pixel circuit 40 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light emitting element 400, a second reset circuit 500, a first light emitting control circuit 600, a second light emitting control circuit 700, a third reset circuit 800, a compensation control circuit 900, and a direct reset circuit 550. Compared with the pixel circuit 10 shown in FIG. 1, the difference of the pixel circuit 40 is that the direct reset circuit 550 is added, and the other structures in the pixel circuit 40 can refer to the related descriptions about FIG. 1 in the above embodiments, which will not be repeated here.

[0150] For example, as shown in FIG. 10, the control end 550m of the direct reset circuit 550 is configured to receive a direct reset control signal RST0, the first end 550a of the direct reset circuit 550 is electrically connected with the second end 100b of the driving circuit 100, the second end 550b of the direct reset circuit 550 is electrically connected with the second reset signal end VINI2 to receive the second reset signal VINI2, and the direct reset circuit 550 is configured to directly apply the second reset signal VINI2 to the second end 100b of the driving circuit 100 in response to the direct reset control signal RST0. For example, when the direct reset control signal RST0 is an enable signal, the direct reset circuit 550 is enabled in response to the direct reset control signal RST0, so that the second reset signal VINI2 can be directly applied to the second end 100b of the driving circuit 100. The direct application of the second reset signal VINI2 to the second end 100b of the driving circuit 100 means that no other elements such as transistors and capacitors are arranged between the direct reset circuit 550 and the driving circuit 100, so that the second reset signal VINI2 can be applied to the second end 100b of the driving circuit 100 without passing through other elements such as transistors and capacitors except the reset circuit 550. In this way, the second end 100b of the driving circuit 100 can be reset more accurately and more quickly by the direct reset circuit 550, so that the voltage of the second end 100b of the driving circuit 100 in the reset stage is more accurate.

[0151] FIG. 11A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 10; FIG. 12 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure. It should be noted that FIG. 11B is a schematic diagram of the pixel circuit 104 shown in FIG. 11A in a reset stage; FIG. 11C is a schematic diagram of the pixel circuit 104 shown in FIG. 11A in a data writing and compensation stage; and FIG. 11D is a schematic diagram of the pixel circuit 104 shown in FIG. 11A in a light emitting stage. In addition, the transistors identified by the dashed lines in FIGS. 11B-11D are in an off state in the corresponding stage.

[0152] For example, the pixel circuit shown in FIG. 10 can be implemented as the pixel circuit structure shown in FIG. 11A.

[0153] For example, as shown in FIG. 11A, the pixel circuit 104 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a third reset transistor T6, a direct reset transistor T7, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light-emitting element OLED. For example, the pixel circuit 104 is different from the pixel circuit 101 (as shown in FIG. 2A) in that the direct reset transistor T7 is added.

[0154] For example, as shown in FIG. 11A, the direct reset circuit 550 includes the direct reset transistor T7, a gate of the direct reset transistor T7 is electrically connected to the direct reset control signal end RST0 to receive the direct reset control signal RST0, a first electrode of the direct reset transistor T7 is electrically connected to the second end 100b of the driving circuit 100, and a second electrode of the direct reset transistor T7 is electrically connected to the second reset signal end VINI2 to receive the second reset signal VINI2. For example, no other elements such as transistors and capacitors are arranged between the second electrode of the driving transistor DT and the direct reset transistor T7, so that the second reset signal VINI2 can be directly applied to the second electrode of the driving transistor DT when the direct reset transistor T7 is turned on.

[0155] For example, the timing diagram corresponding to the pixel circuit 104 can be referred to FIG. 12. For example, as shown in FIG. 11A and FIG. 12, the pixel circuit 104 is different from the pixel circuit 101 shown in FIG. 2A in that the direct reset transistor T7 is added, and the working states (for example, the on state or the off state) of each transistor at different control stages are the same. For example, compared with the timing diagram shown in FIG. 3, the timing states of the data signal DATA, the second reset control signal RST2, the third reset control signal RST3, the first light-emitting control signal EM1, the second light-emitting control signal EM2, and the data scanning signal G1 in the timing diagram in FIG. 12 are unchanged, and the difference is that the timing state corresponding to the direct reset control signal RST0 is added.

[0156] For example, as shown in FIG. 11B and FIG. 12, in the reset stage 1, in the pixel circuit 104, since the data write transistor T1 is multiplexed as the first reset transistor T2 and the data scanning signal G1 is multiplexed as the first reset control signal RST1, the data scanning signal G1 is a high-level signal to turn on the data write transistor T1, and the reference signal REF can be applied to the first electrode of the data write transistor T1 and then applied to the first electrode of the first compensation capacitor Cst1. Secondly, the first light-emitting control signal EM1 is a high-level signal to turn on the first light-emitting control transistor T4, and the third reset control signal RST3 is a high-level signal to turn on the third reset transistor T6, so that the second power supply voltage ELVDD can be applied to the first electrode of the driving transistor DT and then applied to the gate electrode of the driving transistor DT through the third reset transistor T6. At the same time, the second light-emitting control signal EM2 is a low-level signal to turn off the second light-emitting control transistor T5, and the second reset control signal RST2 is a high-level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (the fourth node N4) of the light-emitting element OLED, so that the voltage value of the first electrode of the light-emitting element OLED is the value Vini1 of the first reset signal VINI1.

[0157] For example, as shown in FIG. 10 and FIG. 11B, in the reset stage 1, the driving method further includes: the direct reset control signal RST0 is an on signal to turn on the direct reset circuit 550, and the second reset signal VINI2 is applied to the second end 100b of the driving circuit 100, and the value of the second reset signal VINI2 is Vini2, so that the initial voltage value of the second end 100b of the driving circuit 100 before entering the data write and compensation stage is Vini2. Specifically, for example, as shown in FIG. 11B and FIG. 12, the direct reset control signal RST0 is a high-level signal to turn on the direct reset transistor T7, so that the second reset signal VINI2 is applied to the second electrode of the driving transistor DT to reset the voltage of the second electrode of the driving transistor DT, and the voltage value of the second electrode of the driving transistor DT is the value Vini2 of the second reset signal VINI2.

[0158] For example, as shown in FIG. 11B and FIG. 12, in the data writing and compensation stage 2, the second reset control signal RST2 is a high level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (the fourth node N4) of the light emitting element OLED and the second electrode of the compensation control capacitor Ca, so that the voltage value of the first electrode of the light emitting element OLED is the value Vini1 of the first reset signal VINI1, thereby avoiding the light emitting element OLED emitting light in the data writing and compensation stage 2. At the same time, the data scanning signal G1 is a high level signal to turn on the data writing transistor T1, so that the data signal DATA is applied to the first electrode of the first compensation capacitor Cst1.

[0159] For example, as shown in FIG. 11C and FIG. 12, in the data writing and compensation stage 2, the difference between the initial voltage value Vc11 of the first electrode of the first compensation capacitor Cst1 before entering the data writing and compensation stage and the stable voltage value Vc12 of the first electrode of the first compensation capacitor Cst1 in the data writing and compensation stage is the first change amount AVc1; the difference between the initial voltage value Vc13 of the second electrode of the first compensation capacitor Cst1 before entering the data writing and compensation stage and the stable voltage value Vc14 of the second electrode of the first compensation capacitor Cst1 in the data writing and compensation stage is the second change amount AVc2, and the first change amount AVc1 is equal to the second change amount AVc2.

[0160] For example, as shown in FIG. 11C and FIG. 12, the initial voltage value Vc11 of the first electrode of the first compensation capacitor Cst1 before entering the data writing and compensation stage is the voltage value Vref corresponding to the reference signal REF, and the stable voltage value Vc12 of the first compensation capacitor Cst1 in the data writing and compensation stage is the voltage value Vdata corresponding to the data signal DATA, so that the first change amount AVc1 = Vdata-Vref. The initial voltage value Vc13 of the second electrode of the first compensation capacitor Cst1 before entering the data writing and compensation stage is the value Vini2 of the second reset signal VINI2, and according to the characteristic that the voltages of the first electrode and the second electrode of the first compensation capacitor Cst1 cannot be suddenly changed, the voltage of the second electrode of the first compensation capacitor Cst1 also has the first change amount AVc1, that is, the second change amount AVc2 is equal to the first change amount AVc1. Therefore, the voltage change amount of the second end of the driving transistor DT is also the first change amount AVc1. The initial voltage value of the second end of the driving transistor DT before entering the data writing and compensation stage is the value Vini2 of the second reset signal VINI2, so that the stable voltage value of the second end of the driving transistor DT in the data writing and compensation stage is Vini2+AVc1(△Vc2)=Vini2+Vdata-Vref.

[0161] For example, as shown in FIG. 11C and FIG. 12, before entering the data writing and compensation stage, the initial voltage of the gate of the driving transistor DT is the second power supply voltage ELVDD, and the difference (Vgs) between the second power supply voltage ELVDD and the value Vini2 of the second reset signal VINI2 is greater than the threshold voltage Vth of the driving transistor DT, i.e. Vgs = ELVDD - Vini2 > Vth, thus the driving transistor DT is in the on state, the first pole of the driving transistor DT charges to the second pole of the driving transistor DT until the driving transistor DT is turned off (closed) to make the gate-source voltage Vgs of the driving transistor DT Vth, at this time the voltage value of the gate of the driving transistor DT (the voltage value of the first pole of the compensation control capacitor Ca) is Vini2 + Vdata - Vref + Vth, so that the charging process can make the threshold voltage Vth of the driving transistor DT and other information stored in the compensation control capacitor Ca, thereby completing the data writing and compensation process.

[0162] For example, as shown in FIG. 11D and FIG. 12, in the light emitting stage 3, the first light emitting control signal EM1 is a high level signal to turn on the first light emitting control transistor T4, and the second power supply voltage ELVDD is applied to the first pole of the driving transistor DT. At the same time, the second light emitting control signal EM2 is a high level signal to turn on the second light emitting control transistor T5, and the driving current is applied to the light emitting element OLED through the second light emitting control transistor T5 to make it emit light.

[0163] For example, as shown in FIG. 11D and FIG. 12, in the light emitting stage 3, since the light emitting element OLED is in the light emitting state, the voltage value of the first electrode of the light emitting element OLED (the voltage value of the fourth node N4) and the voltage value of the second pole of the driving transistor DT are both the voltage value Voled corresponding to the light emitting state of the light emitting element OLED, so the change amount AV of the voltage value of the first electrode of the light emitting element OLED is AV = Voled - Vini1. Accordingly, the compensation control capacitor Ca plays a bootstrap role, so that the first pole of the compensation control capacitor Ca also has a change amount AV, thereby making the voltage value of the gate of the driving transistor DT (the voltage value of the second node N2) have a change amount AV, so that the voltage value of the gate of the driving transistor DT is Vini2 + Vdata - Vref + Vth + AV = Vini2 + Vdata - Vref + Vth + Voled - Vini1. The driving transistor DT is in the on state, and the gate-source voltage Vgs of the driving transistor DT is Vgs = Vini2 + Vdata - Vref + Vth + Voled - Voled = (Vini2 - Vini1) + Vdata - Vref + Vth.

[0164] The value I of the driving current flowing through the light emitting element can be obtained according to the following formula:

[0165] I = K x (Vgs - Vth) 2 , K is the conductivity coefficient of the driving transistor DT. That is:

[0166] I = K x (Vini2 - Vini1 + Vdata - Vref) 2

[0167] For example, as shown in FIG. 11D, the value Vini1 of the first reset signal VINI1 can be equal to the value Vini2 of the second reset signal VINI2, thereby making the value I = K x (Vdata - Vref) of the driving current of the light emitting element OLED in the light emitting stage 2 However, embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the value Vini1 of the first reset signal VINI1 can also be not equal to the value Vini2 of the second reset signal VINI2, and embodiments of the present disclosure are not limited thereto.

[0168] According to the above formula, the value I of the driving current flowing through the light emitting element is no longer related to the threshold voltage Vth of the driving transistor DT, thereby achieving compensation of the pixel circuit, solving the problem of threshold voltage Vth drift of the driving transistor DT due to process and long time operation, and eliminating the influence on the driving current, so that the display effect of the display device using the pixel circuit can be improved.

[0169] For example, as shown in FIG. 11C, FIG. 11D and FIG. 12, in the data writing and compensation stage 2 and the light emitting stage 3, the direct reset control signal RST0 is a low level signal, and the direct reset transistor T7 is closed in response to the direct reset control signal RST0. For the working process of the pixel circuit 104 shown in FIG. 11A in the reset stage 1, the data writing and compensation stage 2 and the light emitting stage 3 and the corresponding technical effects, please refer to the related description of FIG. 2A-2C in the above embodiment, which will not be repeated here.

[0170] Of course, embodiments of the present disclosure do not limit the type of direct reset transistor T7, for example, the direct reset transistor T7 can be a P-type transistor, that is, when the direct reset control signal RST0 is a low level signal, the direct reset transistor T7 is opened; when the direct reset control signal RST0 is a high level signal, the direct reset transistor T7 is closed, which can be set according to design requirements.

[0171] FIG. 13 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0172] For example, as shown in FIG. 13, the pixel circuit 50 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light emitting element 400, a second reset circuit 500, a first light emitting control circuit 600, a second light emitting control circuit 700, a third reset circuit 800, a compensation control circuit 900, and an auxiliary compensation circuit 910. Compared with the pixel circuit 10 shown in FIG. 1, the pixel circuit 50 is different in that the auxiliary compensation circuit 910 is added, a first end 910a of the auxiliary compensation circuit 910 is electrically connected with a second end 100b of the driving circuit 100, and a second end 910b of the auxiliary compensation circuit 910 is electrically connected with the second voltage terminal ELVDD. For other structures in the pixel circuit 50, refer to the related description about FIG. 1 in the above embodiments, which will not be repeated here.

[0173] FIG. 14A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 13, and FIG. 14A is a schematic diagram of the pixel circuit 105 shown in FIG. 13 in a reset phase; FIG. 14B is a schematic diagram of the pixel circuit 105 shown in FIG. 13 in a data writing and compensation phase; and FIG. 14C is a schematic diagram of the pixel circuit 105 shown in FIG. 13 in a light emitting phase. In addition, the transistors identified by dashed lines in FIGS. 14B-14C all represent the state of being turned off in the corresponding phase.

[0174] For example, the pixel circuit shown in FIG. 13 can be implemented as the pixel circuit structure shown in FIG. 14A.

[0175] For example, as shown in FIG. 13 and FIG. 14A, the pixel circuit 105 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light emitting control transistor T4, a second light emitting control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, a second compensation capacitor Cst2, and a light emitting element OLED. For example, the pixel circuit 104 is different from the pixel circuit 101 (as shown in FIG. 2A) in that the second compensation capacitor Cst2 is added.

[0176] For example, as shown in FIG. 13 and FIG. 14A, the auxiliary compensation circuit 910 includes the second compensation capacitor Cst2, a first pole of the second compensation capacitor Cst2 is electrically connected with the second end 100b of the driving circuit 100, and a second pole of the second compensation capacitor Cst2 is configured to receive a first constant signal. For example, in the pixel circuit 105 shown in FIG. 14A, the second end of the second compensation capacitor Cst2 is electrically connected with the second voltage terminal ELVDD, and the second power voltage ELVDD serves as the first constant signal, but the implementation of the present disclosure is not limited thereto.

[0177] For example, the timing diagram corresponding to the pixel circuit 105 can refer to FIG. 3. For example, as shown in FIG. 13 and FIG. 14A, the pixel circuit 105 is different from the pixel circuit 101 shown in FIG. 2A in that a second compensation capacitor Cst2 is added, and the working states (e.g., open state or closed state) of the other transistors in different working stages are the same.

[0178] For example, as shown in FIG. 3, FIG. 13 and FIG. 14A, in the reset stage 1, the driving method comprises: making the first reset control signal RST1 an open signal to open the first reset circuit 300, and the first reset circuit 300 applies the reference signal REF to the first electrode of the first compensation capacitor Cst1; secondly, making the first light-emitting control signal EM1 an open signal to open the first light-emitting control circuit 600, and the first light-emitting control circuit 600 applies the second power supply voltage ELVDD to the first end 100a of the driving circuit 100; making the third reset control signal RST3 an open signal to open the third reset circuit 800, and the third reset circuit 800 applies the second power supply voltage ELVDD to the control end 100m of the driving circuit 100; making the second light-emitting control signal EM2 an open signal to open the second light-emitting control circuit 700; and making the second reset control signal RST2 an open signal to open the second reset circuit 500, and the second reset circuit 500 applies the first reset signal VINI1 to the first electrode 400a of the light-emitting element 400, and the first reset signal VINI1 is applied to the second end 100b of the driving circuit 100 through the second light-emitting control circuit 700, and the value of the first reset signal VINI1 is Vini1, so that the initial voltage value of the second end 100b of the driving circuit 100 before entering the data writing and compensation stage 2 is Vini1.

[0179] Specifically, for example, as shown in FIG. 3, FIG. 13 and FIG. 14A, in the pixel circuit 105, since the data writing transistor T1 is multiplexed as the first reset transistor T2 and the data scanning signal G1 is multiplexed as the first reset control signal RST1, the data scanning signal G1 is a high level signal to turn on the data writing transistor T1, and the reference signal REF can be applied to the first electrode of the data writing transistor T1 and then applied to the first electrode of the first compensation capacitor Cst1. Next, the first light emitting control signal EM1 is a high level signal to turn on the first light emitting control transistor T4, and the third reset control signal RST3 is a high level signal to turn on the third reset transistor T6, so that the second power supply voltage ELVDD can be applied to the first electrode of the driving transistor DT and then applied to the gate of the driving transistor DT through the third reset transistor T6. Meanwhile, the second light emitting control signal EM2 is a high level signal to turn on the second light emitting control transistor T5, and the second reset control signal RST2 is a high level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (the fourth node N4) of the light emitting element OLED and then applied to the second electrode (the third node N3) of the driving transistor DT through the second light emitting control transistor T5, so that the voltage value of the second electrode of the driving transistor DT and the voltage value of the first electrode of the light emitting element OLED are both the value Vini1 of the first reset signal VINI1.

[0180] For example, as shown in FIG. 3, FIG. 13 and FIG. 14A, in the data writing and compensation stage 2, the driving method includes: the second reset control signal RST2 is an open signal to turn on the second reset circuit 500, and the second reset circuit 500 applies the first reset signal VINI1 to the first electrode 400a of the light emitting element 400 and the second electrode of the compensation control capacitor Ca.

[0181] Specifically, as shown in FIG. 3 and FIG. 14B, in the data writing and compensation stage 2, the second reset control signal RST2 is a high level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (the fourth node N4) of the light emitting element OLED and the second electrode of the compensation control capacitor Ca, so that the voltage value of the first electrode of the light emitting element OLED is the value Vini1 of the first reset signal VINI1, thereby avoiding the light emitting element OLED emitting light in the data writing and compensation stage 2. Meanwhile, the data scanning signal G1 is a high level signal to turn on the data writing transistor T1, so that the data signal DATA is applied to the first electrode of the first compensation capacitor Cst1.

[0182] For example, as shown in FIG. 3 and FIG. 14B, in the data writing and compensation stage 2, the first compensation capacitor Cst1 and the second compensation capacitor Cst2 are connected in series, the voltage Vc3 of the second end 100b of the driving circuit 100 is (Vdata-Vref) x [C1 / (C1+C2)]+Vini1, Vdata represents the value of the data signal DATA, Vref represents the initial voltage value of the first pole of the first compensation capacitor Cst1 before entering the data writing and compensation stage, C1 represents the capacitance value of the first compensation capacitor Cst1, C2 represents the capacitance value of the second compensation capacitor Cst2, and Vini1 represents the initial voltage value of the second end 100b of the driving circuit 100 before entering the data writing and compensation stage.

[0183] For example, as shown in FIG. 3 and FIG. 14B, the second pole of the first compensation capacitor Cst1 and the first pole of the second compensation capacitor Cst2 are electrically connected, and are both electrically connected to the second pole of the driving transistor DT, so that the first compensation capacitor Cst1 and the second compensation capacitor Cst2 are connected in series. The initial voltage value of the first pole of the first compensation capacitor Cst1 before entering the data writing and compensation stage (i.e. in the reset stage 1) is equal to the value Vref of the reference signal REF, the stable voltage value of the first compensation capacitor Cst1 in the data writing and compensation stage is equal to the value Vdata of the data signal DATA, and the second pole of the second compensation capacitor Cst2 receives the first constant signal when switching from the data writing and compensation stage to the light emitting stage. The change amount of the voltage of the first pole of the first compensation capacitor Cst1 is Vdata-Vref, and thus the change amount of the difference between the voltage of the first pole of the second compensation capacitor Cst2 and the voltage of the second pole of the second compensation capacitor Cst2 is (Vdata-Vref) x [C1 / (C1+C2)]. Since the voltage value of the second pole of the second compensation capacitor Cst2 does not change (i.e. the value of the first constant signal), the change amount of the voltage of the first pole of the second compensation capacitor Cst2 is (Vdata-Vref) x [C1 / (C1+C2)], and the change amount of the voltage of the second pole of the driving transistor DT is (Vdata-Vref) x [C1 / (C1+C2)]. Since the initial voltage value of the second pole of the driving transistor DT before entering the data writing and compensation stage 2 (i.e. the voltage value in the reset stage 1) is Vini1, the voltage Vc3 of the second pole of the driving transistor DT in the data writing and compensation stage 2 is (Vdata-Vref) x [C1 / (C1+C2)]+Vini1.

[0184] For example, as shown in FIG. 3 and FIG. 14B, before entering the data writing and compensation stage, the initial voltage of the gate of the drive transistor DT is the second power supply voltage ELVDD, and the difference (Vgs) between the second power supply voltage ELVDD and the value Vini1 of the first reset signal VINI1 is greater than the threshold voltage Vth of the drive transistor DT, i.e. Vgs = ELVDD - Vini1 > Vth, so the drive transistor DT is in the on state, the first pole of the drive transistor DT charges to the second pole of the drive transistor DT until the drive transistor DT is turned off (closed), so that the gate-source voltage Vgs of the drive transistor DT is Vth, at this time the voltage value of the gate of the drive transistor DT (the voltage value of the first pole of the compensation control capacitor Ca) is Vc3 + Vth = (Vdata - Vref) x [C1 / (C1+C2)] + Vini1 + Vth, so that the threshold voltage Vth of the drive transistor DT and other information can be stored in the compensation control capacitor Ca, thereby completing the data writing and compensation process.

[0185] For example, as shown in FIG. 3, FIG. 13 and FIG. 14C, in the light emitting stage 3, the first light emitting control signal EM1 is an on signal to turn on the first light emitting control circuit 600, and the second light emitting control circuit 700 applies the drive current to the first electrode 400a of the light emitting element 400 to drive it to emit light.

[0186] Correspondingly, as shown in FIG. 3 and FIG. 14C, in the light emitting stage 3, the first light emitting control signal EM1 is a high level signal to turn on the first light emitting control transistor T4, and the second power supply voltage ELVDD is applied to the first pole of the drive transistor DT. At the same time, the second light emitting control signal EM2 is a high level signal to turn on the second light emitting control transistor T5, and the drive current is applied to the light emitting element OLED via the second light emitting control transistor T5 to make it emit light.

[0187] For example, as shown in FIG. 3 and FIG. 14C, in the light emitting stage 3, since the light emitting element OLED is in the light emitting state, the voltage value of the first electrode of the light emitting element OLED (the voltage value of the fourth node N4) and the voltage value of the second electrode of the driving transistor DT (the voltage value of the third node N3) both correspond to the voltage value Voled when the light emitting element OLED emits light, thus the variation amount AV of the voltage value of the first electrode of the light emitting element OLED = Voled-Vini1. Accordingly, the compensation control capacitor Ca plays the bootstrap role, so that the first electrode of the compensation control capacitor Ca also has the variation amount AV, thereby making the voltage value of the gate of the driving transistor DT (the voltage value of the second node N2) have the variation amount AV, so that the voltage value of the gate of the driving transistor DT is Vc3+Vth+AV = (Vdata-Vref) x [C1 / (C1+C2)]+Vini1+Vth+Voled-Vini1 = (Vdata-Vref) x [C1 / (C1+C2)]+Vth+Voled, the driving transistor DT is in the on state, and the gate-source voltage Vgs of the driving transistor DT = (Vdata-Vref) x [C1 / (C1+C2)]+Vth+Voled-Voled = (Vdata-Vref) x [C1 / (C1+C2)]+Vth.

[0188] The value I of the driving current flowing through the light emitting element can be obtained according to the following formula:

[0189] I = K x (Vgs-Vth) 2 , K is the conductive coefficient of the driving transistor DT. That is:

[0190] I = K x {(Vdata-Vref) x [C1 / (C1+C2)]} 2

[0191] According to the above formula, the value I of the driving current flowing through the light emitting element is no longer related to the threshold voltage Vth of the driving transistor DT, thereby the compensation of the pixel circuit can be realized, the problem of the threshold voltage Vth drift of the driving transistor DT caused by the process and long time operation is solved, and the influence of the threshold voltage Vth on the driving current is eliminated, so that the display effect of the display device using the pixel circuit can be improved.

[0192] For example, as shown in FIG. 3, FIG. 14B and FIG. 14C, when entering from the data writing and compensation stage 2 to the light emitting stage 3, the data writing transistor T1 changes from the open state to the closed state, in the process, due to the parasitic capacitance between the gate of the data writing transistor T1 and the first electrode thereof, and the parasitic capacitance is in series with the first storage capacitor Cst1, when the voltage of the gate of the data writing transistor T1 decreases, the parasitic capacitance between the gate of the data writing transistor T1 and the first electrode thereof and the first storage capacitor Cst1 can perform voltage division, so that the change amount of the voltage value of the first electrode of the first storage capacitor Cst1 is small, the setting can reduce the influence of the change of the data writing transistor T1 from the open state to the closed state on the voltage of the second electrode of the driving transistor DT, so that the decrease amount of the voltage value of the second electrode of the driving transistor DT is small, so that the gate-source voltage Vgs of the driving transistor DT is basically unchanged or has small fluctuation, so as to make the driving current flowing through the light emitting element OLED more stable. In addition, when there is also a parasitic capacitance between a signal line and the second electrode of the driving transistor DT, the second electrode of the driving transistor DT serves as one pole of the parasitic capacitance, so that the parasitic capacitance is in series with the second storage capacitor Cst2, when the voltage of the other pole of the parasitic capacitance changes, the parasitic capacitance and the second storage capacitor Cst2 can perform voltage division, so that the change amount of the voltage value of the first electrode of the second storage capacitor Cst2 is small, so as to further stabilize the voltage of the second electrode of the driving transistor DT, so as to make the brightness of the display panel more uniform.

[0193] For example, as shown in FIG. 14A, the capacitance value C2 of the second storage capacitor Cst2 can be 30 times to 100 times of the capacitance value of the parasitic capacitance between the signal line and the second electrode of the driving transistor DT, for example, can be at least one of 30 times to 40 times, 45 times to 65 times, 55 times to 75 times and 60 times to 80 times, but the embodiments of the present disclosure are not limited thereto. For example, the capacitance value C2 of the second storage capacitor Cst2 can be 100 fF to 300 fF, for example, can be at least one of 120 fF to 150 fF, 140 fF to 180 fF, 210 fF to 240 fF, 230 fF to 250 fF and 260 fF to 280 fF, but the embodiments of the present disclosure are not limited thereto. For example, the capacitance value of the parasitic capacitance between the signal line and the second electrode of the driving transistor DT can be 3 fF to 5 fF, for example, can be 3 fF, 3.5 fF, 4 fF and 4.5 fF, but the embodiments of the present disclosure are not limited thereto. In this way, the voltage fluctuation of the other signal lines can affect the gate-source voltage Vgs of the driving transistor DT, and further stabilize the driving current of the driving transistor DT.

[0194] FIG. 15 is a schematic block diagram of another pixel circuit according to at least one embodiment of the present disclosure.

[0195] For example, as shown in FIG. 15, the pixel circuit 60 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light emitting element 400, a second reset circuit 500, a first light emitting control circuit 600, a second light emitting control circuit 700, a third reset circuit 800, a compensation control circuit 900, and an auxiliary compensation circuit 910. Compared with the pixel circuit 50 shown in FIG. 13, the difference of the pixel circuit 60 is that the auxiliary compensation circuit 910 is connected in a different way. In the pixel circuit 60, a first end 910a of the auxiliary compensation circuit 910 is electrically connected to a second end 100b of the driving circuit 100, and a second end 910b of the auxiliary compensation circuit 910 is electrically connected to a first reset signal terminal VINI1. For other structures in the pixel circuit 60, refer to the related description of FIG. 13 in the above embodiments, which will not be repeated here.

[0196] FIG. 16 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 15.

[0197] For example, the pixel circuit shown in FIG. 15 can be implemented as the pixel circuit structure shown in FIG. 16.

[0198] For example, as shown in FIG. 15 and FIG. 16, the pixel circuit 106 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light emitting control transistor T4, a second light emitting control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, a second compensation capacitor Cst2, and a light emitting element OLED. For example, the difference between the pixel circuit 105 and the pixel circuit 104 (as shown in FIG. 14A) is that the second compensation capacitor Cst2 is connected in a different way. Meanwhile, the driving mode of the pixel circuit 106 shown in FIG. 16 is the same as that of the pixel circuit 105 shown in FIG. 14A, and for details, refer to the related description of the above embodiments, which will not be repeated here.

[0199] For example, as shown in FIG. 15 and FIG. 16, the auxiliary compensation circuit 910 includes a second compensation capacitor Cst2, a first pole of the second compensation capacitor Cst2 is electrically connected to a second pole of the driving transistor DT, and a second pole of the second compensation capacitor Cst2 is configured to receive a first constant signal. For example, in the pixel circuit 106 shown in FIG. 16, a second end of the second compensation capacitor Cst2 is electrically connected to the first reset signal terminal VINI1, and the first reset signal VINI1 serves as the first constant signal. In this way, the connection mode of the second compensation capacitor Cst2 can be more flexible to adapt to different design needs.

[0200] For example, in some embodiments of the present disclosure, referring to FIG. 16, the second pole of the second compensation capacitor Cst2 can also be electrically connected with an external constant signal terminal outside the pixel circuit to receive a first constant signal from the external constant signal terminal. In this way, the external constant signal terminal can be used as an independent signal input terminal, so that the voltage of the second pole of the second compensation capacitor Cst2 can be independently controlled to make it more stable.

[0201] FIG. 17 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0202] For example, as shown in FIG. 17, the pixel circuit 60 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light emitting element 400, a second reset circuit 500, a first light emitting control circuit 600, a second light emitting control circuit 700, a third reset circuit 800, a compensation control circuit 900, and an auxiliary circuit 1000. Compared with the pixel circuit 10 shown in FIG. 1, the difference of the pixel circuit 70 is that the auxiliary circuit 1000 is added, for example, as shown in FIG. 17, a first end 1000a of the auxiliary circuit 1000 is electrically connected with the data writing circuit 200, and a second end 1000b of the auxiliary circuit 1000 is configured to receive a second constant signal V0. For other structures in the pixel circuit 70, please refer to the related description of the pixel circuit 10 in the above embodiments, which will not be repeated here.

[0203] FIG. 18 is a circuit diagram of another implementation example of the pixel circuit shown in FIG. 17.

[0204] For example, the pixel circuit shown in FIG. 17 can be implemented as the pixel circuit structure shown in FIG. 18.

[0205] For example, as shown in FIG. 17 and FIG. 18, the pixel circuit 107 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light emitting control transistor T4, a second light emitting control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, an auxiliary capacitor Cb, and a light emitting element OLED. For example, the difference between the pixel circuit 107 and the pixel circuit 101 (as shown in FIG. 2A) is that the auxiliary capacitor Cb is added. Meanwhile, the driving mode of the pixel circuit 107 shown in FIG. 18 is the same as that of the pixel circuit 101 shown in FIG. 2A, and specific details can be referred to the related description of the pixel circuit 101 in the above embodiments, which will not be repeated here.

[0206] For example, as shown in FIGS. 17 and 18, the auxiliary circuit 1000 includes an auxiliary capacitor Cb, a first pole of the auxiliary capacitor Cb is electrically connected with the gate of the data writing transistor T1, and a second pole of the auxiliary capacitor Cb is configured to receive a second constant signal V0. For example, in some embodiments of the present disclosure, the second pole of the auxiliary capacitor Cb can be electrically connected with the second voltage terminal ELVDD, and the second power voltage ELVDD serves as the second constant signal V0. For example, the second pole of the auxiliary capacitor Cb can be electrically connected with the first reset signal terminal VINI1, and the first reset signal VINI1 serves as the second constant signal V0. For example, the second pole of the auxiliary capacitor Cb can be electrically connected with an external constant signal terminal outside the pixel circuit to receive the first constant signal V0 from the external constant signal terminal, which can be set according to design requirements, and embodiments of the present disclosure do not limit the type of the second constant signal.

[0207] For example, as shown in FIG. 18, there is a parasitic capacitor between the gate of the data writing transistor T1 and the first pole thereof, and the parasitic capacitor is in series with the auxiliary capacitor Cb. When the data writing transistor T1 is switched from an open state to a closed state, the setting of the auxiliary capacitor Cb can slow down the change speed of the voltage of the gate of the data writing transistor T1, so that the voltage of the gate of the data writing transistor T1 decreases at a slower speed, thereby making the voltage fluctuation of the first pole of the first compensation capacitor Cst1 smaller, and further reducing the voltage fluctuation of the gate of the driving transistor DT, so that the gate-source voltage Vgs of the driving transistor DT is more stable, which is conducive to improving the display effect of the display panel.

[0208] FIG. 19 is a circuit diagram of another implementation example of the pixel circuit shown in FIG. 1.

[0209] For example, the pixel circuit shown in FIG. 1 can also be implemented as the pixel circuit structure shown in FIG. 19.

[0210] For example, as shown in FIG. 19, the pixel circuit 108 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light-emitting element OLED. For example, the pixel circuit 108 is different from the pixel circuit 101 in FIG. 2A in that the first compensation capacitor Cst1 is connected with the data writing transistor T1 in a different manner, and the remaining structures can refer to the related description about FIG. 2A in the above embodiments, which will not be repeated here.

[0211] For example, as shown in FIG. 1 and FIG. 19, a first pole of the first compensation capacitor Cst1 is electrically connected with a first pole of the data writing transistor T1, a second pole of the first compensation capacitor Cst1 is electrically connected with the data signal terminal DATA to receive the data signal DATA, and a second pole of the data writing transistor T1 is electrically connected with the second terminal 100b (a second pole of the driving transistor DT) of the driving circuit 100. The corresponding timing diagram of the pixel circuit 108 can be referred to FIG. 3, and the working process of the pixel circuit 108 can be referred to the above-mentioned description about FIG. 2A-FIG. 2C in the embodiments, which will not be repeated here.

[0212] For example, as shown in FIG. 19, on the one hand, by combining the data writing transistor T1 with the first storage capacitor Cst1 and other elements, the technical problem of how to compensate the threshold voltage Vth of the driving transistor DT can be solved to eliminate the influence of the threshold voltage Vth on the driving current of the driving transistor DT. On the other hand, since there is a parasitic capacitor between the gate of the data writing transistor T1 and its first pole, and one pole of the parasitic capacitor is electrically connected with the first pole of the first storage capacitor Cst1, thereby making the parasitic capacitor and the first storage capacitor Cst1 in series. For example, when the data signal DATA received by the second pole of the first storage capacitor Cst1 or the reference signal REF has an undesirable fluctuation, the parasitic capacitor between the gate of the data writing transistor T1 and its first pole can perform voltage division with the first storage capacitor Cst1, thereby making the voltage change of the first pole of the data writing transistor T1 smaller, and further reducing the fluctuation of the voltage of the gate of the driving transistor DT, making the gate-source voltage Vgs of the driving transistor DT more stable, so as to improve the display effect of the display panel.

[0213] FIG. 20 is a schematic block diagram of a display device provided in at least one embodiment of the present disclosure. As shown in FIG. 20, the display device 01 includes any one of the pixel circuits provided in the embodiments of the present disclosure. For example, the pixel circuit 001 can be any one of the pixel circuits provided in the embodiments of the present disclosure. The display device 01 can be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other types of devices with display functions. The embodiments of the present disclosure do not limit this.

[0214] The other structures and functions of the display device 01 provided in the embodiments of the present disclosure can be implemented by conventional technologies, and the embodiments of the present disclosure do not limit this. The technical effects of the display device 01 provided in the embodiments of the present disclosure can be referred to the above-mentioned description of the technical effects of the pixel circuit provided in the embodiments of the present disclosure, which will not be repeated here.

[0215] For example, the display device 01 provided by at least one of the embodiments of the present disclosure can be a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function, and the embodiments of the present disclosure are not limited thereto.

[0216] The following points need to be explained:

[0217] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can be referred to the general design.

[0218] (2) In the case of no conflict, the features in the same and different embodiments of the present disclosure can be combined with each other.

[0219] The above only describes the exemplary embodiments of the present disclosure, and is not used to limit the protection scope of the present disclosure, and the protection scope of the present disclosure is determined by the appended claims.

Claims

1. A pixel circuit, comprising: a driving circuit comprising a control terminal, a first terminal and a second terminal, and configured to control a size of a driving current flowing through the first terminal and the second terminal; and a data writing circuit comprising a first terminal and a second terminal, wherein the first terminal of the data writing circuit is electrically connected to the second terminal of the driving circuit, the second terminal of the data writing circuit is configured to receive a data signal, the data writing circuit is configured to write the data signal to the second terminal of the driving circuit in response to a data scanning signal, and comprises a data writing transistor and a first compensation capacitor, wherein a gate of the data writing transistor is configured to receive the data scanning signal, and a first pole of the first compensation capacitor is electrically connected to a first pole of the data writing transistor. A second pole of the first compensation capacitor is electrically connected to the second terminal of the driving circuit, and a second pole of the data writing transistor is electrically connected to a data signal terminal to receive the data signal.

2. The pixel circuit of claim 1, wherein, A capacitance value of the first compensation capacitor is 30 times to 100 times of a capacitance value of a parasitic capacitance between the gate of the data writing transistor and the first pole of the data writing transistor.

3. The pixel circuit of claim 2, wherein, The capacitance value of the first compensation capacitor is 100 fF to 300 fF.

4. The pixel circuit according to claim 2 or 3, wherein, The second pole of the first compensation capacitor is electrically connected to the data signal terminal to receive the data signal, and the second pole of the data writing transistor is electrically connected to the second terminal of the driving circuit.

5. The pixel circuit of claim 1, wherein, 6.The pixel circuit of any one of claims 2-5, further comprising: a first reset circuit, a control terminal of the first reset circuit is configured to receive a first reset control signal, a first terminal of the first reset circuit is electrically connected to the first pole of the first compensation capacitor, and a second terminal of the first reset circuit is electrically connected to a reference signal terminal to receive a reference signal, the first reset circuit is configured to write the reference signal to the second terminal of the driving circuit with the first compensation capacitor in response to the first reset control signal. The first reset circuit comprises a first reset transistor, a gate of the first reset transistor is electrically connected to the first reset control terminal to receive the first reset control signal, a first pole of the first reset transistor is electrically connected to the first pole of the first compensation capacitor, and a second pole of the first reset transistor is electrically connected to the reference signal terminal to receive the reference signal; 7. The pixel circuit of claim 6, wherein, The data writing transistor is multiplexed as the first reset transistor, and the data scanning signal is multiplexed as the first reset control signal, The second pole of the data writing transistor is also electrically connected to the reference signal terminal to receive the reference signal, and is configured to apply the reference signal to the second terminal of the driving circuit with the first compensation capacitor. The data signal terminal is multiplexed as the reference signal terminal, and is configured to receive the data signal and the reference signal respectively in different time periods; or 8. The pixel circuit of claim 7, wherein, The data signal terminal and the reference signal terminal are different signal terminals independent of each other. ​ 9. The pixel circuit of claim 6, wherein, The first reset circuit includes a first reset transistor, a gate of the first reset transistor is electrically connected with the first reset control end to receive the first reset control signal, a first pole of the first reset transistor is electrically connected with the first pole of the first compensation capacitor, and a second pole of the first reset transistor is electrically connected with the reference signal end to receive the reference signal. The data write transistor and the first reset transistor are respectively independently controlled transistors, a gate of the data write transistor is electrically connected with a data control end, a gate of the first reset transistor is electrically connected with the first reset control end, the data control end and the first reset control end are respectively independent different signal ends, and the data signal end and the reference signal end are respectively independent different signal ends.

10. The pixel circuit according to any one of claims 1-9, further comprising: a light emitting element configured to emit light under driving of the driving current, wherein a second end of the driving circuit is electrically connected with a first electrode of the light emitting element, the driving circuit is configured to control a magnitude of the driving current flowing through the light emitting element, and a second electrode of the light emitting element is electrically connected with the first voltage end to receive the first power voltage; a second reset circuit, wherein a control end of the second reset circuit is configured to receive a second reset control signal, a first end of the second reset circuit is electrically connected with the first electrode of the light emitting element, and a second end of the second reset circuit is electrically connected with the first reset signal end to receive the first reset signal, and the second reset circuit is configured to apply the first reset signal to the first electrode of the light emitting element in response to the second reset control signal.

11. The pixel circuit according to claim 10, wherein the second reset circuit includes a second reset transistor, a gate of the second reset transistor is electrically connected with a second reset control end to receive the second reset control signal, a first pole of the second reset transistor is electrically connected with the first electrode of the light emitting element, and a second pole of the second reset transistor is electrically connected with the first reset signal end to receive the first reset signal; a gate of the data write transistor is electrically connected with a gate of the second reset transistor, the data write transistor and the second reset transistor share the gate, the data scanning signal serves as the second reset control signal, and the data transistor and the second reset transistor are of the same type; or a gate of the data transistor and a gate of the second reset transistor are independent of each other and not electrically connected.

12. The pixel circuit according to claim 10 or 11, further comprising: a first light emitting control circuit, wherein a control terminal of the first light emitting control circuit is configured to receive a first light emitting control signal, a first terminal of the first light emitting control circuit is electrically connected with the first terminal of the driving circuit, and a second terminal of the first light emitting control circuit is electrically connected with the second voltage terminal to receive the second power voltage, and the first light emitting control circuit is configured to apply the second power voltage to the first terminal of the driving circuit in response to the first light emitting control signal; and a second light emitting control circuit, wherein a control terminal of the second light emitting control circuit is configured to receive a second light emitting control signal, the second light emitting control signal being different from the first light emitting control signal, a first terminal of the second light emitting control circuit is electrically connected with the second terminal of the driving circuit, and a second terminal of the second light emitting control circuit is electrically connected with the first electrode of the light emitting element, and the second light emitting control circuit is configured to apply the driving current to the light emitting element in response to the second light emitting control signal.

13. The pixel circuit according to any one of claims 10-12, further comprising: a direct reset circuit, wherein a control terminal of the direct reset circuit is configured to receive a direct reset control signal, a first terminal of the direct reset circuit is electrically connected with the second terminal of the driving circuit, and a second terminal of the direct reset circuit is electrically connected with a second reset signal terminal to receive a second reset signal, and the direct reset circuit is configured to directly apply the second reset signal to the second terminal of the driving circuit in response to the direct reset control signal. the direct reset circuit comprises a direct reset transistor, a gate of the direct reset transistor is electrically connected with the direct reset control signal terminal to receive the direct reset control signal, a first pole of the direct reset transistor is electrically connected with the second terminal of the driving circuit, and a second pole of the direct reset transistor is electrically connected with the second reset signal terminal to receive the second reset signal.

14. The pixel circuit of claim 13, wherein, the value of the first reset signal is equal to the value of the second reset signal.

15. The pixel circuit according to any one of claims 12-14, wherein the first light emitting control circuit comprises a first light emitting control transistor, a gate of the first light emitting control transistor is electrically connected with the first light emitting control terminal to receive the first light emitting control signal, a first pole of the first light emitting control transistor is electrically connected with the first terminal of the driving circuit, and a second pole of the first light emitting control transistor is electrically connected with the second voltage terminal to receive the second power voltage; the second light emitting control circuit comprises a second light emitting control transistor, a gate of the second light emitting control transistor is electrically connected with the second light emitting control terminal to receive the second light emitting control signal, a first pole of the second light emitting control transistor is electrically connected with the second terminal of the driving circuit, and a second pole of the second light emitting control transistor is electrically connected with the first electrode of the light emitting element.

16. The pixel circuit according to any one of claims 10-15, further comprising: The auxiliary compensation circuit comprises a second compensation capacitor, wherein a first pole of the second compensation capacitor is electrically connected with the second end of the driving circuit, and a second pole of the second compensation capacitor is configured to receive a first constant signal.

17. The pixel circuit of claim 16, wherein, the second pole of the second compensation capacitor is electrically connected with the second voltage terminal, and the second power voltage is as the first constant signal; or the second pole of the second compensation capacitor is electrically connected with the first reset signal terminal, and the first reset signal is as the first constant signal; or the second pole of the second compensation capacitor is electrically connected with an external constant signal terminal outside the pixel circuit to receive the first constant signal from the external constant signal terminal.

18. The pixel circuit of any one of claims 1-17, further comprising: the auxiliary circuit comprises an auxiliary capacitor, wherein a first pole of the auxiliary capacitor is electrically connected with the gate of the data writing transistor, and a second pole of the auxiliary capacitor is configured to receive a second constant signal.

19. The pixel circuit of any one of claims 12 or 15, further comprising: a third reset circuit, wherein a control terminal of the third reset circuit is configured to receive a third reset control signal, a first terminal of the third reset circuit is electrically connected with the first terminal of the driving circuit, a second terminal of the third reset circuit is electrically connected with the control terminal of the driving circuit, and the third reset circuit is configured to allow the second power voltage to be applied to the control terminal of the driving circuit in response to the third reset control signal; and a compensation control circuit comprising a compensation control capacitor, wherein a first pole of the compensation control capacitor is electrically connected with the control terminal of the driving circuit, and a second pole of the compensation control capacitor is electrically connected with the first electrode of the light emitting element.

20. The pixel circuit of claim 19, wherein, the driving circuit comprises a driving transistor, the gate of the driving transistor is as the control terminal of the driving circuit, the first pole of the driving transistor is as the first terminal of the driving circuit, and the second pole of the driving transistor is as the second terminal of the driving circuit; and the third reset circuit comprises a third reset transistor, the gate of the third reset transistor is electrically connected with the third reset control terminal to receive the third reset control signal, the first pole of the third reset transistor is electrically connected with the first pole of the driving transistor, and the second pole of the third reset transistor is electrically connected with the gate of the driving transistor.

21. A display device comprising the pixel circuit of any one of claims 1-20.

22. A driving method of a pixel circuit, applicable to the pixel circuit of any one of claims 1-20, the driving method comprising: in a data writing and compensation phase, allowing the data scanning signal to be an on signal to turn on the data writing transistor, and writing the data signal into the second terminal of the driving circuit through the data writing transistor and the first compensation capacitor.

23. The driving method according to claim 22, wherein The pixel circuit further comprises a data write circuit, a control end of the data write circuit is configured to receive a data scanning signal, a first end of the data write circuit is electrically connected with the second end of the drive circuit, and a second end of the data write circuit is electrically connected with the data signal end to receive the data signal; The driving method further comprises: In the data writing and compensation stage, the data scanning signal is an open signal to write the data signal into the second end of the drive circuit; and When entering the light emitting stage from the data writing and compensation stage, the data scanning signal is changed from the open signal to a closed signal to close the data write transistor, wherein in the light emitting stage, the data scanning signal remains the closed signal.

24. The driving method according to claim 22 or 23, wherein In the step of writing the data signal into the second end of the drive circuit through the data write transistor and the first compensation capacitor, The difference between the initial voltage value Vc11 of the first pole of the first compensation capacitor before entering the data writing and compensation stage and the stable voltage value Vc12 of the first pole of the first compensation capacitor in the data writing and compensation stage is a first change amount ΔVc1, The difference between the initial voltage value Vc13 of the second pole of the first compensation capacitor before entering the data writing and compensation stage and the stable voltage value Vc14 of the second pole of the first compensation capacitor in the data writing and compensation stage is a second change amount ΔVc2, and the first change amount ΔVc1 is equal to the second change amount ΔVc2.

25. The driving method according to claim 22 or 23, wherein The pixel circuit further comprises an auxiliary compensation circuit, the auxiliary compensation circuit comprises a second compensation capacitor, wherein a first pole of the second compensation capacitor is electrically connected with the second end of the drive circuit, and a second pole of the second compensation capacitor is configured to receive a first constant signal; In the step of writing the data signal into the second end of the drive circuit through the data write transistor and the first compensation capacitor, The first compensation capacitor and the second compensation capacitor are connected in series, and in the data writing and compensation stage, the voltage Vc3 of the second end of the drive circuit is Vdata-Vref)×[C1 / (C1+C2)]+Vini1, Vdata represents the value of the data signal, Vref represents the initial voltage value of the first pole of the first compensation capacitor before entering the data writing and compensation stage, C1 represents the capacitance value of the first compensation capacitor, C2 represents the capacitance value of the second compensation capacitor, and Vini1 represents the initial voltage value of the second end of the drive circuit before entering the data writing and compensation stage.

26. The driving method according to claim 24 or 25, wherein The pixel circuit further comprises a light emitting element, a first reset circuit, a second reset circuit, a third reset circuit, a first light emitting control circuit, and a second light emitting control circuit, The second end of the driving circuit is electrically connected with the first electrode of the light emitting element, and the driving circuit is configured to control the size of the driving current flowing through the light emitting element; the control end of the first reset circuit is configured to receive a first reset control signal, the first end of the first reset circuit is electrically connected with the first pole of the first compensation capacitor, and the second end of the first reset circuit is electrically connected with a reference signal end to receive a reference signal; the control end of the second reset circuit is configured to receive a second reset control signal, the first end of the second reset circuit is electrically connected with the first electrode of the light emitting element, and the second end of the second reset circuit is electrically connected with a first reset signal end to receive a first reset signal; the control end of the third reset circuit is configured to receive a third reset control signal, the first end of the third reset circuit is electrically connected with the first end of the driving circuit, and the second end of the third reset circuit is electrically connected with the control end of the driving circuit; the control end of the first light emitting control circuit is configured to receive a first light emitting control signal, the first end of the first light emitting control circuit is electrically connected with the first end of the driving circuit, and the second end of the first light emitting control circuit is electrically connected with a second voltage end to receive a second power voltage; the control end of the second light emitting control circuit is configured to receive a second light emitting control signal, the first end of the second light emitting control circuit is electrically connected with the second end of the driving circuit, and the second end of the second light emitting control circuit is electrically connected with the first electrode of the light emitting element; The driving method further comprises: a reset stage before the compensation stage, The first reset control signal is an open signal to open the first reset circuit, wherein the first reset circuit applies the reference signal to the first pole of the first compensation capacitor; the first light emitting control signal is an open signal to open the first light emitting control circuit, wherein the first light emitting control circuit applies the second power voltage to the first end of the driving circuit; the third reset control signal is an open signal to open the third reset circuit, wherein the third reset circuit applies the second power voltage to the control end of the driving circuit; the second reset control signal is an open signal to open the second reset circuit, wherein the second reset circuit applies the first reset signal to the first electrode of the light emitting element; and The second light emitting control signal is an open signal to open the second light emitting control circuit; the first reset signal is applied to the second end of the driving circuit through the second light emitting control circuit, and the value of the first reset signal is Vini1, so that the initial voltage value of the second end of the driving circuit before entering the data writing and compensation stage is Vini1; and / or, The pixel circuit further comprises a direct reset circuit, a control end of the direct reset circuit is configured to receive a direct reset control signal, a first end of the direct reset circuit is electrically connected with the second end of the driving circuit, and a second end of the direct reset circuit is electrically connected with a second reset signal end to receive a second reset signal; in the light-emitting stage, the driving method further comprises: taking the direct reset control signal as an opening signal to open the direct reset circuit, applying the second reset signal to the second end of the driving circuit, and taking a value of the second reset signal as Vini2, so that an initial voltage value of the second end of the driving circuit before entering the data writing and compensation stage is Vini2.

27. The driving method according to claim 22 or 23, wherein The pixel circuit further comprises a compensation control circuit, and the compensation control circuit comprises a compensation control capacitor, wherein a first pole of the compensation control capacitor is electrically connected with the gate of the driving transistor, and a second pole of the compensation control capacitor is electrically connected with the first electrode of the light-emitting element. The driving method further comprises: in the data writing and compensation stage, taking the second reset control signal as an opening signal to open the second reset circuit, wherein the second reset circuit applies the first reset signal to the first electrode of the light-emitting element and the second pole of the compensation control capacitor.

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