Three-layer parallel enhanced gan-HFET and preparation method therefor

Abstract

Disclosed is a preparation method for a three-layer parallel enhanced GaN-HFET. The method comprises: preparing three heterojunction structures, which are stacked upwards, and using a lower high-resistance gallium nitride layer and an upper silicon nitride protection layer of each heterojunction structure to isolate the electrical properties of different heterojunction structures, so that the electrical properties of different heterojunction structures do not affect each other, wherein each heterojunction structure has a complete gate-electrode region, drain-electrode region and source-electrode region, and by means of forming two sections of square gate, source and drain metal through holes in a termination region, metal interconnections are implemented between gate electrodes, drain electrodes and source electrodes of the three heterojunction structures; moreover, an H ion passivation P-GaNl process also avoids etching damage caused by an etching process, thereby greatly improving the reliability capability of a device. Further disclosed is a three-layer parallel enhanced GaN-HFET.

Description

A three-layer parallel enhanced GaN-HFET and its preparation method Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-layer parallel enhanced GaN-HFET and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN) is a wide-bandgap semiconductor and a typical representative of third-generation semiconductors. GaN's breakdown electric field is 11 times that of silicon, its bandgap is 3.1 times wider, its heterojunction electron mobility is 1.4 times that of silicon, and its electron saturation drift velocity is 2.7 times that of silicon. Consequently, GaN is resistant to high temperatures, high voltages, and high frequencies. Compared to first-generation silicon-based semiconductor devices, GaN devices offer higher voltage resistance, faster switching frequencies, and lower on-resistance, making them widely used in power electronics.

[0003] Gallium nitride material growth can be divided into bulk crystal growth and epitaxial growth of crystalline thin films. Bulk crystal growth primarily involves ammonothermal, high-pressure, and sodium-melt methods. All three methods have very low growth rates. Therefore, the current mainstream technology for preparing gallium nitride (GaN) is heteroepitaxial growth of GaN thin films (a few microns to a few millimeters) on other substrates. The main epitaxial growth techniques include MOCVD (metal-organic chemical vapor deposition), MBE (hydride vapor phase epitaxy), and HVPE (molecular beam epitaxy). MOCVD uses a thermal decomposition reaction to perform vapor phase epitaxy on a substrate, growing a variety of compound semiconductors and thin single crystals, making it suitable for the production of heterostructured materials. It offers advantages such as easy growth control and mass production. MBE uses molecular or atomic beam deposition (MBE) on a heated crystalline substrate for epitaxial deposition, offering the highest quality and a hydrogen-free environment. HVPE involves flowing HCl over gallium metal to generate GaCl vapor, which then flows to the substrate and reacts with NH3 to form GaN. It has the advantages of the fastest growth rate and simpler growth technology.

[0004] The most commonly used substrate materials for GaN heteroepitaxial growth are sapphire, SiC, and Si. Due to factors such as heat dissipation and substrate cost, power devices often use Si as the substrate material. Due to the significant lattice mismatch between Si and GaN, stress relief in epitaxial materials is currently achieved through methods such as transition layers, insertion layers, and in-situ passivation.

[0005] Early GaN materials were primarily used in LED light-emitting devices, lasers, and photodetectors. It wasn't until 1994 that MK Khan discovered that AlGaN and GaN generate high-concentration two-dimensional electron gas (2DEG). This is due to the wide bandgap of AlGaN and GaN materials, resulting in strong voltage resistance. Furthermore, the interfacial conduction band gap between AlGaN and GaN exhibits strong piezoelectric and spontaneous polarization effects, which favor the formation of deep, narrow quantum wells and the accumulation of high-density 2DEGs. Due to its distribution and transport characteristics, the 2DEG exhibits significantly higher mobility and saturation velocity than bulk electrons. This led to the introduction of GaN into ultra-high-frequency and high-speed applications. This modulation-doped heterojunction is the basic structure of the heterojunction field-effect transistor (HFET). The device's drain and source electrodes form ohmic contacts to the 2DEG, while the gate forms a Schottky contact. Gate voltage is used to control the on / off switching of the 2DEG. Depletion-mode devices suffer from drawbacks such as false onset, unsafe conditions, and system instability.

[0006] Because depletion-mode devices can be prone to false turn-on and unsafe conditions, as well as complex circuit design and system instability, E-Mode HEMTs are becoming increasingly important in power device applications. Currently, mainstream enhancement-mode HEMT fabrication methods include recessed structures, P-type gates, F ion implantation, and polarization cancellation.

[0007] Taking P-type gate technology as an example, the preparation of the entire mainstream GaN HFET in the market includes the following steps.

[0008] First, a buffer layer of AlGaN, a high-resistance, voltage-resistant GaN layer, a GaN channel layer, an AlGaN barrier layer, and a P-type GaN cap layer are grown on a silicon substrate. The fabrication process includes etching the drain and source regions, depositing ohmic metal in these regions, implanting hydrogen ions in all P-GaN regions except beneath the gate, depositing Schottky metal in the gate region, and then performing passivation and PAD windowing.

[0009] Although GaN HFET devices have superior performance to traditional Si devices, there are still some problems that restrict their application. For power devices, device size and power density are important concerns. GaN HFET is a device based on the heterojunction of AlGaN and GaN. Currently, the AlGaN barrier layer and GaN channel layer generated by heteroepitaxial growth on the market are both planar layers, so the prepared GaN HFET devices are also horizontal devices. Compared with Si MOS and SiC MOS devices with vertical structures of the same voltage, they have advantages in high frequency and heat resistance. However, the prepared devices are often larger in size and have lower power density, which conflicts with the development trend of smaller and more integrated microelectronic devices. Summary of the Invention

[0010] In response to the above problems, the present invention provides a three-layer parallel enhanced GaN-HFET structure with the same withstand voltage, the same size and higher current flow, and a preparation method thereof.

[0011] A method for preparing a three-layer parallel enhanced GaN-HFET comprises the following steps:

[0012] S100, selecting a silicon substrate and performing P-type doping;

[0013] S200, heteroepitaxial growth of a graded AlGaN transition layer on a silicon substrate;

[0014] According to the order of growth, the first transition layer material Al 0.8 Ga 0.2 N, second transition layer material Al 0.5 Ga 0.5 N and the third transition layer material Al 0.2 Ga 0.8 N;

[0015] S300, heteroepitaxially growing a GaN high-resistance layer on the third transition layer material Al0.2Ga0.8N;

[0016] S400, growing a GaN channel layer on the GaN high-resistance layer;

[0017] S500, growing an AlGaN barrier layer on the GaN channel layer;

[0018] S600, depositing a P-type GaN cap layer on the AlGaN barrier layer;

[0019] S700, implanting high-energy F ions into the device terminal region;

[0020] Destroy the P-GaN layer, AlGaN barrier layer, GaN channel layer and GaN high-resistance layer lattice atoms at the terminal to isolate the terminal from the source region;

[0021] S800, preparation of ohmic metal in the source and drain regions;

[0022] S900, preparation of Schottky metal in the gate region;

[0023] S1000: Protect the P-Gan in the gate area and inject H ions into the P-Gan in the rest of the source area for passivation.

[0024] S1100, depositing a silicon nitride protective layer and performing a planarization process;

[0025] S1200, repeating steps S300 to S1000 in sequence to produce a second layer structure;

[0026] S1300: Square through-holes are etched simultaneously at the terminal positions of the gate, source, and drain. Metal is filled in the etched through-holes to make the first section of metal through-holes, and then planarization is performed.

[0027] S1400, depositing a silicon nitride protective layer and performing a planarization process;

[0028] S1500, repeat step S1200 to make the third layer structure;

[0029] S1600: The gate, source, and drain electrodes are simultaneously etched into through holes at the terminal position, metal is filled in the through holes, the second section of metal through holes is made, and then planarization is performed;

[0030] S1700, depositing a silicon nitride protective layer and performing a planarization process;

[0031] S1800, depositing a PI glue passivation layer.

[0032] Specifically, in step S100, a single crystal silicon substrate with a thickness of 1 mm is selected, and boron diffusion is performed to achieve a resistivity of 1 Ω*cm, thereby converting the single crystal silicon into a P-type silicon substrate.

[0033] Specifically, in step S200, the thickness of the first transition layer is 0.4um, the AlN content is 80%, and the GaN content is 20%; the thickness of the second transition layer is 0.3um, the AlN content is 50%, and the GaN content is 50%; the thickness of the third transition layer is 0.3um, the AlN content is 20%, and the GaN content is 80%.

[0034] Specifically, in step S300, the thickness of the GaN high resistance layer is 4 μm, the doping element is C, and the resistivity is 10 9 Ω*cm.

[0035] Specifically, in step S400, an n-type GaN channel layer with a thickness of 0.4 μm is grown by heteroepitaxial growth. The GaN channel layer is doped with Si at a doping concentration of 3e15.

[0036] Specifically, in step S500, an AlGaN barrier layer with a thickness of 0.05 μm is heteroepitaxially grown on the GaN channel layer using a MOCVD process; the AlGaN barrier layer is doped with Si at a doping concentration of 2e16.

[0037] Specifically, in step S600, a MOCVD process is used to heteroepitaxially grow a P-type GaN cap layer with a thickness of 0.1 μm, and the doping element is Mg with a concentration of 2e18.

[0038] Specifically, in step S800 , the source region uses Ti / Al / Ti as ohmic metal with a total thickness of 300 nm, an annealing temperature of 550° C., and an annealing time of 70 seconds.

[0039] Specifically, in step S900 , the gate region uses Ti / Al / Ti as Schottky metal with a total thickness of 400 nm, an annealing temperature of 450° C., and an annealing time of 130 s.

[0040] Specifically, in step S1300, after the terminal area is blocked and the gate, source, and drain metals of the second layer structure are completed, a small hole with a length and width of 1 um is etched in the terminal area, and the hole is etched to the surface of the first layer of metal. The metal is then filled and the surface terminal area is etched. The metal deposited on the second layer of metal is connected to the gate, source, and drain metals, and then flattened.

[0041] The present invention employs a three-layer stacked heterojunction structure. Each layer is electrically isolated using a high-resistance gallium nitride layer beneath it and a protective silicon nitride layer above it, ensuring that the electrical properties of the different layers do not interfere with each other. Each layer has complete gate, drain, and source regions. Two square metal vias are formed at the terminals to interconnect the gate, drain, and source regions of the three-layer structure. Furthermore, the H-ion passivation P-GaN process avoids etching damage, significantly improving device reliability. The YJGAN65030C1 device fabricated using this structure boasts a withstand voltage of 680V (see Figure 18) and a current of 30A (see Figure 19). This offers significant current advantages over commercially available SJ Si MOS and SiC MOS devices of the same withstand voltage and size. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a schematic structural diagram of step S100,

[0043] FIG2 is a schematic structural diagram of step S200,

[0044] FIG3 is a schematic structural diagram of step S300,

[0045] FIG4 is a schematic structural diagram of step S400,

[0046] FIG5 is a schematic structural diagram of step S500,

[0047] FIG6 is a schematic structural diagram of step S600,

[0048] FIG7 is a schematic structural diagram of step S700,

[0049] FIG8 is a schematic structural diagram of step S800,

[0050] FIG9 is a schematic structural diagram of step S900,

[0051] FIG10 is a schematic structural diagram of step S1000,

[0052] FIG11 is a schematic structural diagram of step S1100,

[0053] FIG12 is a schematic structural diagram of step S1200,

[0054] FIG13 is a schematic structural diagram of step S1300.

[0055] FIG14 is a schematic structural diagram of step S1400.

[0056] FIG15 is a schematic structural diagram of step S1500.

[0057] FIG16 is a schematic structural diagram of step S1600.

[0058] FIG17 is a schematic structural diagram of step S1700.

[0059] FIG18 is a schematic structural diagram of step S1800.

[0060] Figure 19 is a 680V withstand voltage test diagram of the YJGAN65030C1 device.

[0061] Figure 20 is a 30A current flow test diagram of the YJGAN65030C1 device. Implementation Method

[0062] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0063] A method for preparing a three-layer parallel enhanced GaN-HFET comprises the following steps:

[0064] S100, selecting a silicon substrate and performing P-type doping, as shown in FIG1 ;

[0065] S200, heteroepitaxially growing a graded AlGaN transition layer on a silicon substrate, as shown in FIG2 ;

[0066] According to the order of growth, the first transition layer material Al 0.8 Ga 0.2 N, second transition layer material Al 0.5 Ga 0.5 N and the third transition layer material Al 0.2 Ga 0.8 N;

[0067] S300, as shown in FIG3 ; using MOCVD process, heteroepitaxially growing a GaN high-resistance layer on the third transition layer material Al0.2Ga0.8N;

[0068] S400, growing a GaN channel layer on the GaN high-resistance layer, as shown in FIG4 ;

[0069] S500, growing an AlGaN barrier layer on the GaN channel layer, as shown in FIG5;

[0070] S600, depositing a P-type GaN cap layer on the AlGaN barrier layer, as shown in FIG6;

[0071] S700: High-energy F ion implantation is performed on the terminal region of the device. The source region is the center region of the device, and the terminal region is the edge region of the device surrounding the source region. High-energy F ion implantation is used to destroy the lattice and isolate the terminal region to ensure that the heterojunction interface in this region does not generate two-dimensional electron gas.

[0072] First, use photoresist to protect the source region, and then use a high-energy particle implanter to implant F ions into the terminal region to destroy the P-GaN layer, AlGaN barrier layer, GaN channel layer and GaN high-resistance layer lattice atoms at the terminal, isolating the terminal from the source region; as shown in Figure 7;

[0073] S800, preparing ohmic metal in the source and drain regions; as shown in FIG8 ;

[0074] S900: Schottky metal (or gate metal) is prepared in the gate region, as shown in FIG9 ;

[0075] S1000: Protect the P-Gan in the gate area and inject H ions into the P-Gan in the rest of the source area for passivation.

[0076] The P-GaN in the gate region is protected using photoresist, and then H ions are implanted into the P-GaN in other regions not coated with photoresist using an ion implanter, so that the Mg in the P-GaN in other regions not coated with photoresist reacts with H to form an H-Mg complex, as shown in FIG10 ;

[0077] S1100, depositing a silicon nitride protective layer and performing a planarization process, as shown in FIG11 ;

[0078] S1200, repeating steps S300 to S1000 in sequence to produce a second layer structure; as shown in FIG12;

[0079] S1300: Square through holes are etched at the terminal positions of the gate, source, and drain electrodes simultaneously. Metal is filled in the etched through holes to form the first section of metal through holes, forming the first connection metal, and then planarization is performed; as shown in FIG13;

[0080] S1400, depositing a silicon nitride protective layer and performing a planarization process, as shown in FIG14 ;

[0081] S1500, repeat step S1200 to make the third layer structure; as shown in Figure 15;

[0082] S1600: The gate, source, and drain electrodes are simultaneously etched to form through holes at the terminal positions. Metal is filled in the through holes to form the second section of metal through holes, forming the first connection metal, and then planarization is performed; as shown in FIG16 ;

[0083] S1700, depositing a silicon nitride protective layer and performing a planarization process, as shown in FIG17 ;

[0084] S1800, depositing a PI glue passivation layer, as shown in FIG18 ;

[0085] It is further defined that in step S100, a single crystal silicon substrate with a thickness of 1 mm is selected and boron diffusion is performed to achieve a resistivity of 1 Ω*cm, thereby converting the single crystal silicon into a P-type silicon substrate.

[0086] It is further defined that in step S200, the thickness of the first transition layer is 0.4um, the AlN content is 80%, and the GaN content is 20%; the thickness of the second transition layer is 0.3um, the AlN content is 50%, and the GaN content is 50%; the thickness of the third transition layer is 0.3um, the AlN content is 20%, and the GaN content is 80%.

[0087] Further defined, in step S300, the thickness of the GaN high resistance layer is 4 μm, the doping element is C, and the resistivity is 10 9 Ω*cm.

[0088] It is further defined that in step S400, an n-type GaN channel layer with a thickness of 0.4 μm is grown by heteroepitaxial growth, and the doping element of the GaN channel layer is Si with a doping concentration of 3e15.

[0089] It is further defined that in step S500, an AlGaN barrier layer with a thickness of 0.05 μm is heteroepitaxially grown on the GaN channel layer using a MOCVD process; the AlGaN barrier layer is doped with Si at a doping concentration of 2e16.

[0090] It is further defined that in step S600, a P-type GaN cap layer with a thickness of 0.1 μm is grown heteroepitaxially by using an MOCVD process, and the doping element is Mg with a concentration of 2e18.

[0091] It is further defined that in step S800, the source region uses Ti / Al / Ti as the ohmic metal with a total thickness of 300 nm, an annealing temperature of 550° C., and an annealing time of 70 s.

[0092] It is further defined that in step S900 , the gate region uses Ti / Al / Ti as Schottky metal with a total thickness of 400 nm, an annealing temperature of 450° C., and an annealing time of 130 s.

[0093] It is further defined that in step S1300, after the terminal area is blocked and the gate, source and drain metals of the second layer structure are completed, a small hole with a length and width of 1um is etched in the terminal area, and the hole is etched to the surface of the first layer of metal. Then, the metal is filled and the surface terminal area is etched. The metal deposited on the gate, source and drain is connected on the surface of the second layer of metal, and then flattened.

[0094] It is further defined that in step S1600, after the terminal area is blocked and the gate, source and drain metals of the third layer structure are completed, a small hole with a length and width of 1um is etched in the terminal area, and the hole is etched to the surface of the second layer of metal. Then, the metal is filled and the surface terminal area is etched. The metal deposited on the gate, source and drain is connected on the surface of the third layer of metal, and then flattened.

[0095] Due to spontaneous polarization and piezoelectric polarization effects, a high concentration of two-dimensional electron gas will be generated at the interface between the AlGaN barrier layer and the GaN channel layer, which is the basis of the GaN-HFET structure; the P-type GaN cap layer is used to transform the HFET from a depletion-mode device to an enhancement-mode device; the gate-source-drain metal electrodes are used to make ohmic contacts, Schottky contacts and electrical conduction; the GaN high-resistance layer is used to ensure that the device does not break down vertically and that the electrical properties of different heterojunction layers do not affect each other; the SiN protective layer has the functions of protection and electrical isolation.

[0096] Regarding the content disclosed in this case, the following points need to be explained:

[0097] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;

[0098] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to form new embodiments;

[0099] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a three-layer parallel enhanced GaN-HFET, characterized in that: The following steps are involved: S100, selecting a silicon substrate and performing P-type doping; S200, heteroepitaxially grown graded AlGaN transition layer on silicon substrate; According to the growth order, the first transition layer material Al 0.8 Ga 0.2 N, the second transition layer material Al 0.5 Ga 0.5 N and the third transition layer material Al 0.2 Ga 0.8 N; S300, heteroepitaxially growing a GaN high resistance layer on the third transition layer material Al0.2Ga0.8N; S400, growing a GaN channel layer on the GaN high resistance layer; S500, growing an AlGaN barrier layer on the GaN channel layer; S600, depositing a P-type GaN cap layer on the AlGaN barrier layer; S700, implanting high energy F ions into the device terminal region; Destroy the P-GaN layer, AlGaN barrier layer, GaN channel layer and GaN high-resistance layer lattice atoms at the terminal to isolate the terminal from the source region; S800, preparation of ohmic metal in the source and drain regions; S900, preparation of Schottky metal in the gate region; S1000, the P-Gan in the gate area is protected, and the P-Gan in the rest of the source area is passivated by injecting H ions; S1100, depositing a silicon nitride protective layer and performing a planarization process; S1200, repeating steps S300 to S1000 in sequence to produce a second layer structure; S1300, the gate, source, and drain are simultaneously etched to form a square through hole at the terminal position, and metal is filled in the etched through hole to make the first section of metal through hole, and then flattening is performed; S1400, depositing a silicon nitride protective layer and performing a planarization process; S1500, repeat step S1200 to make the third layer structure; S1600, the gate, source, and drain are simultaneously etched into through holes at the terminal position, metal is filled in the through holes, the second section of metal through holes is made, and then flattening is performed; S1700, depositing a silicon nitride protective layer and performing a planarization process; S1800, depositing a PI glue passivation layer.

2. The method for preparing a three-layer parallel enhanced GaN-HFET according to claim 1, characterized in that: In step S100, a single crystal silicon substrate with a thickness of 1 mm is selected, and boron diffusion is performed to achieve a resistivity of 1Ω*cm, so that the single crystal silicon becomes a P-type silicon substrate.

3. The method for preparing a three-layer parallel enhanced GaN-HFET according to claim 1, characterized in that: In step S200, the thickness of the first transition layer is 0.4um, the ALN content is 80%, and the GaN content is 20%; the thickness of the second transition layer is 0.3um, the ALN content is 50%, and the GaN content is 50%; the thickness of the third transition layer is 0.3um, the ALN content is 20%, and the GaN content is 80%.

4. The method for preparing a three-layer parallel enhanced GaN-HFET according to claim 1, characterized in that: In step S300, the thickness of the GaN high resistance layer is 4 μm, the doping element is C, and the resistivity is 10 9 Ω*cm.

5. The method for preparing a three-layer parallel enhanced GaN-HFET according to claim 1, characterized in that: In step S400, an n-type GaN channel layer with a thickness of 0.4 um is grown by heteroepitaxial growth, and the GaN channel layer is doped with Si at a doping concentration of 3e15.

6. The method for preparing a three-layer parallel enhanced GaN-HFET according to claim 1, characterized in that: In step S500, an AlGaN barrier layer with a thickness of 0.05 um is heteroepitaxially grown on the GaN channel layer using a MOCVD process; the AlGaN barrier layer is doped with Si at a doping concentration of 2e16.

7. The method for preparing a three-layer parallel enhanced GaN-HFET according to claim 1, characterized in that: In step S600, a P-type GaN cap layer with a thickness of 0.1 um is heteroepitaxially grown by MOCVD process, and the doping element is Mg with a concentration of 2e18.

8. The method for preparing a three-layer parallel enhanced GaN-HFET according to claim 1, characterized in that: In step S800, the source region uses Ti / Al / Ti as ohmic metal with a total thickness of 300 nm, an annealing temperature of 550° C., and an annealing time of 70 seconds.

9. The method for preparing a three-layer parallel enhanced GaN-HFET according to claim 1, characterized in that: In step S900, the gate region uses Ti / Al / Ti as Schottky metal with a total thickness of 400 nm, an annealing temperature of 450° C., and an annealing time of 130 s.

10. The method for preparing a three-layer parallel enhanced GaN-HFET according to claim 1, characterized in that: In step S1300, after the terminal area is blocked and the gate, source and drain metals of the second layer structure are completed, a small hole with a length and width of 1 um is etched in the terminal area, and the hole is etched to the surface of the first layer of metal. Then the metal is filled and the surface terminal area is etched to connect the metal deposited on the second layer of metal with the gate, source and drain, and then the hole is planarized.

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