Quantum bit component and preparation method therefor, and quantum chip and chip preparation system

Abstract

A quantum bit component and a preparation method therefor, and a quantum chip and a chip preparation system, which relate to the technical field of micro-nano machining. The preparation method comprises: preparing on a substrate an underlying film of a quantum bit component (S510); preparing an underlying circuit on the basis of the underlying film (S520), wherein the surface of the underlying circuit is provided with a nitride passivation layer; and preparing, on the substrate, quantum bits which are connected to the underlying circuit (S530), so as to obtain the quantum bit component.

Description

Quantum bit component, preparation method, quantum chip and chip preparation system

[0001] This application claims priority to the Chinese patent application filed on August 29, 2023, with application number 202311114907.6 and invention name “Quantum bit component, preparation method, quantum chip and chip preparation system”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of micro-nano processing technology, and in particular to a quantum bit component, a preparation method, a quantum chip, and a chip preparation system. Background Art

[0003] How to extend the coherence of quantum systems is an important issue for quantum computers. Among them, the impact of superconducting materials on coherence is mainly the TLS loss of the material itself, and the TLS loss mainly comes from the oxide layer on the surface of the material.

[0004] In related technologies, the commonly used aluminum film can be replaced with a niobium or tantalum film with a thinner oxide layer, or the oxide layer can be removed with hydrofluoric acid and then placed in a refrigerator for vacuum cooling as soon as possible to reduce TLS loss.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a quantum bit component, a preparation method, a quantum chip, and a chip preparation system, which can improve the coherence of quantum bits. The technical solution is as follows.

[0007] In one aspect, a qubit assembly is provided, comprising:

[0008] The underlying circuits and qubits;

[0009] The bottom circuit surface has a nitride passivation layer.

[0010] In another aspect, a method for preparing a quantum bit assembly is provided, the method comprising:

[0011] preparing a bottom film of a quantum bit component on a substrate;

[0012] preparing a bottom circuit based on the bottom film, wherein the surface of the bottom circuit has a nitride passivation layer;

[0013] A quantum bit connected to the underlying circuit is prepared on the substrate to obtain the quantum bit assembly.

[0014] In another aspect, a quantum chip is provided, comprising the quantum bit component described above.

[0015] On the other hand, a chip preparation system is provided, the system comprising: an evaporation machine, a glue coating machine, a photolithography machine and an etching machine;

[0016] The evaporator is used to prepare the bottom film of the quantum bit component on the substrate;

[0017] The coating machine, the photolithography machine and the etching machine are used to prepare a bottom layer circuit based on the bottom layer film, and the surface of the bottom layer circuit has a nitride passivation layer;

[0018] The evaporator, the glue coater, the photolithography machine and the etching machine are also used to prepare quantum bits connected to the underlying circuit on the substrate to obtain the quantum bit assembly.

[0019] In some embodiments, the system further includes a nitridation treatment device for performing nitridation treatment to obtain the underlying circuit after the coater and the photolithography machine expose and etch the underlying film according to the pattern of the underlying circuit.

[0020] In some embodiments, the nitridation processing equipment includes a nitridation chamber for placing a first product obtained after exposing and etching the bottom film in a nitrogen environment and heating it to a first temperature.

[0021] In some embodiments, the first temperature is 800 degrees Celsius.

[0022] In some embodiments, the nitridation treatment equipment includes a plasma cleaner or a plasma etcher, and the plasma cleaner or the plasma etcher is used to place the first product obtained after exposing and etching the underlying film in a nitrogen plasma injection environment and heat it to a second temperature and maintain it for a specified time.

[0023] In some embodiments, the second temperature is 300 degrees Celsius, and the specified time period is 10 minutes.

[0024] In some embodiments, the nitridation processing equipment includes an evaporator for evaporating a nitride passivation layer on the first product obtained after exposing and etching the underlying film.

[0025] In some embodiments, the system further comprises:

[0026] A cleaning machine is used to rinse the surface of the first product to remove the oxide layer on the surface of the first product.

[0027] In some embodiments, the system further comprises a nitridation treatment device for performing a nitridation treatment on the underlying film;

[0028] The coating machine, the photolithography machine and the etching machine are used to expose and etch the bottom film after nitridation treatment according to the pattern of the bottom circuit to obtain the bottom circuit.

[0029] The beneficial effects brought about by the technical solution provided in the embodiments of the present application include at least: in the process of preparing the quantum bit component, a nitride passivation layer is prepared on the surface of the underlying circuit. Since the nitride passivation layer can effectively prevent oxidation of the film surface, the above-mentioned quantum bit component can reduce the generation of TLS loss and extend the coherence time of the quantum chip. In other words, the above-mentioned solution can be used to prepare superconducting quantum chips with long decoherence, thereby improving the decoherence performance of the superconducting quantum chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a flow chart of the preparation of a superconducting quantum chip involved in this application;

[0031] FIG2 is a schematic structural diagram of a quantum bit assembly according to an embodiment of the present application;

[0032] FIG3 is a schematic structural diagram of another quantum bit component involved in an embodiment of the present application;

[0033] FIG4 is a schematic structural diagram of a quantum chip involved in an embodiment of the present application;

[0034] FIG5 is a flow chart of a method for preparing a quantum bit assembly provided by an exemplary embodiment of the present application;

[0035] FIG6 is a flow chart of a method for preparing a quantum bit assembly according to an embodiment of the present application;

[0036] FIG7 is a schematic diagram of a nitride passivation layer deposited on an underlying film involved in the present application;

[0037] FIG8 is a schematic diagram of an etched groove sidewall oxide layer involved in the present application;

[0038] FIG9 is a flow chart of a method for preparing a quantum bit assembly according to an embodiment of the present application;

[0039] FIG10 is a schematic diagram of nitrogen ion implantation according to an exemplary embodiment of the present application;

[0040] FIG11 is a flow chart of a method for preparing a quantum bit assembly according to an exemplary embodiment of the present application;

[0041] FIG12 is a flow chart of the preparation of a quantum bit assembly according to the embodiment shown in FIG11 ;

[0042] FIG13 is a schematic diagram of a chip preparation system according to an exemplary embodiment of the present application;

[0043] FIG14 is a schematic diagram of an application scenario of a solution provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] Qubit: In quantum information science, it is the unit of measurement for quantum information. Unlike a classical bit, which can only be in one of the states 0 or 1, a qubit can be in both states simultaneously, a quantum superposition of 0 and 1.

[0045] A Josephson junction, also known as a superconducting tunnel junction, is typically composed of two superconductors sandwiched by a very thin barrier layer (thickness ≤ the coherence length of a Cooper pair), such as the S (superconductor)-I (semiconductor or insulator)-S (superconductor) structure, abbreviated as SIS. In a Josephson junction, superconducting electrons can tunnel from one side of the semiconductor or insulator film to the other by the tunneling effect.

[0046] One process for preparing a Josephson junction is as follows: an electron beam exposure method is used to create a structural pattern containing an undercut (also known as a Dolan bridge structure) on a double-layer electron beam photoresist on the substrate surface. A double-tilt evaporation method is then used to prepare the junction region, first by obliquely depositing a superconducting metal film, oxidizing it to form an oxide insulating layer, and then vertically depositing the superconducting metal film.

[0047] TLS loss: refers to the phenomenon that the two-level system (TLS) in the superconducting quantum chip material interacts with the microwaves in the quantum chip, thereby shortening the coherence time of the quantum bit.

[0048] Exposure: A micro-nano processing technology mainly involving ultraviolet lithography, which involves coating photoresist on the surface of a substrate sample, then irradiating ultraviolet light through a mask onto the substrate surface, using photochemical reactions to change the properties of the light-irradiated part of the photoresist, and then dissolving the light-reactive area into a specific solution to achieve the purpose of making a specific pattern on the substrate.

[0049] Etching: A micromachining process that uses dry and wet (liquid) methods to corrode metal or other materials to form the desired structure.

[0050] Undercut: In the double-layer photoresist process, a window is opened by exposing and developing the upper layer of photoresist. The lower layer of photoresist continues to corrode in the developer and expands laterally, forming a structure that is narrow at the top and wide at the bottom.

[0051] Degumming solution: An organic solvent that can remove the residual photoresist that has not reacted with light after the sample is exposed and developed.

[0052] Quantum computers are attracting increasing attention due to their more powerful computing capabilities than traditional computers. Among them, quantum computing solutions based on superconducting systems are more eye-catching due to their good scalability and compatibility with existing semiconductor technologies.

[0053] The powerful computing power of quantum computing primarily stems from quantum superposition. However, superposition states based on quantum mechanics are easily disturbed by the environment and depolarized to classical states. The time required for depolarization is called relaxation time, and its length directly affects the computing power of quantum computers. Therefore, how to prolong the coherence of quantum systems has become a key issue for quantum computers.

[0054] The influence of superconducting materials on coherence is mainly the TLS loss of the material itself. The TLS loss mainly comes from the oxide layer on the surface of the material. In order to reduce the TLS loss, some solutions are usually adopted, such as replacing the commonly used aluminum film with a niobium or tantalum film with a thinner oxide layer, or using hydrofluoric acid to remove the oxide layer and then placing it in a refrigerator for vacuum cooling as soon as possible.

[0055] Superconducting quantum chips are one of the important carriers that can be used to study quantum computing. They are generally composed of a substrate, a waveguide film layer (also commonly known as a large circuit structure), a quantum bit structure, and other structures.

[0056] Please refer to Figure 1, which shows a flow chart of the preparation of a superconducting quantum chip involved in this application. As shown in Figure 1, the method may include the following steps:

[0057] Step 101: Clean the substrate.

[0058] Among them, the substrate is mainly sapphire or silicon wafer. The purpose of cleaning is mainly to remove organic impurities on the surface of the substrate. In addition, the step of cleaning the silicon wafer is also to remove the natural oxide layer on the surface of the silicon wafer.

[0059] Step 102: growing a bottom film of quantum bits on a substrate.

[0060] Among them, the bottom film can be selected from aluminum film, niobium film or tantalum film. The bottom film is mainly used to prepare large-scale structures such as transmission lines, resonant cavities, and capacitors of quantum chips;

[0061] Among them, the resonant cavity and capacitor have become the main sources of TLS loss due to the large distribution of microwave fields.

[0062] Step 103: Expose the bottom film to prepare transmission lines, resonant cavities, capacitors, etc.

[0063] Step 104: Prepare a Josephson junction to form a quantum bit by using an angled coating method.

[0064] Step 105, measuring the quantum bit at low temperature.

[0065] It should be noted that in the steps of preparing quantum chips, since the bottom film needs to be exposed after the bottom film coating in step 102, the bottom film will be oxidized in the air, resulting in TLS loss of the material itself, which in turn affects the coherence of the quantum bit.

[0066] Please refer to Figure 2, which shows a schematic diagram of the structure of a quantum bit assembly involved in an embodiment of the present application. As shown in Figure 2, part (a) of Figure 2 is a top view of the quantum bit assembly, and part (b) of Figure 2 is a cross-sectional view of the quantum bit assembly. The quantum bit assembly includes the following parts:

[0067] The underlying circuit 201 and the quantum bit 202 .

[0068] The surface of the bottom circuit 201 has a nitride passivation layer 201 a.

[0069] That is, the quantum bit component includes an underlying circuit 201 and a quantum bit 202 , and the surface of the underlying circuit 201 has a layered structure of a nitride passivation layer 201 a .

[0070] The nitride passivation layer 201 a may correspond to the material of the bottom circuit 201 . For example, the material of the bottom circuit 201 is metal niobium, and the nitride passivation layer 201 a is a niobium nitride passivation layer.

[0071] Among them, the nitride passivation layer 201a may also not correspond to the material of the underlying circuit 201, and the nitride passivation layer 201a can be evaporated by coating. For example, the material of the underlying circuit 201 is metal aluminum, and then a nitride passivation layer 201a of niobium nitride or tantalum nitride is evaporated on the underlying circuit 201.

[0072] To summarize, the quantum bit assembly shown in the embodiment of the present application includes an underlying circuit 201 and a quantum bit 202, and the surface of the underlying circuit 201 has a nitride passivation layer 201a, wherein the nitride passivation layer 201a can prevent oxidation of the underlying circuit surface 201, thereby reducing the generation of TLS loss and extending the coherence time of the quantum bit.

[0073] Based on the embodiment shown in FIG2 above, please refer to FIG3, which shows a schematic diagram of the structure of another quantum bit assembly involved in the embodiment of the present application. As shown in FIG3, part (a) of FIG3 is a top view of the quantum bit assembly, and part (b) of FIG3 is a cross-sectional view of the quantum bit assembly. The quantum bit assembly includes the following parts:

[0074] The underlying circuit 201 and the quantum bit 202 .

[0075] The surface of the bottom circuit 201 has a nitride passivation layer 201 a.

[0076] As shown in FIG. 3 , in a possible implementation, the side surface of the etching groove 203 of the bottom circuit has a nitride passivation layer 203 a .

[0077] After the underlying thin film is exposed and etched according to the pattern of the underlying circuit, the inner wall of the etching groove 203 is still likely to be oxidized because it is not covered by the passivation layer. Therefore, the nitride passivation layer on the inner wall of the etching groove 203 can further prevent oxidation of the sidewall of the etching groove.

[0078] In this regard, the embodiment of the present application is based on the embodiment shown in FIG. 2 , and the side surface of the etching groove 203 of the bottom circuit also has a layered structure of a nitride passivation layer 203 a .

[0079] That is, the quantum bit component includes an underlying circuit 201 and a quantum bit 202, and the surface of the underlying circuit 201 has a layered structure of a nitride passivation layer 201a, and the side of the etching groove 203 of the underlying circuit has a layered structure of a nitride passivation layer 203a.

[0080] The nitride passivation layer 203a may correspond to the material of the bottom circuit 203. For example, the material of the bottom circuit 203 is metal tantalum, and the nitride passivation layer 201a is a tantalum nitride passivation layer.

[0081] Among them, the nitride passivation layer 203a may also not correspond to the material of the underlying circuit 201. The nitride passivation layer 203a can be evaporated by coating. For example, the material of the underlying circuit 201 is metal aluminum, and then a nitride passivation layer 203a of niobium nitride or tantalum nitride is evaporated on the side of the etched groove 203.

[0082] The quantum bit assembly shown in the embodiment of the present application includes an underlying circuit 201 and a quantum bit 202, and the surface of the underlying circuit 201 has a nitride passivation layer 201a, and the inner wall of the etching groove 203 has a nitride passivation layer 203a. The nitride passivation layer 201a and the nitride passivation layer 203a can prevent oxidation of the surface of the underlying circuit 201 and the inner wall of the etching groove 203, reduce the generation of TLS loss, and extend the coherence time of the quantum bit.

[0083] In a possible implementation, the material of the bottom circuit is metal niobium, metal tantalum or metal aluminum, and the nitride passivation layer is a niobium nitride passivation layer, a tantalum nitride passivation layer or an aluminum nitride passivation layer.

[0084] In an embodiment of the present application, the material of the underlying circuit may be a superconducting material that can be nitrided, for example, the material of the underlying circuit is metal aluminum, metal niobium or metal tantalum, and accordingly, the above-mentioned nitride passivation layer may be an aluminum nitride passivation layer, a niobium nitride passivation layer or a tantalum nitride passivation layer.

[0085] For example, when the material of the above-mentioned underlying circuit is metal aluminum, the above-mentioned nitride passivation layer can be an aluminum nitride passivation layer; or, when the material of the above-mentioned underlying circuit is metal niobium, the above-mentioned nitride passivation layer can be a niobium nitride passivation layer; when the material of the above-mentioned underlying circuit is metal tantalum, the above-mentioned nitride passivation layer can be aluminum nitride tantalum passivation layer.

[0086] Alternatively, the material of the underlying circuit and the material of the nitride passivation layer may not correspond to each other. For example, when the material of the underlying circuit is metallic aluminum, the nitride passivation layer may be a niobium nitride passivation layer or a tantalum nitride passivation layer; or, when the material of the underlying circuit is metallic niobium, the nitride passivation layer may be an aluminum nitride passivation layer or a tantalum nitride passivation layer; or, when the material of the underlying circuit is metallic tantalum, the nitride passivation layer may be an aluminum nitride passivation layer or a niobium nitride passivation layer.

[0087] The underlying circuit can be made of superconducting materials that can be nitrided, such as metal aluminum, metal niobium or metal tantalum. This not only facilitates the formation of a nitride passivation layer on the surface of the underlying circuit or the inner wall of the etching groove, but the nitride passivation layer can also inhibit the oxidation of the surface of the underlying circuit or the inner wall of the etching groove, reduce the generation of TLS loss, and extend the coherence time of the quantum bit; it can also improve the universality of this technical solution and can be widely used in superconducting thin films such as aluminum film, niobium film or tantalum film.

[0088] In a possible implementation, the bottom layer circuit includes at least one of the following structures: a resonant cavity, a capacitor, and a transmission line.

[0089] Among them, in quantum bit components, the resonant cavity and capacitor have become the main sources of TLS loss because they are distributed with a large number of microwave fields; in addition, the transmission line is also a large structure, which will also bring certain TLS loss.

[0090] In this regard, in an embodiment of the present application, in an underlying circuit including at least one structure of a resonant cavity, a capacitor, and a transmission line, the surface of the underlying circuit is covered with a nitride passivation layer to suppress the formation of an oxide layer on the surface of structures such as the resonant cavity, the capacitor, and the transmission line, thereby effectively reducing the generation of TLS and extending the coherence time of the quantum bit.

[0091] In a possible implementation, the thickness of the nitride passivation layer is 5-10 nanometers.

[0092] In the embodiments of the present application, the thickness of the nitride passivation layer on the underlying circuit surface and the sides of the etched grooves can be controlled to 5-10 nanometers. This can suppress oxidation on the underlying circuit surface and the sides of the etched grooves; it can also prevent excessive thickness of the nitride passivation layer from affecting the performance of the qubit component.

[0093] Please refer to Figure 4, which shows a schematic structural diagram of a quantum chip involved in an embodiment of the present application. As shown in Figure 4, the quantum chip provided in an embodiment of the present application includes one or more quantum bit components 401, and the quantum bit component 401 can be the quantum bit component of Figure 2 or Figure 3 above.

[0094] Please refer to Figure 5, which shows a flow chart of a method for preparing a quantum bit assembly provided by an exemplary embodiment of the present application. This method can prepare the quantum bit assembly shown in Figure 2 or Figure 3; as shown in Figure 5, the method can include the following steps:

[0095] Step 510: Prepare the bottom film of the quantum bit component on the substrate.

[0096] In the embodiment of the present application, a bottom film layer may be prepared on the substrate first, for example, by evaporating a superconducting material on the substrate through an evaporation machine, thereby preparing / growing a bottom film layer on the substrate.

[0097] Among them, the bottom film can be made of superconducting materials that can be nitrided, such as aluminum film, niobium film or tantalum film, to facilitate the subsequent generation of a nitride passivation layer on the surface of the bottom circuit to inhibit the oxidation of the bottom circuit surface or the inner wall of the etching groove, reduce the generation of TLS loss, and extend the coherence time of the quantum bit.

[0098] Before preparing the bottom film of the quantum bit component on the substrate, the substrate can be cleaned to remove organic impurities and oxide layers on the substrate.

[0099] Step 520: preparing a bottom circuit based on the bottom film, wherein the surface of the bottom circuit has a nitride passivation layer.

[0100] In an embodiment of the present application, the underlying circuit on the substrate can be prepared by performing steps such as photoresist spin coating, exposure, photoresist cleaning, and underlying film etching on the underlying film according to the pattern / mask of the underlying circuit. During this process, the underlying film will also be nitrided so that the surface of the underlying circuit can have a nitride passivation layer. The nitride passivation layer can prevent oxidation of the surface of the underlying circuit, reduce the generation of TLS loss, and extend the coherence time of the quantum bit.

[0101] The nitride passivation layer may be a niobium nitride passivation layer, a tantalum nitride passivation layer or an aluminum nitride passivation layer.

[0102] Step 530: Prepare quantum bits connected to the underlying circuit on the substrate to obtain a quantum bit assembly.

[0103] After preparing the underlying circuit with a nitride passivation layer, quantum bits connected to the underlying circuit can be further prepared. Since the surface of the underlying circuit has a nitride passivation layer, the oxidation phenomenon on the surface of the underlying circuit will be suppressed in the subsequent preparation process, and the final quantum bit component will have better coherence.

[0104] In summary, the scheme shown in the embodiment of the present application is a quantum bit component prepared in which the surface of the underlying circuit has a nitride passivation layer. Since the nitride passivation layer can effectively prevent the oxidation of the film surface, the above-mentioned quantum bit component can reduce the generation of TLS loss and extend the coherence time of the quantum chip. In other words, the above-mentioned scheme can be used to prepare superconducting quantum chips with long decoherence, thereby improving the decoherence performance of the superconducting quantum chip.

[0105] Based on the embodiment shown in Figure 5, please refer to Figure 6, which shows a flow chart of the method for preparing a quantum bit component provided by an embodiment of the present application. As shown in Figure 6, step 520 in the embodiment shown in Figure 5 can be implemented as steps 520a and 520b.

[0106] Step 520a: Performing a nitridation process on the bottom film.

[0107] In one possible implementation, the nitriding method shown in the embodiment of the present application may include the following steps:

[0108] First, a bottom film is grown on a substrate, for example, by evaporation.

[0109] The bottom film may be an aluminum film, a niobium film or a tantalum film, the coating thickness may be 100-200 nm, and magnetron sputtering may be preferably selected as the coating method.

[0110] Afterwards, a nitride passivation layer can be grown in situ on the underlying film.

[0111] Among them, since aluminum nitride has a piezoelectric effect, which affects subsequent sample measurements, the passivation layer can be selected as niobium nitride or tantalum nitride, and the thickness of the passivation layer is 5-10 nm.

[0112] In a possible implementation, the nitriding method shown in the embodiment of the present application may further include:

[0113] 1) The bottom film is placed in a nitrogen environment and heated to a first temperature.

[0114] That is, one method of nitridation treatment is to place the underlying film in a nitrogen environment and apply a first temperature to the underlying film so that the nitrogen reacts with the underlying film to generate nitride, thereby forming a nitride passivation layer to prevent oxidation.

[0115] In one possible implementation, the first temperature is 800 degrees Celsius.

[0116] Optionally, the temperature applied to the bottom film is generally above 800 degrees Celsius, and 800 degrees Celsius can be selected in the embodiment of the present application.

[0117] 2) placing the bottom film in a nitrogen plasma implantation environment and heating it to a second temperature, and maintaining it for a specified time.

[0118] Optionally, in order to increase the reaction efficiency, another method of nitridation treatment is to directly use nitrogen plasma, and the equipment can be selected as a plasma stripper or a plasma etcher.

[0119] In order to improve the injection efficiency, a certain temperature can be applied to the underlying film. At this time, a few nanometers of nitride can be generated to form a nitride passivation layer to prevent oxidation.

[0120] In a possible implementation, the second temperature is 300 degrees Celsius, and the specified time is 10 minutes.

[0121] Optionally, the temperature applied to the bottom film can be heated to 300° C., and the nitrogen plasma injection time can be 10 minutes.

[0122] In summary, the solution shown in the embodiment of the present application can prevent the oxidation of the underlying film and reduce the TLS loss after the nitride is grown, because the TLS loss of the nitride is less than that of the oxide.

[0123] Step 520b: Expose and etch the nitrided bottom film according to the pattern of the bottom circuit to obtain the bottom circuit.

[0124] In an embodiment of the present application, after the bottom film is nitrided based on step 520a, the bottom film can be subjected to steps such as photoresist spin coating, exposure, photoresist cleaning, and bottom film etching according to the pattern / mask of the bottom circuit to prepare the bottom circuit on the substrate.

[0125] Because the underlying thin film is nitrided during the fabrication of the underlying circuit, the surface of the underlying circuit is protected by a nitride passivation layer, which suppresses oxidation on the surface of the underlying circuit and ultimately results in a qubit component with improved coherence.

[0126] The scheme shown in the embodiment of the present application can ultimately obtain a quantum bit component that is the quantum bit component of FIG2 above. As shown in FIG2 , the surface of the underlying circuit 201 has a nitride passivation layer 201a. The nitride passivation layer 201a can prevent oxidation of the surface of the underlying circuit, reduce the generation of TLS loss, extend the coherence time of the quantum bit, and improve the coherence of the quantum bit.

[0127] Please refer to Figure 7, which shows a schematic diagram of a nitride passivation layer deposited on an underlying film involved in this application. As shown in Figure 7, after depositing the underlying superconducting film, a passivation layer can be introduced on the film surface to prevent oxidation of the film. This method of growing a nitride passivation layer is relatively simple. However, in subsequent steps, it is still necessary to perform photoresist spin coating, exposure, photoresist cleaning, and etching of the underlying film on the underlying film. At this time, the sidewalls of the etched grooves are still oxidized because they are not covered by the passivation layer. Please refer to Figure 8, which shows a schematic diagram of an oxide layer on the sidewalls of the etched grooves involved in this application.

[0128] Based on the embodiment shown in Figure 5, please refer to Figure 9, which shows a flow chart of the method for preparing a quantum bit component provided by an embodiment of the present application. As shown in Figure 9, step 520 in the embodiment shown in Figure 5 can be implemented as step 520c.

[0129] Step 520c: After exposing and etching the bottom film according to the pattern of the bottom circuit, perform nitridation treatment to obtain the bottom circuit.

[0130] After the bottom film is exposed and etched according to the pattern of the bottom circuit, the inner wall of the etching groove is not covered by the passivation layer and may still be oxidized. The oxidation of the etching groove can be shown in the schematic diagram of the etching groove sidewall oxide layer shown in Figure 8 above.

[0131] Therefore, after the steps of photoresist spin coating, exposure, photoresist cleaning, and etching of the underlying film, the surface of the underlying film and the side walls of the etching groove can be nitrided to obtain an underlying circuit with a nitride passivation layer on the surface, thereby avoiding oxidation of the underlying film and the side walls of the etching groove, reducing the generation of TLS, extending the coherence time of the quantum bit, and improving the coherence of the quantum bit.

[0132] In one possible implementation, the nitriding treatment includes:

[0133] The first product obtained by exposing and etching the bottom film is placed in a nitrogen environment and heated to a first temperature.

[0134] That is, one method of nitridation treatment is to place the product obtained after the underlying film is subjected to the steps of photoresist spin coating, exposure, photoresist cleaning, and underlying film etching according to the pattern of the underlying circuit in a nitrogen environment, and apply a first temperature to the film so that the nitrogen and the film react to generate nitride, thereby forming a nitride passivation layer to prevent oxidation.

[0135] The nitride passivation layer can prevent oxidation of the underlying film and the sidewalls of the etched groove, reduce the generation of TLS loss, extend the coherence time of the quantum bit, and improve the coherence of the quantum bit.

[0136] In one possible implementation, the first temperature is 800 degrees Celsius. Optionally, the first temperature may be lower than 800 degrees Celsius, or higher than 800 degrees Celsius. For example, the first temperature may be between 700 degrees Celsius and 900 degrees Celsius.

[0137] The temperature applied to the film is generally above 800 degrees Celsius, and 800 degrees Celsius is selected in this embodiment. On the one hand, this provides a suitable ambient temperature for the nitrogen to react with the underlying film to form nitrides; on the other hand, it prevents the ambient temperature from being too low, which could affect the anti-oxidation properties of the nitride or the nitride passivation layer.

[0138] In one possible implementation, the nitriding treatment includes:

[0139] The first product obtained after exposing and etching the bottom film is placed in a nitrogen plasma injection environment and heated to a second temperature and maintained for a specified time.

[0140] Among them, in order to increase the reaction efficiency, another nitridation treatment method is to directly use nitrogen plasma, and the equipment can be selected as a plasma stripper or a plasma etcher.

[0141] That is to say, another method of nitridation treatment is to place the product obtained after the underlying film is subjected to the steps of photoresist spin coating, exposure, photoresist cleaning, and underlying film etching according to the pattern of the underlying circuit, into a nitrogen plasma injection environment, so that the nitrogen and the underlying film react to generate nitride, forming a nitride passivation layer to prevent oxidation.

[0142] The nitride passivation layer can prevent oxidation of the underlying film and the sidewalls of the etched groove, reduce the generation of TLS loss, extend the coherence time of the quantum bit, and improve the coherence of the quantum bit.

[0143] Among them, the equipment can be a plasma stripper or a plasma etcher.

[0144] In order to improve the injection efficiency, a certain temperature can be applied to the film. At this time, a few nanometers of nitride can be generated to form a nitride passivation layer to prevent oxidation.

[0145] In one possible implementation, the second temperature is 300 degrees Celsius, and the specified duration is 10 minutes. Alternatively, the second temperature can be lower than 300 degrees Celsius, or higher than 300 degrees Celsius; for example, the second temperature can be between 250 degrees Celsius and 350 degrees Celsius. Alternatively, the specified duration can be higher than 10 minutes, or lower than 10 minutes; for example, the specified duration can be between 15 minutes and 25 minutes.

[0146] In the embodiment of the present application, the temperature applied to the film can be heated to approximately 300°C, and the nitrogen plasma injection time can be approximately 10 minutes. This, on the one hand, provides a suitable ambient temperature and reaction time for the nitrogen gas to react with the underlying film to form the nitride; on the other hand, it prevents the oxidation resistance of the nitride or the nitride passivation layer from being affected by excessively high or low ambient temperatures or excessively short or long reaction times.

[0147] In one possible implementation, the nitriding treatment includes:

[0148] A nitride passivation layer is evaporated on the first product obtained after exposing and etching the bottom film.

[0149] For example, a nitride passivation layer may be obtained by evaporating nitride in an in-situ coating manner.

[0150] For example, the following process flow can be performed in situ: a first product is obtained by exposing and etching the underlying film, the photoresist is cleaned, and a nitride passivation layer is grown on the first product. The underlying film can be an aluminum film, a niobium film, or a tantalum film. Because aluminum nitride has a piezoelectric effect that affects subsequent sample measurements, the nitride passivation layer can be a niobium nitride or tantalum nitride passivation layer.

[0151] Alternatively, after the first product is obtained by exposing and etching the underlying film, the natural oxide layer on the surface of the first product may be cleaned before the nitride passivation layer is evaporated.

[0152] Since nitrides have lower TLS losses than oxides, the nitride passivation layer can prevent oxidation of the underlying film after growth, thereby reducing TLS losses. The embodiments of the present application can improve the universality of the technical solution and can be widely used in superconducting thin films such as aluminum films, niobium films, or tantalum films.

[0153] In a possible implementation, before the nitriding treatment, the method further includes:

[0154] The surface of the first product is rinsed to remove an oxide layer on the surface of the first product.

[0155] That is to say, the etched sample needs to be rinsed first and then nitrided.

[0156] Among them, hydrofluoric acid can be used for rinsing, the purpose of which is to remove the surface oxide layer.

[0157] Since nitride is directly generated on the surface of the bottom film, the bottom film can be made of niobium film or tantalum film. The specific implementation steps of the above embodiment can be:

[0158] First, the etched sample is rinsed with hydrofluoric acid to remove the surface oxide layer;

[0159] Then, the film is placed in a nitrogen environment and a temperature is applied to the film, generally above 800°C, so that the nitrogen reacts with the film to form nitride.

[0160] To increase reaction efficiency, nitrogen plasma can be used directly, using a plasma stripper or plasma etcher. To improve injection efficiency, the film can be heated to a suitable temperature, such as 300°C, and the nitrogen plasma injection time can be 10 minutes.

[0161] At this time, several nanometers of nitride can be generated, which can provide good protection for the surface of the film and the side walls of the etching groove.

[0162] Based on the solution shown in the embodiment of the present application, an improved method is provided for performing nitrogen ion implantation after etching, wherein the injection direction of the nitrogen ions is at a certain angle, and the sample below needs to be rotated during the injection so that the sidewalls of the etched groove can be implanted with nitrogen ions. Please refer to Figure 10, which shows a schematic diagram of a nitrogen ion implantation shown in an exemplary embodiment of the present application. As shown in Figure 10, part (a) of Figure 10 is a schematic diagram of the nitrogen ion implantation process, and part (b) of Figure 10 is a schematic diagram of the generation of a nitride passivation layer after nitridation treatment.

[0163] The solution shown in the embodiment of this application can ultimately result in a qubit assembly such as the qubit assembly shown in FIG. 3 . As shown in FIG. 3 , the qubit assembly includes an underlying circuit 201 and a qubit 202. The surface of the underlying circuit 201 has a nitride passivation layer 201a, and the inner wall of the etched groove 203 has a nitride passivation layer 203a. Nitride passivation layers 201a and 203a can prevent oxidation of the underlying circuit surface, reduce TLS loss, and extend the coherence time of the qubit.

[0164] Based on the embodiment shown in FIG5 , please refer to FIG11 , which shows a flow chart of a method for preparing a quantum bit assembly according to an embodiment of the present application. As shown in FIG11 , step 530 in the embodiment shown in FIG5 can be implemented as steps 530a, 530b, 530c, 530d, and 530e.

[0165] Step 530a: Prepare a quantum bit structure that is not connected to the underlying circuit through a Dolan bridge photoresist structure; the quantum bit structure includes a three-layer structure, which includes a first superconducting portion and a second superconducting portion that intersect each other, and an insulating layer between the first superconducting portion and the second superconducting portion.

[0166] The qubit structure is located in the extension direction of the underlying circuit, that is, there is an exposed substrate between the underlying circuit and the qubit structure.

[0167] In the embodiments of the present application, the qubit structure is a Josephson junction, that is, a superconductor-insulator-superconductor structure, where the first superconducting portion and the second superconducting portion are separated by an insulating layer. This qubit structure can be fabricated using a Dolan bridge photoresist structure.

[0168] Among them, the Dolan bridge photoresist structure is a photoresist structure used to prepare a Josephson junction.

[0169] In a possible implementation, step 530a may include the following steps:

[0170] 1) Applying a first photoresist layer on the sample in step 520 and performing a first bake, wherein the first photoresist layer defines a quantum bit structure;

[0171] The first photoresist may be a positive photoresist, a negative photoresist, or a combination of multiple layers of photoresist.

[0172] The first baking temperature is the soft baking temperature of the first photoresist.

[0173] For example, polymethyl methacrylate (PMMA) photoresist may be coated on the sample obtained in step 520 and baked at 160 degrees Celsius for 10 minutes.

[0174] 2) performing exposure, development, and fixing treatment on the sample to obtain a Dolan bridge photoresist structure. Unlike the conventional structure, the Dolan bridge photoresist structure in the embodiment of the present application does not include a portion connecting the quantum bit structure to the external circuit waveguide;

[0175] The exposure method may be electron beam exposure.

[0176] The developer may be methyl isobutyl ketone (MIBK) or a mixture of MIBK and isopropyl alcohol (IPA).

[0177] The fixing solution may be IPA.

[0178] For example, in this step, the sample can be placed in an electron beam exposure machine, exposed at a certain dose, then taken out and placed in a developer with a MIBK:IPA ratio of 1:3 for development, and then placed in IPA for fixing to obtain a Dolan bridge structure.

[0179] 3) Perform dual-angle evaporation on the sample:

[0180] ① Vertically evaporate the first superconducting material;

[0181] ②Preparing the insulating layer;

[0182] ③ Vapor-deposit the first superconducting material at a certain tilt angle.

[0183] Among them, the evaporation methods include electron beam evaporation, magnetron sputtering, or thermal evaporation, and the equipment used may include a dual-tilt multi-chamber coating machine.

[0184] The insulating layer may be an oxide layer.

[0185] The preparation method of the insulating layer may include dynamic oxygen oxidation or static constant pressure oxygen oxidation in a vacuum chamber.

[0186] The tilt angle of the inclined evaporation is 20°-70°.

[0187] The first superconducting material may be aluminum, tantalum, niobium, etc.

[0188] For example, in this step, the sample can be placed in a double-tilt multi-chamber evaporation coating machine, and aluminum with a thickness of 30nm can be vertically evaporated first. Then, static oxidation is used to form an oxide insulating layer on the aluminum surface, and then aluminum with a thickness of 30nm can be obliquely evaporated to form a Josephson junction structure.

[0189] Step 530b: Use a degumming solution to clean the sample in step 530a to obtain a structure containing a quantum bit structure that is not connected to the underlying circuit.

[0190] In a possible implementation, the debonding solution may include acetone, N-Methylpyrrolidone (NMP), or Remover PG (an NMP-based special debonding agent).

[0191] For example, in this step, the sample obtained in step 530a can be placed in NMP for debonding and stripping.

[0192] Step 530c: removing the insulating layer from the first target region on the upper surface of the first superconducting portion and the insulating layer from the second target region on the upper surface of the second superconducting portion.

[0193] The first target area is the entire or partial area on the upper surface of the first superconducting portion outside the area corresponding to the second superconducting portion; correspondingly, the second target area is the entire or partial area on the upper surface of the second superconducting portion outside the area corresponding to the first superconducting portion.

[0194] In the embodiment of the present application, since the first superconducting portion and the second superconducting portion intersect with each other, a portion of the upper surface of the first superconducting portion is obscured by the second superconducting portion, while the remaining portion is exposed. To address this issue, in the solution shown in the embodiment of the present application, the insulating layer is removed from a portion of the exposed area on the upper surface of the first superconducting portion (i.e., the aforementioned first target area) so that the position of the first superconducting portion corresponding to the aforementioned first target area is not covered by the insulating layer. Accordingly, the solution shown in the embodiment of the present application also removes the insulating layer from a portion of the upper surface of the second superconducting portion (i.e., the aforementioned second target area).

[0195] In a possible implementation, step 530c may include the following steps:

[0196] 1) A second photoresist is coated on the sample in step 530b and a second baking is performed. The photoresist defines the portion where the quantum bit structure is connected to the underlying circuit.

[0197] The second photoresist may be a positive photoresist, a negative photoresist, or a combination of multiple layers of photoresist, or may be a photoresist of the same type as the first photoresist.

[0198] The second baking temperature is the soft baking temperature of the second photoresist.

[0199] For example, in this step, AZ6112 photoresist may be coated on the surface of the sample obtained in step 530b and then baked at 100 degrees Celsius for a period of time.

[0200] 2) Perform photolithography, development, and fixing to obtain a corresponding defined pattern, and then use an etching method to remove the exposed portion of the insulating layer produced in step 530a.

[0201] The above-mentioned photolithography method may include ultraviolet exposure or laser direct writing.

[0202] The developer may be tetramethylammonium hydroxide (TMAH) or a diluted TMAH solution.

[0203] The above etching methods include physical and / or reactive etching, and the etching equipment may include an ion beam etcher, a dry etcher, and the like.

[0204] For example, in this step, the sample can be placed in a laser direct writing device to engrave a pattern, then placed in a 2.38% concentration TMAH developer for development, and then fixed in deionized water to obtain the pattern of the connection area. The sample is then placed in an ion beam etcher to perform argon ion physical etching to remove the approximately 5 nm thick oxide insulating layer on the surface of the connection area exposed by the two layers of aluminum evaporated in step 530a.

[0205] Step 530d: Evaporate a connection layer on the underlying circuit, the quantum bit structure, and the substrate between the underlying circuit and the quantum bit structure. The connection layer is used to connect the first superconducting part and the second superconducting part to the underlying circuit in different areas respectively.

[0206] In one possible implementation, a second superconducting material (or other superconducting material other than the second superconducting material) may be evaporated onto the sample in step 530c to connect the quantum bit structure to the underlying circuit.

[0207] The above-mentioned evaporation method may include electron beam evaporation, magnetron sputtering, thermal evaporation, etc.

[0208] For example, in this step, the sample obtained in step 530c can be placed in an electron beam evaporation coating machine to evaporate aluminum with a thickness of 100 nm to connect the Josephson junction to the underlying circuit.

[0209] Step 530e: Use a degumming solution to clean the sample in step 530d to obtain a quantum bit component containing a quantum bit structure connected to the underlying circuit.

[0210] In a possible implementation, the degumming solution may include acetone, NMP, Remover PG, etc.

[0211] For example, in this step, the sample obtained in step 530d can be immersed in NMP for peeling, and finally a quantum bit component containing a quantum bit structure connected to an underlying circuit is obtained.

[0212] Please refer to Figure 12, which shows a preparation flow chart of the quantum bit component involved in the embodiment shown in Figure 11; as shown in Figure 12, after the above-mentioned step 530a, the surface of the quantum bit structure at this time is still oxidized because it is not covered by the passivation layer. Therefore, the sample obtained in step 530a can be nitrided to inhibit the oxidation of the surface of the quantum bit structure and avoid affecting the characteristics of the subsequent quantum bit components.

[0213] In a possible implementation, before step 530b, the step further includes: performing nitriding treatment on the sample in step 530a.

[0214] In a possible implementation, the nitridation treatment includes: placing the sample in step 530a in a nitrogen environment and heating it to a third temperature.

[0215] In a possible implementation, the third temperature is 800 degrees Celsius.

[0216] Specifically, one nitridation method involves placing a sample obtained by forming a qubit structure disconnected from the underlying circuitry using a Dolan bridge photoresist structure in a nitrogen atmosphere and heating it to 800 degrees Celsius. This allows the nitrogen to react with the surface of the qubit structure to form a nitride, which then forms a nitride passivation layer to prevent oxidation. This nitride passivation layer prevents oxidation of the qubit surface, reduces TLS losses, extends the coherence time of the qubit, and improves the coherence of the qubit.

[0217] In a possible implementation, the nitridation treatment includes placing the sample in step 530a in a nitrogen plasma injection environment, heating the sample to a fourth temperature, and maintaining the temperature for a specified period of time.

[0218] In order to increase the reaction efficiency, nitrogen plasma can be used directly, and the equipment can be selected as a plasma stripper or a plasma etcher.

[0219] In a possible implementation, the fourth temperature is 300 degrees Celsius, and the specified time is 10 minutes.

[0220] Another nitridation method involves placing a sample obtained by preparing a qubit structure disconnected from the underlying circuitry using a Dolan bridge photoresist structure, heating it to 300 degrees Celsius for 10 minutes in a nitrogen plasma-injected environment. This allows the nitrogen to react with the surface of the qubit structure to form a nitride, which forms a nitride passivation layer to prevent oxidation. This nitride passivation layer prevents oxidation of the qubit structure surface, reduces TLS loss, extends the coherence time of the qubit, and improves the coherence of the qubit.

[0221] In a possible implementation, the nitridation treatment includes: evaporating a nitride passivation layer on the sample in step 530a.

[0222] That is to say, the nitride passivation layer can be obtained by evaporating the nitride in a coating manner.

[0223] For example, a nitride passivation layer can be grown in situ on the surface of the qubit structure. The nitride passivation layer can be made of niobium nitride or tantalum nitride. Because nitrides exhibit lower TLS losses than oxides, the nitride passivation layer can prevent oxidation of the qubit surface and reduce TLS losses.

[0224] After preparing a quantum bit structure with a nitride passivation layer on the surface, a connection layer connecting the quantum bit structure and the underlying circuit can be further prepared. Since the surface of the underlying circuit and the surface of the quantum bit structure have a nitride passivation layer, the oxidation phenomenon of the surface of the underlying circuit and the surface of the quantum bit structure will be suppressed in the subsequent preparation process, and the final quantum bit component will have better coherence.

[0225] As shown in FIG12 , after the above step 530d, the surface of the connecting layer is still oxidized because it is not covered by the passivation layer. Therefore, the sample obtained in step 530d can be nitrided to inhibit the oxidation of the surface of the connecting layer and avoid affecting the characteristics of subsequent quantum bit components.

[0226] In a possible implementation, before step 530e, the step further includes: performing nitriding treatment on the sample in step 530d.

[0227] In a possible implementation, the nitridation treatment includes: placing the sample in step 530d in a nitrogen environment and heating it to a fifth temperature.

[0228] In one possible implementation, the fifth temperature is 800 degrees Celsius.

[0229] Specifically, one nitridation method involves placing a sample obtained by evaporating a connecting layer on the underlying circuitry, qubit structure, and the substrate between the underlying circuitry and qubit structure in a nitrogen atmosphere and heating it to 800 degrees Celsius. This allows the nitrogen to react with the surface of the connecting layer to form a nitride, forming a nitride passivation layer that prevents oxidation. This nitride passivation layer prevents oxidation of the connecting layer surface, reduces TLS loss, extends the coherence time of the qubit, and improves the coherence of the qubit.

[0230] In a possible implementation, the nitridation treatment includes: placing the sample in step 530d in a nitrogen plasma injection environment, heating it to a sixth temperature, and maintaining it for a specified period of time.

[0231] Among them, in order to increase the reaction efficiency, another nitridation treatment method is to directly use nitrogen plasma, and the equipment can be selected as a plasma stripper or a plasma etcher.

[0232] In a possible implementation, the sixth temperature is 300 degrees Celsius, and the specified time is 10 minutes.

[0233] Another nitridation method involves placing the sample obtained after evaporating a connecting layer on the underlying circuit, qubit structure, and the substrate between the underlying circuit and qubit structure in a nitrogen plasma-injected environment, heating it to 300 degrees Celsius for 10 minutes. This allows the nitrogen to react with the surface of the connecting layer to form a nitride, forming a nitride passivation layer that prevents oxidation. This nitride passivation layer can prevent oxidation of the connecting layer surface, reduce TLS loss, extend the coherence time of the qubit, and improve the coherence of the qubit.

[0234] In a possible implementation, the nitridation treatment includes: evaporating a nitride passivation layer on the sample in step 530d.

[0235] That is to say, the nitride passivation layer can be obtained by evaporating the nitride in a coating manner.

[0236] For example, after in-situ evaporation of a connection layer on the substrate between the underlying circuitry, the qubit structure, and the underlying circuitry and qubit structure, a nitride passivation layer is grown on the surface of the sample. The nitride passivation layer can be made of niobium nitride or tantalum nitride. Because nitrides have lower TLS loss than oxides, the nitride passivation layer can prevent oxidation of the connection layer surface after growth, thereby reducing TLS loss.

[0237] After preparing a connection layer with a nitride passivation layer on the surface, a quantum bit component in which the quantum bit structure is connected to the underlying circuit can be further prepared. Since the surface of the underlying circuit, the surface of the quantum bit structure and the surface of the connection layer all have a nitride passivation layer, the oxidation phenomenon of the surface of the underlying circuit, the surface of the quantum bit structure and the surface of the connection layer will be suppressed in the subsequent preparation process, and the quantum bit component finally obtained will have better coherence.

[0238] FIG13 shows a schematic diagram of a chip manufacturing system according to an exemplary embodiment of the present application. The chip manufacturing system can be implemented as a production line device. As shown in FIG13 , the chip manufacturing system includes:

[0239] Evaporation machine 1301, glue coating machine 1302, photolithography machine 1303 and etching machine 1304;

[0240] Evaporation machine 1301, used to prepare the bottom film of the quantum bit component on the substrate;

[0241] The glue coater 1302, the photolithography machine 1303 and the etching machine 1304 are used to prepare the bottom circuit based on the bottom film, and the surface of the bottom circuit has a nitride passivation layer;

[0242] The evaporator 1301, the glue coater 1302, the photolithography machine 1303 and the etcher 1304 are also used to prepare quantum bits connected to the underlying circuit on the substrate to obtain quantum bit components.

[0243] In one possible implementation, the system further includes a nitridation treatment device for performing nitridation treatment to obtain the underlying circuit after the coater 1302 and the photolithography machine 1303 expose and etch the underlying film according to the pattern of the underlying circuit.

[0244] In a possible implementation, the nitridation treatment equipment includes a nitridation chamber 1306 for placing a first product obtained after exposing and etching the bottom film in a nitrogen environment and heating it to a first temperature.

[0245] In one possible implementation, the first temperature is 800 degrees Celsius.

[0246] In one possible implementation, the nitridation treatment equipment includes a plasma cleaner or a plasma etcher, which is used to place the first product obtained after exposing and etching the underlying film in a nitrogen plasma injection environment and heat it to a second temperature and maintain it for a specified time.

[0247] In a possible implementation, the second temperature is 300 degrees Celsius, and the specified time is 10 minutes.

[0248] In a possible implementation, the nitridation treatment equipment includes an evaporator 1301, which is used to evaporate a nitride passivation layer on the first product obtained after exposing and etching the underlying film.

[0249] In one possible implementation, the system further includes:

[0250] The cleaning machine 1305 is used to rinse the surface of the first product to remove the oxide layer on the surface of the first product.

[0251] In one possible implementation, the system further includes a nitriding treatment device for performing a nitriding treatment on the bottom film;

[0252] The glue coater 1302, the photolithography machine 1303 and the etcher 1304 are used to expose and etch the bottom film after nitridation treatment according to the pattern of the bottom circuit to obtain the bottom circuit.

[0253] Optionally, the production line equipment also includes a power supply to supply power to electrical equipment such as the processor, the etcher 1304 , the photolithography machine 1303 , and the evaporation machine 1301 .

[0254] Optionally, the machines are spatially connected via conveyor belts, or the movement of the prepared products between the machines is accomplished using a robotic arm.

[0255] Optionally, the production line equipment further includes a memory, which can be used to store at least one computer instruction, and the processor executes the at least one computer instruction so that the production line equipment executes the above-mentioned quantum bit component preparation method.

[0256] Please refer to Figure 14, which shows a schematic diagram of an application scenario of a solution provided by an embodiment of the present application. As shown in Figure 14, the application scenario can be a superconducting quantum computing platform, which includes: a quantum computing device 1401, a dilution refrigerator 1402, a control device 1403, and a computer 1404.

[0257] Quantum computing device 1401 is a circuit that operates on physical qubits. Quantum computing device 1401 can be implemented as a quantum chip, such as a superconducting quantum chip operating near absolute zero. This quantum chip can be produced using the methods described in the above embodiments of this application. Dilution refrigerator 1402 is used to provide an absolute zero temperature environment for the superconducting quantum chip.

[0258] Control device 1403 controls quantum computing device 1401, and computer 1404 controls control device 1403. For example, a pre-written quantum program is compiled into instructions by software in computer 1404 and sent to control device 1403 (e.g., an electronic / microwave control system). Control device 1403 converts these instructions into electronic / microwave control signals, which are then input into dilution refrigerator 1402 to control the superconducting qubits, which are kept at a temperature below 10 mK. The reading process is the opposite, with the read waveform being transmitted to quantum computing device 1401.

Claims

1. A quantum bit component, the quantum bit component comprising: The underlying circuits and quantum bits; The bottom circuit surface has a nitride passivation layer.

2. The quantum bit component according to claim 1, wherein the side surfaces of the etched grooves of the underlying circuit have a nitride passivation layer.

3. The quantum bit assembly according to claim 1 or 2, characterized in that: The material of the bottom circuit is metal niobium, metal tantalum or metal aluminum; The nitride passivation layer is a niobium nitride passivation layer, a tantalum nitride passivation layer or an aluminum nitride passivation layer.

4. The quantum bit component according to any one of claims 1 to 3, wherein the underlying circuit comprises at least one of the following structures: Resonant cavity, capacitor and transmission line.

5. According to any one of claims 1 to 4, the quantum bit component, the thickness of the nitride passivation layer is 5-10 nanometers.

6. A method for preparing a quantum bit component, the method comprising: Preparing a bottom film of a quantum bit component on a substrate; Preparing a bottom layer circuit based on the bottom layer film, wherein the surface of the bottom layer circuit has a nitride passivation layer; A quantum bit connected to the underlying circuit is prepared on the substrate to obtain the quantum bit assembly.

7. The method according to claim 6, wherein preparing a bottom layer circuit based on the bottom layer film comprises: After the bottom layer film is exposed and etched according to the pattern of the bottom layer circuit, a nitridation treatment is performed to obtain the bottom layer circuit.

8. The method according to claim 7, wherein the nitriding treatment comprises: The first product obtained by exposing and etching the bottom film is placed in a nitrogen environment and heated to a first temperature.

9. The method according to claim 8, wherein the first temperature is 800 degrees Celsius.

10. The method according to claim 7, wherein the nitriding treatment comprises: The first product obtained after exposing and etching the bottom film is placed in a nitrogen plasma injection environment and heated to a second temperature, and maintained for a specified period of time.

11. The method according to claim 7, wherein the nitriding treatment comprises: A nitride passivation layer is evaporated on the first product obtained after exposing and etching the bottom film.

12. The method according to any one of claims 7 to 11, before the nitriding treatment, further comprising: The surface of the first product is rinsed to remove an oxide layer on the surface of the first product.

13. The method according to any one of claims 6 to 12, wherein the step of preparing a bottom layer circuit based on the bottom layer film comprises: Performing nitridation treatment on the bottom film; According to the pattern of the bottom layer circuit, the bottom layer film after nitridation is exposed and etched to obtain the Bottom layer circuit.

14. A quantum chip, comprising the quantum bit component according to any one of claims 1 to 5.

15. A chip preparation system, comprising: Evaporation machines, glue coating machines, photolithography machines and etching machines; The evaporator is used to prepare the bottom film of the quantum bit component on the substrate; The glue coating machine, the photolithography machine and the etching machine are used to prepare a bottom layer circuit based on the bottom layer film, and the bottom layer circuit surface has a nitride passivation layer; The evaporator, the glue coater, the photolithography machine and the etching machine are also used to prepare quantum bits connected to the underlying circuit on the substrate to obtain the quantum bit assembly.

16. The system according to claim 15, wherein the glue coater, the photolithography machine and the etcher are used to expose and etch the bottom film according to the pattern of the bottom circuit, and then perform nitridation treatment to obtain the bottom circuit.

17. The system of claim 16, wherein the nitriding process comprises: The first product obtained by exposing and etching the bottom film is placed in a nitrogen environment and heated to a first temperature.

18. The system of claim 17, wherein the first temperature is 800 degrees Celsius.

19. The system of claim 16, wherein the nitriding process comprises: The first product obtained after exposing and etching the bottom film is placed in a nitrogen plasma injection environment and heated to a second temperature, and maintained for a specified period of time.

20. The system of claim 16, wherein the nitriding process comprises: A nitride passivation layer is evaporated on the first product obtained after exposing and etching the bottom film.

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