Integrated circuit unit, gate drive circuit, and display panel

Abstract

An integrated circuit unit, a gate drive circuit, and a display panel. The integrated circuit unit comprises a first control sub-circuit (20), a second control sub-circuit (30), a third control sub-circuit (40), a fourth control sub-circuit (50) and an output sub-circuit (60). The second control sub-circuit (30) assists with control via several gating signals, the first control sub-circuit (20) and the second control sub-circuit (30) control the potential of a first node (N1), and the first node (N1) assists the third control sub-circuit (40) and the fourth control sub-circuit (50) in controlling the potentials of a second node (N2), a third node (N3) and a fourth node (N4), so as to control an output signal of the output sub-circuit (60). The integrated circuit unit does not need to be cascaded, and outputs a signal that is not controlled by other integrated circuit units. Therefore, the integrated circuit unit may be applied to a gate drive circuit, thereby realizing the output of a random frame displacement signal.

Description

Integrated circuit unit, gate drive circuit and display panel Technical Field

[0001] The present invention relates to display driving technology, and in particular to an integrated circuit unit, a gate driving circuit and a display panel. Background Art

[0002] Active-matrix organic light-emitting diodes (AMOLEDs) are poised to replace LCDs as the mainstream choice for next-generation displays due to their high contrast, wide viewing angles, and fast response times. OLED products inherently require EL devices to generate light, and the required current is provided by driver transistors. Due to variations in driver transistors, achieving uniform light emission requires increased consistency in device characteristics. This requires external compensation and shutdown compensation to address this issue.

[0003] Common external compensation methods have problems such as being unable to output random frame displacement signals or having overly complex circuits.

[0004] Summary of the Invention

[0005] The purpose of the present application is to provide an integrated circuit unit, a gate driving circuit and a display panel with a simple structure and capable of achieving random gating.

[0006] The present application discloses an integrated circuit unit, comprising:

[0007] A first control subcircuit is connected to the second clock signal terminal, the first power signal terminal and the first node, and controls the first node to an effective potential according to the second clock signal;

[0008] a second control subcircuit connected to the first node, the second clock signal terminal, the third clock signal terminal, the fifth power signal terminal, and a plurality of strobe signal terminals, and controlling the first node to an inactive potential according to the third clock signal and the signals of the plurality of strobe signal terminals;

[0009] a third control subcircuit connected to the first node, the second node, the third node, the fourth node, the third clock signal terminal, the fourth clock signal terminal, the second power signal terminal, the fifth power signal terminal, and the sixth power signal terminal, and controlling the second node and the third node to switch between a valid potential and an invalid potential;

[0010] a fourth control subcircuit connected to the first node, the second node, the third node, the fourth node, the fourth clock signal terminal, the first power signal terminal, and the fifth power signal terminal, and controlling the fourth node to switch between an effective potential and an ineffective potential;

[0011] The output sub-circuit is connected to the second node, the fourth node, the first clock signal terminal, the fourth power signal terminal and the output signal terminal, and outputs a driving signal under the control of the second node and the fourth node.

[0012] Optionally, the integrated circuit unit further includes a reset subcircuit connected to the reset signal terminal, the first node, the second node, and the fourth control subcircuit, for resetting the first node, the second node, and the fourth node.

[0013] Optionally, the third control subcircuit includes a second node control module, and the second node control module includes:

[0014] a twenty-second transistor, wherein a first electrode of the twenty-second transistor is connected to the second power signal terminal, a second electrode of the twenty-second transistor is connected to the second node, and a control electrode of the twenty-second transistor is connected to the third clock signal terminal;

[0015] a twenty-third transistor, wherein a first electrode of the twenty-third transistor is connected to the fifth power signal terminal, a second electrode of the twenty-third transistor is connected to the second node, and a first control electrode of the twenty-third transistor is connected to the fourth node;

[0016] A fourteenth transistor and a fifteenth transistor are connected in series between the fifth power signal terminal and the second node, a first control electrode of the fourteenth transistor is connected to the first node, and a first control electrode of the fifteenth transistor is connected to the fourth clock signal terminal.

[0017] Optionally, the fourteenth transistor, the fifteenth transistor and the twenty-third transistor are multi-control electrode structures, and the second control electrodes of the fourteenth transistor, the fifteenth transistor and the twenty-third transistor are all connected to the third node.

[0018] Optionally, the third control subcircuit includes a third node control module, and the third node control module includes:

[0019] a twenty-first transistor, wherein a first electrode of the twenty-first transistor is connected to the third node, and a second electrode of the twenty-first transistor is connected to the sixth power signal terminal;

[0020] a second energy storage unit connected between the third node and the fourth node;

[0021] A nineteenth transistor and a twentieth transistor are connected in series between the third node and the second power signal terminal, the control electrode of the nineteenth transistor is connected to the first node, and the control electrode of the twentieth transistor is connected to the fourth clock signal terminal.

[0022] Optionally, the third control subcircuit includes a third node control module, and the third node in the third node control module is directly connected to the sixth power signal terminal.

[0023] Optionally, the second control subcircuit includes a number of gating transistors connected in parallel, the number of which is less than or equal to a number of the gating signal terminals, and the control electrode of each of the gating transistors is connected to one of the gating signal terminals.

[0024] Optionally, a first electrode of the plurality of parallel-connected selection transistors is connected to the third clock signal terminal, and a second electrode is connected to the control electrode of the twelfth transistor to control the conduction between the second clock signal terminal and the first node.

[0025] Optionally, among the selection signal terminals connected to the plurality of selection transistors, a pulse width of the selection signal at the nth selection signal terminal is twice a pulse width of the selection signal at the n-1th selection signal terminal.

[0026] Optionally, the high level width and the low level width of the selection signal in one cycle of each of the selection signal terminals are equal.

[0027] Optionally, the fourth control subcircuit includes:

[0028] a twenty-seventh transistor, wherein a first electrode of the twenty-seventh transistor is connected to the fifth power signal terminal, a second electrode of the twenty-seventh transistor is connected to the fourth node, and a first control electrode of the twenty-seventh transistor is connected to the third node;

[0029] A twenty-fourth transistor and a twenty-sixth transistor are connected in series between the fourth node and the first power signal terminal, the control electrode of the twenty-fourth transistor is connected to the fourth clock signal terminal, and the control electrode of the twenty-sixth transistor is connected to the first node.

[0030] Optionally, the twenty-seventh transistor has a multi-control electrode structure, and the fourth control sub-circuit further includes:

[0031] a thirty-third transistor, a first electrode of the thirty-third transistor being connected to the reset signal terminal, and a second electrode of the thirty-third transistor being connected to the fifth node;

[0032] a fifth energy storage unit connected between the second node and the fifth node;

[0033] A second control electrode of the twenty-seventh transistor is connected to the fifth node.

[0034] Optionally, the fourth control subcircuit further includes:

[0035] The twenty-ninth transistor has a multi-control electrode structure, the first electrode of the twenty-ninth transistor is connected to the fifth power supply signal terminal, the second electrode of the twenty-ninth transistor is connected to the first node, the first control electrode of the twenty-ninth transistor is connected to the third clock signal terminal, and the second control electrode of the twenty-ninth transistor is connected to the fifth node.

[0036] The present application also discloses a gate drive circuit, comprising a plurality of integrated circuit unit groups, wherein the integrated circuit unit groups include at least one integrated circuit unit as described above, the number of the selection signal terminals is twice the number of the selection transistors, and the selection signal terminals include a plurality of positive selection signal terminals and a plurality of negative selection signal terminals whose signals are opposite to those of the positive selection signal terminals.

[0037] Optionally, the integrated circuit unit group includes four integrated circuit units, the integrated circuit units in the same group are connected to the selected communication end in the same order, and the integrated circuit units in the same group are connected to each clock signal end in a different order.

[0038] Optionally, different groups of the integrated circuit units have different connections with the selection signal terminal.

[0039] The present application also discloses a display panel, comprising the gate driving circuit as described above.

[0040] Compared with the related art, the integrated circuit unit of the present application does not need to be cascaded, and the signal it outputs is not controlled by other integrated circuit units. It can be applied to the gate control circuit to output a random frame displacement signal.

[0041] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0043] FIG1 is a block diagram of an integrated circuit unit of the present application.

[0044] FIG2 is a circuit diagram of an integrated circuit unit according to an embodiment of the present application.

[0045] FIG3 is a circuit diagram of another embodiment of the integrated circuit unit of the present application.

[0046] FIG4 is a circuit diagram of another embodiment of the integrated circuit unit of the present application.

[0047] FIG5 is a circuit diagram of another embodiment of the integrated circuit unit of the present application.

[0048] FIG6 is a circuit diagram of another embodiment of the integrated circuit unit of the present application.

[0049] FIG. 7 is a timing diagram of an integrated circuit unit according to an embodiment of the present application.

[0050] FIG8 is a connection diagram of an embodiment of a gate driving circuit of the present application.

[0051] FIG9 is a timing diagram of the selection signal terminal of the integrated circuit unit of the present application. DETAILED DESCRIPTION

[0052] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0053] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in this specification should have the same ordinary meaning as those having ordinary skill in the art to which this application belongs. The terms "first," "second," and similar terms used in this specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather indicate the presence of one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are used for convenience only and are not intended to limit the scope of the present disclosure to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0054] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0055] In the related art, general external compensation methods have problems such as being unable to output random frame displacement or having overly complex circuits.

[0056] To solve the above technical problems, the present application provides an integrated circuit unit, which includes:

[0057] The first control sub-circuit 20 is connected to the second clock signal terminal CLKB, the first power signal terminal VGH1 and the first node N1, and controls the first node N1 to a valid potential according to the second clock signal;

[0058] The second control sub-circuit 30 is connected to the first node N1, the second clock signal terminal CLKB, the third clock signal terminal CLKC, the fifth power signal terminal VGL2, and a plurality of strobe signal terminals, and controls the first node N1 to an inactive potential according to the third clock signal and the signals of the plurality of strobe signal terminals;

[0059] a third control sub-circuit 40 connected to the first node N1, the second node N2, the third node N3, the fourth node N4, the third clock signal terminal CLKC, the fourth clock signal terminal CLKD, the second power signal terminal VGH2, the fifth power signal terminal VGL2, and the sixth power signal terminal VGL3, and controlling the second node N2 and the third node N3 to switch between a valid potential and an invalid potential;

[0060] a fourth control sub-circuit 50 connected to the first node N1, the second node N2, the third node N3, the fourth node N4, the fourth clock signal terminal CLKD, the first power signal terminal VGH1, and the fifth power signal terminal VGL2, and controlling the fourth node N4 to switch between an active potential and an inactive potential;

[0061] The output sub-circuit 60 is connected to the second node N2, the fourth node N4, the first clock signal terminal CLKA, the fourth power signal terminal VGL1 and the output signal terminal SCOUT, and outputs a driving signal under the control of the second node N2 and the fourth node N4.

[0062] In order to solve the above technical problems, the present application further provides a gate driving circuit, which includes the above integrated circuit unit.

[0063] The present application also provides a display panel, comprising the above-mentioned gate driving circuit.

[0064] The integrated circuit unit of the present application does not need to be cascaded, and the signal it outputs is not controlled by other integrated circuit units. It can be applied to a gate control circuit to output a random frame displacement signal.

[0065] The following will describe in detail the various embodiments of the present application that are consistent with the above-mentioned creative concepts.

[0066] The transistors used in this disclosure may be triodes, thin-film transistors, field-effect transistors, or other devices with similar characteristics. The transistors may be P-type transistors or N-type transistors. In the embodiments of this disclosure, to distinguish the two electrodes of the transistor other than the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0067] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0068] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0069] The present application provides an integrated circuit unit.

[0070] As shown in Figures 1 and 2, the reset sub-circuit 20 is connected to the reset signal terminal TRS, the first node N1, the second node N2, and the fourth control sub-circuit 50, and resets the first node N1, the second node N2, and the fourth node N4. It includes a sixteenth transistor T16 and a seventeenth transistor T17. The sixteenth transistor T16 has a first electrode connected to the second node N2, a second electrode connected to the first power supply signal terminal VGH1, and a control electrode connected to the reset signal terminal TRS, so as to reset the second node N2 in response to the reset signal. The seventeenth transistor T17 has a first electrode connected to the first node N1, a second electrode connected to the fifth power supply signal terminal VGL2, and a control electrode connected to the reset signal terminal TRS, so as to reset the first node N1 in response to the reset signal. The reset signal terminal TRS is also connected to the third control sub-circuit 40 and the fourth control sub-circuit 50, so as to reset the third node N3 and the fourth node N4 in response to the reset signal.

[0071] The first control subcircuit 20 is connected to the second clock signal terminal CLKB, the first power signal terminal VGH1, and the first node N1. The first control subcircuit 20 includes a first transistor T1 and a first energy storage unit C1. The first transistor T1 has a first electrode connected to the first node N1, a second electrode connected to the first power signal terminal VGH1, and a control electrode connected to the second clock signal terminal CLKB. Under the control of the second clock signal, the transistor controls the first power signal to connect to the first node N1, thereby raising the voltage level of the first node N1.

[0072] The second control subcircuit 30 is connected to the first node N1, the second clock signal terminal CLKB, the third clock signal terminal CLKC, the fifth power supply signal terminal VGL2, and several selection signal terminals. The second control subcircuit 30 includes a tenth transistor T10, a twelfth transistor T12, and several selection transistors connected in parallel. One end of the plurality of selection transistors connected in parallel is connected to the third clock signal terminal CLKC, and the other end is connected to the first electrode of the tenth transistor T10 and the control electrode of the twelfth transistor T12. The second electrode of the tenth transistor T10 is connected to the fifth power supply signal terminal VGL2, and the control electrode is connected to the second clock signal terminal CLKB. The first electrode of the twelfth transistor T12 is connected to the second clock signal terminal CLKB, and the second electrode is connected to the first node N1.

[0073] The number of gate transistors connected in parallel can be changed according to needs, and can be 1, 3, 6, 8, or 11, etc. The number of the plurality of gate signal terminals is greater than or equal to the number of gate transistors, and the control electrode of each gate transistor is connected to a gate signal terminal. Among the gate signal terminals connected to the plurality of gate transistors, the pulse width of the gate signal of the nth gate signal terminal is twice the pulse width of the gate signal of the n-1th gate signal terminal, where n>1. The high-level width and the low-level width of the gate signal in one cycle of each gate signal terminal are equal. This embodiment takes 8 gate transistors and 8 gate signal terminals as an example. The 8 gate transistors are respectively the second transistor T2 to the 9th transistor T9, and the 8 gate signal terminals are the first gate signal terminal D0 to the eighth gate signal terminal D7. The 8 gate transistors are connected to the 8 gate signal terminals accordingly. One cycle of the eighth gate signal terminal D7 can cover 2^8 cycles of the first gate signal terminal D0. One high level segment of the eighth selection signal terminal D7 can cover 2^7 cycles of the first selection signal terminal D0.

[0074] When the third clock signal terminal CLKC is at a high level and any one of the eight selection signal terminals connected to the selection transistors is a high level signal, the second control sub-circuit 30 controls the twelfth transistor T12 to be turned on to connect the second clock signal terminal CLKB and the first node N1, thereby pulling the level of the first node N1 down.

[0075] Optionally, the number of selection signal terminals can be greater than 8, and a selection signal terminal with a phase opposite to any one of the first selection signal terminal D0 to the eighth selection signal terminal D7 can be added. For example, a ninth selection signal terminal D0' with a phase opposite to the first selection signal terminal D0 can be added. Alternatively, 8 signal terminals, from the ninth selection signal terminal D0' to the sixteenth selection signal terminal D7', with phases opposite to the first selection signal terminal D0 to the eighth selection signal terminal D7, can be added. One of a pair of selection signal terminals with opposite phases is selected to be connected to the control electrode of the selection transistor. Taking 8 pairs of selection signal terminals with opposite phases as an example, there can be 2^8 combinations, which can achieve 2^8 effective outputs with different timings.

[0076] The third control subcircuit 40 is connected to the first node N1, the second node N2, the third node N3, the fourth node N4, the third clock signal terminal CLKC, the fourth clock signal terminal CLKD, the second power signal terminal VGH2, the fifth power signal terminal VGL2, and the sixth power signal terminal VGL3. The third control subcircuit 40 includes a second node control module 41 and a third node control module 42.

[0077] The second node control module 41 includes a 22nd transistor T22 for pulling up the potential of the second node N2, and a 14th transistor T14, a 15th transistor T15, and a 23rd transistor T23 for pulling down the potential of the second node N2. The 22nd transistor T22 has a first electrode connected to the second power signal terminal VGH2, a second electrode connected to the second node N2, and a control electrode connected to the third clock signal terminal CLKC. The 23rd transistor T23 has a first electrode connected to the fifth power signal terminal VGL2, a second electrode connected to the second node N2, and a first control electrode connected to the fourth node N4. The 14th transistor T14 has a first electrode connected to the second node N2, a second electrode connected to the first electrode of the 15th transistor T15, and a control electrode connected to the first node N1. The 15th transistor T15 has a second electrode connected to the fifth power signal terminal VGL2, and a control electrode connected to the fourth clock signal terminal CLKD.

[0078] In an alternative embodiment, the third node control module 42 includes a nineteenth transistor T19 and a twentieth transistor T20 for pulling up the potential of the third node N3, a twenty-first transistor T21 for pulling down the potential of the third node N3, and a second energy storage unit C2 connecting the third node N3 and the fourth node N4. The nineteenth transistor T19 has a first electrode connected to the second power supply signal terminal VGH2, a second electrode connected to the first electrode of the twentieth transistor T20, and a control electrode connected to the first node N1. The twentieth transistor T20 has a second electrode connected to the third node N3, and a control electrode connected to the fourth clock signal terminal CLKD. The twenty-first transistor T21 has a first electrode connected to the sixth power supply signal terminal VGL3, a second electrode connected to the third node N3, and a control electrode connected to the reset signal terminal TRS.

[0079] The fourteenth transistor T14 , the fifteenth transistor T15 and the twenty-third transistor T23 have a multi-control electrode structure, and second control electrodes of the fourteenth transistor T14 , the fifteenth transistor T15 and the twenty-third transistor T23 are all connected to the third node N3 .

[0080] The fourth control subcircuit 50 is connected to the first node N1, the second node N2, the third node N3, the fourth node N4, the fourth clock signal terminal CLKD, the first power signal terminal VGH1, and the fifth power signal terminal VGL2. The fourth control subcircuit 50 includes a twenty-fourth transistor T24 and a twenty-sixth transistor T26 for pulling the potential of the fourth node N4 high, and a twenty-seventh transistor T27 for pulling the potential of the fourth node N4 low. A first electrode of the twenty-fourth transistor T24 is connected to the first power signal terminal VGH1, a second electrode is connected to the first electrode of the twenty-sixth transistor T26, and a control electrode is connected to the fourth clock signal terminal CLKD. A second electrode of the twenty-sixth transistor T26 is connected to the fourth node N4, and a control electrode is connected to the first node N1. A first electrode of the twenty-seventh transistor T27 is connected to the fifth power signal terminal VGL2, a second electrode is connected to the fourth node N4, and a control electrode is connected to the second node N2. Optionally, a third energy storage unit C3 is provided between the control electrode of the twenty-seventh transistor T27 and the fifth power signal terminal VGL2.

[0081] The output sub-circuit 60 is connected to the second node N2, the fourth node N4, the first clock signal terminal CLKA, the fourth power signal terminal VGL1, and the output signal terminal SCOUT. The output sub-circuit 60 includes a thirty-first transistor T31 that controls the output signal terminal SCOUT to output the first clock signal terminal CLKA, and a thirty-second transistor T32 that controls the output signal terminal SCOUT to output the fourth power signal terminal VGL1. The thirty-first transistor T31 has a first electrode connected to the first clock signal terminal CLKA, a second electrode connected to the output signal terminal SCOUT, and a control electrode connected to the fourth node N4. The thirty-second transistor T32 has a first electrode connected to the fourth power signal terminal VGL1, a second electrode connected to the output signal terminal SCOUT, and a control electrode connected to the second node N2. Optionally, a fourth energy storage unit C4 is provided between the output signal terminal SCOUT and the control electrode of the thirty-first transistor T31.

[0082] As shown in Figure 3, in an optional embodiment, a twenty-ninth transistor T29 and a thirtieth transistor T30 are further connected in series between the fourth node N4 and the fifth power signal terminal VGL2. The control electrodes of the twenty-ninth transistor T29 and the thirtieth transistor T30 are both connected to the third clock signal terminal CLKC. The configuration of the twenty-ninth transistor T29 and the thirtieth transistor T30 can more effectively lower the voltage of the fourth node N4, allowing the thirty-first transistor T31 to be more completely turned off. Optionally, a twenty-eighth transistor T28 is connected in series in the path between the fourth node, the twenty-seventh transistor T27, and the fifth power signal terminal VGL2. An eighteenth transistor T18 is connected in series in the path between the first node N1, the seventeenth transistor T17, and the fifth power signal terminal VGL2. A thirteenth transistor T13 is connected in series in the path between the first node N1, the twelfth transistor T12, and the second clock signal terminal CLKB to prevent leakage. Optionally, an eleventh transistor T11 may be provided, with a first electrode connected to the first power signal terminal VGH1, a control electrode connected to the first node N1, and a second electrode connected between the twelfth transistor T12 and the thirteenth transistor T13, and between the seventeenth transistor T17 and the eighteenth transistor T18, respectively. Optionally, a twenty-fifth transistor T25 may be provided, with a first electrode connected to the first power signal terminal VGH1, a control electrode connected to the fourth node N4, and a second electrode connected between the twenty-ninth transistor T29 and the thirtieth transistor T30. The aforementioned anti-leakage measures may be selectively added according to actual application circumstances, and different anti-leakage measures may also be selectively combined for use.

[0083] As shown in FIG4 , in an optional embodiment, the fourth control subcircuit 50 further includes a thirty-third transistor T33. A first electrode of the thirty-third transistor T33 is connected to the reset signal terminal TRS, and a second electrode is connected to the fifth node N5. A fifth energy storage unit C5 is connected between the second node N2 and the fifth node N5. A twenty-seventh transistor T27 has a multi-control electrode structure, with a first control electrode of the twenty-seventh transistor T27 connected to the second node N2 and a second control electrode connected to the fifth node N5.

[0084] As shown in FIG5 , in an optional embodiment, the fourth control subcircuit 50 further includes a twenty-ninth transistor T29 having a multi-control electrode structure. The twenty-ninth transistor T29 has a first electrode connected to the fifth power signal terminal VGL2, a second electrode connected to the fourth node N4, a first control electrode connected to the third clock signal terminal CLKC, and a second control electrode connected to the fifth node N5.

[0085] 6 , in an alternative embodiment, the third node N3 is directly connected to the sixth power signal terminal VGL3 .The third node N3 is connected to the second control electrodes of the fourteenth transistor T14 , the fifteenth transistor T15 , and the twenty-third transistor T23 .

[0086] As shown in FIG6 , in an alternative embodiment, the twenty-seventh transistor T27 has a multi-control electrode structure, wherein a first control electrode of the twenty-seventh transistor T27 is connected to the second node N2, and a second control electrode is connected to the seventh power signal terminal VGL4. Alternatively, the second control electrode may be connected to the sixth power signal terminal VGL3 instead of the seventh power signal terminal VGL4.

[0087] As shown in FIG7 , which is a timing diagram of an alternative embodiment, the reset signal terminal TRS is first reset, raising the potential of the second node N2 while simultaneously lowering the potential of the third node N3 to the potential of the sixth power signal terminal VGL3. The potential of the sixth power signal terminal VGL3 is lower than the potential of the fifth power signal terminal VGL2. This ensures that the potential of the second node N2 is effectively maintained when the reset signal terminal TRS outputs a low potential.

[0088] Phase 1 S1: The second clock signal terminal CLKB outputs a high potential, and the potential of the first node N1 is pulled high. When the third clock signal terminal CLKC outputs a high potential, since the selection signal terminals D0 to D7 are all low, the twelfth transistor T12 is turned off, and the potential of the first node N1 remains high.

[0089] Phase 2 S2: The fourth clock signal terminal CLKD outputs a high potential, and the first node N1 maintains a high potential. The second node N2 is pulled low, the third node N3 is pulled high to the potential of the second power supply signal terminal VGH2, and the fourth node N4 is pulled high to the potential of the first power supply signal terminal VGH1. Since the potential of VGH2 is lower than that of VGH1, the potential of the third node N3 is lower than that of the fourth node N4. The thirty-first transistor T31 is turned on.

[0090] Phase 3 S3: The fourth node N4 maintains a high potential, the first clock signal terminal CLKA outputs a high potential, and the output signal terminal SCOUT outputs a high potential. The fourth node N4 is coupled to a higher potential due to the fourth energy storage unit C4, and the third node N3 is also coupled to a higher potential due to the second energy storage unit C2.

[0091] Phase 4 S4: The third clock signal terminal CLKC outputs a high potential, the fourth node N4 is pulled low, and the second node N2 is pulled high. At this time, the first selection signal terminal D0 outputs a high potential, and the potential of the first node N1 is pulled low. Because the potential of the third node N3 is lower than the potential of the fourth node N4, the third node N3 is coupled to a lower potential, which can better turn off the fourteenth transistor T14, the fifteenth transistor T15, and the twenty-third transistor T23.

[0092] Fifth stage S5: the first node N1 maintains a low potential, the fourth clock signal terminal CLKD outputs a high potential, the fourth node N4 maintains a low potential, the second node N2 maintains a high potential, and the output signal terminal SCOUT outputs a low potential.

[0093] The integrated circuit unit of the present application controls the potential of the first node N1 through the first control subcircuit 20 and the second control subcircuit 30. This, in turn, controls the potentials of the second, third, and fourth nodes via the first node N1 in conjunction with a clock signal, thereby controlling the output signal at the output signal terminal SCOUT. This process eliminates the need for cascading with other integrated circuit units. When applied to a gate drive circuit, this unit can achieve random compensation for a specific pixel row. The stable regulation of the second node N2 improves the stability of the output subcircuit 60 and reduces the impact on the thirty-second transistor T32.

[0094] As shown in Figures 8 and 9. The present application also discloses a gate drive circuit, which includes multiple integrated circuit unit groups. An integrated circuit unit group includes at least one of the above-mentioned integrated circuit units. Each integrated circuit unit includes n gate transistors. The gate drive circuit includes 2n gate signal terminals, wherein the 2n gate signal terminals include D0, D0', D1, D1', D2, D2', D3, D3', D4, D4', D5, D5', ... Dn, D'n, a total of 16 signal terminals, wherein D0', D1', D2', D3', D4', D5', ... Dn' are respectively the inverted signals of D0, D1, D2, D3, D4, D5, ... Dn. The pulse width of Da is twice the pulse width of Da-1. Different groups of integrated circuit units have different connections to the gate signal terminals. The number of gate transistors in the present application can be set according to requirements.

[0095] In an optional embodiment, the control electrode of the a-th gate transistor among the n gate transistors is selectively connected to one of Da or Da', where a is greater than 0 and less than n. The integrated circuit units in the same integrated circuit unit group are connected to the gate signal terminal in the same manner. By analogy, 2n+1 integrated circuit unit groups can be made to work independently. Optionally, an integrated circuit unit group includes four integrated circuit units, and these four integrated circuit units realize shift output through a connection sequence different from that of each clock signal terminal. Therefore, the gate drive circuit of this embodiment can realize 2n+3 rows working independently. In the row shift stage, the gate drive circuit can adjust the signal output sequence of the gate signal terminal and the always signal terminal to shift rows. In the blanking stage, the gate drive circuit can adjust the signal output random frame shift of the gate signal terminal and the always signal terminal to realize random external compensation.

[0096] The present application also discloses a display panel, comprising the above-mentioned gate driving circuit.

[0097] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.

[0098] It should be understood that the present description is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0099] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. An integrated circuit unit, characterized in that: include: A first control subcircuit is connected to the second clock signal terminal, the first power signal terminal and the first node, and controls the first node to an effective potential according to the second clock signal; A second control subcircuit is connected to the first node, the second clock signal terminal, the third clock signal terminal, the fifth power signal terminal and a plurality of strobe signal terminals, and controls the first node to an invalid potential according to the third clock signal and the signals of the plurality of strobe signal terminals; A third control subcircuit is connected to the first node, the second node, the third node, the fourth node, the third clock signal terminal, the fourth clock signal terminal, the second power signal terminal, the fifth power signal terminal and the sixth power signal terminal, and controls the second node and the third node to switch between a valid potential and an invalid potential; a fourth control subcircuit connected to the first node, the second node, the third node, the fourth node, the fourth clock signal terminal, the first power signal terminal and the fifth power signal terminal, and controlling the fourth node to switch between a valid potential and an invalid potential; The output sub-circuit is connected to the second node, the fourth node, the first clock signal terminal, the fourth power signal terminal and the output signal terminal, and outputs a driving signal under the control of the second node and the fourth node.

2. The integrated circuit unit according to claim 1, characterized in that: The integrated circuit unit further includes a reset subcircuit connected to the reset signal terminal, the first node, the second node, and the fourth control subcircuit, and resets the first node, the second node, and the fourth node.

3. The integrated circuit unit according to claim 1, characterized in that: The third control subcircuit includes a second node control module, and the second node control module includes: a twenty-second transistor, wherein a first electrode of the twenty-second transistor is connected to the second power signal terminal, a second electrode of the twenty-second transistor is connected to the second node, and a control electrode of the twenty-second transistor is connected to the third clock signal terminal; a twenty-third transistor, wherein a first electrode of the twenty-third transistor is connected to the fifth power signal terminal, a second electrode of the twenty-third transistor is connected to the second node, and a first control electrode of the twenty-third transistor is connected to the fourth node; A fourteenth transistor and a fifteenth transistor are connected in series between the fifth power signal terminal and the second node, the first control electrode of the fourteenth transistor is connected to the first node, and the first control electrode of the fifteenth transistor is connected to the fourth clock signal terminal.

4. The integrated circuit unit according to claim 3, characterized in that: The fourteenth transistor, the fifteenth transistor and the twenty-third transistor are multi-control electrode structures, and the second control electrodes of the fourteenth transistor, the fifteenth transistor and the twenty-third transistor are all connected to the third node.

5. The integrated circuit unit according to claim 1, characterized in that: The third control subcircuit includes a third node control module, and the third node control module includes: a twenty-first transistor, a first electrode of the twenty-first transistor being connected to the third node, and a second electrode of the twenty-first transistor being connected to the sixth power signal terminal; A second energy storage unit is connected between the third node and the fourth node; A nineteenth transistor and a twentieth transistor are connected in series between the third node and the second power signal terminal, the control electrode of the nineteenth transistor is connected to the first node, and the control electrode of the twentieth transistor is connected to the fourth clock signal terminal.

6. The integrated circuit unit according to claim 1, characterized in that: The third control subcircuit comprises a third node control module, and the third node in the third node control module is directly connected to the sixth power signal terminal.

7. The integrated circuit unit according to claim 1, characterized in that: The second control subcircuit includes a number of parallel-connected gating transistors whose number is less than or equal to a number of the gating signal terminals, and a control electrode of each of the gating transistors is connected to one of the gating signal terminals.

8. The integrated circuit unit according to claim 7, characterized in that: The first electrodes of the plurality of parallel-connected selection transistors are connected to the third clock signal terminal, and the second electrodes are connected to the control electrode of the twelfth transistor to control the conduction between the second clock signal terminal and the first node.

9. The integrated circuit unit according to claim 8, characterized in that: Among the selection signal terminals connected to the selection transistors, the pulse width of the selection signal at the nth selection signal terminal is twice the pulse width of the selection signal at the n-1th selection signal terminal.

10. The integrated circuit unit according to claim 9, characterized in that: The high level width and the low level width of the selection signal in one cycle of each of the selection signal terminals are equal.

11. The integrated circuit unit according to claim 2, characterized in that: The fourth control subcircuit comprises: a twenty-seventh transistor, wherein a first electrode of the twenty-seventh transistor is connected to the fifth power signal terminal, a second electrode of the twenty-seventh transistor is connected to the fourth node, and a first control electrode of the twenty-seventh transistor is connected to the third node; A twenty-fourth transistor and a twenty-sixth transistor are connected in series between the fourth node and the first power signal terminal, the control electrode of the twenty-fourth transistor is connected to the fourth clock signal terminal, and the control electrode of the twenty-sixth transistor is connected to the first node.

12. The integrated circuit unit according to claim 11, characterized in that: The twenty-seventh transistor has a multi-control electrode structure, and the fourth control subcircuit further includes: a thirty-third transistor, a first electrode of the thirty-third transistor being connected to the reset signal terminal, and a second electrode of the thirty-third transistor being connected to the fifth node; a fifth energy storage unit connected between the second node and the fifth node; A second control electrode of the twenty-seventh transistor is connected to the fifth node.

13. The integrated circuit unit according to claim 12, characterized in that: The fourth control subcircuit further includes: The twenty-ninth transistor has a multi-control electrode structure, the first electrode of the twenty-ninth transistor is connected to the fifth power supply signal terminal, the second electrode of the twenty-ninth transistor is connected to the first node, the first control electrode of the twenty-ninth transistor is connected to the third clock signal terminal, and the second control electrode of the twenty-ninth transistor is connected to the fifth node.

14. A gate drive circuit, characterized in that: It comprises a plurality of integrated circuit unit groups, wherein the integrated circuit unit groups comprise at least one integrated circuit unit as described in any one of claims 1 to 13, the number of the selection signal terminals is twice the number of the selection transistors, and the selection signal terminals comprise a plurality of positive selection signal terminals and a plurality of negative selection signal terminals which are opposite to the signals of the positive selection signal terminals.

15. The gate driving circuit according to claim 14, characterized in that: The integrated circuit unit group includes four integrated circuit units. The integrated circuit units in the same group are connected to the selected communication terminal in the same order, and the integrated circuit units in the same group are connected to each clock signal terminal in a different order.

16. The gate driving circuit according to claim 15, characterized in that: Different groups of the integrated circuit units have different connections with the selection signal terminal.

17. A display panel, characterized in that: Comprising a gate drive circuit as described in any one of claims 14-16.

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