Array substrate and display panel

Abstract

Embodiments of the present disclosure provide an array substrate and a display panel. The array substrate comprises a plurality of first active patterns, a plurality of first metal wires, and a plurality of conductive portions. The conductive portions comprise first conductive portions and second conductive portions which are distributed in a first direction. Adjacent first metal wires on two sides of one conductive portion comprise first sub-metal wires and second sub-metal wires. The first sub-metal wires are electrically connected to second portions. First portions are electrically connected to first electrodes by means of the conductive portions. At least the distance between the orthographic projection of the second conductive portions on a substrate and the orthographic projection of the first sub-metal wires on the substrate is greater than the distance between the orthographic projection of the second conductive portions on the substrate and the orthographic projection of the second sub-metal wires on the substrate.

Description

Array substrate and display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on August 30, 2023, with application number PCT / CN2023 / 115924 and invention name "Array substrate, display panel and display device"; this application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 22, 2024, with application number PCT / CN2024 / 083398 and invention name "Array substrate, display panel and display device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present invention relates to the field of semiconductor technology, and in particular to an array substrate and a display panel. Background Art

[0004] Virtual reality technology seamlessly integrates real-world and virtual-world information. Compared to conventional display products, the most notable feature of VR display products is their ultra-high resolution. Liquid crystal display (LCD) technology is currently the best choice for achieving ultra-high PPI. This is because LCD display architectures use only a single switching transistor (TFT) in the pixel area, making it highly suitable for achieving high PPI.

[0005] Summary of the Invention

[0006] The present disclosure provides an array substrate and a display panel. The array substrate includes:

[0007] substrate;

[0008] The first active layer is located on one side of the substrate and includes: a plurality of first active patterns; the first active patterns include: a first portion and a second portion distributed along a first direction;

[0009] The first metal layer includes: a plurality of first metal lines; the second portion overlaps with a portion of the orthographic projection of the first metal line on the substrate;

[0010] The second metal layer includes: a plurality of second metal lines extending along a second direction;

[0011] The first conductive layer comprises: a plurality of conductive parts; an orthographic projection of at least one of the plurality of conductive parts on the substrate is located between orthographic projections of adjacent first metal lines on the substrate;

[0012] The second conductive layer includes: a plurality of first electrodes;

[0013] Among them, the first metal wires adjacent to the two sides of the conductive part include: a first sub-metal wire, and a second sub-metal wire; wherein, the first sub-metal wire is electrically connected to the second part; the first part is electrically connected to the first electrode through the conductive part; the distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the first sub-metal wire on the substrate is greater than the distance between the orthographic projection of the conductive part and the second sub-metal wire on the substrate.

[0014] In a possible embodiment, the conductive portions adjacent to each other on both sides of the first sub-metal line include: a first sub-conductive portion and a second sub-conductive portion; wherein the first sub-metal conductive portion is electrically connected to the first sub-metal line via a transistor;

[0015] The distance between the orthographic projection of the first sub-metal wire on the substrate and the orthographic projection of the first sub-conductive portion on the substrate is greater than the distance between the orthographic projection of the first sub-metal wire on the substrate and the orthographic projection of the second sub-conductive portion on the substrate.

[0016] In one possible embodiment, the conductive portion includes: a first conductive portion and a second conductive portion distributed along the first direction; an orthographic projection of the first conductive portion on the substrate overlaps with an orthographic projection of the first portion on the substrate, and an orthographic projection of the second conductive portion overlaps with an orthographic projection of the second portion on the substrate; and the first conductive portion and the second conductive portion extend in different directions;

[0017] At least the distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of the second conductive portion and the orthographic projection of the second sub-metal line on the substrate.

[0018] In a possible implementation manner, the second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line;

[0019] The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0020] In a possible implementation manner, the second conductive portion, the first sub-metal line, and the second sub-metal line satisfy the following relationship:

[0021] 0.05μm≤(ab) / 2≤0.15μm; wherein, a represents the distance between the orthographic projection of the first outer edge on the substrate 11 and the orthographic projection of the first sub-metal trace on the substrate, and b represents the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0022] In a possible embodiment, the first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; the first sub-metal portions and the second sub-metal portions extend in different directions;

[0023] The first conductive portion extends along an extending direction of the second sub-metal portion, and the second conductive portion extends along the extending direction of the first sub-metal portion.

[0024] In one possible implementation, the second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line; an extension line of the first outer edge intersects an extension line of the second outer edge;

[0025] The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0026] In a possible embodiment, the first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; the first sub-metal portions and the second sub-metal portions extend in different directions;

[0027] The first outer edge extends along the first direction; the extending direction of the second outer edge is the same as the extending direction of the first sub-metal portion.

[0028] In a possible implementation manner, the second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line;

[0029] The first outer edge includes: a first sub-edge portion and a second sub-edge portion; the second sub-edge portion is located on a side of the first sub-edge portion away from the first conductive portion, and the second sub-edge portion is located on a side of an extension line of the first sub-edge portion toward the first sub-metal trace;

[0030] The distance between the orthographic projection of the second sub-edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0031] In a possible embodiment, the first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; the first sub-metal portions and the second sub-metal portions extend in different directions;

[0032] The second sub-edge extends along an extending direction of the first sub-metal portion.

[0033] In a possible implementation manner, the first sub-edge extends along an extension direction of the second sub-metal portion; and the second outer edge extends along the extension direction of the first sub-metal portion.

[0034] In a possible implementation manner, a first bending portion is provided between the first sub-metal portion and the second sub-metal portion; and the first outer edge has a second bending portion;

[0035] The orthographic projection of the second bent portion on the substrate is located in an area between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the first connecting line on the substrate, wherein the first metal edge is the outer edge of the second metal wire facing the first conductive portion, and the first connecting line is a connecting line of the first bent portions of two adjacent first metal wires.

[0036] In a possible embodiment, the array substrate further includes: a third metal layer located on a side of the first active layer facing the substrate; the third metal layer includes: a plurality of third metal wires extending along the second direction; the orthographic projection of the third metal wire on the substrate covers the orthographic projection of the second metal wire on the substrate;

[0037] The orthographic projection of the second bending portion on the substrate is located in a region between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the second metal edge on the substrate, and the second metal edge is the outer edge of the third metal wire facing the first conductive portion.

[0038] In a possible implementation manner, the first outer edge has a second bent portion;

[0039] The orthographic projection of the second bent portion on the substrate overlaps with the orthographic projection of the first metal edge on the substrate. The first metal edge is the outer edge of the second metal wire facing the first conductive portion.

[0040] In a possible implementation, the distance between the two ends of the first sub-metal portion in the second direction is equal to the distance between the two ends of the second sub-metal portion in the second direction; and the second direction is perpendicular to the first direction.

[0041] In a possible embodiment, the first conductive portion is located between two adjacent first sub-metal portions in the second direction; the second conductive portion is located between two adjacent second sub-metal portions in the second direction; and the extension direction of the first conductive portion is the same as the extension direction of the first sub-metal portion.

[0042] In a possible embodiment, the first electrode includes: a first electrode portion and a second electrode portion distributed along the first direction; the extension direction of the first electrode portion is the same as the extension direction of the first sub-metal portion, and the extension direction of the second electrode portion is the same as the extension direction of the second sub-metal portion.

[0043] In a possible implementation manner, the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the second conductive portion on the substrate have an overlapping area, and are electrically connected at the overlapping position.

[0044] In a possible implementation manner, the first conductive portion has a third outer edge facing the first sub-metal line, and a fourth outer edge facing the second sub-metal line; the third edge is parallel to the fourth outer edge.

[0045] In a possible implementation, the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0046] In a possible implementation, the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is equal to the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0047] In a possible implementation, the first outer edge, the second outer edge, and the third outer edge satisfy the following relationship:

[0048] a>c>b, where c represents the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate.

[0049] In a possible implementation, the second conductive portion has a fifth outer edge extending along the second direction, and the fifth outer edge is located on a side of the second metal wire away from the first conductive portion.

[0050] In a possible implementation, the second conductive portion has a fifth outer edge extending along the second direction, and the orthographic projection of the second metal line on the substrate covers the orthographic projection of the fifth outer edge on the substrate.

[0051] In a possible implementation manner, the second metal wire has a sixth outer edge extending along the second direction;

[0052] The orthographic projection of a portion of the sixth outer edge on the substrate coincides with the orthographic projection of the fifth outer edge on the substrate.

[0053] In one possible embodiment, the second portion includes: a first sub-portion and a second sub-portion; the first sub-portion extends along the second direction, and an orthographic projection of the first sub-portion on the substrate overlaps with an orthographic projection of the first metal line on the substrate; the second sub-portion connects the first sub-portion and the first portion;

[0054] The plurality of first active patterns include: a first active pattern row and a second active pattern row; the first active pattern row and the second active pattern row extend along the second direction and are arranged overlappingly along the first direction;

[0055] The first active pattern row and the second active pattern row both include a plurality of first active patterns; and in the first active pattern row, the second sub-portion extends along a third direction; in the second active pattern row, the second sub-portion extends along a fourth direction, and the third direction intersects the fourth direction.

[0056] In a possible implementation manner, in the first active pattern row, the first sub-portion and the first portion are located on different sides of the second sub-portion; in the second active pattern row, the first sub-portion and the first portion are located on the same side of the second sub-portion.

[0057] In a possible implementation, the first metal line includes: a first sub-metal portion, a second sub-metal portion, and a third sub-metal portion alternately arranged along the first direction;

[0058] The second sub-metal portion extends along the first direction; the first sub-metal portion is located on one side of an extension line of the second sub-metal portion, and the third sub-metal portion is located on the other side of the extension line of the second sub-metal portion.

[0059] In a possible implementation manner, a distance between two ends of the first sub-metal portion in the second direction is equal to a distance between two ends of the third sub-metal portion in the second direction.

[0060] In a possible implementation, the plurality of first active patterns include: a third active pattern row and a fourth active pattern row; the third active pattern row and the fourth active pattern row extend along the second direction and are arranged overlappingly along the first direction;

[0061] The third active pattern row and the fourth active pattern row each include a plurality of first active patterns; in the same third active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; in the same fourth active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; between two adjacent first metal lines, the first active pattern of the third active pattern row and the first active pattern of the fourth active pattern row are electrically connected to different first metal lines.

[0062] In a possible implementation manner, the first portion extends along the first direction, and the second portion is located on one side of an extension line of the first portion;

[0063] In the third active pattern row, the opening at the first angle formed by the intersection of the first portion and the second portion and the opening at the second angle formed by the intersection of the first sub-metal portion and the second sub-metal portion are opposite to each other; in the fourth active pattern row, the opening at the first angle formed by the intersection of the first portion and the second portion are opposite to the opening at the third angle formed by the intersection of the third sub-metal portion and the next second sub-metal portion in the first direction.

[0064] In a possible implementation manner, the first portion extends along the first direction, and the second portion is located on one side of an extension line of the first portion;

[0065] In the third active pattern row, the opening at the first angle formed by the intersection of the first portion and the second portion and the opening at the second angle formed by the intersection of the first sub-metal portion and the second sub-metal portion are oriented on the same side; in the fourth active pattern row, the opening at the first angle formed by the intersection of the first portion and the second portion and the opening at the third angle formed by the intersection of the third sub-metal portion and the next second sub-metal portion in the first direction are oriented on the same side.

[0066] In a possible implementation, the plurality of first active patterns include: a plurality of active pattern rows; the active pattern rows include: a plurality of first active patterns sequentially arranged along the second direction;

[0067] In the same active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; between two adjacent first metal lines, the first active patterns in the active pattern row are electrically connected to the same first metal line.

[0068] In one possible embodiment, the array substrate includes: a first via hole, a second via hole, and a third via hole; the first active pattern is electrically connected to the conductive portion through the first via hole; the conductive portion is electrically connected to the first electrode through the second via hole; the first active pattern is electrically connected to the first metal line through the third via hole;

[0069] The second conductive layer includes: a plurality of first electrode rows extending along the second direction and sequentially arranged along the first direction; the first electrode rows include: a plurality of first electrodes sequentially arranged along the first direction;

[0070] The orthographic projection of the first active pattern electrically connected to the first electrodes in the Mth row through the first via holes and the second via holes on the substrate overlaps with the orthographic projection of the first electrodes in the M-1th row on the substrate.

[0071] In a possible implementation, a portion of the first electrode extends in the same direction as the second sub-metal portion; and another portion of the first electrode extends in the same direction as the third sub-metal portion.

[0072] In a possible implementation, the first metal wire extends along a first direction, the first portion extends along the first direction, and the conductive portion extends along the first direction;

[0073] The distance between the orthographic projection of all the conductive parts on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of all the conductive parts on the substrate and the orthographic projection of the second sub-metal line on the substrate.

[0074] In a possible implementation manner, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0075] 15%≤i2 / i1≤75%, where i1 represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the first sub-metal wire on the substrate, and i2 represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the second sub-metal wire on the substrate.

[0076] In a possible implementation manner, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0077] 3%≤(i1-i2) / i3≤15%, where i3 represents the minimum distance between adjacent first sub-metal lines and second sub-metal lines.

[0078] In a possible implementation manner, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0079] 60%≤i4 / i3≤95%, where i4 represents the length of the conductive portion in a direction perpendicular to the first direction.

[0080] In a possible embodiment, one end of the conductive portion is electrically connected to the first portion, and the other end extends toward the second metal line and exceeds the second metal line to form a protrusion, and the orthographic projection of the protrusion on the substrate overlaps with the orthographic projection of the first active pattern on the substrate.

[0081] In one possible implementation, the first conductive layer is located on a side of the first active layer facing away from the substrate; the first electrode is located on a side of the first conductive layer facing away from the substrate; the array substrate further includes: a first insulating layer located between the first active layer and the first conductive layer, and a first via hole penetrating the first insulating layer, the conductive portion being electrically connected to the first portion through the first via hole;

[0082] The array substrate further includes: a second insulating layer located between the first conductive layer and the first electrode, and a second via hole penetrating the second insulating layer; the first electrode is electrically connected to the conductive portion through the second via hole;

[0083] In a direction perpendicular to the first direction, at least two adjacent second via holes form an integrated connected structure.

[0084] In a possible embodiment, the second via has two side walls extending perpendicular to the first direction; at least one of the side walls has a protruding structure, and the orthographic projection of the protruding structure on the substrate is located in the area between the orthographic projections of two adjacent first electrodes on the substrate in the second direction.

[0085] In a possible embodiment, the array substrate further includes: a color resist layer located between the second insulating layer and the second conductive layer; the color resist layer includes: a plurality of color resist portions; and the orthographic projection of at least part of the color resist portions on the substrate overlaps with the orthographic projection of the first metal line on the substrate.

[0086] In one possible implementation, the array substrate has a display area and a non-display area located outside the display area; further comprising, located in the non-display area: a second active layer located on a side of the first active layer facing the substrate, a driving source and drain located on a side of the second active layer facing away from the substrate, and a driving gate;

[0087] The second active layer is located between the third metal layer and the substrate; the driving gate is located in the third metal layer; the driving source and drain are located in the first metal layer; the second active layer is located between the third metal layer and the first active layer; the driving source and drain are located in the second metal layer; the driving gate is located in the third metal layer;

[0088] The material of the first active layer includes metal oxide; the material of the second active layer includes low-temperature polysilicon.

[0089] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0090] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0091] FIG1A is a schematic diagram showing a crosstalk problem in a display panel;

[0092] FIG1B is a second schematic diagram of a display panel having crosstalk defects;

[0093] FIG1C is a third schematic diagram of a display panel having crosstalk defects;

[0094] FIG1D is a fourth schematic diagram of a display panel having crosstalk defects;

[0095] FIG2A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0096] FIG2B is a schematic diagram of a single film layer of the third metal layer in FIG2A ;

[0097] FIG2C is a schematic diagram of a single film layer of the first active layer in FIG2A ;

[0098] FIG2D is a schematic diagram of a single film layer of the second metal layer in FIG2A ;

[0099] FIG2E is a schematic diagram of a single film layer of the first metal layer in FIG2A ;

[0100] FIG2F is a schematic diagram of a single film layer of the first conductive layer in FIG2A ;

[0101] FIG2G is a schematic diagram of a single film layer of the second conductive layer in FIG2A ;

[0102] FIG3 is a schematic cross-sectional view of the dashed line A1A2 in FIG2A ;

[0103] FIG4A is a schematic diagram of a pixel electrode and associated structures provided by an embodiment of the present disclosure;

[0104] FIG4B is a schematic diagram of a first metal wire M11 and associated structures provided in an embodiment of the present disclosure;

[0105] FIG4C is a schematic diagram of adjacent pixel electrodes and associated structures provided by an embodiment of the present disclosure;

[0106] FIG. 4D is a diagram of the first coupling capacitor C corresponding to FIG. 4A . dp1 Schematic diagram of the composition;

[0107] FIG. 4E is a diagram of the second coupling capacitor C corresponding to FIG. 4A . dp2 Schematic diagram of the composition;

[0108] FIG5 is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0109] FIG6A is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0110] FIG6B is a schematic diagram of a single film layer of the first conductive layer in FIG6A ;

[0111] FIG6C is a fourth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0112] FIG7 is a fifth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0113] FIG8A is a sixth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0114] FIG8B is a schematic diagram of a single film layer where the data line is located in FIG8A;

[0115] FIG9A is a seventh schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0116] FIG9B is an eighth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0117] FIG9C is a ninth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0118] FIG9D is a schematic diagram of a single film layer of the first conductive layer in FIG9C ;

[0119] FIG9E is a schematic diagram of a single film layer of the first metal layer in FIG9C ;

[0120] FIG9F is a tenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0121] FIG9G is an eleventh schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0122] FIG9H is a twelfth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0123] FIG9I is a thirteenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0124] FIG10A is a fourteenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0125] FIG10B is a fifteenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0126] FIG10C is a sixteenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0127] FIG10D is a seventeenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0128] FIG10E is a schematic cross-sectional view taken along dotted line A0 in FIG10D ;

[0129] FIG11 is a schematic cross-sectional view of an array substrate provided in an embodiment of the present disclosure;

[0130] FIG12A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0131] FIG12B is a schematic diagram of a single film layer of the third metal layer in FIG12A;

[0132] FIG12C is a schematic diagram of a single film layer of the first active layer in FIG12A;

[0133] FIG12D is a schematic diagram of a single film layer of the second metal layer in FIG12A;

[0134] FIG12E is a schematic diagram of a single film layer of the first metal layer in FIG12A;

[0135] FIG12F is a schematic diagram of a single film layer of the first conductive layer in FIG12A;

[0136] FIG12G is a schematic diagram of a single film layer of the second conductive layer in FIG12A;

[0137] FIG12H is an eighteenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0138] FIG13 is a schematic cross-sectional view of the dashed line A1A2 in FIG12A ;

[0139] FIG14A is a schematic diagram of only a portion of the film layer in FIG12A;

[0140] FIG14B is a second schematic diagram of only a portion of the film layer in FIG12A;

[0141] FIG15A is a schematic diagram of a pixel electrode and associated structures provided by an embodiment of the present disclosure;

[0142] FIG15B is a schematic diagram of a first metal wire M11 and associated structures provided in an embodiment of the present disclosure;

[0143] FIG15C is a schematic diagram of adjacent pixel electrodes and associated structures provided by an embodiment of the present disclosure;

[0144] FIG. 15D is a diagram of the first coupling capacitor C corresponding to FIG. 15A . dp1 Schematic diagram of the composition;

[0145] FIG. 15E is a diagram of the second coupling capacitor C corresponding to FIG. 15A . dp2 Schematic diagram of the composition;

[0146] FIG16 is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0147] FIG17A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0148] FIG. 17B is a diagram of the first coupling capacitor C corresponding to FIG. 17A . dp1 Schematic diagram of the composition;

[0149] FIG. 17C is a diagram of the second coupling capacitor C corresponding to FIG. 17B . dp2 Schematic diagram of the composition;

[0150] FIG18 is a schematic diagram of a stack of only a portion of the film layers in FIG17A;

[0151] FIG19 is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0152] FIG20A is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0153] FIG20B may be a schematic diagram of a single film layer of the third metal wire M31 in FIG20A ;

[0154] FIG20C is a schematic diagram of a larger area of ​​FIG20B;

[0155] FIG21 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure;

[0156] FIG22 is a second cross-sectional schematic diagram of the array substrate provided in an embodiment of the present disclosure;

[0157] FIG23A is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0158] FIG23B is a schematic diagram of a single film layer of the third conductive layer in FIG23A;

[0159] FIG23C is a schematic diagram of a larger area of ​​FIG23B;

[0160] FIG24 is a schematic diagram of the display panel structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0161] Those skilled in the art will readily appreciate that the methods and contents may be transformed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited solely to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be combined arbitrarily unless there is a conflict.

[0162] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0163] In this specification, ordinal numbers such as "first", "second", and "third" are provided to avoid confusion among constituent elements, rather than to limit the quantity. The "plurality" in this disclosure may include two or more.

[0164] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0165] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0166] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0167] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0168] The gate of a transistor can also be referred to as the control electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0169] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0170] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0171] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0172] In this specification, "approximately" and "substantially" are used without strict limits and allow for process and measurement errors. In this specification, "substantially the same" may refer to values ​​that differ by less than 10%.

[0173] In related virtual reality (VR) head-mounted display products, the coupling capacitance Cdp1 between a data line and its electrically connected pixel is 1.322 Ff; the coupling capacitance Cdp2 between a data line and an adjacent pixel is 1.173 Ff. The difference in coupling capacitance between Cdp1 and Cdp2 (i.e., |Cdp1-Cdp2| / Cdp1) is 11.27%, a significant difference. In a column inversion structure, the coupling capacitance between two adjacent data lines (loaded with data signals of opposite polarity) affects the pixel electrode significantly, causing the pixel electrode voltage to easily deviate from the level, thereby easily causing crosstalk in the vertical direction.

[0174] Specifically, as shown in FIG1A , there is a first coupling capacitor C between the data line and its own pixel electrode (the own pixel electrode can be understood as the pixel electrode electrically connected to the data line) inside the pixel. dp1 , and a second coupling capacitor C with an adjacent pixel electrode (a pixel electrode not electrically connected to the data line) dp2 , when C dp1 >C dp2When the difference is large, conventional crosstalk problems may occur. For example, when displaying a picture with white in the middle and black at the edges as shown in FIG1B , the picture may appear bright at the top and dark at the bottom, with the middle as the boundary, as shown in FIG1C . Specifically, in conjunction with FIG1B , FIG1C and FIG1D , pixel A1 and pixel A2 are two pixels at different positions on the same data line, pixel B1 and pixel B2 are two pixels at different positions on the same data line, pixel B1 and pixel A1 are two pixels in the same row on adjacent data lines, and pixel B2 and pixel A2 are two pixels in the same row on adjacent data lines; when the pixel self-coupling effect (the first coupling capacitor C dp1 ) and mutual coupling effect (second coupling capacitance C dp2 ) are inconsistent, the charging voltage of pixel A1 is the positive voltage of L127, which will be pulled up by the voltage of L255 in the middle of the screen, causing the voltage difference between pixel A1 and the common electrode voltage (Vcom) to increase, and the display is bright; the charging voltage of pixel A2 is still the negative voltage of the previous frame, which will be pulled up by the voltage of L255 in the middle of the screen, causing the voltage difference between pixel A2 and the common electrode voltage (Vcom) to decrease, and the display is dark, that is, the undesirable phenomenon of bright top and dark bottom of the Crosstalk screen occurs.

[0175] In view of this, referring to Figures 2A-2G, Figure 3, and Figure 9A, wherein Figure 2B is a schematic diagram of a single film layer of the third metal layer in Figure 2A, Figure 2C is a schematic diagram of a single film layer of the first active layer in Figure 2A, Figure 2D is a schematic diagram of a single film layer of the second metal layer in Figure 2A, Figure 2E is a schematic diagram of a single film layer of the first metal layer in Figure 2A, Figure 2F is a schematic diagram of a single film layer of the first conductive layer in Figure 2A, Figure 2G is a schematic diagram of a single film layer of the second conductive layer in Figure 2A, Figure 3 is a schematic diagram of a cross-section at the dotted line A1A2 in Figure 2A, and Figure 4A is a schematic diagram of only a portion of the film layers in Figure 2A. An embodiment of the present disclosure provides an array substrate, which includes:

[0176] substrate 11;

[0177] The first active layer C1 is located on one side of the substrate 11 and includes a plurality of first active patterns C11. The first active pattern C11 includes a first portion CA and a second portion CB distributed along a first direction X. The second portion CB and the first portion CA extend in a different direction. The different extending directions can be understood as extending directions that are not on the same straight line.

[0178] The first metal layer M1 includes: a plurality of first metal lines M11; an orthographic projection of a first portion CA on the substrate 11 is located between orthographic projections of adjacent first metal lines M11 on the substrate 11; a portion of the orthographic projection of a second portion CB on the substrate 11 overlaps with a portion of the orthographic projection of the first metal line M11 on the substrate 11; specifically, the first metal line M11 may be a data line; specifically, the display area AA may have a plurality of first transistors; the second portion CB may serve as a first electrode of the first transistor at a position where it overlaps with the first metal line M11; the second portion CB may be conductive at a position where it overlaps with the first metal line M11, thereby achieving electrical connection between the first transistor and the data line;

[0179] The second metal layer M2 includes: a plurality of second metal lines M21 extending along the second direction Y;

[0180] The first conductive layer D1 includes: a plurality of conductive portions D11 located in the display area AA; the orthographic projection of at least one of the plurality of conductive portions D11 on the substrate 11 is located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; the conductive portion D11 includes: a first conductive portion DA and a second conductive portion DB distributed along the first direction X; the orthographic projection of the first conductive portion DA on the substrate 11 overlaps with the orthographic projection of the first portion CA on the substrate 11, and the second conductive portion DB overlaps with the orthographic projection of the second portion CB on the substrate 11; the first conductive portion DA and the second conductive portion DB extend in different directions; specifically, the first conductive layer D1 may be a transparent conductive layer, and the conductive portion D11 may serve as the second electrode of the first transistor, connecting the first active pattern C11 to the first electrode D21; specifically, the orthographic projection of the conductive portion D11 on the substrate 11 may be a meander, and the maximum length of the conductive portion D11 in the first direction X may be greater than the length in the second direction Y;

[0181] The second conductive layer D2 includes: a plurality of first electrodes D21 located in the display area AA; specifically, the second conductive layer D2 may be a transparent conductive layer, and the material of the second conductive layer D2 may be the same as that of the first conductive layer D1; specifically, the first electrodes D21 may be pixel electrodes; specifically, the orthographic projections of the first electrodes D21 on the substrate 11 may be located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; specifically, the orthographic projections of the first electrodes D21 on the substrate 11 may be in a meandering shape; the length of the first electrodes D21 in the first direction X may be greater than the length in the second direction Y;

[0182] Among them, the first metal wire M11 adjacent to both sides of the conductive part D11 includes: a first sub-metal wire MA, and a second sub-metal wire MB; wherein the first sub-metal wire MA is electrically connected to the second part CB, that is, the first metal wire M11 electrically connected to the second part CB is used as the first sub-metal wire MA, and the other first metal wire M11 is used as the second sub-metal wire MB; the first part CA is electrically connected to the first electrode D21 through the conductive part D11; at least the distance a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the distance b between the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0183] In the embodiment of the present disclosure, at least the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the spacing b between the orthographic projection of the second conductive portion DB and the second sub-metal line MB on the substrate 11. This can increase the spacing between the second conductive portion DB and the first sub-metal line MA, thereby reducing the capacitance between the second conductive portion DB and the first sub-metal line MA, and increasing the capacitance between the second sub-metal line MB, thereby reducing the difference between the two, thereby improving poor vertical crosstalk.

[0184] The first metal line M11 and its associated structure can form a first coupling capacitor Cdp1 with its own pixel electrode and its associated structure; the first metal line M11 and its associated structure can form a second coupling capacitor Cdp2 with the adjacent pixel electrode and its associated structure; wherein the own pixel electrode and its associated structure can be the area shown in the dotted box in FIG4A, and specifically can include: the first electrode D21 (as shown in the dotted box S1 in FIG4A), and the conductive portion D11 connected to the first electrode D21 through the second via K2 (as shown in the dotted box S2 in FIG4A), and the conductive portion D11 through the first via K The first active pattern C11 connected to the first active pattern C11 is located at a portion of the second metal line M21 on a side away from the second metal line M21 in the first direction X (as shown by the dotted box S3 in FIG4A , that is, the portion of the first active pattern C11 located below the second metal line M21. Since the time during which each row of pixels is turned on is very short within a display frame, it can be considered that the gate of the first transistor in the pixel is turned off for most of the time, and the portion of the first active pattern C11 covered by the second metal line M21 can be considered as an insulator). The first metal line M11 and the associated structure can be shown as shown by the dotted box in FIG4B . The region may specifically include: the first metal line M11 (as shown in the dotted box S4 in FIG4B ), and a portion of the first active pattern C11 electrically connected to the first metal line M11 through the third via K3 and located on the side of the second metal line M21 close to the second metal line M21 in the first direction X (as shown in the dotted box S5 in FIG4B , that is, the portion of the first active pattern C11 located on the upper side of the second metal line M21); the adjacent pixel electrode and associated structure may be as shown in the dotted box in FIG4C , and specifically include: the adjacent first electrode D21 (as shown in the dotted box S6 in FIG4C ), And the adjacent conductive portion D11 to which the adjacent first electrode D21 is connected through the second via K2 (as shown in the dotted box S7 in Figure 4C ), and the adjacent first active pattern C11 to which the adjacent conductive portion D11 is connected through the first via K1 is located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dotted box S8 in Figure 4C , that is, the portion of the first active pattern C11 located on the lower side of the second metal line M21); the composition of the first coupling capacitor Cdp1 can be as shown in Figure 4D , and the composition of the second coupling capacitor Cdp2 can be as shown in Figure 4E .

[0185] After research by the inventors of this application, it was found that the main reason for the difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2 is the asymmetry of the design of the first active pattern C11. In addition, since the film layer between the first active layer C1 and the first conductive layer D1 is relatively thin, and the first active pattern C11 and the conductive portion D11 in the first coupling capacitor Cdp1 overlap up and down (as shown in the area of ​​the thick solid frame S in FIG4D ), the facing capacitance is relatively large, while there is no such overlap in the second coupling capacitor Cdp2, thereby forming a difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2. (In addition, although the overlapping area between the first active pattern C11 and the first electrode D21 in the first coupling capacitor Cdp1 is larger than the overlapping area between the first active pattern C11 and the conductive portion D11, due to the presence of a thicker film layer between the first active pattern C11 and the first electrode D21, the overlapping capacitance is very small and the difference can be ignored); and since there is only one film layer between the first metal wire M11 and the conductive portion D11, the lateral capacitance formed by the first metal wire M11 and the conductive portion D11 dominates the second coupling capacitor Cdp2.

[0186] In the embodiment of the present disclosure, by making the distance a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 greater than the distance b between the orthographic projection of the second conductive part DB on the substrate 11 and the second sub-metal line MB on the substrate 11, the lateral capacitance between the first metal line M11 and the second conductive part DB can be increased, thereby increasing the second coupling capacitance Cdp2. Since the overlapping capacitance between the first active pattern C11 and the conductive part D11 (the area shown by the thick solid box S in Figure 4D) accounts for the majority of the first coupling capacitance Cdp1, the reduced distance between the conductive part D11 and the second sub-metal line MB will not have a significant impact on the first coupling capacitance Cdp1, thereby reducing the difference between the second coupling capacitance Cdp2 and the first coupling capacitance Cdp1, thereby improving poor vertical crosstalk.

[0187] It should be noted that the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be the minimum spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11; when the outer edge of the orthographic projection of the second conductive portion DB on the substrate 11 is partially uneven due to the manufacturing process, the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be the average spacing between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11; similarly, in the second conductive portion DB When the outer edge of the orthographic projection of the substrate 11 is straight, the spacing b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 can be the minimum spacing b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11. When the outer edge of the orthographic projection of the second conductive portion DB on the substrate 11 is partially uneven due to manufacturing processes, the spacing b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 can be the average spacing between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11. The spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11, and the spacing b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 can be a comparison of the spacings between the second conductive portion DB and the first sub-metal line MA and the second sub-metal line MB on the same straight line parallel to the second direction Y.

[0188] It should be noted that the first sub-metal line MA is electrically connected to the second portion CB. This can be understood as the first sub-metal line MA being electrically connected to the second portion CB via the first transistor.

[0189] In a possible embodiment, referring to FIG. 2A and FIG. 9A , the second conductive portion DB has a first outer edge w1 facing the first sub-metal wire MA, and a second outer edge w2 facing the second sub-metal wire MB; a distance a between the orthographic projection of the first outer edge w1 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is greater than a distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate 11.

[0190] In one possible embodiment, referring to FIG2A , the first metal wire M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along a first direction X; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the first conductive portion DA extends along the extension direction of the second sub-metal portion M1b, and the second conductive portion DB extends along the extension direction of the first sub-metal portion M1a; specifically, the extension direction of the first conductive portion DA is the same as the extension direction of the second sub-metal portion M1b, and the extension direction of the second conductive portion DB is the same as the extension direction of the first sub-metal portion M1a.

[0191] In one possible embodiment, as shown in Figures 2A and 9A , the first outer edge w1 is parallel to the second outer edge w2. In the disclosed embodiment, the conductive portion D11 can be shifted rightward as a whole, thereby ensuring that the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the distance b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0192] In a possible embodiment, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.05μm≤(ab) / 2≤0.15μm; in a possible embodiment, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.05μm≤(ab) / 2≤0.2μm; in a possible embodiment, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.1μm≤(ab) / 2≤0.15μm; specifically, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.06μm≤(ab) / 2≤0.14μm; specifically, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.07μm≤(ab) / 2≤0.13μm; specifically, the second conductive portion DB , and the first sub-metal line MA and the second sub-metal line MB can satisfy the relationship: 0.08μm≤(ab) / 2≤0.12μm; specifically, the second conductive part DB, and the first sub-metal line MA and the second sub-metal line MB can satisfy the relationship: 0.09μm≤(ab) / 2≤0.11μm; specifically, the second conductive part DB, and the first sub-metal line MA and the second sub-metal line MB can satisfy the relationship: (ab) / 2=0.1μm; in the embodiment of the present disclosure, after the second conductive part DB is shifted right by 0.1μm, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.253Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.264Ff; the coupling capacitance difference between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.87%, which can greatly reduce the coupling influence of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0193] In one possible embodiment, the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 can be in the range of 0.65 μm to 0.08 μm; in one possible embodiment, the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 can be in the range of 0.7 μm to 0.75 μm.

[0194] In one possible embodiment, the spacing b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be in the range of 0.4 μm to 0.55 μm; in one possible embodiment, the spacing b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be in the range of 0.45 μm to 0.5 μm.

[0195] In one possible embodiment, the spacing range between the first sub-metal wire MA and the second sub-metal wire MB may be 3μm to 6μm; in one possible embodiment, the spacing range between the first sub-metal wire MA and the second sub-metal wire MB may be 4μm to 5μm; in one possible embodiment, the spacing range between the first sub-metal wire MA and the second sub-metal wire MB may be 4μμm, 4.1μμm, 4.2μμm, 4.3μμm, 4.4μμm, 4.5μμm, 4.6μμm, 4.7μμm, 4.8μμm, 4.9μμm, or 5μm.

[0196] In a possible embodiment, referring to FIG. 2A and FIG. 9A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0197] 15%≤i2(b) / i1(a)≤75%, where i1(a) represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11, and i2(b) represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0198] It should be noted that, referring to Figures 2A and 9A, when the conductive part D11 is shifted to the right as a whole, the minimum spacing i1 between the conductive part D11 and the first sub-metal wire MA is equal to the spacing a between the second conductive part DB and the first sub-metal wire MA, that is, i1=a; similarly, when the conductive part D11 is shifted to the right as a whole, the minimum spacing i2 between the conductive part D11 and the second sub-metal wire MA is equal to the spacing b between the second conductive part DB and the first sub-metal wire MA, that is, i2=b.

[0199] In a possible embodiment, referring to FIG. 2A and FIG. 9A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0200] 3%≤(i1-i2) / i3≤15%, wherein i3 represents the minimum distance between adjacent first sub-metal lines MA and second sub-metal lines MB.

[0201] 2A and 9A , the minimum spacing i3 between adjacent first and second metal sub-wires MA and MB may be the spacing between the right edge of the first metal sub-wire MA and the left edge of the second metal sub-wire MB.

[0202] In a possible embodiment, referring to FIG. 2A and FIG. 9A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0203] 60%≤i4 / i3≤95%, where i4 represents the length of the conductive portion D11 in a direction perpendicular to the first direction X.

[0204] In one possible embodiment, referring to FIG2A and FIG9A , the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 70% ≤ i4 / i3 ≤ 90%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 75% ≤ i4 / i3 ≤ 85%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 78% ≤ i4 / i3 ≤ 85%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: : i4 / i3=78%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy i4 / i3=79%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=79.64%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=80%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=81%.

[0205] In a possible embodiment, referring to FIG. 2A and FIG. 9A , the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be 0.35 μm to 1.15 μm; the minimum spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be 0.05 μm to 0.85 μm.

[0206] In a possible embodiment, referring to FIG2A and FIG9A , the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 can be 0.3 μm to 1.5 μm; the minimum spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be 0.2 μm to 1 μm.

[0207] In one possible embodiment, referring to FIG2A and FIG9A , the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 2 μm to 10 μm; in one possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 4 μm to 8 μm; in one possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5 μm to 6 μm; in one possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.1 μm, 5.2 μm, 5.3 μm, 5.4 μm, 5.5 μm, 5.6 μm, 5.7 μm, 5.8 μm, 5.8 μm or 6.0 μm; in one possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.65 μm.

[0208] In a possible embodiment, referring to Figures 2A and 9A, the length i4 of the conductive portion D11 in the direction perpendicular to the first direction X may be 2 μm to 8 μm; in a possible embodiment, the length i4 of the conductive portion D11 in the direction perpendicular to the first direction X may be 3 μm to 6 μm; in a possible embodiment, the length i4 of the conductive portion D11 in the direction perpendicular to the first direction X may be 4 μm to 5 μm; in a possible embodiment, the length i4 of the conductive portion D11 in the direction perpendicular to the first direction X may be 4.1 μm, 4.2 μm, 4.3 μm, 4.4 μm, 4.5 μm, 4.6 μm, 4.7 μm, 4.8 μm, 4.9 μm or 5.0 μm.

[0209] In a possible implementation, referring to FIG. 2A and FIG. 9A , a length i4 of the conductive portion D11 perpendicular to the first direction X may be 4.5 μm; and a minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.65 μm.

[0210] In a possible embodiment, referring to FIG5 and FIG9B , the second conductive portion DB has a first outer edge w1 facing the first sub-metal wire MA, and a second outer edge w2 facing the second sub-metal wire MB; an extension line of the first outer edge w1 intersects with an extension line of the second outer edge w2; a distance a between the orthographic projection of the first outer edge w1 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is greater than a distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate 11. In the embodiment of the present disclosure, the upper end of the conductive portion D11 can be straightened, so that the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the distance b between the orthographic projection of the second conductive portion DB and the second sub-metal line MB on the substrate 11; specifically, after the upper end of the conductive portion D11 is straightened, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.187Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.176Ff; the coupling capacitance difference between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.93%, which can greatly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0211] In one possible embodiment, referring to FIG5 , the first metal wire M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b alternately arranged along a first direction; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the first outer edge w1 extends along the first direction X; the second outer edge w2 extends along the extension direction of the first sub-metal portion M1a. Specifically, the extension direction of the second outer edge w2 is the same as the extension direction of the first sub-metal portion M1a.

[0212] In a possible embodiment, in combination with Figures 6A, 6B, 9C, and 9D, the second conductive portion DB has a first outer edge w1 facing the first sub-metal wire MA, and a second outer edge w2 facing the second sub-metal wire MB; the first outer edge w1 includes: a first sub-edge portion w11, and a second sub-edge portion w12; the second sub-edge portion w12 is located on a side of the first sub-edge portion w11 away from the first conductive portion DA, and the second sub-edge portion w12 is located on a side of the extension line of the first sub-edge portion w11 facing the first sub-metal trace MA; a distance a between the orthographic projection of the second sub-edge w12 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is greater than a distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate. In the embodiment of the present disclosure, the upper end of the conductive portion D11 can be retracted, thereby achieving a distance a between the orthographic projection of the second sub-edge w12 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11, which is greater than the distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate.

[0213] In a possible embodiment, as shown in FIG6A and FIG6B, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.3μm≤ab≤0.9μm; specifically, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.4μm≤ab≤0.8μm; specifically, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.5μm≤ab≤0.7μm; specifically, the second conductive portion DB, and the first sub-metal wire MA, the second sub-metal wire MB can satisfy the relationship: 0.5μm≤ab≤0.7μm; specifically, the second conductive portion DB, and the first sub-metal wire MA and the second sub-metal wire MB can satisfy the relationship: ab = 0.6μm; in the embodiment of the present disclosure, after the upper end of the conductive portion D11 is retracted by 0.6um, the first coupling capacitance Cdp1 between the first metal wire M11 and the connected pixel is 1.185Ff; the second coupling capacitance Cdp2 between the first metal wire M11 and the adjacent pixel is 1.175Ff; the coupling capacitance difference between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.84%, which can greatly reduce the coupling effect of the coupling capacitance on the first metal wire M11, thereby avoiding the occurrence of vertical crosstalk.

[0214] In one possible embodiment, in combination with Figures 6A and 6B, the first metal wire M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along a first direction X; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the second sub-edge w12 extends along the extension direction of the first sub-metal portion M1a, specifically, the extension direction of the second sub-edge w12 is the same as the extension direction of the first sub-metal portion M1a.

[0215] In a possible embodiment, in combination with Figures 6A and 6B, the first sub-edge w11 extends along the extension direction of the second sub-metal portion M1b; the second outer edge w21 extends along the extension direction of the first sub-metal portion M1a; specifically, the extension direction of the first sub-edge w11 is the same as the extension direction of the outer edge of the first conductive portion DA toward the first sub-metal wire MA, that is, the extension line of the outer edge of the first conductive portion DA toward the first sub-metal wire MA can be used as the first sub-edge w11; the extension direction of the second sub-edge w12 is parallel to the extension direction of the second outer edge w2.

[0216] In a possible embodiment, as shown in Figure 6C, there is a first bending portion O between the first sub-metal portion M1a and the second sub-metal portion M1b; the first outer edge w1 has a second bending portion Q; the second bending portion Q is located in the area between the orthographic projection of the first metal edge f1 on the substrate 11 and the orthographic projection of the first connecting line OO on the substrate 11, wherein the first metal edge f1 is the outer edge of the second metal wire M21 facing the first conductive portion DA, that is, the lower edge of the second metal wire M21; the first connecting line OO is the first bending portion O connecting line of two adjacent first metal wires M11.

[0217] In a possible embodiment, referring to FIG9C , the first metal wire M11 includes: a first sub-metal portion M1a, a second sub-metal portion M1b, and a third sub-metal portion M1c arranged alternately along the first direction X; the second sub-metal portion M1b extends along the first direction X; the first sub-metal portion M1a is located on one side of the extension line of the second sub-metal portion M1b, and the third sub-metal portion M1c is located on the other side of the extension line of the second sub-metal portion M1b; a fourth bend R is provided between the second sub-metal portion M1b and the third sub-metal portion M1c; the first outer edge w1 has a second bend Q; the orthographic projection of the second bend Q on the substrate 11 is located in the area between the orthographic projection of the first metal edge f1 on the substrate 11 and the orthographic projection of the second connecting line RR on the substrate 11, wherein the first metal edge f1 is the outer edge of the second metal wire M21 facing the first conductive portion DA, that is, the lower edge of the second metal wire M21; the second connecting line RR is the fourth bend R connecting line of two adjacent first metal wires M11.

[0218] In a possible embodiment, in combination with Figures 6C and 9C, the array substrate further includes: a third metal layer M3 located on the side of the first active layer C1 facing the substrate 11; the third metal layer M3 includes: a plurality of third metal wires M31 extending along the second direction Y; the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second metal wire M21 on the substrate; the orthographic projection of the second bend portion Q on the substrate 11 is located in the area between the orthographic projection of the first metal edge f1 on the substrate 11 and the orthographic projection of the second metal edge f2 on the substrate 11, and the second metal edge f2 is the outer edge of the third metal wire M31 on the side facing the first conductive portion DA.

[0219] In one possible embodiment, as shown in conjunction with Figures 6A and 6B , the first outer edge w1 has a second bend Q; the orthographic projection of the second bend Q on the substrate 11 overlaps with the orthographic projection of the first metal edge f1 on the layer substrate 11, wherein the first metal edge f1 is the outer edge of the second metal wire M21 facing the first conductive portion DA. In the disclosed embodiment, the orthographic projection of the second bend Q on the substrate 11 overlaps with the orthographic projection of the first metal edge f1 on the layer substrate 11, thereby achieving a larger spacing between the second conductive portion DB and the first sub-metal wire MA while ensuring the conductive effect of the second via K2 (which connects the conductive portion D11 to the first electrode D21), thereby avoiding the situation where the improper positioning of the second bend Q may affect the conductive effect of the second via K2 connecting the conductive portion D11 to the first electrode D21.

[0220] In a possible embodiment, as shown in Figures 6A, 6B, 9C, and 9D, the second outer edge w2 includes a third bend P, and the orthographic projection of the third bend P on the substrate 11 may overlap with the orthographic projection of the first connecting line OO on the substrate 11.

[0221] In one possible embodiment, as shown in Figures 2A, 5, or 6A, the first conductive portion DA is located between two adjacent first sub-metal portions M1a in the second direction Y; the second conductive portion DB is located between two adjacent second sub-metal portions M1b in the second direction Y. The first conductive portion DA extends in the same direction as the first sub-metal portion M1a. That is, within conductive portion D11, the bending trends of the first conductive portion DA and the second conductive portion DB align with the bending trend of the first metal wire M11, and conductive portion D11 bends accordingly at the location where the first metal wire M11 bends.

[0222] In one possible embodiment, referring to FIG. 2A , the first electrode D21 includes: a first electrode portion DC and a second electrode portion DD distributed along a first direction X; an extension direction of the first electrode portion DC is the same as an extension direction of the first sub-metal portion M1a, and an extension direction of the second electrode portion DD is the same as an extension direction of the second sub-metal portion M1b.

[0223] It should be noted that, in Figure 2A, only part of the second electrode portion DD is shown. The second electrode portion DD may have more parts, but the extension direction of the remaining parts of the second electrode portion DD that are not shown may be consistent with the extension direction of the second electrode portion DD shown in the figure. It is only an extension in the extension direction. Specifically, it can be combined with Figure 8A. The embodiments of the present disclosure are not limited to this.

[0224] In a possible implementation, as shown in FIG. 2A , the orthographic projection of the first electrode portion DC on the substrate 11 and the orthographic projection of the second conductive portion DB on the substrate 11 have an overlapping area and are electrically connected at the overlapping position.

[0225] In a possible embodiment, as shown in FIG. 2A , the first conductive portion DA has a third outer edge w3 facing the first sub-metal wire MA and a fourth outer edge w4 facing the second sub-metal wire MB; the third edge w3 is parallel to the fourth outer edge w4.

[0226] In one possible embodiment, as shown in FIG2A , the distance c between the orthographic projection of the third outer edge w3 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is greater than the distance d between the orthographic projection of the fourth outer edge w4 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate 11. In other words, the conductive portion D11 can be shifted rightward as a whole to achieve a distance a between the second conductive portion DB and the first sub-metal trace MA that is greater than the distance b between the second conductive portion DB and the second sub-metal trace MB.

[0227] In one possible embodiment, as shown in Figure 6A, the distance c between the orthographic projection of the third outer edge w3 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11 is equal to the distance d between the orthographic projection of the fourth outer edge w4 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate 11.

[0228] In a possible implementation, as shown in FIG6A , the first outer edge w1 , the second outer edge w2 , and the third outer edge w4 satisfy the following relationship:

[0229] a>c>b, where c represents the distance between the orthographic projection of the third outer edge w3 on the substrate and the orthographic projection of the first sub-metal trace MA on the substrate. This means that, based on the overall offset, the bending point Q moves upward, further increasing the distance between the first sub-metal trace MA and the conductive portion D11.

[0230] In a possible implementation, as shown in FIG. 2A , the second conductive portion DB has a fifth outer edge w5 extending along the second direction Y. The fifth outer edge w5 is located on a side of the second metal line M21 away from the first conductive portion DA.

[0231] In one possible embodiment, as shown in FIG7 , the second conductive portion DB has a fifth outer edge w5 extending along the second direction Y. The orthographic projection of the second metal line M21 on the substrate covers the orthographic projection of the fifth outer edge w5 on the substrate. In the disclosed embodiment, by retracting the upper end of the second conductive portion DB relative to the second metal line M21, the facing capacitance generated by the vertical overlap of the first active pattern C11 and the conductive portion D11 in the first coupling capacitor Cdp1 (such as the area indicated by the thick solid box S in FIG4D ) can be reduced or eliminated, thereby reducing the first coupling capacitor Cdp1, reducing the coupling capacitance difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2, and reducing the coupling effect of the coupling capacitor on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0232] In the disclosed embodiment, after the upper end of the second conductive portion DB is retracted into the second metal line M21, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.259Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.136Ff; and the coupling capacitance difference between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 9.77%, which can significantly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0233] In a possible embodiment, as shown in FIG. 7 , the second metal wire M21 has a sixth outer edge w6 extending along the second direction Y; the orthographic projection of a portion of the sixth outer edge w6 on the substrate 11 coincides with the orthographic projection of the fifth outer edge w5 on the substrate 11 .

[0234] In one possible embodiment, referring to FIG. 8A , the second portion CB includes a first sub-portion CB1 and a second sub-portion CB2. The first sub-portion CB1 extends along the second direction Y, and the orthographic projection of the first sub-portion CB1 on the substrate 11 overlaps with the orthographic projection of the first metal line M11 on the substrate 11. The second sub-portion CB2 connects the first sub-portion CB1 and the first portion CA. The plurality of first active patterns C11 include a first active pattern row C100 and a second active pattern row C200. The first active pattern row C100 and the second active pattern row C200 extend along the second direction Y and are arranged to overlap along the first direction X.

[0235] Both the first active pattern row C100 and the second active pattern row C200 include multiple first active patterns C11. In the first active pattern row C100, the second sub-portion CB2 extends along the third direction Z1. In the second active pattern row C200, the second sub-portion CB2 extends along the fourth direction Z2, with the third direction Z1 intersecting the fourth direction Z2. Specifically, for the two adjacent first sub-metal lines MA and the second sub-metal line MB on either side of the conductive portion D11, the second sub-portion CB2 of the first active pattern row C100 can be located in the first direction X and offset to one side of the first sub-metal line MA, while the second sub-portion CB2 of the second active pattern row C200 can be located in the first direction X and offset to one side of the second sub-metal line MB.

[0236] In the embodiment implemented in FIG8A , by making the first active pattern C11 of adjacent rows a mirror-image structure, darker pixel rows and brighter pixel rows can be alternately distributed. If the pixels in the odd-numbered rows are brighter, the pixels in the even-numbered rows are darker. The brightness difference between the upper and lower rows of pixels is neutralized, reducing the coupling effect of the coupling capacitor on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk. Specifically, in the odd-numbered pixel rows, the first coupling capacitor Cdp1 between the first metal line M11 and the connected pixels is 1.192Ff, and in the odd-numbered pixel rows, the first metal line M11 is 0.010Ff. The second coupling capacitance Cdp2 between M11 and the adjacent pixel is 1.301Ff; in the even pixel rows, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.312Ff, and in the even pixel rows, the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.177Ff; in the odd rows, the pixel second coupling capacitance Cdp2 is greater than the first coupling capacitance Cdp1, and in the even pixel rows, the first coupling capacitance Cdp1 is greater than the second coupling capacitance Cdp2, and the brightness difference between the upper and lower rows of pixels is neutralized.

[0237] In a possible implementation manner, the third direction Z1 and the fourth direction Z2 are located on different sides of the first direction X.

[0238] In one possible embodiment, the angle formed between the third direction Z1 and the first direction X is in a range of 10° to 80°; in one possible embodiment, the angle formed between the third direction Z1 and the first direction X is in a range of 20° to 70°; in one possible embodiment, the angle formed between the third direction Z1 and the first direction X is in a range of 30° to 60°; in one possible embodiment, the angle formed between the third direction Z1 and the first direction X is in a range of 40° to 50°.

[0239] In one possible embodiment, the angle formed between the fourth direction Z2 and the first direction X is in a range of 10° to 80°; in one possible embodiment, the angle formed between the fourth direction Z2 and the first direction X is in a range of 20° to 70°; in one possible embodiment, the angle formed between the fourth direction Z2 and the first direction X is in a range of 30° to 60°; in one possible embodiment, the angle formed between the fourth direction Z2 and the first direction X is in a range of 40° to 50°.

[0240] In a possible implementation, as shown in FIG8A , in the first active pattern row C100 , the first sub-portion CB1 and the first portion CA are located on different sides of the second sub-portion CB2 ; in the second active pattern row C200 , the first sub-portion CB1 and the first portion CA are located on the same side of the second sub-portion CB2 .

[0241] In a possible embodiment, as shown in Figures 2A and 3, the first conductive layer D1 is located on the side of the first active layer C1 facing away from the substrate 11; the array substrate further includes: a first insulating layer F1 located between the first active layer C1 and the first conductive layer D1, and a first via K1 passing through the first insulating layer F1, and the conductive portion D11 is electrically connected to the first portion CA through the first via K1.

[0242] In one possible embodiment, as shown in Figures 2A and 3, the first electrode D21 is located on a side of the first conductive layer D1 facing away from the substrate 11; the array substrate further includes: a second insulating layer F2 located between the first conductive layer D1 and the first electrode D21, and a second via K2 passing through the second insulating layer F2; the first electrode D21 is electrically connected to the K2 conductive portion D11 through the second via hole.

[0243] In one possible implementation, the first insulating layer F1 includes one or a combination of the following:

[0244] a first gate insulating layer 15;

[0245] a first interlayer dielectric layer 16;

[0246] A second interlayer dielectric layer 17 .

[0247] 3 , the first interlayer dielectric layer 16 may be located on a side of the first gate insulating layer 15 away from the substrate 11 ; the second interlayer dielectric layer 17 may be located on a side of the first interlayer dielectric layer 16 away from the substrate 11 .

[0248] In a possible implementation, as shown in FIG. 3 , the first insulating layer F1 includes: a first gate insulating layer 15 , a first interlayer dielectric layer 16 , and a second interlayer dielectric layer 17 .

[0249] In a possible embodiment, in combination with FIG2A and FIG3 , the array substrate further includes: a third via K3 penetrating the first interlayer dielectric layer 16 and the second interlayer dielectric layer 17 , and the first metal wire M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via K3 .

[0250] In one possible embodiment, as shown in FIG2A , the orthographic projection of the third metal wire M31 on the substrate 11 overlaps the orthographic projection of the second via K2 on the substrate 11. Specifically, the orthographic projection of the second metal wire M21 on the substrate 11 overlaps the orthographic projection of the second via K2 on the substrate 11. In one possible embodiment, the orthographic projection of the second via K2 on the substrate 11 is located at the overlapping region of the first electrode D21 and the conductive portion D11 on the substrate 11. In this way, the first electrode D21 and the conductive portion D11 are electrically connected in the overlapping region through the second via K2.

[0251] The orthographic projection of the first metal wire M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. In one possible embodiment, the orthographic projection of the first via K1 on the substrate 11 is located at an overlapping region between the orthographic projections of the first portion CA of the first active pattern C11 and the conductive portion D11 on the substrate 11. In this way, the first portion CA and the conductive portion D11 are electrically connected at the overlapping region through the first via K1.

[0252] In one possible embodiment, the orthographic projection of the first metal line M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. Specifically, the orthographic projection of the third via K3 on the substrate 11 is located at the overlapping region of the orthographic projections of the first metal line M11 and the second portion CB of the first active pattern C11 on the substrate 11. In this way, the first metal line M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via K3.

[0253] In one possible embodiment, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 are both located between the orthographic projections of the first sub-metal wire MA and the second sub-metal wire MB on the substrate 11. In one possible embodiment, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 have a gap in the first direction X.

[0254] In a specific implementation, the thickness of the first insulating layer F1 between the first active layer C1 and the first conductive layer D1 can be adjusted by adjusting at least one or a combination of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17. In combination with rightward shifting of the conductive portion D11 and / or upward shifting of the second metal trace M21, precise capacitance difference control can be achieved to reduce the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 difference.

[0255] In a possible embodiment, as shown in FIG3 , the thickness of at least one of the first gate insulating layer 15 , the first interlayer dielectric layer 16 , and the second interlayer dielectric layer 17 is greater than

[0256] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0257] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0258] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0259] In a possible implementation, the third metal line M31 may be used to shield at least a portion of the first active pattern C11 of the first transistor to prevent external ambient light from illuminating the first active pattern C11 and affecting the characteristics of the first transistor.

[0260] In one possible implementation, as shown in FIG2A , the orthographic projection of the third metal line M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In the disclosed embodiment, the orthographic projection of the third metal line M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11, that is, the third metal line M31 of the array substrate covers the second via K2, which can reduce the risk of light leakage from the second via K2 on the array substrate.

[0261] In one possible embodiment, as shown in FIG8B , the distance g1 between the two ends of the first sub-metal portion M1a in the second direction Y is equal to the distance g2 between the two ends of the second sub-metal portion M1b in the second direction Y; the second direction Y is perpendicular to the first direction X. That is, the rightward offset of the two ends of the first sub-metal portion M1a in the second direction Y is equal to the leftward offset of the two ends of the second sub-metal portion M1b in the second direction Y. As a result, the first metal wire M11 generally extends along the first direction Y.

[0262] In one possible embodiment, referring to Figures 9A-9C, the first metal line M11 includes: a first sub-metal portion M1a, a second sub-metal portion M1b, and a third sub-metal portion M1c arranged alternately along a first direction X; the second sub-metal portion M1b extends along the first direction X; the first sub-metal portion M1a is located on one side of an extension line of the second sub-metal portion M1b, and the third sub-metal portion M1c is located on the other side of the extension line of the second sub-metal portion M1b. In the disclosed embodiment, for a 2P2D pixel structure, the first metal line M11 is bent (the extension directions of the corresponding first metal line M11 portions of the upper and lower rows of pixel electrodes intersect), and the offsets of the corresponding first metal line M11 portions of the upper and lower rows of pixel electrodes are equal (the offsets of the first metal line M11 in the second direction Y are offset), and the middle portion (the second sub-metal portion M1b) is vertical to avoid the occurrence of slanted channels in the first active pattern.

[0263] In a possible implementation, as shown in FIG. 9E , a distance g3 between two ends of the first sub-metal portion M1a in the second direction Y is equal to a distance g4 between two ends of the third sub-metal portion M1c in the second direction Y.

[0264] In one possible embodiment, referring to FIG9A , the first active layer C1 includes: a third active pattern row C300, and a fourth active pattern row C400; the third active pattern row C300 and the fourth active pattern row C400 extend along the second direction Y and are arranged overlappingly along the first direction X; the third active pattern row C300 and the fourth active pattern row C400 each include a plurality of first active patterns C11; in the same third active pattern row C300, each first active pattern C11 is electrically connected to the first metal line M11 on the same side; in the same fourth active pattern row C400, each first active pattern C11 is electrically connected to the first metal line M11 on the same side; between two adjacent first metal lines M11, the first active pattern C11 of the third active pattern row C300 and the first active pattern C11 of the fourth active pattern row C400 are electrically connected to different first metal lines M11.

[0265] In one possible embodiment, referring to FIG9A , the first portion CA extends along the first direction X, and the second portion CB is located on one side of the extension line of the first portion CA; in the third active pattern row C300, the first portion CA and the second portion CB intersect to form an opening at a first angle α1, and the first sub-metal portion M1a and the second sub-metal portion M1b intersect to form an opening at a second angle α2, that is, the deflection direction of the second portion CB relative to the first portion CA is opposite to the deflection direction of the first sub-metal portion M1a relative to the second sub-metal portion M1b; in the fourth active pattern row C400, the first portion CA and the second portion CB intersect to form an opening at a first angle α1, and the third sub-metal portion M1c and the next second sub-metal portion M1b in the first direction X intersect to form an opening at a third angle α3, that is, the deflection direction of the second portion CB relative to the first portion CA is opposite to the deflection direction of the third sub-metal portion M1a relative to the next second sub-metal portion M1b in the first direction X. That is, in combination with Figure 9A, for example, in the third active pattern row C300, the second portion CB is deflected to the left relative to the first portion CA, and the first sub-metal portion M1a is deflected to the right relative to the second sub-metal portion M1b, and the two deflection directions are opposite; in the fourth active pattern row C400, the second portion CB is deflected to the right relative to the first portion CA, and the third sub-metal portion M1c is deflected to the left relative to the next second sub-metal portion M1b in the first direction X, and the two deflection directions are opposite.

[0266] In a possible embodiment, referring to FIG. 9A to FIG. 9C , since the first active pattern C11 of the third active pattern row C300 and the first active pattern C11 of the fourth active pattern row C400 are electrically connected to different first metal lines M11 between two adjacent first metal lines M11, the same first metal line M11 can be used as the first sub-metal line MA in the area where the third active pattern row C300 is located, and can be used as the second sub-metal line MB in the area where the fourth active pattern row C400 is located. Accordingly, for FIG. 9A , the second conductive portion DB is realized by moving the conductive portion D11. When the spacing a between the orthographic projection of the first sub-metal wire MA on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the spacing b between the orthographic projection of the second sub-metal wire MB on the substrate 11, corresponding to the entire display panel, all the conductive portions D11 in one conductive portion row may move as a whole in one direction, while all the conductive portions D11 in the adjacent conductive portion row may move as a whole in another direction. For example, as shown in FIG9A , the conductive portions D11 in the first conductive portion row from top to bottom all move to the right, while the conductive portions D11 in the second conductive portion row all move to the left. Similarly, in combination with FIG9B , by straightening the upper end of the conductive portion D11, the orthographic projection of the second conductive portion DB on the substrate 11 is achieved. When the spacing a between the orthographic projection of the first sub-metal wire MA on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 is greater than the spacing b between the orthographic projection of the second sub-metal wire MB on the substrate 11, corresponding to the entire display panel, all the conductive portions D11 in one conductive portion row may move as a whole. 9B , the conductive portions D11 in the first conductive portion row from top to bottom are all straightened on the left side, while the conductive portions D11 in the second conductive portion row are all straightened on the right side; similarly, in combination with FIG9C , by shrinking one end of the conductive portion D11, it is achieved that the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the distance b between the orthographic projection of the second sub-metal wire MB on the substrate 11, corresponding to the entire display panel, the same side of all the conductive portions D11 in one conductive portion row can be shrinked, while the other side of all the conductive portions D11 in adjacent conductive portion rows can be shrinked, for example, as shown in FIG9C , the conductive portions D11 in the first conductive portion row from top to bottom are all shrinked on the left side, while the conductive portions D11 in the second conductive portion row are all shrinked on the right side.

[0267] In a possible embodiment, referring to FIG. 9F , the first portion CA extends along the first direction X, and the second portion CB is located on one side of the extension line of the first portion CA; in the third active pattern row C300, the first portion CA and the second portion CB intersect to form an opening with a first angle α1, and the first sub-metal portion M1a and the second sub-metal portion M1b intersect to form an opening with a second angle α2 facing the same side; in the fourth active pattern row C400, the first portion CA and the second portion CB intersect to form an opening with a first angle α1, and the first sub-metal portion M1a and the second sub-metal portion M1b intersect to form an opening with a second angle α2, and the first sub-metal portion M1a and the second sub-metal portion M1b intersect to form an opening with a first angle α2. The openings of the portion M1c and the next second sub-metal portion M1b in the first direction X that intersect to form a third angle α3 are oriented toward the same side. That is, in the third active pattern row C300, the deflection direction of the second portion CB relative to the first portion CA is the same as the deflection direction of the first sub-metal portion M1a relative to the second sub-metal portion M1b; in the fourth active pattern row C400, the deflection direction of the second portion CB relative to the first portion CA is the same as the deflection direction of the third sub-metal portion M1a relative to the next second sub-metal portion M1b in the first direction X. That is, in combination with Figure 9F, for example, in the third active pattern row C300, the second portion CB is deflected to the right relative to the first portion CA, and the first sub-metal portion M1a is deflected to the right relative to the second sub-metal portion M1b, and the deflection directions of the two are the same; in the fourth active pattern row C400, the second portion CB is deflected to the left relative to the first portion CA, and the third sub-metal portion M1c is deflected to the left relative to the next second sub-metal portion M1b in the first direction X, and the deflection directions of the two are the same.

[0268] In one possible embodiment, referring to FIG. 9G and FIG. 9H , the plurality of first active patterns C11 include: a plurality of active pattern rows CA0; the active pattern row CA0 includes: a plurality of first active patterns C11 sequentially arranged along the second direction Y; in the same active pattern row CA0, each first active pattern C11 is electrically connected to the first metal line M11 on the same side; between two adjacent first metal lines M11, the first active patterns C11 of the active pattern row CA0 are electrically connected to the same first metal line M11.

[0269] In a possible embodiment, referring to FIG9I , the array substrate includes: a first via K1, a second via K2, and a third via K3; the first active pattern C11 is electrically connected to the conductive portion D11 through the first via K1; the conductive portion D11 is electrically connected to the first electrode D21 through the second via K2; the first active pattern C11 is electrically connected to the first metal wire M11 through the third via K3; the second conductive layer D2 includes: a plurality of first electrode rows D200 extending along the second direction Y and arranged in sequence along the first direction X; the first electrode row D200 includes: a plurality of first electrodes D21 arranged in sequence along the first direction X; the orthographic projection of the first active pattern C11 electrically connected to the first electrode D21 of the Mth row through the first via K1 and the second via K2 on the substrate 1 overlaps with the orthographic projection of the first electrode D21 of the M-1th row on the substrate 1. That is, in the embodiment of the present disclosure, the first active pattern C11 electrically connected to the first electrode D21 in the Mth row may be the first electrode row 200 located in the M-1 row.

[0270] In one possible embodiment, as shown in FIG9I , a portion of the first electrode D21 extends in the same direction as the second sub-metal portion M1b, while another portion of the first electrode D21 extends in the same direction as the third sub-metal portion M1c. In other words, the first electrode D21 bends in the same direction as the first metal wire M11.

[0271] In one possible implementation, referring to Figures 9A to 9H , the orthographic projection of the first active pattern C11 electrically connected to the first electrode D21 of the M-th row through the first via K1 and the second via K2 on the substrate 1 may also overlap with the orthographic projection of the first electrode D21 of the M-th row on the substrate 1. That is, the first active pattern C11 electrically connected to the first electrode D21 of the M-th row may also be in the first electrode row D200.

[0272] In a possible embodiment, in combination with Figures 2A, 3, and 11, the array substrate further includes: a second insulating layer F2 located between the first conductive layer D1 and the second conductive layer D2; the second insulating layer F2 has a second via hole K2; and the first electrode D21 is electrically connected to the conductive portion D11 through the second via hole K2.

[0273] In one possible embodiment, as shown in FIG10A , at least two adjacent second via holes K2 are integrally connected in a direction perpendicular to the first direction X. In the disclosed embodiment, because the second insulating layer F2 is relatively thick, to ensure good electrical connection between the first electrode D21 and the conductive portion D11, the second via holes K2 in the second insulating layer F can be replaced with grooves, that is, at least two adjacent second via holes K2 are integrally connected.

[0274] In one possible embodiment, the second via holes K2 of three sub-pixels may be an integrated connected structure; in another possible embodiment, all the second via holes K2 perpendicular to the second direction X may be an integrated connected structure, that is, the second via holes K2 corresponding to a row of sub-pixels may be an integrated connected structure.

[0275] In one possible embodiment, the second via hole K2 has two sidewalls extending perpendicular to the first direction X; at least one sidewall is wavy or zigzag-shaped. In the disclosed embodiment, the sidewalls of the groove are configured as wavy or zigzag shapes based on the trenching process to prevent photoresist residue within the groove from shorting the first electrodes D21 of adjacent sub-pixels. The wavy / zigzag-shaped protruding edge can be provided on the side facing the first electrode D21 or on both sides of the groove.

[0276] In a possible embodiment, with reference to Figures 10B, 10C, 10D, 10E, and 12H, Figure 10E may be a cross-sectional schematic diagram at the dotted line A0 in Figure 10D. When the second via K2 is an integrally connected structure, that is, multiple second vias K2 are formed in the second direction Y to form a groove, the second via K2 has two sidewalls extending perpendicular to the first direction X; at least one sidewall has a protruding structure K20, and the orthographic projection of the protruding structure K20 on the substrate is located in the region between the orthographic projections of two adjacent first electrodes D21 on the substrate in the second direction Y; the orthographic projection of the protruding structure K20 on the first plane overlaps with the orthographic projection of the first electrode D21 on the first plane, and the first plane is parallel to the first direction X and perpendicular to the substrate. It can be understood that compared with the sidewalls of other regions, the sidewalls of the protruding structure K20 have a longer slope, separating the first electrodes D21 on the adjacent sides, thereby avoiding the problem of short-circuiting the first electrode D21 due to photoresist residue during the exposure process of preparing the first electrode D21.

[0277] In one possible embodiment, in combination with Figures 10B and 10C, a side wall of the second via K2 may have a protruding structure K20. For example, the first electrode D21 in Figure 10B extends toward the side of the third via K3 (that is, the first electrode D21 is in the row where the third via K3 is located), so the protruding structure K20 is arranged on the side of the side wall of the second via K2 close to the third via K3; for another example, the first electrode D21 in Figure 10C extends toward the side of the first via K1 (that is, the first electrode D21 is in the row below the third via K3), so the protruding structure K20 is arranged on the side wall of the second via K2 close to K1; in one possible embodiment, in combination with Figures 10D and 12H, both side walls of the second via K2 may have a protruding structure K20, and the first electrode D21 extends to the side walls on both sides.

[0278] In one possible embodiment, the protruding structure K20 may be a structure that is recessed toward one side of the interior of the second via K2; in another possible embodiment, the protruding structure K20 may also be a structure that is protruding toward the outside of K2; in one possible embodiment, the orthographic projection shape of the protruding structure K20 on the substrate may be a triangle, a trapezoid, a semicircle, or an ellipse.

[0279] In one possible embodiment, as shown in FIG11 , the array substrate further includes: a color resist layer positioned between the second insulating layer F2 and the second conductive layer D2; the color resist layer includes: a plurality of color resist portions 102; and the orthographic projections of at least some of the color resist portions 102 on the substrate 1 overlap with the orthographic projections of the first metal line M11 on the substrate 1. In the disclosed embodiment, when the array substrate is provided with a color resist layer, the additional color resist layer increases the distance between the first electrode D21 and the first metal line M11. That is, in Cdp, the capacitance of the portions facing and lateral to the first electrode D21 and the first metal line M11 is further reduced. If the conductive portion D11 extends beyond the second metal line M21 (gate line) and overlaps the source conductor portion of the first active pattern C11, the resulting Cdp1 offset is more pronounced. Therefore, it is even more necessary to balance the coupling capacitance by offsetting the transfer electrode and other methods provided in the disclosed embodiment. Moreover, when the array substrate is provided with a color resist layer, the thickness of the film between the first electrode D21 and the first metal wire M11 increases, and at least two adjacent second via holes K2 are an integrated connected structure, which can ensure good electrical connection between the first electrode D21 and the conductive portion D11.

[0280] In a possible embodiment, referring to FIG11 , the array substrate further includes: the first electrode D21 may include a first sub-electrode D211 and a second sub-electrode D212; the first sub-electrode D211 is partially located at the bottom of the second via hole K2, partially located at the side wall of the second via hole K2, and partially extended to the surface of the second insulating layer F2 facing away from the substrate 1; the second sub-electrode D212 is located on the side of the first sub-electrode D211 facing away from the substrate 1, and is in direct contact with the portion of the first sub-electrode D211 that is extended to the surface of the second insulating layer F2 facing away from the substrate 1.

[0281] In a possible implementation, as shown in FIG. 11 , the array substrate further includes a filling portion 101 filled in the second via hole K2 to achieve planarization at the first electrode D21 .

[0282] In a possible embodiment, referring to FIG11 , the array substrate further includes: a passivation layer 19 located on the side of the second conductive layer D2 facing away from the substrate 1, a fourth metal layer M4 located on the side of the passivation layer 19 facing away from the substrate 1, and a third conductive layer D3 located on the side of the fourth metal layer M4 facing away from the substrate 1, wherein the fourth metal layer M4 may include a plurality of light-shielding portions M40, and the third conductive layer D3 may be a common electrode layer; the third conductive layer may be in direct contact with the fourth metal layer M4 to reduce the resistance of the common electrode layer through the fourth metal layer M4.

[0283] In a possible implementation, as shown in FIG. 11 , the array substrate further includes a first spacer PS on a side of the passivation layer 19 facing away from the substrate 1 .

[0284] 12A-12G, 13, and 14A, wherein FIG12B is a schematic diagram of a single film layer of the third metal layer in FIG12A, FIG12C is a schematic diagram of a single film layer of the first active layer in FIG12A, FIG12D is a schematic diagram of a single film layer of the second metal layer in FIG12A, FIG12E is a schematic diagram of a single film layer of the first metal layer in FIG12A, FIG12F is a schematic diagram of a single film layer of the first conductive layer in FIG12A, FIG12G is a schematic diagram of a single film layer of the second conductive layer in FIG12A, FIG13 is a schematic diagram of a cross-section at a dotted line A1A2 in FIG12A, and FIG14A is a schematic diagram of only a portion of the film layers in FIG12A. An embodiment of the present disclosure provides an array substrate having a display area AA and a non-display area BB located outside the display area AA, wherein the array substrate includes:

[0285] substrate 11;

[0286] The first active layer C1 is located on one side of the substrate 11 and includes a plurality of first active patterns C11 located in the display area AA. The first active pattern C11 includes a first portion CA extending along the first direction X and a second portion CB extending from one end of the first portion CA.

[0287] The first metal layer M1 includes: a plurality of first metal lines M11 extending along a first direction X; an orthographic projection of a first portion CA on the substrate 11 is located between orthographic projections of adjacent first metal lines M11 on the substrate; a portion of the orthographic projection of a second portion CB on the substrate 11 overlaps with a portion of the orthographic projection of the first metal line M11 on the substrate 11; specifically, the first metal line M11 may be a data line; specifically, the display area AA may have a plurality of first transistors; the second portion CB may serve as a first electrode of the first transistor at a position where it overlaps with the first metal line M11; the second portion CB may be conductive at a position where it overlaps with the first metal line M11, thereby achieving electrical connection between the first transistor and the data line;

[0288] The first conductive layer D1 includes: a plurality of conductive portions D11 located in the display area AA; the orthographic projection of at least one of the plurality of conductive portions D11 on the substrate 11 is located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; specifically, the first conductive layer D1 may be a transparent conductive layer; the conductive portion D11 may serve as the second electrode of the first transistor, electrically connecting the first active pattern C11 to the first electrode D21; specifically, the orthographic projection of the conductive portion D11 on the substrate 11 may be rectangular; the length of the conductive portion D11 in the first direction X may be greater than the length in the second direction Y; specifically, the length of the conductive portion D11 in the first direction X may be equal to the length in the second direction Y;

[0289] The second conductive layer D2 includes: a plurality of first electrodes D21 located in the display area AA; specifically, the second conductive layer D2 may be a transparent conductive layer, and the material of the second conductive layer D2 may be the same as that of the first conductive layer D1; specifically, the first electrodes D21 may be pixel electrodes; specifically, the orthographic projections of the first electrodes D21 on the substrate 11 may be located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; specifically, the orthographic projections of the first electrodes D21 on the substrate 11 may be rectangular; the length of the first electrodes D21 in the first direction X is greater than the length in the second direction Y;

[0290] Among them, the first metal wire M11 on the two adjacent sides of the conductive part D11 includes: a first sub-metal wire MA, and a second sub-metal wire MB; wherein the first sub-metal wire MA is electrically connected to the second part CB, that is, the first metal wire M11 electrically connected to the second part CB is used as the first type metal wire MA; the first part CA is electrically connected to the first electrode D21 through the conductive part D11; the orthographic projection of the conductive part D11 on the substrate 11, and the spacing i1 between the orthographic projection of the first sub-metal wire MA on the substrate 11 are greater than the spacing i2 between the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0291] The first metal line M11 and its associated structure, together with its own pixel electrode and its associated structure, can form a first coupling capacitor C dp1 The first metal line M11 and its associated structure can form a second coupling capacitor C with the adjacent pixel electrode and its associated structure. dp2; Wherein, the pixel electrode itself and the associated structure may be the area shown in the dotted box in FIG15A , and may specifically include: a first electrode D21 (as shown in the dotted box S1 in FIG15A ), and a conductive portion D11 to which the first electrode D21 is connected through the second via K2 (as shown in the dotted box S2 in FIG15A ), and a portion of the first active pattern C11 to which the conductive portion D11 is connected through the first via K1 and located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dotted box S3 in FIG15A , that is, the portion of the first active pattern C11 located below the second metal line M21. Since the time during which each row of pixels is turned on is very short within a display frame, it can be considered that the gate of the first transistor in the pixel is turned off for most of the time, and the portion of the first active pattern C11 covered by the second metal line M21 can be considered as an insulator); the first metal line M11 and the associated structure may be the area shown in the dotted box in FIG15B , and may specifically include: the first metal line M11 (as shown in FIG1 15B ), and a portion of the first active pattern C11 electrically connected to the first metal line M11 through the third via K3, located on the side of the second metal line M21 close to the second metal line M21 in the first direction X (as shown in the dotted box S5 in FIG15B , that is, the portion of the first active pattern C11 located above the second metal line M21); the adjacent pixel electrodes and associated structures may be the area shown in the dotted box in FIG15C , and specifically may include: an adjacent first electrode D21 (as shown in the dotted box S6 in FIG15C ), and an adjacent conductive portion D11 connected to the adjacent first electrode D21 through the second via K2 (as shown in the dotted box S7 in FIG15C ), and a portion of the adjacent first active pattern C11 connected to the adjacent conductive portion D11 through the first via K1, located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dotted box S8 in FIG15C , that is, the portion of the first active pattern C11 located below the second metal line M21); the first coupling capacitor C dp1 The structure can be shown in FIG15D, the second coupling capacitor C dp2 The composition can be shown in FIG15E ;

[0292] After research by the inventors of this application, the first coupling capacitor C dp1 The second coupling capacitor C dp2 The main reason for the difference is the asymmetry of the design of the first active pattern C11, and the thin film between the first active layer C1 and the first conductive layer D1, and the first coupling capacitor C dp1 The first active pattern C11 and the conductive portion D11 overlap up and down (as shown in the thick solid box S in FIG15D ), and the facing capacitance is larger, while the second coupling capacitance C dp2 There is no overlap, thus forming a first coupling capacitor C dp1 The second coupling capacitor Cdp2 The main part of the difference (in addition, although the first coupling capacitor C dp1 In the figure, the overlapping area between the first active pattern C11 and the first electrode D21 is larger than the overlapping area between the first active pattern C11 and the conductive portion D11. However, due to the presence of a thicker film layer between the first active pattern C11 and the first electrode D21, the overlapping capacitance is very small and the difference can be ignored). Since there is only one film layer between the first metal wire M11 and the conductive portion D11, the lateral capacitance formed by the first metal wire M11 and the conductive portion D11 is greater than the second coupling capacitance C. dp2 China dominates.

[0293] In the embodiment of the present disclosure, the distance i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the distance i2 between the orthographic projection of the conductive portion D11 and the second sub-metal line MB on the substrate 11, which can increase the lateral capacitance between the first metal line M11 and the conductive portion D11, thereby increasing the second coupling capacitance C dp2 , and due to the first coupling capacitor C dp1 In the embodiment, the overlapped capacitance between the first active pattern C11 and the conductive portion D11 (the area indicated by the thick solid frame S in FIG15D ) accounts for the majority, and the distance between the conductive portion D11 and the second sub-metal line MB is reduced, which does not affect the first coupling capacitor C dp1 This has a significant impact, thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference in vertical crosstalk is reduced.

[0294] It should be noted that, when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is straight, the spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11; when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is non-straight (for example, due to the process, the edge is partially uneven) or when the orthographic projection of the conductive portion D11 on the substrate 11 is non-rectangular, the spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be the average spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11. similarly, when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is linear, the spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be the minimum spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11; when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is non-linear (for example, due to process manufacturing, the edge has some unevenness) or when the orthographic projection of the conductive portion D11 on the substrate 11 is non-rectangular, the spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be the average spacing between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0295] It should be noted that the first sub-metal wire MA is electrically connected to the second part CB, which can be understood as the first sub-metal wire MA is electrically connected to the second part CB through the first transistor; when the orthographic projection of the conductive part D11 on the substrate 11 is a rectangle, the minimum distance i1 between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 can be the distance between the left edge of the conductive part D11 and the right edge of the first sub-metal wire MA; the minimum distance i2 between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be the distance between the right edge of the conductive part D11 and the left edge of the second sub-metal wire MB.

[0296] In a possible embodiment, with reference to FIG. 12A or FIG. 14A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0297] 15%≤i2 / i1≤75%, where i1 represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11; i2 represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0298] In a possible embodiment, with reference to FIG. 12A or FIG. 14A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0299] 3%≤(i1-i2) / i3≤15%, wherein i3 represents the minimum distance between adjacent first sub-metal lines MA and second sub-metal lines MB.

[0300] Specifically, as shown in FIG. 14A , the minimum spacing i3 between adjacent first and second sub-metal lines MA and MB may be the spacing between the right edge of the first sub-metal line MA and the left edge of the second sub-metal line MB.

[0301] In a possible embodiment, with reference to FIG. 12A or FIG. 14A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0302] 60%≤i4 / i3≤95%, where i4 represents the length of the conductive portion D11 in a direction perpendicular to the first direction X.

[0303] In one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 70% ≤ i4 / i3 ≤ 90%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 75% ≤ i4 / i3 ≤ 85%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 78% ≤ i4 / i3 ≤ 85%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3 =78%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy i4 / i3=79%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=79.64%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=80%; in one possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=81%.

[0304] In one possible embodiment, the minimum distance i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 can be 0.35 μm to 1.15 μm; the minimum distance i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be 0.05 μm to 0.85 μm.

[0305] In one possible embodiment, the minimum distance i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 can be 0.3 μm to 1.5 μm; the minimum distance i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be 0.2 μm to 1 μm.

[0306] In one possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 2μm to 10μm; in one possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 4μm to 8μm; in one possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5μm to 6μm; in one possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.1μm, 5.2μm, 5.3μm, 5.4μm, 5.5μm, 5.6μm, 5.7μm, 5.8μm, 5.8μm or 6.0μm; in one possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.65μm.

[0307] In one possible embodiment, the length i4 of the conductive portion D11 perpendicular to the first direction X may be 2 μm to 8 μm; in one possible embodiment, the length i4 of the conductive portion D11 perpendicular to the first direction X may be 3 μm to 6 μm; in one possible embodiment, the length i4 of the conductive portion D11 perpendicular to the first direction X may be 4 μm to 5 μm; in one possible embodiment, the length i4 of the conductive portion D11 perpendicular to the first direction X may be 4.1 μm, 4.2 μm, 4.3 μm, 4.4 μm, 4.5 μm, 4.6 μm, 4.7 μm, 4.8 μm, 4.9 μm or 5.0 μm.

[0308] In a possible implementation, a length i4 of the conductive portion D11 in a direction perpendicular to the first direction X may be 4.5 μm; and a minimum distance i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.65 μm.

[0309] In one possible embodiment, with reference to Figures 12A, 12C, and 12F, the first portion CA has a first symmetry axis e1 extending along the first direction X, and the first portion CA is symmetrical about the first symmetry axis e1; the conductive portion D11 has a second symmetry axis e2 extending along the first direction X, and the conductive portion D11 is symmetrical about the second symmetry axis e2; the second symmetry axis e2 is located on a side of the first symmetry axis e1 away from the first sub-metal wire MA.

[0310] In a possible embodiment, with reference to Figures 12A, 12F and 12G, the first electrode D21 has a seventh outer edge j1 extending along the first direction X; between two adjacent first metal wires M11, the seventh outer edge j1 is located in the part of the positive projection of the substrate 11, on the side of the first portion CA projected on the substrate 11 away from the first sub-metal wire MA; specifically, as shown in Figure 12F, the seventh outer edge j1 may be the right edge of the first electrode D21; the conductive portion D11 has an eighth outer edge j2 extending along the first direction X; between two adjacent first metal wires M11, the eighth outer edge j2 is located in the part of the positive projection of the substrate 11, on the side of the first portion CA projected on the substrate 11 away from the first sub-metal wire MA; specifically, as shown in Figure 12G, the eighth outer edge j2 may be the right edge of the conductive portion D11; between two adjacent first metal wires M11, the eighth outer edge j2 is located in the part of the positive projection of the substrate 11, on the side of the seventh outer edge j1 away from the first sub-metal wire MA.

[0311] In a possible embodiment, in combination with Figures 12A, 12F and 12G, the first electrode D21 has a ninth outer edge j3 extending along the first direction X; between two adjacent first metal wires M11, the ninth outer edge j3 is in the part of the positive projection of the substrate 11, and is located on the side where the positive projection of the first portion CA on the substrate 11 is close to the first sub-metal wire MA; specifically, as shown in Figure 12F, the ninth outer edge j3 may be the left edge of the first electrode D21; the conductive portion D11 has a tenth outer edge j4 extending along the first direction X; between two adjacent first metal wires M11, the tenth outer edge j4 is in the part of the positive projection of the substrate 11, and is located on the side where the positive projection of the first portion CA on the substrate 11 is close to the first sub-metal wire MA; specifically, as shown in Figure 12G, the tenth outer edge j4 may be the left edge of the conductive portion D11; between two adjacent first metal wires M11, the tenth outer edge j4 is in the part of the positive projection of the substrate 11, and is located on the side where the positive projection of the ninth outer edge j3 on the substrate 11 is away from the first sub-metal wire MA. In the embodiment of the present disclosure, the conductive portion D11 is moved away from the first sub-metal line MA, thereby increasing the second coupling capacitance C dp2 , thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1The difference in vertical crosstalk is reduced.

[0312] In a specific implementation, as shown in FIG12A , the conductive portion D11 can be moved to a side away from the first sub-metal line MA, thereby increasing the second coupling capacitor C dp2 In another possible embodiment, as shown in FIG. 16 , the conductive portion D11 may not be moved. Instead, the conductive portion D11 may be moved away from the first sub-metal line MA to the side away from the first sub-metal line MA, i.e., the width of D11 along the second direction Y is increased, and the minimum distance i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 is reduced. This can also increase the second coupling capacitance C. dp2 .

[0313] Specifically, as shown in Figure 16, the first electrode D21 has a ninth outer edge j3 extending along the first direction X; between two adjacent first metal wires M11, the ninth outer edge j3 is in the part of the positive projection of the substrate 11, and is located on the side of the positive projection of the first portion CA on the substrate 11 close to the first sub-metal wire MA; specifically, as shown in Figure 16, the ninth outer edge j3 can be the left edge of the first electrode D21; the conductive portion D11 has a tenth outer edge j4 extending along the first direction X; between two adjacent first metal wires M11, the tenth outer edge j4 is in the part of the positive projection of the substrate 11, and is located on the side of the positive projection of the first portion CA on the substrate 11 close to the first sub-metal wire MA; specifically, as shown in Figure 16, the tenth outer edge j4 can be the left edge of the conductive portion D11; between two adjacent first metal wires M11, the ninth outer edge j3 is in the part of the positive projection of the substrate 11, and coincides with the tenth outer edge j4 on the part of the positive projection of the substrate 11. In the embodiment of the present disclosure, the second coupling capacitance C is increased by moving the conductive portion D11 away from the edge of the first sub-metal line MA and away from the first sub-metal line MA. dp2 , thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference in vertical crosstalk is reduced.

[0314] It should be noted that, in order to clearly illustrate the positional relationship of the various structures of the embodiments of the present disclosure, Figures 12A to 19 are marked with the edges and positional relationship between the first electrode D21 of the second row and the conductive part D11, the first active pattern C11, the first sub-metal wire MA, and the second sub-metal wire MB. In a specific implementation, the first electrode D21 of each row and the conductive part D11, the first active pattern C11, the first sub-metal wire MA, and the second sub-metal wire MB corresponding to the current row also satisfy the relevant edge and positional relationships, but the embodiments of the present disclosure are not limited to this.

[0315] In addition, it should be noted that, for example, in FIG12G , the second row of first electrodes D21 from top to bottom only illustrates a portion of the complete first electrode D21 due to the limitation of the illustrated range. The complete pattern of the first electrode D21 can be as shown in the first row of first electrodes D21 from top to bottom, but the embodiments of the present disclosure are not limited to this.

[0316] In one possible embodiment, as shown in Figure 2A and Figure 14B, one end of the conductive portion D11 is electrically connected to the first portion CA, and the other end extends toward the side of the second metal line M21 and exceeds the second metal line M21 to form a protrusion S. The orthographic projection of the protrusion S on the substrate overlaps with the orthographic projection of the first active pattern C11 on the substrate.

[0317] In a possible implementation, as shown in FIG. 12C and FIG. 14B , the array substrate further includes: a second metal layer M2 located between the first active layer C1 and the first conductive layer D1 , the second metal layer M2 including: a plurality of second metal lines M21 extending along the second direction Y;

[0318] The first portion CA includes: a first sub-portion CA1, a second sub-portion CA2, and a third sub-portion CA3, which are sequentially distributed along the first direction X. The orthographic projection of the second sub-portion CA2 on the substrate overlaps with the orthographic projection of the second metal line M21 on the substrate 11. The first sub-portion CA1 is located on the side of the second sub-portion CA2 facing the second portion CB, and the third sub-portion CA3 is located on the side of the second sub-portion CA2 away from the second portion CB. That is, the portion of the first portion CA that overlaps with the projection of the second metal line M21 is the second sub-portion CA2.

[0319] The orthographic projection of the first sub-portion CA1 on the substrate 11 overlaps with the orthographic projection of the conductive portion D11 on the substrate 11. Specifically, the orthographic projection of the first sub-portion CA1 on the substrate 11 overlaps with the orthographic projection of the conductive portion D11 on the substrate 11, as shown in the thick solid line frame S in FIG14B .

[0320] In a possible embodiment, in combination with Figures 12A, 13, 17A, and 18, where Figure 18 is a schematic diagram of the stacking of some film layers in Figure 17A, the array substrate further includes: a second metal layer M2 located between the first active layer C1 and the first conductive layer D1, the second metal layer M2 including: a plurality of second metal wires M21 extending along the second direction Y; the second portion CB including: a fourth sub-portion CB1 connected to the first portion CA and extending along the third direction, and a fifth sub-portion CB2 connected to the fourth sub-portion CB1, the first metal wire M11 being electrically connected to the fifth sub-portion CB2; the second direction Y intersects the first direction X, and the third direction Z intersects with the first direction X; the conductive portion D11 includes: an eleventh outer edge j5 extending along the second direction Y and toward the fifth sub-portion CB2, specifically, as shown in Figure 17A, the eleventh outer edge j5 can be the upper edge of the conductive portion D11; the second metal wire M21 has a twelfth outer edge j6 extending along the second direction Y and toward the fifth sub-portion CB2, specifically, as shown in Figure 17A, the twelfth outer edge j6 can be the upper edge of the second metal wire M21; the orthographic projection of the twelfth outer edge j6 on the substrate 11 is located on the side of the orthographic projection of the eleventh outer edge j5 on the substrate 11 facing the orthographic projection of the fifth sub-portion CB2 on the substrate 11.

[0321] In the embodiment of the present disclosure, the second metal line M21 has a twelfth outer edge j6 extending along the second direction Y and toward the fifth sub-portion CB2, that is, the second metal line M21 is moved up (after the second metal line M21 is moved up, the first coupling capacitor C dp1 The structure can be shown in FIG17B, the second coupling capacitor C dp2 The structure can be as shown in FIG17C ), the second metal line M21 can shield the overlapping capacitance of the first active pattern C11 and the conductive portion D11 (that is, it can shield the capacitance of the area shown by the thick solid frame S in FIG15D ), thereby reducing the first coupling capacitance C dp1 The overlapping capacitance accounts for a large proportion in the first coupling capacitance, reducing the first coupling capacitance C dp1 The second metal wire M21 moves upward, and the lateral capacitance between the first metal wire M11 and the conductive portion D11 (constituting the second coupling capacitor C dp2 The main part of the) has little effect, which can reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference in vertical crosstalk is reduced.

[0322] Specifically, the second metal line M21 may be a gate line.

[0323] Specifically, the second direction Y may be perpendicular to the first direction X; the angle formed by the third direction Z and the first direction X may be 0° to 90°; specifically, the angle formed by the third direction Z and the first direction X may be 30° to 60°; specifically, the angle formed by the third direction Z and the first direction X may be 45°.

[0324] In one possible embodiment, as shown in conjunction with Figures 12A, 12C, 12F, and 12G, the length g1 of the orthographic projection of the first electrode D21 on the substrate 11 along the second direction Y may be equal to the length g2 of the orthographic projection of the conductive portion D11 on the substrate 11 along the second direction Y. The length g1 of the orthographic projection of the first electrode D21 on the substrate 11 along the second direction Y may be less than the minimum spacing i3 between adjacent first and second sub-metal lines MA and MB. In one possible embodiment, as shown in conjunction with Figures 12A, 12C, 12F, and 12G, the length g4 of the orthographic projection of the first electrode D21 on the substrate 11 along the first direction X may be greater than the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 along the first direction X. In one possible embodiment, with reference to Figures 12A, 12C, 12F, and 12G, the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 along the first direction X may be one-fifth to four-fifths of the length g4 of the orthographic projection of the first electrode D21 on the substrate 11 along the first direction X; in one possible embodiment, the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 along the first direction X may be one-half of the length g4 of the orthographic projection of the first electrode D21 on the substrate 11 along the first direction X.

[0325] In one possible embodiment, as shown in FIG12A , the orthographic projection of the conductive portion D11 on the substrate 11 may cover the orthographic projection of the gap between two adjacent first electrodes D21 on the substrate 11 in the first direction X. In one possible embodiment, as shown in FIG12A , the overlapping area of ​​the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first electrode D21 on the substrate 11 may account for one-fifth to four-fifths of the orthographic projection area of ​​the conductive portion D11 on the substrate 11; in one possible embodiment, as shown in FIG12A , the overlapping area of ​​the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first electrode D21 on the substrate 11 may account for one-third of the orthographic projection area of ​​the conductive portion D11 on the substrate 11.

[0326] In one possible embodiment, with reference to Figures 12A, 12C, 12F and 12G, the distance g6 between two adjacent first electrodes D21 in the first direction X may be one-fifth to four-fifths of the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 in the first direction X; in one possible embodiment, with reference to Figures 12A, 12C, 12F and 12G, the distance g6 between two adjacent first electrodes D21 in the first direction X may be one-third of the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 in the first direction X.

[0327] In one possible embodiment, as shown in Figures 12A, 12C, 12F and 12G, the maximum length g3 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the second direction Y may be less than the length g2 of the orthographic projection of the conductive portion D11 on the substrate 11 along the second direction Y.

[0328] In one possible embodiment, with reference to FIG12C , the maximum length g7 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X may be one-third to three-thirds of the maximum length g8 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X; in one possible embodiment, with reference to FIG12C , the maximum length g7 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X may be one-half of the maximum length g8 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X.

[0329] In one possible embodiment, with reference to FIG12C , a maximum length g9 of the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11 along the first direction X may be one-third to three-thirds of a maximum length g10 of the orthographic projection of the second portion CB of the first active pattern C11 on the substrate 11 along the first direction X; in one possible embodiment, with reference to FIG12C , a maximum length g9 of the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11 along the first direction X may be one-half of the maximum length g10 of the orthographic projection of the second portion CB of the first active pattern C11 on the substrate 11 along the first direction X; a maximum length g11 of the orthographic projection of the fifth sub-portion CB2 of the first active pattern C11 on the substrate 11 along the first direction X may be one-half of the maximum length g10 of the orthographic projection of the second portion CB of the first active pattern C11 on the substrate 11 along the first direction X.

[0330] In one possible embodiment, with reference to FIG12C , a maximum length g12 of the orthographic projection of the fifth sub-portion CB2 of the first active pattern C11 on the substrate 11 along the second direction Y may be equal to a maximum length g3 of the orthographic projection of the first portion CA of the first active pattern C11 on the substrate 11 along the second direction Y; in one possible embodiment, with reference to FIG12C , a maximum length g12 of the orthographic projection of the fifth sub-portion CB2 of the first active pattern C11 on the substrate 11 along the second direction Y may be greater than a length g13 of the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11 along the second direction Y.

[0331] In a possible embodiment, as shown in Figures 17A and 18, the distance d1 between the orthographic projection of the twelfth outer edge j6 on the substrate 11 and the orthographic projection of the eleventh outer edge j5 on the substrate 11 in the first direction X is one-fifth to four-fifths of the length d2 of the orthographic projection of the second metal wire M21 on the substrate 11 in the first direction X.

[0332] In one possible embodiment, as shown in conjunction with FIG17A and FIG18 , the orthographic projection of the second metal line M21 on the substrate 11 covers the orthographic projection of the eleventh outer edge j5 on the substrate 11. That is, the maximum upward movement of the second metal line M21 does not exceed the upper edge of the conductive portion D11.

[0333] In one possible implementation, a distance d1 between an orthographic projection of the twelfth outer edge j6 on the substrate 11 and an orthographic projection of the eleventh outer edge j5 on the substrate 11 in the first direction X is 1 μm to 3 μm. In one possible implementation, a distance d1 between an orthographic projection of the twelfth outer edge j6 on the substrate 11 and an orthographic projection of the eleventh outer edge j5 on the substrate 11 in the first direction X is 1.5 μm.

[0334] In a specific implementation, as shown in FIG12A , the second coupling capacitance C can be reduced by simply making the minimum distance i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 larger than the minimum distance i2 between the orthographic projection of the conductive portion D11 and the second sub-metal wire MB on the substrate 11 (i.e., shifting the conductive portion D11 to the right). dp2 With the first coupling capacitor C dp1 17A and 18 , the second coupling capacitance C can be reduced by only making the orthographic projection of the twelfth outer edge j6 on the substrate 11 located on the side where the orthographic projection of the eleventh outer edge j5 on the substrate 11 faces the orthographic projection of the fifth sub-portion CB2 on the substrate 11 (i.e., moving the second metal wire M21 upward). dp2 With the first coupling capacitor C dp119 , the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is made greater than the minimum spacing i2 between the orthographic projection of the conductive portion D11 and the second sub-metal wire MB on the substrate 11 (i.e., the conductive portion D11 is shifted to the right). At the same time, the orthographic projection of the twelfth outer edge j6 on the substrate 11 is located on the side where the orthographic projection of the eleventh outer edge j5 on the substrate 11 faces the orthographic projection of the fifth sub-portion CB2 on the substrate 11 (i.e., the second metal wire M21 is shifted upwards), thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0335] In one possible embodiment, as shown in conjunction with FIG12A and FIG13 , the first conductive layer D1 is located on a side of the first active layer C1 facing away from the substrate 11. The array substrate further includes: a first insulating layer F1 located between the first active layer C1 and the first conductive layer D1, and a first via K1 extending through the first insulating layer F1. The conductive portion D11 is electrically connected to the first portion CA via the first via K1. Between two adjacent first metal wires M11, the first via K1 is located at the center O1 of the orthographic projection of the substrate 11, and the minimum spacing d3 between the first via K1 and the first sub-metal wire MA is greater than the minimum spacing d4 between the first via K1 and the second sub-metal wire MB. In the disclosed embodiment, when the conductive portion D11 is shifted rightward, the first via K1 connecting the conductive portion D11 to the first active pattern C11 is also shifted rightward to prevent the conductive portion D11 from being affected by the rightward shift of the first via K1 while the first via K1 is not.

[0336] In one possible embodiment, as shown in conjunction with FIG12A and FIG13 , the first electrode D21 is located on a side of the first conductive layer D1 facing away from the substrate 11. The array substrate further includes: a second insulating layer F2 located between the first conductive layer D1 and the first electrode D21, and a second via K2 extending through the second insulating layer F2. The first electrode D21 is electrically connected to the K2 conductive portion D11 via the second via. Between two adjacent first metal wires M11, the second via K2 is located at the center O2 of the orthographic projection of the substrate 11, and the minimum spacing d5 between the second via K2 and the first sub-metal wire MA is greater than the minimum spacing d6 between the second via K2 and the second sub-metal wire MB. In the disclosed embodiment, when the conductive portion D11 is shifted rightward, the second via K2, which provides electrical connection between the first electrode D21 and the conductive portion D11, is also shifted rightward to prevent the conductive portion D11 from shifting rightward while the second via K2 does not, thereby affecting the electrical connection between the first electrode D21 and the conductive portion D11.

[0337] In one possible embodiment, at least a portion of the orthographic projection of the first via K1 on the substrate 11 does not overlap with at least a portion of the orthographic projection of the second via K2 on the substrate 11. In one possible embodiment, as shown in conjunction with FIG12A and FIG13 , the entire orthographic projection of the first via K1 on the substrate 11 does not overlap with the entire orthographic projection of the second via K2 on the substrate 11.

[0338] In one possible implementation, the first insulating layer F1 includes one or a combination of the following:

[0339] a first gate insulating layer 15;

[0340] a first interlayer dielectric layer 16;

[0341] A second interlayer dielectric layer 17 .

[0342] 13 , the first interlayer dielectric layer 16 may be located on a side of the first gate insulating layer 15 away from the substrate 11 ; the second interlayer dielectric layer 17 may be located on a side of the first interlayer dielectric layer 16 away from the substrate 11 .

[0343] In a possible implementation, as shown in FIG. 13 , the first insulating layer F1 includes: a first gate insulating layer 15 , a first interlayer dielectric layer 16 , and a second interlayer dielectric layer 17 .

[0344] In a possible embodiment, in combination with FIG2A and FIG13 , the array substrate further includes: a third via K3 penetrating the first interlayer dielectric layer 16 and the second interlayer dielectric layer 17 , and the first metal wire M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via K3 .

[0345] In one possible embodiment, as shown in FIG12A , the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. Specifically, the orthographic projection of the second metal wire M21 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In one possible embodiment, the orthographic projection of the second via K2 on the substrate 11 is located at the overlapping region of the first electrode D21 and the conductive portion D11 on the substrate 11. In this way, the first electrode D21 and the conductive portion D11 are electrically connected in the overlapping region through the second via K2.

[0346] In one possible embodiment, the orthographic projection of the third metal line M31 on the substrate 11 covers the orthographic projection of the first via K1 on the substrate 11. The orthographic projection of the first metal line M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. In one possible embodiment, the orthographic projection of the first via K1 on the substrate 11 is located in the overlapping region of the orthographic projection of the first portion CA of the first active pattern C11 and the conductive portion D11 on the substrate 11. In this way, the first portion CA and the conductive portion D11 are electrically connected in the overlapping region through the first via K1.

[0347] In one possible embodiment, the orthographic projection of the first metal line M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. Specifically, the orthographic projection of the third via K3 on the substrate 11 is located at the overlapping region of the orthographic projections of the first metal line M11 and the second portion CB of the first active pattern C11 on the substrate 11. In this way, the first metal line M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via K3.

[0348] In one possible embodiment, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 are both located between the orthographic projections of the first sub-metal wire MA and the second sub-metal wire MB on the substrate 11. In one possible embodiment, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 have a gap in the first direction X. Specifically, the length of the gap between the first via K1 and the second via K2 in the first direction X may be one-quarter to three-quarters of the length of the conductive portion D11 in the first direction X.

[0349] In one possible embodiment, the third via K3 has a third via symmetry axis e3 extending along the second direction Y; the first electrode D21 has a first electrode outer edge j7 extending along the second direction Y and toward the side of the electrically connected conductive portion D11; the distance between the third via symmetry axis e3 and the first electrode outer edge j7 in the first direction X may be one quarter to three quarters of the length of the first electrode D21 along the first direction X; in one possible embodiment, the distance between the third via symmetry axis e3 and the first electrode outer edge j7 in the first direction X may be one half of the length of the first electrode D21 along the first direction X, and the third via symmetry axis e3 is located at a position where the length of the first electrode D21 along the first direction X is half.

[0350] In a specific implementation, the thickness of the first insulating layer F1 between the first active layer C1 and the first conductive layer D1 can be adjusted by adjusting at least one or a combination of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17. In combination with rightward shifting of the conductive portion D11 and / or upward shifting of the second metal trace M21, precise capacitance difference control can be achieved to reduce the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 difference.

[0351] In a possible embodiment, as shown in FIG13 , the thickness of at least one of the first gate insulating layer 15 , the first interlayer dielectric layer 16 , and the second interlayer dielectric layer 17 is greater than

[0352] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0353] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0354] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0355] In one possible embodiment, as shown in FIG13 , the array substrate further includes a third metal layer M3 located on the side of the first active layer C1 facing the substrate 11. The third metal layer M3 includes a plurality of third metal lines M31 extending along a second direction Y. The orthographic projections of the third metal lines M31 on the substrate 11 overlap the orthographic projections of the second metal lines M21 on the substrate 11. Specifically, the third metal lines M31 can be used to shield at least a portion of the first active pattern C11 of the first transistor to prevent ambient light from illuminating the first active pattern C11 and affecting the characteristics of the first transistor.

[0356] In one possible embodiment, as shown in FIG12A , the orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the gap between two adjacent first electrodes D21 in the first direction X on the substrate 11. In one possible embodiment, as shown in FIG12A , the orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the first portion CA of the first active pattern C11 on the substrate 11, and the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11. The orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the conductive portion D11 on the substrate 11.

[0357] In one possible implementation, as shown in FIG12A , the orthographic projection of the third metal line M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In the disclosed embodiment, the orthographic projection of the third metal line M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11, that is, the third metal line M31 of the array substrate covers the second via K2, which can reduce the risk of light leakage from the second via K2 on the array substrate.

[0358] Since virtual reality (VR) headsets are near-eye displays, and the images displayed on the LCD screen need to be magnified multiple times by the imaging system before they can enter the human eye, even though the current VR display resolution has reached more than 1000PPI, the screen door effect caused by the shading structure can still be seen in the entire display. In view of this, in a possible embodiment, referring to Figures 20A, 20B and 20C, wherein Figure 20B may be a single-film schematic diagram of the third metal wire M31 in Figure 20A, Figure 20B may also be a partial schematic diagram at the dotted box J1 in Figure 20C, and Figure 20C may be a schematic diagram of a larger range of Figure 20B, the array substrate includes: a plurality of pixel light-transmitting areas P, the plurality of pixel light-transmitting areas P include: a plurality of pixel light-transmitting area rows H extending along a first direction X and arranged along a second direction Y; at least one pixel light-transmitting area row H among the plurality of pixel light-transmitting area rows H includes: a first pixel light-transmitting area P1, a second pixel light-transmitting area P2, and a third pixel light-transmitting area P3; the light wavelength range emitted by the third pixel light-transmitting area P3 is smaller than the light wavelength range emitted by the first pixel light-transmitting area P1 , and a light band range smaller than that of the second pixel light-transmitting area P2; specifically, the first pixel light-transmitting area P1 can be a pixel light-transmitting area emitting red light, the second pixel light-transmitting area P2 can be a pixel light-transmitting area emitting green light, and the third pixel light-transmitting area P3 can be a pixel light-transmitting area emitting blue light; the third metal wire M31 includes: a third metal wire main portion M310 extending along the second direction Y, and a first blocking structure Z1 connected to the third metal wire main portion M310; the maximum length h1 of the first blocking structure Z1 in the first direction X is greater than the maximum length h3 of the third metal wire main portion M310 in the first direction X; the orthographic projection of the first blocking structure Z1 on the substrate 11 is located in the gap between the orthographic projections of at least partially adjacent two third pixel light-transmitting areas P3 on the substrate 11 in the first direction X.

[0359] Specifically, the array substrate further includes: a spacer (not shown in the figure, but specifically, its orthographic projection shape and position on the substrate 11 can be as shown in FIG20C , i.e., the orthographic projection shape of the spacer on the substrate 11 can be an octagon, and can be located in the gap between at least partially adjacent orthographic projections of two third pixel light-transmitting areas P3 on the substrate 11 in the first direction X); and an orthographic projection of the first blocking structure Z1 on the substrate 11, covering the orthographic projection of the spacer on the substrate 11. In other words, the orthographic projection of the spacer on the substrate 11 is located in the gap between at least partially adjacent orthographic projections of two third pixel light-transmitting areas P3 on the substrate 11 in the first direction X.

[0360] In the embodiment of the present disclosure, placing the spacer in the gap between the light-transmitting areas of adjacent blue pixels effectively reduces the human eye's sensitivity to compensation for obstructions (such as a black matrix) at the position of the spacer (blue pixels have lower brightness than green and red pixels, so placing the spacer in the gap between the light-transmitting areas of adjacent blue pixels will result in a smaller visual difference between light and dark for the human eye than placing it on green and red pixels).

[0361] In a possible embodiment, referring to Figures 20A, 20B and 20C, the third metal wire M31 also includes: a second shielding structure Z2 connected to the third metal wire main portion M310; the maximum length h2 of the second shielding structure Z2 in the first direction X is greater than the maximum length h3 of the third metal wire main portion M310 in the first direction X, and is less than the maximum length h1 of the first shielding structure Z1 in the first direction X; the orthographic projection of the second shielding structure Z1 on the substrate 11 is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the second direction Y, and the orthographic projection of the second shielding structure Z2 on the substrate 11 does not overlap with the orthographic projection of the first shielding structure Z1 on the substrate 11.

[0362] In the embodiment of the present disclosure, the orthographic projection of the second blocking structure Z1 on the substrate 11 is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the second direction Y, and the orthographic projection of the second blocking structure Z2 on the substrate 11 does not overlap with the orthographic projection of the first blocking structure Z1 on the substrate 11. That is, the second blocking structure Z1 can be set at a position without spacers between adjacent blue pixels, reducing the brightness difference between the positions of the blue pixels with spacers and without spacers, making the brightness more evenly distributed in the entire pixel area, thereby reducing the screen door effect and improving the visual effect.

[0363] In a possible implementation, a length m3 of the third pixel light-transmitting area P3 in the first direction X is smaller than a length m1 of the first pixel light-transmitting area P1 in the first direction X, and smaller than a length m2 of the second pixel light-transmitting area P2 in the first direction X.

[0364] Specifically, the pixel light-transmitting area P can be understood as the effective display area of ​​the pixel, which can be an area in the pixel area that is not blocked by the blocking structure (such as a light-shielding layer, a gate line, a data line, a black matrix, etc.). Specifically, in a possible embodiment, as shown in Figure 20C, the pixel light-transmitting area P can be shown as a white area.

[0365] In one possible embodiment, the length m1 of the first pixel light-transmitting area P1 in the first direction X is equal to the length m2 of the second pixel light-transmitting area P2 in the first direction X. In the embodiment of the present disclosure, the second shielding structure Z2 is set by setting the length m3 of the third pixel light-transmitting area P3 in the first direction X to be shorter. Moreover, compared with the first pixel light-transmitting area P1 and the second pixel light-transmitting area P2 having a longer output light wavelength range, the brightness of the third pixel light-transmitting area P3 having a smaller output light wavelength range is lower, which can effectively reduce the sensitivity of the human eye to the second shielding structure Z2, and can reduce the brightness difference between the position with spacers and the position without spacers between the third pixel light-transmitting area P3, so that the brightness is more evenly distributed in the entire pixel area, thereby reducing the screen door effect and improving the visual effect.

[0366] In the disclosed embodiment, a spacer can be placed in the gap between the light-transmitting areas of adjacent blue pixels, effectively reducing the human eye's sensitivity to compensation for obstructions (such as a black matrix) at the spacer position (blue pixels have lower brightness than green and red pixels, so placing a spacer in the gap between the light-transmitting areas of adjacent blue pixels creates a smaller visual difference between light and dark for the human eye than placing it on green and red pixels). In addition, a second blocking structure Z2 can be set at a position without a spacer between adjacent blue pixels, reducing the brightness difference between the blue pixel positions with and without spacers, making the brightness distribution more uniform across the entire pixel area, thereby reducing the screen door effect and improving the visual effect.

[0367] In one possible embodiment, the wavelength range of light emitted by the third pixel light-transmitting area P3 may also be greater than the wavelength range of light emitted by the first pixel light-transmitting area P1, and greater than the wavelength range of light emitted by the second pixel light-transmitting area P2. Specifically, the third pixel light-transmitting area P3 may be a red pixel light-transmitting area, the first pixel light-transmitting area P1 may be a blue pixel light-transmitting area, and the second pixel light-transmitting area P2 may be a green pixel light-transmitting area. In other words, the second blocking structure Z2 may be provided in at least a portion of the gap between two adjacent red pixel light-transmitting areas, and a spacer may be placed in the gap between two adjacent red pixel light-transmitting areas.

[0368] In one possible implementation, as shown in FIG20C , the orthographic projections of the first blocking structure Z1 and the second blocking structure Z2 on the substrate 11 are alternately distributed along the first direction X. Specifically, the first blocking structure Z1 and the second blocking structure Z2 may be located in the same column, such as the column where the third pixel light-transmitting area P3 is located.

[0369] In one possible embodiment, the orthographic projection shape of the first blocking structure Z1 on the substrate 11 may be the same as the orthographic projection shape of the spacer on the substrate 11. For example, the orthographic projection shape of the spacer on the substrate 11 may be a hexagon, an octagon, a circle, or an ellipse; the orthographic projection shape of the first blocking structure Z1 on the substrate 11 may also be a hexagon, an octagon, a circle, or an ellipse.

[0370] Specifically, the orthographic projection of the second blocking structure Z2 on the substrate 11 may be a rectangle. The maximum length of the second blocking structure Z2 in the first direction X may be greater than the maximum length in the second direction Y.

[0371] Specifically, the ratio of the maximum length h2 of the second blocking structure Z2 in the first direction X to the maximum length h1 of the first blocking structure Z1 in the first direction X is greater than or equal to 0.78.

[0372] Specifically, the orthographic projection shape of the second shielding structure Z2 on the substrate 11 is a rectangle, and the maximum length h2 of the second shielding structure Z2 in the first direction X can be the length of the vertical side of the rectangle along the first direction X; the orthographic projection shape of the first shielding structure Z1 on the substrate 11 is an octagon, and the maximum length h1 of the first shielding structure Z1 in the first direction X can be the distance between two opposite sides of the octagon parallel to the second direction Y.

[0373] In a possible embodiment, referring to FIG20C , in the pixel light-transmitting area row H, the first pixel light-transmitting area P1, the second pixel light-transmitting area P2, and the third pixel light-transmitting area P3 are arranged in sequence along the second direction Y; the pixel light-transmitting areas P with the same output light wavelength band range are located in the same first direction X, that is, the first pixel light-transmitting area P1 is located in the same column, the second pixel light-transmitting area P2 is located in the same column, and the third pixel light-transmitting area P3 is located in the same column.

[0374] In one possible embodiment, the maximum length h2 of the second blocking structure Z2 in the first direction X may be in the range of 8μm to 12μm, specifically, for example, 8μm, 9μm, 10μm, 10.5μm, 11μm, 12μm; the maximum length h1 of the first blocking structure Z1 in the first direction X may be in the range of 10μm to 15μm, specifically, for example, 10μm, 11μm, 12μm, 13μm, 13.5μm, 14μm, 15μm; the maximum length h3 of the third metal wire main portion M310 in the first direction X may be in the range of 5μm to 10μm, specifically, for example, 5μm, 6μm, 7μm, 7.5μm, 8μm, 9μm, 10μm.

[0375] In one possible embodiment, as shown in Figures 21 and 22, the array substrate further includes, located in the non-display area BB, a second active layer C2 located on the side of the first active layer C1 facing the substrate 11, a driving source and drain electrode (including a driving source electrode MQ2 and a driving drain electrode MQ3) located on the side of the second active layer C2 facing away from the substrate 11, and a driving gate electrode MQ1. Specifically, the array substrate may include a gate drive circuit for the non-display area BB. The gate drive circuit board includes a plurality of second transistors. The second transistors may include a second active layer C2, a driving source and drain electrode (including a driving source electrode MQ2 and a driving drain electrode MQ3), and a driving gate electrode MQ1. In the disclosed embodiment, the array substrate utilizes LTPO (Low Temperature Polycrystalline Oxide) technology, integrating two types of TFTs (Thin Film Transistors)—LTPS (Low Temperature Poly-Silicon) and oxide. This enables AR and VR products to have high resolution (Pixel Per Inch), high aperture ratio, and high transmittance.

[0376] In one possible embodiment, as shown in Figures 21 and 22, the array substrate further includes: a first drive electrode MD1, a second drive electrode MD2, a third drive electrode MD3, and a fourth drive electrode MD4 located in the non-display area BB. The first drive electrode MD1 is electrically connected to the second drive electrode MD2, and the third drive electrode MD3 is electrically connected to the fourth drive electrode MD4. Specifically, the first drive electrode MD1 can serve as a first signal line, and the third drive electrode MD3 can serve as a second signal line. The first signal line can include a signal line electrically connected to a gate drive circuit and / or a signal line electrically connected to a multiplexer; the second signal line can include a signal line electrically connected to a gate drive circuit and / or a signal line electrically connected to a multiplexer. The first signal line can include: an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line. The second signal line can include: an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line.

[0377] In one possible embodiment, as shown in FIG. 21 , the second active layer C2 is located between the third metal layer M3 and the substrate 11; the drive gate MQ1 is located in the third metal layer M3; and the drive source and drain electrodes (including the drive source electrode MQ2 and the drive drain electrode MQ3) are located in the first metal layer M1. In the disclosed embodiment, the drive gate MQ1 is located in the third metal layer M3; and the drive source and drain electrodes are located in the first metal layer M1. This allows the corresponding drive gate MQ1 and drive source and drain electrodes in the non-display area to be formed simultaneously with the third metal layer M3 and the first metal layer M1 in the display area AA, simplifying the display panel manufacturing process.

[0378] In a possible embodiment, referring to FIG21 , the first driving electrode MD1 and the third driving electrode MD3 may be located in the first metal layer M1; the second driving electrode MD2 may be located in the third metal layer M3, and the fourth driving electrode MD4 may be located in the second metal layer M2; and thus, the first driving electrode MD1 and the third driving electrode MD3 corresponding to the non-display area may be formed while the first metal layer M1 of the display area AA is formed; the fourth driving electrode MD4 corresponding to the non-display area may be formed while the second metal layer M2 of the display area AA is formed; and the second driving electrode MD2 corresponding to the non-display area may be formed while the third metal layer M3 of the display area AA is formed, thereby simplifying the manufacturing process of the display panel.

[0379] In one possible embodiment, at least part of the routing of the second metal layer M2 and at least part of the routing of the third metal layer M3 can be electrically connected by jumping layers in the non-display area BB. For example, the second metal line M21 and the third metal line M31 can be electrically connected in the non-display area BB to enable the transistors in the display area AA to form a dual-gate structure.

[0380] In one possible embodiment, as shown in FIG22 , the second active layer C2 is located between the third metal layer M3 and the first active layer C1; the driver source and drain electrodes (including the driver source electrode MQ2 and the driver drain electrode MQ3) are located in the second metal layer M2; and the driver gate electrode MQ1 is located in the third metal layer M3. In the disclosed embodiment, the driver source and drain electrodes are located in the second metal layer M2; the driver gate electrode MQ1 is located in the third metal layer M3. This allows the corresponding driver gate electrode MQ1 and driver source and drain electrodes in the non-display area to be formed simultaneously with the third metal layer M3 and the second metal layer M2 in the display area AA, simplifying the display panel manufacturing process.

[0381] In a possible embodiment, as shown in Figure 22, the first driving electrode MD1 can be located in the first metal layer M1; the second driving electrode MD2 can be located in the second metal layer M2, and the third driving electrode MD3 can be located in the third metal layer M3; then, the first driving electrode MD1 corresponding to the non-display area can be formed while the first metal layer M1 of the display area AA is formed; the second driving electrode MD2 corresponding to the non-display area can be formed while the second metal layer M2 of the display area AA is formed; and the third driving electrode MD3 corresponding to the non-display area can be formed while the third metal layer M3 of the display area AA is formed, which can simplify the manufacturing process of the display panel.

[0382] In one possible embodiment, with reference to Figures 21 and 23A-23C, where Figure 23B is a pattern of the third conductive layer corresponding to Figure 23A, and Figure 23B may also be a partial schematic diagram of the dashed box in Figure 23C, i.e., Figure 23C is a schematic diagram of a larger area of ​​Figure 23B, the array substrate further includes: a third conductive layer D3 located on a side of the second conductive layer D2 facing away from the substrate, the third conductive layer D3 including a plurality of hollows L, the orthographic projections of the hollows L on the substrate 11 overlapping with the portions of the first electrodes D21 on the substrate 11. In the disclosed embodiment, the array substrate further includes the third conductive layer D3, the third conductive layer D3 including a plurality of hollows L, the orthographic projections of the hollows L on the substrate 11 overlapping with the portions of the first electrodes D21 on the substrate 11. This allows the first electrodes D21 and the third conductive layer D3 to form a fringe electric field at the hollows L, thereby driving liquid crystal deflection. In the embodiment of the present disclosure, the driving mode of the display panel may be a novel Fringe Field Switching (FFS) mode, or an Advanced Super Dimension Switch (ADS) mode.

[0383] It should be noted that, in order to clearly illustrate the various film layers, Figure 23A only illustrates the hollow L shape of the third conductive layer D3. The complete pattern of the third conductive layer D3 can be shown in Figure 23B, and the pattern of a larger area in Figure 23B can be shown in Figure 23C.

[0384] Specifically, the third conductive layer D3 may be a common electrode layer, forming an electric field with the first electrode D21 to drive the liquid crystal molecules between the array substrate and the opposite substrate.

[0385] In one possible embodiment, the third conductive layer D3 may include: a plurality of hollow rows extending along the first direction X and arranged along the second direction Y; the hollow rows include: a plurality of hollows L sequentially arranged along the first direction X. In one possible embodiment, as shown in Figures 23A-23C, the hollows L may correspond one-to-one to the first electrodes D21.

[0386] In one possible embodiment, the portion of the hollow L projected on the substrate 11 overlaps with the portion of the first metal wire M11 projected on the substrate 11; in one possible embodiment, the portion of the hollow L projected on the substrate 11 overlaps with the portion of the third metal wire M31 projected on the substrate 11; in one possible embodiment, the portion of the hollow L projected on the substrate 11 overlaps with the portion of the third metal wire M31 projected on the substrate 11.

[0387] In a possible implementation manner, the orthographic projection of the second metal wire M21 on the substrate 11 covers the orthographic projection of the gap between two adjacent hollow rows on the substrate 11 .

[0388] In a possible embodiment, referring to Figures 21 and 22, the array substrate further includes: a fourth metal layer M4 located on the side of the third conductive layer D3 facing the substrate 11 and in contact with the third conductive layer D3; the fourth metal layer M4 includes: a plurality of fourth metal wires M41 extending along the first direction X, and the orthographic projection of the fourth metal wire M41 on the substrate 11 covers the orthographic projection of the first metal wire M11 on the substrate 11.

[0389] Specifically, the conductivity of the fourth metal layer M4 may be better than that of the third conductive layer D3. The plurality of fourth metal wires M41 provided on the array substrate and in contact with the third conductive layer D3 may reduce the resistance of the third conductive layer D3.

[0390] In a possible implementation, as shown in FIG21 , the display panel may further include at least one of the following:

[0391] a buffer layer 12 located between the substrate 11 and the second active layer C2;

[0392] a second gate insulating layer 13 located between the second active layer C2 and the third metal layer M3;

[0393] a third interlayer dielectric layer 14 located between the third metal layer M3 and the first active layer C1;

[0394] a first gate insulating layer 15 located between the first active layer C1 and the second metal layer M2;

[0395] a first interlayer dielectric layer 16 located between the second metal layer M2 and the first metal layer M1;

[0396] a second interlayer dielectric layer 17 located between the first metal layer M1 and the first conductive layer D1;

[0397] a first planar layer 18 located between the first conductive layer D1 and the second conductive layer D2;

[0398] The second planarization layer 19 is located between the second conductive layer D2 and the fourth metal layer M4.

[0399] In some examples, at least one of the buffer layer 12, the second gate insulating layer 13, the third interlayer dielectric layer 14, the first gate insulating layer 15, the first interlayer dielectric layer 16, the second interlayer dielectric layer 17, the first planarizing layer 18, and the second planarizing layer 19 can be an inorganic insulating layer, for example, any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) can be used, and can be a single layer, a multilayer, or a composite layer.

[0400] In one possible embodiment, the material of the first active layer C1 includes a rare earth element-doped metal oxide. Specifically, the material of the first active layer C1 is a metal oxide semiconductor material, which may include any one or more of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxide (RE-OS), wherein the rare earth element-doped metal oxide may include lanthanide-doped metal oxide (Ln-OS). The crystal state of the active layer material may be amorphous, partially crystalline, or polycrystalline. In the disclosed embodiment, the material of the first active layer C1 is a rare earth element-doped metal oxide. The first active layer C1 can maintain stable performance even when exposed to light, thereby eliminating the need for a light shielding layer in the light-transmitting region P, further improving the aperture ratio of the display panel. In the embodiment of the present disclosure, the first active layer C1 of the display region transistor may be an oxide active layer. That is, the thin film transistor with an oxide active layer has advantages such as low leakage current.

[0401] In one possible embodiment, the material of the second active layer C2 includes low-temperature polysilicon. Considering the current immaturity of high-transition oxide gate driver circuit design, which results in larger transistors in the gate driver circuit and an excessively large frame, in the disclosed embodiment, the gate driver circuit in the non-display area may utilize low-temperature polysilicon transistors.

[0402] In the embodiment of the present disclosure, the first active layer C1 of the first transistor in the display area can be an oxide active layer, and the second active layer C2 of the second transistor in the non-display area can be a polysilicon active layer. Since oxide thin-film transistors have advantages such as low leakage current, and low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display panel to form a low-temperature polycrystalline oxide display panel. By utilizing the advantages of both, high resolution (Pixel Per Inch, PPI) and low-frequency driving can be achieved, which can reduce power consumption and improve display quality. For example, the array substrate provided in the embodiment of the present disclosure combines the technical effects of high mobility and narrow frame of the second transistor of the second active layer C2 made of polysilicon material, and the display effect of high transmittance of the first transistor of the first active layer C1 made of metal oxide semiconductor material. When the array substrate is used in a display panel, the display effect of virtual reality can be further improved.

[0403] In one possible embodiment, the first active layer C1 and the second active layer C2 may also be the same layer and the same material; specifically, the first active layer C1 and the second active layer C2 may both be oxide active layers. Specifically, for example, the materials of the first active layer C1 and the second active layer C2 may include: amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), or indium zinc tin oxide (IZTO). In the embodiment of the present disclosure, when the active layers of the transistors in the display area and the non-display area are both oxide active layers, the second transistor in the non-display area and the first transistor in the display area can both adopt an oxide dual-gate structure, and the bottom gate size of the second transistor in the non-display area is larger than the top gate size (the single-side wrapping size can be 0.5μm to 2μm), which can effectively improve the on-state current and device stability of the second transistor in the non-display area; for the first transistor in the display area, the bottom gate size can be smaller than the top gate size (the bottom gate is 0.3μm to 0.6μm smaller than the top gate on one side), which can avoid affecting the aperture ratio.

[0404] In a possible embodiment, the material of the first conductive layer D1 may include: metal oxide (eg, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0405] In a possible embodiment, the material of the second conductive layer D2 may include: metal oxide (eg, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0406] In a possible embodiment, the material of the third conductive layer D3 may include: metal oxide (eg, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0407] In one possible embodiment, at least two of the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 are made of the same material. In another possible embodiment, the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 may also be made of different materials.

[0408] In one possible embodiment, the material of at least one of the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may include: any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0409] In one possible embodiment, at least two of the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are made of the same material. In another possible embodiment, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may also be made of different materials.

[0410] In some examples, the substrate 11 may be a flexible substrate or a rigid substrate. For example, the rigid substrate may include a glass substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. The material of the semiconductor layer may be amorphous silicon (a-Si). However, the embodiments of the present disclosure are not limited to this.

[0411] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure and also includes an opposite substrate arranged opposite to the array substrate.

[0412] In a possible implementation, the counter substrate may include a counter substrate, a black matrix located on one side of the counter substrate, and an optical adhesive layer located on a side of the black matrix facing away from the counter substrate.

[0413] In a possible implementation, the display panel further includes: a color filter layer; the color filter layer may be located on the opposite substrate, or the color filter layer may be located on the array substrate.

[0414] FIG24 is a schematic diagram of the structure of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG24 , the display panel may include: a timing controller 20, a data driver 40, a gate drive circuit, and a sub-pixel array 10. The gate drive circuit may include at least one driver, such as a scan driver 30. The timing controller 20, the data driver 40, and the gate drive circuit may be located in a non-display area outside the display area of ​​the display panel. The sub-pixel array 10 located in the display area may include a plurality of sub-pixels PX arranged in a regular pattern. The scan driver 30 may be configured to provide a scan signal to the sub-pixel PX along a scan line; the data driver 40 may be configured to provide a data signal to the sub-pixel PX along a data line; and the timing controller 20 may be configured to control the scan driver 30 and the data driver 40.

[0415] In some examples, the timing controller 20 may provide grayscale values ​​and control signals suitable for the specifications of the data driver 40 to the data driver 40. The timing controller 20 may also provide clock signals, initial signals, and other signals suitable for the specifications of the scan driver 30 to the scan driver 30. The data driver 40 may use the grayscale values ​​and control signals received from the timing controller 20 to generate data voltages to be supplied to the data lines D1 to Dn. For example, the data driver 40 may use the clock signal to sample the grayscale values ​​and apply data signals corresponding to the grayscale values ​​to the data lines D1 to Dn on a sub-pixel row basis. The scan driver 30 may use the clock signal, initial signals, and other signals received from the timing controller 20 to generate scan signals to be supplied to the scan lines G1 to Gm. For example, the scan driver 30 may sequentially supply scan signals having on-level pulses to the scan lines. In some examples, the scan driver 30 may include a shift register that sequentially transmits scan initial signals provided in the form of on-level pulses to the next stage of circuitry under the control of the clock signal to generate the scan signals. Where n and m are both natural numbers.

[0416] In some examples, the gate driver circuit can be directly provided on the substrate. For example, the gate driver can be provided in the peripheral areas on the left and right sides of the display area. In some examples, the gate driver can be formed together with the sub-pixel in the process of forming the sub-pixel. However, this embodiment does not limit the location or formation method of the gate driver. In some examples, the gate driver can be provided on a separate chip or printed circuit board to connect to the pads or pads formed on the substrate.

[0417] In some examples, the data driver 40 can be provided on a separate chip or printed circuit board, and connected to the sub-pixels PX via signal access pins provided on the substrate. For example, the data driver 40 can be provided using a chip on glass, a chip on plastic, a chip on film, etc., and connected to the signal access pins on the substrate. The timing controller 20 can be provided separately from the data driver 40 or integrated with the data driver 40. However, this embodiment is not limited to this.

[0418] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0419] In the embodiment of the present disclosure, the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the minimum spacing i2 between the orthographic projection of the conductive portion D11 and the second sub-metal line MB on the substrate 11, which can increase the lateral capacitance between the first metal line M11 and the conductive portion D11, thereby increasing the second coupling capacitance C dp2 , and due to the first coupling capacitor C dp1 In the embodiment, the overlapped capacitance between the first active pattern C11 and the conductive portion D11 (the area indicated by the thick solid frame S in FIG15D ) accounts for the majority, and the distance between the conductive portion D11 and the second sub-metal line MB is reduced, which does not affect the first coupling capacitor C dp1 This has a significant impact, thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference in vertical crosstalk is reduced.

[0420] It should be noted that in this disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for producing a specific pattern, and then using the same mask through a single patterning process. That is, one patterning process corresponds to one mask (also known as a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0421] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0422] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; The first active layer is located on one side of the substrate and includes: a plurality of first active patterns; the first active patterns include: a first portion and a second portion distributed along a first direction; The first metal layer comprises: a plurality of first metal wires; the second portion overlaps with a portion of the first metal wires projected orthographically on the substrate at a portion of the second portion projected orthographically on the substrate; The second metal layer includes: a plurality of second metal lines extending along a second direction; The first conductive layer comprises: a plurality of conductive parts; the orthographic projection of at least one of the plurality of conductive parts on the substrate is located between the orthographic projections of adjacent first metal lines on the substrate; The second conductive layer includes: a plurality of first electrodes; Among them, the first metal wires adjacent to the two sides of the conductive part include: a first sub-metal wire, and a second sub-metal wire; wherein the first sub-metal wire is electrically connected to the second part; the first part is electrically connected to the first electrode through the conductive part; the distance between the conductive part's orthographic projection on the substrate and the first sub-metal wire's orthographic projection on the substrate is greater than the distance between the conductive part and the second sub-metal wire's orthographic projection on the substrate.

2. The array substrate according to claim 1, wherein: The conductive parts adjacent to the first sub-metal line on both sides include: a first sub-conductive part and a second sub-conductive part; wherein the first sub-metal conductive part is electrically connected to the first sub-metal line through a transistor; The distance between the orthographic projection of the first sub-metal line on the substrate and the orthographic projection of the first sub-conductive portion on the substrate is greater than the distance between the orthographic projection of the first sub-metal line on the substrate and the orthographic projection of the second sub-conductive portion on the substrate.

3. The array substrate according to claim 1 or 2, wherein: The conductive portion includes: a first conductive portion and a second conductive portion distributed along the first direction; the orthographic projection of the first conductive portion on the substrate has an overlapping area with the orthographic projection of the first portion on the substrate, and the orthographic projection of the second conductive portion on the substrate has an overlapping area with the orthographic projection of the second portion; the first conductive portion and the second conductive portion have different extending directions; At least the distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the second sub-metal line on the substrate.

4. The array substrate according to claim 3, wherein: The second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line; The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

5. The array substrate according to claim 4, wherein: The second conductive portion and the first sub-metal line and the second sub-metal line satisfy the following relationship: 0.05μm≤(ab) / 2≤0.15μm; wherein a represents the distance between the orthographic projection of the first outer edge on the substrate 11 and the orthographic projection of the first sub-metal routing on the substrate, and b represents the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

6. The array substrate according to claim 4 or 5, wherein: The first metal line includes: first sub-metal parts and second sub-metal parts arranged alternately along the first direction; the first sub-metal parts and the second sub-metal parts extend in different directions; The first conductive portion extends along an extending direction of the second sub-metal portion, and the second conductive portion extends along the extending direction of the first sub-metal portion.

7. The array substrate according to claim 3, wherein: The second conductive portion has a first outer edge facing the first sub-metal line and a second outer edge facing the second sub-metal line; an extension line of the first outer edge intersects with an extension line of the second outer edge; The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

8. The array substrate according to claim 7, wherein: The first metal line includes: first sub-metal parts and second sub-metal parts arranged alternately along the first direction; the first sub-metal parts and the second sub-metal parts extend in different directions; The first outer edge extends along the first direction; the extending direction of the second outer edge is the same as the extending direction of the first sub-metal portion.

9. The array substrate according to claim 3, wherein: The second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line; The first outer edge includes: a first sub-edge portion and a second sub-edge portion; the second sub-edge portion is located on a side of the first sub-edge portion away from the first conductive portion, and the second sub-edge portion is located on a side of an extension line of the first sub-edge portion toward the first sub-metal wiring; The distance between the orthographic projection of the second sub-edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

10. The array substrate according to claim 9, wherein: The first metal line includes: first sub-metal parts and second sub-metal parts arranged alternately along the first direction; the first sub-metal parts and the second sub-metal parts extend in different directions; The second sub-edge extends along an extending direction of the first sub-metal portion.

11. The array substrate according to claim 10, wherein: The first sub-edge extends along an extension direction of the second sub-metal portion; and the second outer edge extends along the extension direction of the first sub-metal portion.

12. The array substrate according to claim 10, wherein: A first bending portion is provided between the first sub-metal portion and the second sub-metal portion; and a second bending portion is provided at the first outer edge; The orthographic projection of the second bending portion on the substrate is located in a region between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the first connecting line on the substrate, wherein the first metal edge is the outer edge of the second metal wire facing the first conductive portion, and the first connecting line is a connecting line of the first bending portions of two adjacent first metal wires.

13. The array substrate according to claim 12, wherein: The array substrate further comprises: a third metal layer located on the side of the first active layer facing the substrate; the third metal layer comprises: a plurality of third metal wires extending along the second direction; the orthographic projection of the third metal wire on the substrate covers the orthographic projection of the second metal wire on the substrate; The orthographic projection of the second bending portion on the substrate is located in a region between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the second metal edge on the substrate, and the second metal edge is the outer edge of the third metal wire facing the first conductive portion.

14. The array substrate according to claim 9, wherein: The first outer edge has a second bending portion; The orthographic projection of the second bent portion on the substrate overlaps with the orthographic projection of the first metal edge on the substrate, and the first metal edge is the outer edge of the second metal wire facing the first conductive portion.

15. The array substrate according to any one of claims 6, 8, 11-14, wherein: The distance between two ends of the first sub-metal portion in the second direction is equal to the distance between two ends of the second sub-metal portion in the second direction; and the second direction is perpendicular to the first direction.

16. The array substrate according to any one of claims 6, 8, 11-15, wherein: The first conductive portion is located between two adjacent first sub-metal portions in the second direction; the second conductive portion is located between two adjacent second sub-metal portions in the second direction; and an extending direction of the first conductive portion is the same as an extending direction of the first sub-metal portion.

17. The array substrate according to any one of claims 6, 8, 11-15, wherein: The first electrode includes: a first electrode portion and a second electrode portion distributed along the first direction; an extending direction of the first electrode portion is the same as an extending direction of the first sub-metal portion, and an extending direction of the second electrode portion is the same as an extending direction of the second sub-metal portion.

18. The array substrate according to claim 17, wherein: The orthographic projection of the first electrode portion on the substrate has an overlapping area with the orthographic projection of the second conductive portion on the substrate, and the first electrode portion and the second conductive portion are electrically connected at the overlapping position.

19. The array substrate according to any one of claims 5 to 18, wherein: The first conductive portion has a third outer edge facing the first sub-metal line and a fourth outer edge facing the second sub-metal line; the third edge is parallel to the fourth outer edge.

20. The array substrate according to claim 19, wherein: The distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

21. The array substrate according to claim 20, wherein: The distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is equal to the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

22. The array substrate according to any one of claims 19 to 21, wherein: The first outer edge, the second outer edge, and the third outer edge satisfy the following relationship: a>c>b, wherein c represents the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal wiring on the substrate.

23. The array substrate according to any one of claims 1 to 22, wherein: The second conductive portion has a fifth outer edge extending along the second direction, and the fifth outer edge is located at a side of the second metal line away from the first conductive portion.

24. The array substrate according to any one of claims 1 to 23, wherein: The second conductive portion has a fifth outer edge extending along the second direction, and the orthographic projection of the second metal line on the substrate covers the orthographic projection of the fifth outer edge on the substrate.

25. The array substrate according to claim 24, wherein: The second metal line has a sixth outer edge extending along the second direction; The orthographic projection of a portion of the sixth outer edge on the substrate coincides with the orthographic projection of the fifth outer edge on the substrate.

26. The array substrate according to any one of claims 1 to 25, wherein: The second portion includes: a first sub-portion and a second sub-portion; the first sub-portion extends along the second direction, and the orthographic projection of the first sub-portion on the substrate overlaps with the orthographic projection of the first metal line on the substrate; the second sub-portion connects the first sub-portion and the first portion; The plurality of first active patterns include: a first active pattern row and a second active pattern row; the first active pattern row and the second active pattern row extend along a second direction and are arranged overlappingly along the first direction; The first active pattern row and the second active pattern row both include a plurality of first active patterns; and in the first active pattern row, the second sub-portion extends along a third direction; in the second active pattern row, the second sub-portion extends along a fourth direction, and the third direction intersects the fourth direction.

27. The array substrate according to claim 26, wherein: In the first active pattern row, the first sub-portion and the first portion are located on different sides of the second sub-portion; in the second active pattern row, the first sub-portion and the first portion are located on the same side of the second sub-portion.

28. The array substrate according to claim 4, 7 or 9, wherein: The first metal line includes: a first sub-metal portion, a second sub-metal portion, and a third sub-metal portion alternately arranged along the first direction; The second sub-metal portion extends along the first direction; the first sub-metal portion is located on one side of an extension line of the second sub-metal portion, and the third sub-metal portion is located on the other side of the extension line of the second sub-metal portion.

29. The array substrate according to claim 28, wherein: The distance between two ends of the first sub-metal portion in the second direction is equal to the distance between two ends of the third sub-metal portion in the second direction.

30. The array substrate according to claim 28 or 29, wherein: The plurality of first active patterns include: a third active pattern row and a fourth active pattern row; the third active pattern row and the fourth active pattern row extend along the second direction and are arranged overlappingly along the first direction; The third active pattern row and the fourth active pattern row both include a plurality of first active patterns; in the same third active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; in the same fourth active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; between two adjacent first metal lines, the first active pattern of the third active pattern row and the first active pattern of the fourth active pattern row are electrically connected to different first metal lines.

31. The array substrate according to claim 30, wherein: The first portion extends along the first direction, and the second portion is located on one side of an extension line of the first portion; In the third active pattern row, the first portion and the second portion intersect to form an opening of a first angle, and the first sub-metal portion and the second sub-metal portion intersect to form an opening of a second angle are opposite to each other; in the fourth active pattern row, the first portion and the second portion intersect to form an opening of a first angle, and the third sub-metal portion and the next second sub-metal portion in the first direction intersect to form an opening of a third angle.

32. The array substrate according to claim 30, wherein: The first portion extends along the first direction, and the second portion is located on one side of an extension line of the first portion; In the third active pattern row, the opening at the first angle formed by the intersection of the first portion and the second portion and the opening at the second angle formed by the intersection of the first sub-metal portion and the second sub-metal portion are oriented to the same side; in the fourth active pattern row, the opening at the first angle formed by the intersection of the first portion and the second portion and the opening at the third angle formed by the intersection of the third sub-metal portion and the next second sub-metal portion in the first direction are oriented to the same side.

33. The array substrate according to claim 28 or 29, wherein: The plurality of first active patterns include: a plurality of active pattern rows; the active pattern rows include: a plurality of the first active patterns sequentially arranged along the second direction; In the same active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; between two adjacent first metal lines, the first active patterns in the active pattern row are electrically connected to the same first metal line.

34. The array substrate according to any one of claims 28 to 33, wherein: The array substrate comprises: a first via hole, a second via hole, and a third via hole; the first active pattern is electrically connected to the conductive part through the first via hole; the conductive part is electrically connected to the first electrode through the second via hole; the first active pattern is electrically connected to the first metal wire through the third via hole; The second conductive layer includes: a plurality of first electrode rows extending along the second direction and arranged in sequence along the first direction; the first electrode rows include: a plurality of first electrodes arranged in sequence along the first direction; The orthographic projection of the first active pattern electrically connected to the first electrodes in the Mth row through the first via holes and the second via holes on the substrate overlaps with the orthographic projection of the first electrodes in the M-1th row on the substrate.

35. The array substrate according to claim 34, wherein: An extension direction of a portion of the first electrode is the same as an extension direction of the second sub-metal portion; an extension direction of another portion of the first electrode is the same as an extension direction of the third sub-metal portion.

36. The array substrate according to claim 1, wherein: The first metal line extends along a first direction, the first portion extends along the first direction, and the conductive portion extends along the first direction; The distance between the orthographic projection of all the conductive parts on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of all the conductive parts on the substrate and the orthographic projection of the second sub-metal line on the substrate.

37. The array substrate according to any one of claims 1 to 3, wherein: The conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 15%≤i2 / i1≤75%, wherein i1 represents the minimum distance between the orthographic projection of the conductive portion on the substrate and the orthographic projection of the first sub-metal line on the substrate, and i2 represents the minimum distance between the orthographic projection of the conductive portion on the substrate and the orthographic projection of the second sub-metal line on the substrate.

38. The array substrate according to claim 37, wherein: The conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 3%≤(i1-i2) / i3≤15%, wherein i3 represents the minimum distance between adjacent first sub-metal lines and second sub-metal lines.

39. The array substrate according to claim 38, wherein: The conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 60%≤i4 / i3≤95%, wherein i4 represents the length of the conductive portion in a direction perpendicular to the first direction.

40. The array substrate according to any one of claims 1 to 3, wherein: One end of the conductive portion is electrically connected to the first portion, and the other end extends toward the second metal line and exceeds the second metal line to form a protrusion, and the orthographic projection of the protrusion on the substrate overlaps with the orthographic projection of the first active pattern on the substrate.

41. The array substrate according to any one of claims 1 to 40, wherein: The first conductive layer is located on a side of the first active layer away from the substrate; The first electrode is located on a side of the first conductive layer facing away from the substrate; The array substrate further includes: a first insulating layer located between the first active layer and the first conductive layer, and a first via hole penetrating the first insulating layer, wherein the conductive portion is electrically connected to the first portion through the first via hole; The array substrate further includes: a second insulating layer located between the first conductive layer and the first electrode, and a second via hole penetrating the second insulating layer; the first electrode is electrically connected to the conductive portion through the second via hole; In a direction perpendicular to the first direction, at least two adjacent second via holes are an integrated connected structure.

42. The array substrate according to claim 41, wherein: The second via hole has two side walls extending perpendicular to the first direction; at least one of the side walls has a protruding structure, and the orthographic projection of the protruding structure on the substrate is located in a region between the orthographic projections of two adjacent first electrodes on the substrate in the second direction.

43. The array substrate according to claim 41 or 42, wherein: The array substrate further includes: a color resist layer located between the second insulating layer and the second conductive layer; the color resist layer includes: a plurality of color resist portions; an orthographic projection of at least part of the color resist portions on the substrate overlaps with an orthographic projection of the first metal line on the substrate.

44. The array substrate according to any one of claims 1 to 43, wherein: The array substrate has a display area and a non-display area located outside the display area; further comprising: a second active layer located on a side of the first active layer facing the substrate, a driving source and drain located on a side of the second active layer away from the substrate, and a driving gate located in the non-display area; The second active layer is located between the third metal layer and the substrate; The driving gate is located at the third metal layer; The driving source and drain are located in the first metal layer; The second active layer is located between the third metal layer and the first active layer; The driving source and drain are located in the second metal layer; The driving gate is located at the third metal layer; The material of the first active layer includes: metal oxide; the material of the second active layer includes: low temperature polysilicon.

45. A display panel, wherein: Comprising an array substrate as described in any one of claims 1-44.

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