On-chip opto-electronic interconnection structure and semiconductor chip

Abstract

Disclosed in the present utility model are an on-chip opto-electronic interconnection structure and a semiconductor chip. In the on-chip opto-electronic interconnection structure, an optical signal layer is vertically connected to an electrical signal layer by means of an opto-electronic interconnection layer, and the transmission of an electrical signal is directly connected to the optical signal layer along a shortest or second shortest path by means of the opto-electronic interconnection layer. The present utility model has the advantages that: the power loss of an electrical signal can be reduced, thereby ensuring the quality of the electrical signal; and it is not necessary to introduce a digital signal processing module in a traditional opto-electronic interconnection chip, thereby reducing the overall design difficulty of the semiconductor chip.

Description

On-chip optoelectronic interconnection structure, semiconductor chip Technical Field

[0001] The utility model belongs to the field of semiconductor chip interconnection architecture, and in particular relates to an on-chip photoelectric interconnection structure and a semiconductor chip. Background Art

[0002] With the advancement of technology, integrated circuits are entering the angstrom era, forcing quantum effects to be factored into chip design, significantly extending R&D cycles. To overcome this weakness, three-dimensional stacked integration has been continuously developed over the past few decades. By introducing the concept of grains, silicon bridge structures enable monolithic integration of multiple chips, transforming "board-to-board" connections between chips into connections within the chip itself.

[0003] The concept of integrated optics is based on the use of micro- and nano-etching techniques to form specific optical waveguide structures on planar substrates. Based on this concept, researchers have already achieved integrated active and passive optoelectronic platforms using silicon (Si) as the waveguide material. Waveguide structures can also be constructed using other Group IV or compound semiconductors, doped semiconductor oxynitrides, optical crystal films, or doped bulk crystals.

[0004] Optical interconnection is a technology that uses various optical transmission media to connect components or subsystems within a computer system and transmit information at high speed via light. It can achieve optical interconnection at different levels, such as between computers, circuit boards, and chips. As an information carrier, light has the advantages of independent propagation, contactless connection, and extremely high space-time bandwidth product. Currently, the most advanced on-chip optical interconnection systems still use a hybrid optoelectronic flow-out approach, forming the optical and electrical signal layers simultaneously on a single silicon wafer through advanced photolithography processes. This means that when the electrical signal layer is transmitted to the optical signal layer, it still needs to pass through the top copper wire interconnect layer. Therefore, the signal compensation and clock recovery required to deal with signal attenuation and distortion must be considered, which greatly increases the complexity of the entire chip layout design.

[0005] Utility Model Content

[0006] The purpose of the present utility model is to address the deficiencies of the existing technology and provide an on-chip optoelectronic interconnection structure and a semiconductor chip. In the on-chip optoelectronic interconnection structure, the optical signal layer and the electrical signal layer are vertically connected through the optoelectronic interconnection layer, which can improve the integration of the overall optoelectronic interconnection chip, reduce the power loss of the electrical signal, and reduce the difficulty of optoelectronic chip design.

[0007] The purpose of the utility model is achieved through the following technical solutions: an on-chip optoelectronic interconnection structure, comprising an optical signal layer, an electrical signal layer and an optoelectronic interconnection layer, wherein the optical signal layer and the electrical signal layer are vertically connected through the optoelectronic interconnection layer;

[0008] The optical signal layer comprises a first isolation layer, a second isolation layer and a third isolation layer, wherein the first isolation layer is embedded with an optical signal processing layer, and the second isolation layer is embedded with an optical signal transmission layer and an electrical signal printing layer;

[0009] The electrical signal layer comprises an electrical signal interconnection layer, an electrical signal active layer, an electrical signal substrate layer and a fourth isolation layer, wherein the fourth isolation layer has bonding contacts embedded therein;

[0010] The second isolation layer, the third isolation layer and the fourth isolation layer are all provided with a through-hole structure, and the through-hole structure is used to connect the electrical signal printing layer and the bonding contact, or connect the optical signal processing layer, the electrical signal printing layer and the bonding contact, or connect the optical signal processing layer and the bonding contact.

[0011] Furthermore, the optical signal is introduced into the optical signal layer from an external light source through the light source port.

[0012] Furthermore, electrical signals are exchanged and communicated between the optical signal layer and the electrical signal layer through the optoelectronic interconnection layer.

[0013] Furthermore, the electrical signal imprinting layer and the optical signal transmission layer are located on the same horizontal plane.

[0014] Furthermore, the third isolation layer has bonding contacts embedded in the layer with the bonding contacts exposed on the surface, and the through-hole structures in the layer are connected to the electrical signal layer through the bonding contacts.

[0015] Furthermore, a surface of the bonding contact in the fourth isolation layer is exposed and connected to the bonding contact in the third isolation layer.

[0016] Furthermore, the optical signal layer and the electrical signal layer are respectively derived from independent semiconductor wafer substrates.

[0017] The utility model also discloses a semiconductor chip realized by the on-chip photoelectric interconnection structure.

[0018] The beneficial effect of this utility model is that the electrical signal is transmitted directly through the optoelectronic interconnect layer along the shortest or second-shortest path to the optical signal layer, greatly avoiding voltage drop loss and waveform distortion during voltage signal transmission. After amplification, the electrical signal can be directly applied to the optical signal layer without the need for waveform pre-shaping through digital signal processing, greatly expanding the bandwidth between the electrical and optical channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG1 is an overall schematic diagram of an on-chip optoelectronic interconnection structure provided by the present disclosure;

[0020] FIG2 is a schematic diagram of an on-chip optoelectronic interconnection structure according to an embodiment of the present disclosure;

[0021] FIG3 is a schematic diagram of an on-chip optoelectronic interconnection structure according to another embodiment of the present disclosure;

[0022] In the figure, 100 is the optical signal layer, 101 is the optoelectronic interconnection layer, 102 is the electrical signal layer, 103 is the light source port, 104 is the external light source, 200a is the first isolation layer, 200b is the second isolation layer, 200c is the third isolation layer, 200d is the fourth isolation layer, 201 is the optical signal processing layer, 202 is the optical signal transmission layer, 203 is the electrical signal printing layer, 204 is the first through-hole structure, 205a is the first bonding contact, 205b is the second bonding contact, 206 is the second through-hole structure, 207 is the electrical signal interconnection layer, 208 is the electrical signal active layer, and 209 is the electrical signal substrate layer. DETAILED DESCRIPTION

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0025] For clarity, the following description of embodiments of the present invention and related structures primarily features a single interconnect structure formed on a semiconductor substrate. However, for efficiency reasons, various embodiments can be implemented at the wafer level to form thousands of interconnect structures across hundreds of semiconductor dies residing on a wafer.

[0026] In terms of overall structure, the on-chip optoelectronic interconnection structure disclosed in the present invention includes an optical signal layer 100, an electrical signal layer 102, and an optoelectronic interconnection layer 101. The optical signal layer 100 and the electrical signal layer 102 are vertically connected through the optoelectronic interconnection layer 101, wherein the optical signal layer 100 is only responsible for the transmission of optical signals and the printing of electrical signals, and the electrical signal layer 102 is only responsible for the processing of electrical signals. The optical signal layer 100 and the electrical signal layer 102 are respectively derived from two independent semiconductor wafer substrates. The optical signal is introduced into the optical signal layer 100 by an external light source 104 through the light source port 103, and the electrical signal is exchanged and connected between the optical signal layer 100 and the electrical signal layer 102 through the optoelectronic interconnection layer 101.

[0027] In the first embodiment of the present invention, an on-chip optoelectronic interconnect structure is disclosed. In this structure, the optical signal layer 100 includes a first isolation layer 200a, a second isolation layer 200b, and a third isolation layer 200c. The first isolation layer 200a includes an optical signal processing layer 201 embedded within it, responsible for photoelectric signal conversion and impedance matching. The second isolation layer 200b includes an optical signal transmission layer 202 and an electrical signal imprinting layer 203 embedded within it. The optical signal transmission layer 202 is responsible for optical signal propagation, while the electrical signal imprinting layer 203 and the optical signal transmission layer 202 are fabricated on the same horizontal plane and are responsible for applying electrical signals. The third isolation layer 200c includes a first bonding contact 205a embedded within it, with the first bonding contact 205a exposed on its surface. A first through-hole structure 204 is provided in the second isolation layer 200b and the third isolation layer 200c, which is used to connect the electrical signal printing layer 203 and the first bonding contact 205a, or to connect the optical signal processing layer 201, the electrical signal printing layer 203 and the first bonding contact 205a, or to connect the optical signal processing layer 201 and the first bonding contact 205a.

[0028] On the other side, the electrical signal layer 102 includes an electrical signal interconnect layer 207, an electrical signal active layer 208, and an electrical signal substrate layer 209. A fourth isolation layer 200d is formed above the electrical signal interconnect layer 207. A second bonding contact 205b is embedded in the fourth isolation layer 200d, with the second bonding contact 205b exposed on the surface. A second through-hole structure 206 is provided in the fourth isolation layer 200d, connecting the electrical signal interconnect layer 207 and the second bonding contact 205b. Once formed, the second bonding contact 205b connects to the first bonding contact 205a, forming the optoelectronic interconnect layer 101, enabling short-distance signal transmission between the optical signal layer 100 and the electrical signal layer 102.

[0029] Another variation of this embodiment may take the following structure:

[0030] A first through-hole structure 204 is provided in the second isolation layer 200b and the third isolation layer 200c, which is used to connect the electrical signal printing layer 203 and the second bonding contact 205b, or to connect the optical signal processing layer 201, the electrical signal printing layer 203 and the second bonding contact 205b, or to connect the optical signal processing layer 201 and the second bonding contact 205b.

[0031] On the other side, the electrical signal layer 102 includes an electrical signal interconnect layer 207, an electrical signal active layer 208, and an electrical signal substrate layer 209. A fourth isolation layer 200d is formed above the electrical signal interconnect layer 207. A second bonding contact 205b is embedded in the fourth isolation layer 200d, with the second bonding contact 205b exposed on the surface. A second through-hole structure 206 is provided in the fourth isolation layer 200d, connecting the electrical signal interconnect layer 207 and the second bonding contact 205b. Once formed, the second bonding contact 205b connects to the first through-hole structure 204, forming the optoelectronic interconnect layer 101, enabling short-distance signal transmission between the optical signal layer 100 and the electrical signal layer 102.

[0032] It should be noted that the difference between this deformed structure and the aforementioned first embodiment is that the optical signal layer 100 and the electrical signal layer 102 in the first embodiment should be directly connected by wafer or chip bonding, while in this deformed structure, the optical signal layer 100 and the electrical signal layer 102 are first bonded together and then connected by forming a first through-hole structure 204.

[0033] In a second embodiment of the present invention, an on-chip optoelectronic interconnect structure is disclosed. In this structure, the optical signal layer 100 includes a first isolation layer 200a, a second isolation layer 200b, and a third isolation layer 200c. The first isolation layer 200a includes an optical signal processing layer 201 embedded within it, responsible for photoelectric signal conversion and impedance matching. The second isolation layer 200b includes an optical signal transmission layer 202 and an electrical signal imprinting layer 203 embedded within it. The optical signal transmission layer 202 is responsible for optical signal propagation, while the electrical signal imprinting layer 203 and the optical signal transmission layer 202 are fabricated on the same horizontal plane and are responsible for applying electrical signals. A first through-hole structure 204 is provided in the second isolation layer 200b and the third isolation layer 200c.

[0034] On the other side, the electrical signal layer 102 includes an electrical signal interconnect layer 207, an electrical signal active layer 208, and an electrical signal substrate layer 209. A fourth isolation layer 200d is formed on the electrical signal interconnect layer 207. The fourth isolation layer 200d has a second bonding contact 205b embedded therein. A second through-hole structure 206 is also provided in the fourth isolation layer 200d.

[0035] First via structure 204 is used to connect electrical signal inlay layer 203 and second bonding contact 205b, or to connect optical signal processing layer 201, electrical signal inlay layer 203 and second bonding contact 205b, or to connect optical signal processing layer 201 and second bonding contact 205b. Second via structure 206 is used to connect electrical signal interconnect layer 207 and second bonding contact 205b. The contact portion between first via structure 204 and second bonding contact 205b forms optoelectronic interconnect layer 101, enabling short-distance signal transmission between optical signal layer 100 and electrical signal layer 102.

[0036] The above description is only a preferred embodiment of the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. An on-chip optoelectronic interconnection structure, comprising an optical signal layer, an electrical signal layer and an optoelectronic interconnection layer, characterized in that: The optical signal layer is vertically connected to the electrical signal layer via an optoelectronic interconnection layer; The optical signal layer comprises a first isolation layer, a second isolation layer and a third isolation layer, the first isolation layer has an optical signal processing layer embedded therein, and the second isolation layer has an optical signal transmission layer and an electrical signal printing layer embedded therein; The electrical signal layer comprises an electrical signal interconnection layer, an electrical signal active layer, an electrical signal substrate layer and a fourth isolation layer, wherein the fourth isolation layer has a bonding contact embedded therein; The second isolation layer, the third isolation layer and the fourth isolation layer are all provided with a through-hole structure, and the through-hole structure is used to connect the electrical signal printing layer and the bonding contact, or to connect the optical signal processing layer, the electrical signal printing layer and the bonding contact, or to connect the optical signal processing layer and the bonding contact.

2. The on-chip optoelectronic interconnection structure according to claim 1, characterized in that: The optical signal is introduced into the optical signal layer from an external light source through the light source port.

3. The on-chip optoelectronic interconnection structure according to claim 1, characterized in that: The electrical signals are exchanged and communicated between the optical signal layer and the electrical signal layer through the optoelectronic interconnection layer.

4. The on-chip optoelectronic interconnection structure according to claim 1, characterized in that: The electrical signal imprinting layer and the optical signal transmission layer are located at the same horizontal plane.

5. The on-chip optoelectronic interconnection structure according to claim 1, characterized in that: The third isolation layer has a bonding contact embedded in the layer with the bonding contact exposed on the surface, and the through-hole structure in the layer is connected to the electrical signal layer through the bonding contact.

6. The on-chip optoelectronic interconnection structure according to claim 5, characterized in that: The surface of the bonding contact in the fourth isolation layer is exposed and connected to the bonding contact in the third isolation layer.

7. The on-chip optoelectronic interconnection structure according to claim 1, characterized in that: The optical signal layer and the electrical signal layer come from independent semiconductor wafer substrates respectively.

8. A semiconductor chip, characterized in that: The invention comprises an on-chip optoelectronic interconnection structure as claimed in any one of claims 1 to 7.

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