Semiconductor device

Abstract

Provided is a semiconductor device which has a novel configuration. This semiconductor device includes a memory cell, a first sense amplifier, a product-sum operation circuit, and a second sense amplifier. The first sense amplifier, the second sense amplifier, and the product-sum operation circuit are provided in a first element layer. The memory cell is provided in a second element layer. The second element layer is provided in a layer above the first element layer. The memory cell is electrically connected to the first sense amplifier and the product-sum operation circuit with a first bit line interposed therebetween. The second sense amplifier is electrically connected to the first sense amplifier and the product-sum operation circuit via a second bit line. The first sense amplifier has a function of outputting first data held in the memory cell to the product-sum operation circuit and the second sense amplifier in accordance with a column selection signal. The product-sum operation circuit has a function of executing a product-sum operation of the first data and the second data supplied from the second sense amplifier over the second bit line in accordance with the column selection signal.

Description

Semiconductor Devices

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, efforts to combat global warming have become increasingly important. Energy consumption continues to increase, and carbon dioxide emissions, one of the causes of global warming, have yet to be reduced. Simply reducing energy consumption may actually result in a loss of convenience. To reduce energy consumption without sacrificing convenience, low-power consumption technologies are becoming extremely important.

[0004] In AI (Artificial Intelligence) technology, power consumption increases as performance improves, and technological development for reducing power consumption is being actively pursued. In AI technology, the following operations are repeated: sequentially reading data stored in a memory circuit, performing an operation using the data in an arithmetic circuit, and storing the data obtained by the operation in a memory. Therefore, the power consumption required for data transmission between the memory circuit and the arithmetic circuit becomes dominant. As a countermeasure, a technology known as in-memory computing or near-memory computing has been proposed (e.g., Patent Document 1), in which a memory circuit and an arithmetic circuit are integrated using a transistor including an oxide semiconductor (also referred to as an OS transistor).

[0005] US Patent Publication No. 2021 / 0024083

[0006] When transmitting data between a memory circuit and an arithmetic circuit, a sense amplifier is required to read the data stored in the arithmetic circuit. Therefore, in order to integrate the memory circuit and the arithmetic circuit and reduce the power consumption required for data transmission, it is effective to arrange the memory circuit and the sense amplifier, and the sense amplifier and the arithmetic circuit, in close proximity. The memory circuit can be arranged in close proximity by placing it directly above the sense amplifier. The arithmetic circuit can also be arranged in close proximity by arranging it alternately with the sense amplifier.

[0007] A sense amplifier requires a signal to control the sense amplifier. Also, an arithmetic circuit requires a signal to control the arithmetic circuit. In other words, a control circuit to control the sense amplifier and a control circuit to control the arithmetic circuit are required. This increases the circuit area. Furthermore, if separate signals are supplied to the sense amplifier and the arithmetic circuit, wiring is required to supply these signals. This increases the circuit area. Furthermore, an increase in the number of wirings and circuit area may increase power consumption and reduce the arithmetic processing speed.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with improved arithmetic processing speed.An object of one embodiment of the present invention is to provide a miniaturized semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure.

[0009] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc.

[0010] One embodiment of the present invention is a semiconductor device including a memory cell, a first sense amplifier, a product-sum operation circuit, and a second sense amplifier, wherein the first sense amplifier, the second sense amplifier, and the product-sum operation circuit are provided in a first element layer, the memory cell is provided in a second element layer, and the second element layer is provided in an upper layer of the first element layer, the memory cell is electrically connected to the first sense amplifier and the product-sum operation circuit via a first bit line, and the second sense amplifier is electrically connected to the first sense amplifier and the product-sum operation circuit via a second bit line, the first sense amplifier has a function of outputting first data held in the memory cell to the product-sum operation circuit and the second sense amplifier in response to a column selection signal, and the product-sum operation circuit has a function of performing a product-sum operation on the first data and second data supplied from the second sense amplifier via the second bit line in response to the column selection signal.

[0011] In one embodiment of the present invention, the semiconductor device preferably includes a memory cell including a first transistor, and the first transistor includes a first semiconductor layer including an oxide semiconductor in a channel formation region.

[0012] In one embodiment of the present invention, the first semiconductor layer preferably has a fin-like shape.

[0013] In one aspect of the present invention, the semiconductor device preferably has a portion where the first bit line is provided parallel to a direction perpendicular to the substrate surface on which the first element layer is provided, between the memory cell and the first sense amplifier, and between the memory cell and the sum-of-products operation circuit.

[0014] In one aspect of the present invention, the semiconductor device preferably includes a second transistor, and the second transistor includes a second semiconductor layer having silicon in a channel formation region.

[0015] In one aspect of the present invention, a semiconductor device is preferably provided which has a column line side driving circuit which outputs a column selection signal, the column line side driving circuit being electrically connected to a column line which supplies the column selection signal, and the column line being alternately connected to a first sense amplifier and a product-sum calculation circuit in the direction in which the column line extends.

[0016] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0017] According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with improved processing speed can be provided. Alternatively, according to one embodiment of the present invention, a miniaturized semiconductor device can be provided. Alternatively, a semiconductor device with a novel structure can be provided.

[0018] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification.

[0019] FIGS. 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 2A to 2C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 3A and 3B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 4A and 4B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 5A to 5C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 6A to 6G are diagrams illustrating a configuration example of a semiconductor device. FIGS. 7A to 7C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 8A to 8C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 9A and 9B are diagrams illustrating a configuration example of a semiconductor device. FIG. 10 is a diagram illustrating a configuration example of a semiconductor device. FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. FIG. 12 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 13A is a diagram illustrating a configuration example of a transistor included in a semiconductor device. FIG. 13B is a diagram illustrating an equivalent circuit of a memory cell. FIGS. 14A to 14C are cross-sectional views illustrating a configuration example of a transistor included in a semiconductor device. FIG. 15A is a plan view illustrating a configuration example of a transistor included in a semiconductor device. 15B to 15D are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 16A is a plan view illustrating an example of the configuration of a transistor included in a semiconductor device. FIGS. 16B to 16D are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 17 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 18A is a diagram illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 18B is a diagram illustrating an equivalent circuit of a memory cell. FIGS. 19A and 19B are plan views illustrating an example of the configuration of a transistor included in a semiconductor device, and FIG. 19C is a cross-sectional view illustrating an example of the configuration of a transistor included in a semiconductor device. FIGS. 20A and 20B are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 21 is a cross-sectional view illustrating an example of the configuration of a transistor included in a semiconductor device. FIGS. 22A and 22B are schematic diagrams illustrating an example of the configuration of a transistor included in a semiconductor device.23A and 23B are plan views illustrating configuration examples of transistors included in a semiconductor device, and FIGS. 23C and 23D are cross-sectional views illustrating configuration examples of transistors included in a semiconductor device. FIGS. 24A to 24D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 25A to 25D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 26A and 26B are diagrams illustrating an example of an electronic component. FIGS. 27A to 27D are diagrams illustrating an example of an electronic component. FIGS. 28A and 28B are diagrams illustrating an example of an electronic device. FIGS. 29A to 29C are diagrams illustrating an example of an electronic device. FIG. 30 is a diagram illustrating an example of a mainframe computer.

[0020] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0021] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0022] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0023] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0024] Furthermore, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "[n]", or "[m, n]" may be added to the reference numeral. For example, the second wiring GL is described as wiring GL[2].

[0025] Embodiment 1 A structure, operation, and the like of a semiconductor device that is one embodiment of the present invention will be described.

[0026] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0027] 1A is a schematic diagram illustrating a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 functions as an accelerator that executes a program (also referred to as a kernel or a kernel program) called from a host program. The semiconductor device 100 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0028] The semiconductor device 100 has an element layer 10 and an element layer 40 stacked on the element layer 10. In the schematic diagram shown in Fig. 1A, the element layers 10 and 40 are shown separated from each other to make it easier to understand the arrangement of the elements that make up the semiconductor device 100. The element layer is a layer in which semiconductor elements such as transistors or capacitors are provided.

[0029] The element layer 10 includes a functional circuit section 11 in which a plurality of global sense amplifier sections 20 and product-sum operation circuit sections 30 are arranged in close proximity, as well as a data sense amplifier section 12, a global sense amplifier drive circuit 13, a column line side drive circuit 14, and a word line side drive circuit 15. The global sense amplifier section 20 may be referred to as a first sense amplifier section, and the data sense amplifier section 12 may be referred to as a second sense amplifier section. The product-sum operation circuit section 30 may be referred to as an operation circuit section.

[0030] 1A, in order to explain the arrangement of each component, the Z-axis direction is defined as a direction perpendicular or approximately perpendicular to the surface of the element layer 10 (e.g., a surface on which an interlayer insulating layer is provided). For ease of understanding, the Z-axis direction may be referred to as a direction perpendicular to the surface of the element layer 10 in the specification. Note that "approximately perpendicular" refers to a state in which the elements are arranged at an angle of 85° to 95°.

[0031] In this specification and drawings, the X direction, Y direction, and Z direction may be defined to explain the arrangement of each element. For example, in the schematic diagram shown in FIG. 1A, the X direction, Y direction, and Z direction are defined to explain the arrangement of each element constituting the semiconductor device 100. The X direction, Y direction, and Z direction are perpendicular or approximately perpendicular to each other.

[0032] The element layer 10 has a transistor having silicon (Si transistor) in a semiconductor layer having a channel formation region. The element layer 10 is an element layer in which a semiconductor layer having a channel formation region is provided in a silicon substrate, or an element layer in which a silicon semiconductor layer having a channel formation region is bonded to a silicon substrate.

[0033] Although the substrate provided in the element layer 10 is described as a silicon substrate, this embodiment is not limited to this. The silicon substrate refers to a substrate using silicon as a semiconductor material, for example, a single-crystal silicon substrate. The substrate is not limited to silicon, and may be made of materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), and GaAlAs (gallium aluminum arsenide).

[0034] The Si transistors in the element layer 10 are made of highly crystalline silicon, such as monocrystalline silicon or polycrystalline silicon. The highly crystalline silicon in the element layer 10 allows for high field-effect mobility and faster operation. Therefore, the element layer 10 can be provided with an integrated global sense amplifier section 20, a product-sum operation circuit section 30, a data sense amplifier section 12, a global sense amplifier driver circuit 13, a column line driver circuit 14, and a word line driver circuit 15.

[0035] The element layer 40 has a memory cell array 42 having a plurality of memory cells 41. The memory cell array 42 functions as a memory circuit unit that stores data used in the product-sum operation circuit unit 30. The memory cells 41 function as memory circuits that store data. The data stored (stored) in the memory cells 41 is data (weight data) corresponding to weight parameters used in the product-sum operation of the neural network. By using digital data for the weight data, a semiconductor device that is resistant to noise and capable of high-speed operation can be obtained. The weight data may also be analog data.

[0036] The weight data may be configured to perform arithmetic processing using 1-bit data (i.e., data of '1' or '0'), or may be configured to perform arithmetic processing using multi-bit data. In the case of multi-bit (e.g., n-bit) data, the weight data may be supplied using a number of wires corresponding to the number of bits.

[0037] The element layer 40 includes a transistor including an oxide semiconductor (OS transistor) in a semiconductor layer having a channel formation region. The element layer 40 including the OS transistor can be stacked over the element layer 10. By providing the element layer 40 over the element layer 10, the transistor density per unit area can be increased.

[0038] Examples of metal oxides used in OS transistors include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide). Furthermore, an In—Zn oxide can be used as the metal oxide used in an OS transistor. The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0039] FIG. 1B is a block diagram for explaining the global sense amplifier section 20 and the product-sum operation circuit section 30 included in the semiconductor device 100. As shown in FIG.

[0040] In the functional circuit unit 11, a plurality of global sense amplifier units 20 and a plurality of product-sum operation circuit units 30 are arranged side by side in the column direction (Y direction in the drawing). The global sense amplifier unit 20 has a plurality of global sense amplifiers GSA. The product-sum operation circuit unit 30 has a plurality of product-sum operation circuits MAC. The global sense amplifiers GSA may be referred to as first sense amplifiers. The product-sum operation circuits MAC may be referred to as operation circuits.

[0041] The data sense amplifier section 12 has a plurality of data sense amplifiers DSA. The data sense amplifiers DSA receive input write data W ＤＡＴＡ The data sense amplifier DSA amplifies the potential difference between the data bit line DBL (DBL_1 and DBL_2 are exemplified in the drawing) and the inverted data bit line DBLB (not shown) in accordance with the read data R. ＤＡＴＡ The data sense amplifier DSA is sometimes called a second sense amplifier.

[0042] The data bit line DBL and the inverted data bit line DBLB may be referred to as a data bit line pair DBL-DBLB. As shown in FIG. 1B, the data bit line DBL may be illustrated, and the inverted data bit line DBLB may be omitted. The data bit line DBL may be referred to as a second bit line.

[0043] The data bit line pair DBL-DBLB is a wiring for bidirectionally inputting and outputting data between the data sense amplifier DSA and the global sense amplifier GSA. The data bit line pair DBL-DBLB is also a wiring for inputting data from the data sense amplifier DSA to the product-sum calculation circuit MAC and outputting the resulting product-sum calculation data to the data sense amplifier DSA. Note that if the data inputted and outputted by the data bit line pair DBL-DBLB is multi-bit, multiple wirings are required.

[0044] The column line side driver circuit 14 supplies a column selection signal CSE to the global sense amplifier GSA and the product-sum operation circuit MAC via the column line CSEL. The column selection signal CSE is a signal that, for example, turns on a transistor functioning as a switch (selected state or selected) when it is at H level and turns off the transistor when it is at L level. The column line CSEL is connected to the column line side driver circuit 14. The column line CSEL is alternately connected to the global sense amplifier GSA of the global sense amplifier unit 20 and the product-sum operation circuit MAC of the product-sum operation circuit unit 30 in the direction in which the column line CSEL extends (Y direction).

[0045] The global sense amplifier drive circuit 13 outputs a sense amplifier control signal SAEN for the global sense amplifier GSA. The word line side drive circuit 15 outputs a word line selection signal for driving the word line WL connected to the memory cell 41. The global sense amplifier drive circuit 13 may also be referred to as a sense amplifier drive circuit.

[0046] The global sense amplifier GSA is connected to the memory cell 41 via a bit line BL and an inverted bit line BLB arranged in the Z direction. The global sense amplifier GSA is arranged close to the product-sum calculation circuit MAC and connected to the product-sum calculation circuit MAC. The global sense amplifier GSA is controlled by a sense amplifier control circuit SAEN and a column selection signal CSE.

[0047] The global sense amplifier GSA is a signal for bidirectionally inputting and outputting data between the global sense amplifier GSA of the selected column and the data sense amplifier DSA in response to the column selection signal CSE. Specifically, in response to the column selection signal CSE, the global sense amplifier GSA outputs data held in the memory cell 41 to the data sense amplifier DSA. In addition, in response to the column selection signal CSE, the data sense amplifier DSA outputs the write data W ＤＡＴＡ is output to the global sense amplifier GSA.

[0048] The bit line BL and the inverted bit line BLB may be referred to as a bit line pair BL-BLB. The bit line BL may be illustrated, and the inverted bit line BLB may be omitted. The global sense amplifier GSA may be referred to as a first sense amplifier. The bit line BL may be referred to as a first bit line.

[0049] The product-sum calculation circuit MAC is a circuit that performs product-sum calculation processing on input data input via the data bit line DBL and weight data held in the memory cell 41. The product-sum calculation circuit MAC is connected to the memory cell 41 via a bit line pair BL-BLB provided in the Z direction (a direction parallel to the direction perpendicular to the substrate surface). The product-sum calculation circuit MAC is disposed adjacent to the global sense amplifier GSA and is connected to the global sense amplifier GSA. The product-sum calculation circuit MAC is controlled by a column selection signal CSE.

[0050] The column selection signal CSE supplied to the product-sum operation circuit MAC is a selection signal for selectively supplying the data held in the memory cells 41 read by the global sense amplifier GSA to the product-sum operation circuit MAC. Specifically, the column selection signal CSE causes the selected global sense amplifier GSA to output the data held in the memory cells 41 connected to that global sense amplifier GSA to the product-sum operation circuit MAC. The column selection signal CSE supplied to the product-sum operation circuit MAC is a control signal for performing product-sum operation processing. For example, it can function as a clock signal for performing product-sum operation processing, a control signal for performing quantization processing, an output control signal for product-sum operation data obtained by product-sum operation processing, and a reset signal for a register holding the product-sum operation data.

[0051] A semiconductor device according to one embodiment of the present invention has a configuration in which a large number of global sense amplifiers GSA and multiply-accumulate circuits MAC are arranged directly under memory cells 41, and a column select signal CSE of the global sense amplifiers GSA is used as a control signal for the multiply-accumulate circuits MAC. This allows the memory cells 41, the global sense amplifiers GSA, and the multiply-accumulate circuits MAC to be arranged in close proximity. This makes it possible to realize near-memory computing and reduce the power consumption required for data transmission between the memory circuits and the arithmetic circuits.

[0052] Furthermore, in the semiconductor device according to one aspect of the present invention, signals for controlling the product-sum calculation circuits MAC can be output from the column line side driver circuit 14 for controlling the global sense amplifier GSA, thereby reducing the number of driver circuits for driving the product-sum calculation circuits MAC. In addition, the column lines CSEL for transmitting column control signals can be used as wiring for supplying control signals to the product-sum calculation circuits MAC, thereby reducing the number of wirings for transmitting control signals for driving the product-sum calculation circuits MAC. Therefore, the semiconductor device according to one aspect of the present invention can achieve miniaturization, reduced power consumption, and improved arithmetic processing speed by suppressing an increase in circuit area.

[0053] 2A is a schematic diagram illustrating an example configuration of a memory cell 41, a product-sum operation circuit MAC, and a global sense amplifier GSA. Fig. 2A illustrates a configuration in which an element layer 40 having memory cells 41 is provided above an area in which the product-sum operation circuit MAC, global sense amplifiers GSA (GSA_1 to GSA_28), column lines CSEL_1 to CSEL_31, and data bit line pairs DBL_1, DBLB_1, DBL_2, and DBLB_2 described in Fig. 1B are provided. For improved visibility, Fig. 2A omits the memory cells 41 on the global sense amplifiers GSA_1 to GSA_28. The memory cells 41 are connected to the product-sum operation circuit MAC and the global sense amplifier GSA via bit line pairs BL-BLB.

[0054] FIG. 2A shows an example of a configuration for performing a multiply-and-accumulate operation on 8-bit input data (A) and 8-bit weight data (W), as well as a multiply-and-accumulate operation on bias data. As an example, the weight data W is assumed to perform 3×3, or 27, types of filter processing. The bias data is configured to add one type of bias value. In this case, the weight data and bias data are output from eight bit line pairs, so 27+1 (28) global sense amplifiers GSA are required to output the data necessary for the filter processing and the addition of the bias data. FIG. 2A illustrates global sense amplifiers GSA_1 to GSA_28. For 8-bit weight data, the global sense amplifier GSA_1 corresponds to eight bit lines BL[0] to BL[7]. Since the eight bit lines BL, BL[0] to BL[7], form 8-bit weight data, 28×8 (224) bit line pairs BL-BLB are provided for the global sense amplifiers GSA_1 to GSA_28.

[0055] The data bit line pair DBL-DBLB that transmits 8-bit input data (A) also consists of eight data bit lines DBL[0] to DBL[7].

[0056] Note that one embodiment of the present invention is not limited to the above-mentioned examples of the number of bits, the number of filters, or the number of wirings. Furthermore, although a configuration for performing product-sum calculation processing will be described, the present invention is not limited to this, and a configuration for performing other calculation processing may also be used.

[0057] 2A, the column lines CSEL_1 to CSEL_28 transmit column selection signals CSE_1 to CSE_28 to the global sense amplifiers GSA_1 to GSA_28. The column selection signals CSE_1 to CSE_28 enable bidirectional input and output of data between the global sense amplifiers GSA_1 to GSA_28 of the selected column and the data sense amplifier DSA_1 (not shown).

[0058] 2A, the column lines CSEL_1 to CSEL_31 transmit the column selection signals CSE_1 to CSE_31 to the product-sum calculation circuit MAC as the column selection signals CSE. The column selection signals CSE_1 to CSE_28 supplied to the column lines CSEL_1 to CSEL_28 enable selection of data (weight data W) to be supplied to a multiplication circuit (not shown) included in the product-sum calculation circuit MAC from the global sense amplifiers GSA_1 to GSA_28 of the selected column.

[0059] Although not shown in Fig. 2A, it is preferable to provide a number of global sense amplifiers GSA corresponding to the number of column lines CSEL. For example, in the configuration of Fig. 2A, global sense amplifiers GSA_29 to GSA_31 can be provided corresponding to column lines CSEL_29 to CSEL_31. Unlike global sense amplifiers GSA_1 to GSA_28, global sense amplifiers GSA_29 to GSA_31 do not supply data to the product-sum calculation circuit MAC, but can input and output data bidirectionally to and from the data bit line DBL.

[0060] 2B is a diagram illustrating a selector 50 included in the multiply-accumulate circuit MAC for outputting weight data selected by column selection signals CSE_1 to CSE_28. The global sense amplifiers GSA_1 to GSA_28 shown in FIG. 2B output 8-bit data as described above. For example, the global sense amplifier GSA_1 corresponds to eight bit lines BL[0] to BL[7]. The column selection signals CSE_1 to CSE_28 can select one of the global sense amplifiers GSA_1 to GSA_28 to output 8-bit weight data W.

[0061] The product-sum operation circuit MAC includes, for example, a multiplier circuit, an adder circuit, a register, a quantizer circuit, an output circuit, and the like, in addition to a selection signal for controlling the selector. Therefore, other control signals include a clock signal, a reset signal, an input control signal, and an output control signal. The clock signal can be used by utilizing the logical sum of the column selection signals CSE_1 to CSE_28. Control signals such as the reset signal, input control signal, and output control signal can be obtained by using the column selection signals CSE_29 to CSE_31 supplied via column lines CSEL_29 to CSEL_31.

[0062] In a semiconductor device according to one aspect of the present invention, the column lines CSEL for transmitting column control signals can be shared by the multiply-accumulate circuit MAC and the global sense amplifier GSA. This reduces the amount of wiring required to transmit control signals for driving the multiply-accumulate circuit MAC. As a result, miniaturization, reduced power consumption, and improved processing speed can be achieved by suppressing an increase in circuit area.

[0063] 2C is a schematic diagram for explaining a transistor 51 provided in the element layer 10 and a transistor 53 provided in the element layer 40 in the schematic diagram in which the element layer 10 and the element layer 40 are stacked as shown in FIG. 2C also illustrates a bit line pair BL-BLB that connects the memory cell 41 illustrated in FIG. 2A to the product-sum circuit MAC and the global sense amplifier GSA.

[0064] When the semiconductor layer 52 of the transistor 51 is an oxide semiconductor (metal oxide), the memory cell 41 can be formed using the above-described OS transistor.

[0065] By using silicon for the semiconductor layer 54 of the transistor 53, it is possible to provide the product-sum circuit MAC and the global sense amplifier GSA in the element layer 10 configured with the above-described Si transistors.

[0066] By locating the element layer 40 in which the memory cells 41 are provided on the element layer in which the product-sum operation circuit MAC and the global sense amplifier GSA are provided, it is possible to increase the memory capacity required for arithmetic processing in the semiconductor device functioning as an accelerator, i.e., the number of memory circuits, compared to when the memory cells 41, the product-sum operation circuit MAC, and the global sense amplifier GSA are arranged on the same layer. Increasing the memory capacity reduces the number of times data required for arithmetic processing is transferred from an external storage device to the semiconductor device, thereby achieving lower power consumption.

[0067] When a memory circuit such as the memory cell 41 and an arithmetic circuit such as the product-accumulation circuit MAC are on separate chips, the bus width is limited according to the number of pins on the chip. On the other hand, in a configuration in which the memory cell 41 and the product-accumulation circuit MAC are stacked as in one embodiment of the present invention, the number of parallel data required for arithmetic processing can be increased according to the opening where the bit line pair BL-BLB is provided, thereby enabling efficient arithmetic processing.

[0068] Figure 3A illustrates an element layer 40 having product-sum circuits MAC_P, MAC_Q and global sense amplifiers GSA_P, GSA_Q arranged adjacent to each other in the direction in which the column line CSEL extends, as well as memory cells 41P, 41Q, in the schematic diagram shown in Figure 2A.

[0069] Memory cell 41P is connected to the bit line pair BL_P and BLB_P. Memory cell 41Q is connected to the bit line pair BL_Q and BLB_Q. It is preferable that the bit line pair BL_P and BLB_P and the bit line pair BL_P and BLB_P are not connected. This configuration allows the product-sum calculation circuits MAC_P and MAC_Q and the global sense amplifiers GSA_P and GSA_Q to write and read different weight data or to perform calculation processing using weight data.

[0070] 3B is a diagram illustrating a bit line BL_V that connects the product-sum operation circuit MAC_P and the global sense amplifier GSA_P to the memory cell 41P and between the product-sum operation circuit MAC_Q and the global sense amplifier GSA_Q to the memory cell 41Q, as shown in FIG. 3A. The bit line BL_V is a bit line that is provided in the Z direction (a direction parallel to the direction perpendicular to the substrate surface) as shown in FIG. 3A and FIG. 3B.

[0071] 3B is a diagram showing bit lines BL_LD and BL_RD connected to bit line BL_V and provided in element layer 40. The lengths of bit lines BL_LD and BL_RD are preferably the same. In other words, the opening for providing bit line BL_V is preferably located near the center of bit line BL provided in element layer 40. This configuration makes it possible to equalize the distances between memory cells 41 and the product-sum circuit MAC and global sense amplifier GSA, and to equalize the parasitic capacitance of bit line pair BL-BLB.

[0072] The semiconductor device 100A shown in Fig. 4A is a modified example of the semiconductor device 100 shown in Fig. 2A. The schematic diagram shown in Fig. 4A illustrates a case where the element layer 40 in Fig. 2A is provided by stacking a plurality of element layers 40_1 and 40_2.

[0073] 4A includes element layers 40_1 and 40_2 in which a plurality of memory cells 41 are arranged. This configuration allows a manufacturing process using the same photomask to be employed for the plurality of element layers 40_1 and 40_2. Therefore, the memory cells 41 can be manufactured using the same manufacturing process repeatedly in the vertical direction, thereby reducing manufacturing costs.

[0074] 4B is a schematic diagram illustrating the semiconductor device 100A having element layers 40_1 to 40_n (n is an integer equal to or greater than 2), including the element layers 40_1 and 40_2 shown in FIG. 4A. Also shown in FIG. 4B is a bit line pair BL-BLB connecting the memory cell 41 shown in FIG. 4A to the product-sum calculation circuit MAC and the global sense amplifier GSA. As shown in FIG. 4B, in the semiconductor device 100A, multiple element layers 40_1 to 40_n are stacked in a vertical or approximately vertical direction relative to the surface of the element layer 10. This configuration allows for an increased number of memory cells 41 arranged per unit area, thereby increasing the memory density.

[0075] 4B increases the number of memory cells 41 connected to the bit line pair BL-BLB, and shortens the bit line pair BL-BLB connecting the memory cell 41 to the product-accumulation circuit MAC and the global sense amplifier GSA. The stacking of the element layer 40 shortens the wiring distance, reducing the parasitic capacitance generated in the bit line pair BL-BLB, and thus enabling low power consumption. Furthermore, weight data can be read from the memory cell 41 to the global sense amplifier GSA at high speed, and the number of bits of weight data can be increased.

[0076] (Configuration Example of Memory Cell 41) A circuit configuration of a memory cell that can be applied to the memory cell 41 will be described. Note that the memory cell 41 is a memory cell that includes an OS transistor. A memory that includes a memory cell that includes an OS transistor may also be referred to as an "OS memory."

[0077] The OS transistor has an extremely low off-state current. Therefore, charge corresponding to data written to the memory cell 41 can be held for a long time. That is, data once written can be held for a long time in the memory cell 41. Therefore, the frequency of data refresh can be reduced, and the power consumption of the semiconductor device 100 of one embodiment of the present invention can be reduced.

[0078] 5A is a diagram illustrating a memory cell array 42 having a plurality of memory cells 41. Illustrated in FIG. 5A are word lines WL_1 to WL_m and bit lines BL_1 to BL_n arranged in a matrix of m rows and n columns (m and n are natural numbers of 2 or greater). Also shown are memory cells 41 connected to each word line WL and bit line BL.

[0079] 5B is a circuit diagram illustrating an example of a circuit configuration applicable to the memory cell 41. The memory cell 41 includes a transistor M1 and a capacitor C1 (also referred to as a capacitance element). The transistor M1 is connected to a word line WL, a bit line BL, and the capacitor C1. The capacitor C1 is connected to a wiring PL that functions as a capacitance line. For example, a voltage GND (low-level power supply potential) is input to the wiring PL. FIG. 5C is a circuit block corresponding to the circuit diagram of FIG. 5B.

[0080] The memory cell 41 shown in FIG. 5B can be a 1T1C type DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) memory cell. DOSRAM refers to a RAM having a 1T (transistor) 1C (capacitor) type memory cell. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current of OS transistors. Because DOSRAM is a 1T1C type memory cell, a large storage capacity can be achieved in the memory cell array 42. Furthermore, by using OS transistors, the data retention period can be increased compared to DRAMs having Si transistors.

[0081] The circuit configuration applicable to the memory cell 41 is not limited to the 1T1C DOSRAM shown in FIG. 5B. For example, FIG. 6A shows another example configuration of a 1T1C memory cell applicable to a DOSRAM. The memory cell 41A shown in FIG. 6A differs from the memory cell 41 shown in FIG. 5B in that the transistor M1 is an OS transistor having a back gate, and the back gate is connected to a wiring BGL. The configuration including the wiring BGL allows the transistor M1 to have improved electrical characteristics.

[0082] The memory cell 41 having an OS transistor can be a nonvolatile oxide semiconductor random access memory (NOSRAM). The memory cell in an NOSRAM is a two-transistor (2T) or three-transistor (3T) gain cell. Since NOSRAM rewrites data by charging and discharging a capacitor, there is no theoretical limit to the number of rewrites and it requires low energy. Therefore, NOSRAM is a memory capable of high-speed operation, low power consumption, and high rewrite endurance. Furthermore, NOSRAM is suitable for long-term data retention because it can read written data nondestructively.

[0083] The memory cell 41B shown in FIG. 6B is a circuit equivalent to a 2T1C NOSRAM. The memory cell 41B includes a transistor M1, a transistor M2, and a capacitor C1. The transistors M1 and M2 are a write transistor and a read transistor, respectively. The transistors M1 and M2 may be OS transistors having semiconductor layers disposed in different layers or may be OS transistors having semiconductor layers disposed in the same layer. The memory cell 41B is illustrated as being connected to a write bit line WBL, a read bit line RBL, a write word line WWL, a read word line RWL, and a source line SL.

[0084] 6C is a circuit equivalent to a 3T1C NOSRAM. The memory cell 41C includes transistors M1, M2, and M3, and a capacitor C1. The transistors M1, M2, and M3 are a write transistor, a read transistor, and a select transistor, respectively. The transistors M1, M2, and M3 may be OS transistors whose semiconductor layers are arranged in different layers or may be OS transistors whose semiconductor layers are arranged in the same layer.

[0085] Since the write transistor is an OS transistor, turning off the write transistor allows the memory cells 41B and 41C to continue to hold charge according to data. Therefore, the memory cells 41B and 41C do not consume power to hold data. Therefore, the memory cells 41B and 41C can function as low-power memory cells capable of holding data for a long period of time. The gate of the read transistor functions as a node that holds charge according to data. The read transistor is a transistor that has the function of passing a current according to the potential of the node that holds charge according to data. The select transistor is a transistor that controls the current flowing through the read transistor.

[0086] 6D shows another example of the configuration of a 2T1C gain cell. A memory cell 41D shown in FIG. 6D differs from the memory cell 41B shown in FIG. 6B in that the transistors M1 and M2 are OS transistors each having a back gate, and the back gates are connected to a wiring BGL. For example, a voltage GND is input to the wiring BGL. The inclusion of the wiring BGL allows the transistors M1 and M2 to have improved electrical characteristics.

[0087] 6E shows another example of the configuration of a 3T1C gain cell. A memory cell 41E shown in FIG. 6E differs from the memory cell 41C shown in FIG. 6C in that the transistors M1, M2, and M3 are OS transistors each having a back gate, and the back gates are connected to a wiring BGL. For example, a voltage GND is input to the wiring BGL. The inclusion of the wiring BGL allows the transistors M1, M2, and M3 to have improved electrical characteristics.

[0088] Fig. 6F shows another example of the configuration of a 2T-type gain cell. The memory cell 41F shown in Fig. 6F differs from the memory cell 41B shown in Fig. 6B in that the capacitor C1 is omitted by using the gate capacitance of the read transistor, and the wiring PL is omitted.

[0089] The transistors M1 and M2 in the 2T gain cell shown in FIG. 6F are preferably vertical transistors in which the source electrode and the drain electrode are located at different heights. In a vertical transistor, current flows in the height direction (Z direction) in the channel formation region of the semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel transistor, or a vertical transistor.

[0090] In a vertical transistor, the source region, the channel formation region, and the drain region can at least partially overlap each other in a top view, compared to a horizontal transistor (also called a planar structure or planar type) in which the source electrode and the drain electrode are located at the same height. This allows the vertical transistor to have a smaller occupied area (also called a footprint). Furthermore, the vertical transistor has a structure that allows the channel length to be short and the channel width to be wide, allowing the on-resistance to be small (the on-current to be large).

[0091] Fig. 6G shows another example of the configuration of a 3T gain cell. Memory cell 41G shown in Fig. 6G differs from memory cell 41C shown in Fig. 6C in that capacitor C1 is omitted by using the gate capacitance of the read transistor, and wiring PL is omitted. Transistors M1, M2, and M3 included in the 3T gain cell shown in Fig. 6G are vertical transistors in which the source electrode and drain electrode are located at different heights, thereby reducing the occupied area (also referred to as footprint) and reducing the on-resistance (increasing the on-current).

[0092] (Configuration Example of Global Sense Amplifier GSA) An example of the circuit configuration of the global sense amplifier GSA will be described. Fig. 7A is a circuit diagram of the global sense amplifier GSA. Fig. 7B shows a circuit block corresponding to the circuit diagram. Fig. 7C illustrates a configuration example that combines the circuit block of the memory cell 41 shown in Fig. 5C with the circuit block of the global sense amplifier GSA shown in Fig. 7B.

[0093] 7A includes a sense amplifier 61, a precharge circuit 62, a precharge circuit 63, and a switch circuit 64. Each of the sense amplifier 61, the precharge circuit 62, the precharge circuit 63, and the switch circuit 64 is connected to the bit line pair BL-BLB.

[0094] The sense amplifier 61 has a function of applying a predetermined potential to each of the wiring SAP and the wiring SAN to output a potential corresponding to one of the binary data values ​​to the bit line BL and output a potential corresponding to the other of the binary data values ​​to the inverted bit line BLB. The sense amplifier 61 includes transistors 61_1, 61_2, 61_3, and 61_4. The transistors 61_1 and 61_2 are p-channel transistors. The transistors 61_3 and 61_4 are n-channel transistors. The transistors 61_1 and 61_3 form an inverter circuit that receives the inverted bit line BLB as an input, the bit line BL as an output, the wiring SAP as a high-potential power supply line, and the wiring SAN as a low-potential power supply line. The transistors 61_2 and 61_4 form an inverter circuit that receives the bit line BL as an input, the inverted bit line BLB as an output, the wiring SAP as a high-potential power supply line, and the wiring SAN as a low-potential power supply line.

[0095] The precharge circuit 62 has a function of precharging the bit line pair BL-BLB to a potential VPRE in response to a signal EQB. Specifically, the precharge circuit 62 includes transistors 62_1, 62_2, and 62_3. Each of the transistors 62_1, 62_2, and 62_3 is a p-channel transistor. The transistor 62_1 has a function of turning on or off the bit line pair BL-BLB in response to the signal EQB. The transistor 62_2 has a function of precharging the bit line BL to a potential VPRE in response to the signal EQB. The transistor 62_3 has a function of precharging the inverted bit line BLB to a potential VPRE in response to the signal EQB.

[0096] The precharge circuit 63 has a function of precharging the bit line pair BL-BLB to a potential VPRE in response to a signal EQ. Specifically, the precharge circuit 63 includes transistors 63_1, 63_2, and 63_3. Each of the transistors 63_1, 63_2, and 63_3 is an n-channel transistor. The transistor 63_1 has a function of turning on or off the bit line pair BL-BLB in response to the signal EQ. The transistor 63_2 has a function of precharging the bit line BL to a potential VPRE in response to the signal EQ. The transistor 63_3 has a function of precharging the inverted bit line BLB to a potential VPRE in response to the signal EQ.

[0097] The switch circuit 64 has a function of establishing a conductive state or a non-conductive state between the bit line pair BL-BLB and the data bit line pair DBL-DBLB in response to a column selection signal CSE. Specifically, the switch circuit 64 includes a transistor 64_1 and a transistor 64_2. Each of the transistors 64_1 and 64_2 is an n-channel transistor. The transistor 64_1 has a function of establishing a conductive state or a non-conductive state between the bit line BL and the data bit line DBL in response to the column selection signal CSE. The transistor 64_2 has a function of establishing a conductive state or a non-conductive state between the data bit line DBL and the inverted data bit line DBLB in response to the column selection signal CSE.

[0098] Fig. 7B shows a circuit block corresponding to the circuit diagram of the global sense amplifier GSA described in Fig. 7A. Fig. 7C shows a configuration example in which the circuit block of the global sense amplifier GSA shown in Fig. 7B is combined with the circuit block of the memory cell 41 shown in Fig. 5C.

[0099] 7A to 7C, the potential difference between the bit line BL and the inverted bit line BLB, which varies depending on the charge held in the memory cell 41 when data is read from the memory cell 41, can be amplified and output to the data bit line pair DBL-DBLB in accordance with the column selection signal CSE. Also, the global sense amplifier GSA configuration shown in FIG. 7A to 7C can apply the potential difference between the data bit line pair DBL-DBLB to the bit line pair BL-BLB in accordance with the column selection signal CSE, and write data to the memory cell 41 connected to the bit line pair BL-BLB using the amplified potential difference.

[0100] (Configuration Example of Data Sense Amplifier DSA) An example of the circuit configuration of the data sense amplifier DSA will be described. Fig. 8A is a circuit diagram of the data sense amplifier DSA. Fig. 8B shows a circuit block corresponding to the circuit diagram. Fig. 8C illustrates a configuration example in which the circuit block of the memory cell 41 shown in Fig. 5C and the circuit block of the global sense amplifier GSA shown in Fig. 7B are combined with the circuit block of the data sense amplifier DSA shown in Fig. 8B.

[0101] 8A includes a precharge circuit 65, a sense amplifier 66, a switch circuit 67, a transistor 68, an AND gate 69, and a latch circuit 70. The precharge circuit 65, the sense amplifier 66, and the switch circuit 67 are each connected to the data bit line pair DBL-DBLB.

[0102] The precharge circuit 65 has a function of precharging the data bit line pair DBL-DBLB to the potential of the wiring DSAP in response to the signal DEQ_ENB. The wiring DSAP is a high-potential power supply line. Specifically, the precharge circuit 65 has transistors 65_1, 65_2, and 65_3. Each of the transistors 65_1, 65_2, and 65_3 is a p-channel transistor. The transistor 65_1 has a function of bringing the data bit line DBL and the inverted data bit line DBLB into a conductive state or a non-conductive state in response to the signal DEQ_ENB. The transistor 65_2 has a function of precharging the data bit line DBL to the potential of the wiring DSAP in response to the signal DEQ_ENB. The transistor 65_3 has a function of precharging the inverted data bit line DBLB to the potential of the wiring DSAP in response to the signal DEQ_ENB.

[0103] The sense amplifier 66 has a function of applying a predetermined potential from each of the wirings DSAP and DSAN to output a potential corresponding to one of the binary data values ​​to the data bit line DBL and outputting a potential corresponding to the other of the binary data values ​​to the inverted data bit line DBLB. The sense amplifier 66 includes transistors 66_1, 66_2, 66_3, and 66_4. The transistors 66_1 and 66_2 are p-channel transistors. The transistors 66_3 and 66_4 are n-channel transistors. The transistors 66_1 and 66_3 form an inverter circuit whose input is the inverted data bit line DBLB, whose output is the data bit line DBL, whose wiring DSAP serves as a high-potential power supply line, and whose wiring DSAN serves as a low-potential power supply line. The transistors 66_2 and 66_4 configure an inverter circuit in which the data bit line DBL is used as an input, the inverted data bit line DBLB is used as an output, the wiring SAP is used as a high-potential power supply line, and the wiring SAN is used as a low-potential power supply line.

[0104] The supply of the potential of the wiring DSAN to the sense amplifier 66 is controlled by a signal DSA_EN supplied to a transistor 68. The signal DSA_EN is a signal that controls the state of the sense amplifier 66. When the signal DSA_EN makes the transistor 68 conductive, the sense amplifier 66 is activated, and when the signal DSA_EN makes the transistor 68 non-conductive, the sense amplifier 66 is inactivated.

[0105] The switch circuit 67 switches the write data W to the data bit line pair DBL-DBLB in response to the write control signals WE and WEB. ＤＡＴＡ , W ＤＡＴＡ The write control signal WEB is an inverted signal of the write control signal WE. ＤＡＴＡ _B is the write data W ＤＡＴＡ Specifically, the switch circuit 67 includes transistors 67_1 to 67_4. The transistors 67_1 and 67_3 are n-channel transistors. The transistors 67_2 and 67_4 are p-channel transistors. The transistors 67_1 and 67_2 are used to transmit the write data W to the inverted data bit line DBLB. ＤＡＴＡ The transistors 67_3 and 67_4 function as analog switches that control the supply of write data W to the data bit line DBL. ＤＡＴＡ It functions as an analog switch that controls the supply of

[0106] The AND gate 69 has a function of outputting the potential of the data bit line DBL to the latch circuit 70 in response to the control of the read control signal RE. The latch circuit 70 also receives the output signal of the AND gate 69 in response to the latch signal DLAT and outputs the read data R ＤＡＴＡ It has the function of outputting as

[0107] Fig. 8B shows a circuit block corresponding to the circuit diagram of the data sense amplifier DSA described in Fig. 8A. Fig. 8C shows a configuration example in which the circuit block of the data sense amplifier DSA shown in Fig. 8B is combined with the circuit block of the memory cell 41 and the global sense amplifier GSA shown in Fig. 7C.

[0108] In the configuration of the data sense amplifier DSA shown in FIGS. 8A to 8C, the potential difference between the data bit line pair DBL-DBLB, which varies under the control of the column selection signal CSE, is amplified, and the read data R is output in response to the read control signal RE and the latch signal DLAT. ＤＡＴＡ In the configuration of the data sense amplifier DSA shown in FIGS. 8A to 8C, write data W is input to the data bit line pair DBL-DBLB under the control of the write control signals WE and WEB. ＤＡＴＡ , W ＤＡＴＡ The potential difference resulting from the supply of .sub.B is amplified, and the potential of the data bit line pair DBL-DBLB is applied to the bit line pair BL-BLB by controlling the column selection signal CSE, and the potential difference amplified by the global sense amplifier GSA can be written as data into the memory cell 41 connected to the bit line pair BL-BLB.

[0109] (Configuration Example of Product-Sum Calculation Circuit MAC) An example of the circuit configuration of the product-sum arithmetic circuit MAC will be described. FIG. 9A is a circuit diagram of the product-sum arithmetic circuit MAC. FIG. 9B shows a circuit block corresponding to the circuit diagram. FIG. 10 is a timing chart for explaining an example of the operation of the product-sum arithmetic circuit MAC. FIG. 11 illustrates an example of a configuration that combines the circuit block of the memory cell 41 shown in FIG. 5C, the circuit block of the global sense amplifier GSA shown in FIG. 7B, the circuit block of the data sense amplifier DSA shown in FIG. 8B, and the circuit block of the product-sum arithmetic circuit shown in FIG. 9B.

[0110] 9A includes, as an example, a selector 50, a multiplier circuit 71, an adder circuit 72, an OR gate 73, a register 74, a quantizer circuit 75, an AND gate 76, a register 77, a tri-state buffer 78, and a buffer 79. In addition to the product-sum calculation circuit MAC, FIG. 9A also illustrates global sense amplifiers GSA_1 to GSA_28 connected to the selector 50 described in FIG. 2B.

[0111] The selector 50 switches the weight data W (shown as 8-bit data as an example) read out by the global sense amplifiers GSA_1 to GSA_28 and supplies it to the multiplication circuit 71. In response to the column selection signals CSE_1 to CSE_28, the selector 50 activates one of the global sense amplifiers GSA_1 to GSA_28 connected to the memory cell holding the corresponding weight data, and supplies the weight data W to the multiplication circuit 71.

[0112] The multiplication circuit 71 is supplied with the weight data W (including bias data) and input data A (shown as 8-bit data as an example) via the data bit line DBL. The multiplication circuit 71 outputs multiplication data A×W obtained by multiplying the input data A by the weight data W. The multiplication data A×W is, for example, 16-bit data.

[0113] The adder circuit 72 repeatedly adds the multiplication data A×W and the data held in the register 74. The added data is provided to the input terminal D of the register 74 and held in the register 74. The data held in the register 74 is supplied to the adder circuit 72 from the output terminal Q. The adder circuit 72 can repeatedly add the multiplication data A×W that is sequentially supplied. The register 74 can hold the weight data and the sum-of-products operation data of the input data. The register 74 is reset by a column selection signal CSE_31 that is supplied to the reset terminal RS. The output terminal Q of the register 74, i.e., the data at node N1, i.e., the sum-of-products operation data, becomes, for example, 20-bit data through repeated addition.

[0114] A signal for holding data provided to an input terminal D of the register 74 in the register 74 is provided by an OR gate 73. Column selection signals CSE_1 to CSE_28 are input to the OR gate 73. The column selection signals CSE_1 to CSE_28 are selection signals that go high at different times. Therefore, the output signal of the OR gate 73 can be used as a clock signal during the period when the weight data W is switched and output.

[0115] The quantization circuit 75 is a circuit that performs processing using an activation function and quantization processing. The processing using an activation function is, for example, processing using a rectified linear function (ReLU). The quantization processing quantizes the product-sum operation data of node N1, for example, converting 20-bit product-sum operation data into 8-bit product-sum operation data. After the quantization processing, 8-bit product-sum operation data is output to node N2.

[0116] A signal for controlling the quantization circuit 75 is provided by an AND gate 76. The AND gate 76 receives a column selection signal CSE_29 as well as data supplied via the data bit line DBL. The column selection signal CSE_29 is a selection signal that goes high at a different timing from the signals CSE_1 to CSE_28 and CSE_31. Therefore, activation function processing and quantization processing can be performed at the timing when the weight data and the sum-of-products operation data of the input data are obtained.

[0117] The sum-of-products operation data of node N2, which has been processed by the activation function and quantized, is provided to an input terminal D of a register 77 and stored in the register 77. The data stored in the register 77 is supplied to a tri-state buffer 78 via an output terminal Q. The register 77 can store the sum-of-products operation data of node N2. The register 77 is reset by a column selection signal CSE_31 supplied to a reset terminal RS. The output terminal Q of the register 77, i.e., the sum-of-products operation data of node N3, is switched at the timing of the column selection signal CSE_29. The timing of the column selection signal CSE_29 supplied to the register 77 is delayed because it passes through the buffer 79. Therefore, the timing at which the quantization circuit 75 obtains the sum-of-products operation data can be made different from the timing at which the register 77 stores the sum-of-products operation data of node N2.

[0118] The tri-state buffer 78 is a circuit that outputs the sum-of-products operation data of the node N3 to the data bit line DBL at the timing of the column selection signal CSE_30. The column selection signal CSE_30 is a selection signal that goes high at a different timing from the signals CSE_1 to CSE_29 and CSE_31. Therefore, the sum-of-products operation data that has been processed using the activation function and quantized can be output to the data bit line DBL at a predetermined timing.

[0119] The product-sum operation circuit MAC shown in Fig. 9A described above can be a circuit that is connected to the data bit lines DBL and the global sense amplifiers GSA_1 to GSA_29 and controlled by the column selection signals CSE_1 to CSE_31. Fig. 9B is a circuit block corresponding to the product-sum operation circuit MAC in Fig. 9A.

[0120] 10 shows a timing chart illustrating the operation of the sum-of-products operation circuit MAC shown in FIG. 9A, and the operation will be described below. FIG. 10 illustrates signal changes on the column line CSEL, weight data W, data bit line DBL, inverted data bit line DBLB, node N1, node N2, and node N3. The column line CSEL illustrates column selection signals CSE_1 to CSE_31 supplied to the column line CSEL. The weight data W illustrates global sense amplifiers GSA_1 to GSA_28 that output weight data. The data bit line DBL illustrates input data IN_1 to IN_28 corresponding to input data A, a signal PARAM for controlling the quantization circuit 75, and sum-of-products operation data DOUT. The inverted data bit line DBLB illustrates an inverted signal DOUT_B of the sum-of-products operation data generated when the data on the data bit line DBL is determined. Node N1 shows the initial state Reset due to the reset signal and product-sum operation data MAC_1 to MAC_28. Node N2 shows the data SCL processed by the activation function and quantized. Node N3 shows the initial state Reset due to the reset signal, the processing by the activation function, and product-sum operation data DOUT. The hatched areas indicate a state where the data or potential does not affect the operation (Don't care).

[0121] 10 is a reset operation. In the reset operation, the column selection signal CSE_31 is selected. Therefore, a selection signal is supplied to the reset terminals RS of the registers 74 and 77, resetting the registers 74 and 77. As a result, the nodes N1 and N3 are set to the initial state Reset.

[0122] The periods T1 to T28 shown in FIG. 10 are for the sum-of-products operation. In the sum-of-products operation, column selection signals CSE_1 to CSEL_28 are selected in sequence. For example, during period T1, memory cells connected to the global sense amplifier GSA_1 are selected by the word signal. As a result, when the weight data W is 8 bits, the potentials of the bit lines BL[0] to BL[7] (and the inverted bit lines BLB[0] to BLB[7]) fluctuate. The weight data W stored in the memory cells connected to the global sense amplifier GSA_1 is supplied to the sum-of-products operation circuit MAC by the column selection signal CSE_1. At this time, input data IN_1 is provided to the data bit line DBL via the data sense amplifier DSA or the like, thereby causing the sum-of-products operation circuit MAC to perform the sum-of-products operation. The column selection signal CSE_1 functions as a control circuit within the sum-of-products operation circuit MAC, so that the sum-of-products operation data is stored in the register 74, and the node N1 becomes the sum-of-products operation data MAC_1.

[0123] The multiply-and-accumulate operation is similarly performed during periods T2 to T28. Weight data (including bias data) is switched and supplied to the multiply-and-accumulate circuit MAC from the global sense amplifiers GSA_2 to GSA_28 in response to column selection signals CSE_2 to CSE_28. Input data IN_2 to IN_28 is also switched and supplied from the data sense amplifier DSA via the data bit lines DBL. The register 74 stores the multiply-and-accumulate data using the column selection signals CSE_2 to CSE_28. As a result, the multiply-and-accumulate data can be obtained by switching between the input data and the weight data or bias data.

[0124] The period T29 shown in FIG. 10 is the operation for performing the activation function processing and the quantization processing. In the activation function processing and the quantization processing, the column selection signal CSE_29 is selected. At this time, by providing the signal PARAM to the data bit line DBL via the data sense amplifier DSA or the like, the output signal of the AND gate 76 activates the quantization circuit 75. Therefore, the column selection signal CSE_29 causes the node N2 to become the data SCL that has been processed by the activation function and quantized. The column selection signal CSE_29 is delayed by the buffer 79 and supplied to the register 77. The node N3 becomes the sum-of-products operation data DOUT, which is the data SCL that has been processed by the activation function and quantized.

[0125] 10, the sum-of-products operation data DOUT held at node N3 is output via the data bit line DBL. The tri-state buffer 78 is selected by the column selection signal CSE_30, and the data bit line DBL becomes the sum-of-products operation data DOUT. When the data bit line DBL becomes the sum-of-products operation data DOUT, the data sense amplifier DSA is activated, and the inverted data bit line DBLB becomes the inverted signal DOUT_B of the sum-of-products operation data DOUT.

[0126] FIG. 11 shows an example of a configuration in which the circuit block of the product-sum calculation circuit MAC shown in FIG. 9B is combined with the circuit blocks of the memory cell 41, global sense amplifier GSA, and data sense amplifier DSA shown in FIG. 8C.

[0127] 9A to 11, a plurality of column selection signals CSE can be used as control signals. Also, in the configuration of the product-sum calculation circuit MAC shown in Fig. 8A to 8C, weight data can be switched and input to the product-sum calculation circuit can be used as a control signal for the product-sum calculation circuit.

[0128] As described above, in a semiconductor device according to one aspect of the present invention, the column line CSEL for transmitting a column control signal can be shared by both the product-accumulation circuit MAC and the global sense amplifier GSA. This reduces the wiring required for transmitting control signals for driving the product-accumulation circuit MAC. As a result, miniaturization, reduced power consumption, and improved processing speed can be achieved by suppressing an increase in circuit area.

[0129] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0130] In this embodiment, a cross-sectional structure example of an element layer including stacked OS transistors that can be applied to a semiconductor device or the like will be described. In this embodiment, an example of a cross-sectional schematic diagram that can be applied to a circuit configuration such as a NOSRAM or a DOSRAM will be described.

[0131] <Configuration Example 1 of NOSRAM> Figure 12 shows a cross-sectional configuration example when a three-transistor NOSRAM circuit configuration is used. Figure 12 illustrates a case where element layers UF[1] to UF[3] are stacked on element layer LF. Figure 13A shows an example of the cross-sectional structure of element layer UF[k]. Figure 13B shows an equivalent circuit diagram of Figure 13A.

[0132] The element layer LF is the element layer 10 described in the above-described embodiment 1. An element such as a Si transistor is provided in the element layer LF. The element layer UF is the element layer 40 described in the above-described embodiment 1. An element such as an OS transistor is provided in the element layer UF.

[0133] 12 illustrates a transistor 550 included in the element layer LF. The transistor 550 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate electrode, an insulating layer 315, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314 a and a low-resistance region 314 b functioning as a source region or a drain region.

[0134] Note that the transistor 550 may be either a p-channel type or an n-channel type.

[0135] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0136] Note that the transistor 550 illustrated in FIG. 12 is just an example, and the structure is not limited to this example. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0137] A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between the element layer LF and the element layer UF, or between the kth element layer UF and the k+1th element layer UF. In the present embodiment and the like, the kth element layer UF may be referred to as element layer UF[k], and the k+1th element layer UF may be referred to as element layer UF[k+1]. Here, k is an integer of 1 or more and N or less. In the present embodiment and the like, when "k+α (α is an integer of 1 or more)" or "k-α" is used, the solutions of "k+α" and "k-α" are integers of 1 or more and N or less.

[0138] In addition, multiple wiring layers can be provided depending on the design. In addition, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring and cases where a part of the conductive layer functions as the plug.

[0139] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 550. A conductive layer 328 or the like is embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 or the like is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0140] A wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, in FIG. 12 , an insulating layer 350, an insulating layer 357, an insulating layer 352, and an insulating layer 354 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 357, and the insulating layer 352. The conductive layer 356 functions as a contact plug or a wiring.

[0141] An insulating layer 514 included in the element layer UF is provided over the insulating layer 354. A conductive layer 358 is embedded in the insulating layer 514 and the insulating layer 354. The conductive layer 358 functions as a contact plug or a wiring. For example, a wiring functioning as a bit line and the transistor 550 are connected via the conductive layer 358, the conductive layer 356, the conductive layer 330, or the like.

[0142] The memory cell 41E shown in FIG. 12 has a transistor M2, a transistor M3, and a transistor M1 on an insulating layer 514 as shown in FIG. 13A.

[0143] 12 and 13A share a single island-shaped semiconductor layer 530. In other words, a portion of the island-shaped semiconductor layer 530 functions as a channel formation region for the transistor M2, and another portion functions as a channel formation region for the transistor M3. The source of the transistor M2 and the drain of the transistor M3, or the drain of the transistor M2 and the source of the transistor M3, are shared. Therefore, the area occupied by the transistors M2 and M3 is smaller than when the transistors M2 and M3 are provided independently.

[0144] 12 and 13A, it is possible to configure the memory cell 41E without the transistor M1. The memory cell 41E without the transistor M1 can be a two-transistor NOSRAM, and corresponds to the memory cell 41D shown in FIG. 6D.

[0145] 14A to 14C, an OS transistor will be described. 14A and 14B are schematic cross-sectional views of a transistor 500 that can be used for the transistors M1 to M3.

[0146] 14A and 14B , an insulating layer 516 is disposed over an insulating layer 514. The transistor 500 includes a conductive layer 503 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed over the insulating layer 516 and the conductive layer 503, an insulating layer 524 disposed over the insulating layer 522, a semiconductor layer 530 disposed over the insulating layer 524, conductive layers 542a and 542b disposed apart from each other on the semiconductor layer 530, an insulating layer 580 disposed over the conductive layers 542a and 542b and having an opening formed therein overlapping with the conductive layers 542a and 542b, an insulating layer 545 disposed on a bottom surface and a side surface of the opening, and a conductive layer 560 disposed on the surface on which the insulating layer 545 is formed. The conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 545 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a.

[0147] 14A and 14B , an insulating layer 544 is disposed between the semiconductor layer 530, the conductive layers 542a and 542b, and the insulating layer 580. An insulating layer 574 is disposed on the insulating layer 580, the conductive layer 560, and the insulating layer 545, and an insulating layer 581 is disposed on the insulating layer 574.

[0148] In the transistor 500, the conductive layer 560 functions as a gate electrode, the insulating layer 545 functions as a gate insulating film, and the conductive layers 542a and 542b function as a source electrode and a drain electrode, respectively. The conductive layer 560 may function as a first gate electrode. The conductive layer 503 may function as a second gate electrode. The insulating layers 522 and 524 function as second gate insulating films.

[0149] 14A and 14B , the second gate insulating film has a two-layer structure including insulating layers 522 and 524. However, the second gate insulating film may have a single-layer structure or a stacked structure of three or more layers. In this case, the second gate insulating film is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0150] In the transistor 500, an oxide semiconductor layer is preferably used as the semiconductor layer 530 including a channel formation region. An oxide semiconductor layer that can be used as the semiconductor layer 530 will be described in Embodiment 3 to be described later.

[0151] The channel formation region of a transistor using an oxide semiconductor for a semiconductor layer has a higher oxygen vacancy (V Ｏ It is preferable that the concentration of impurities such as hydrogen, nitrogen, and metal elements is low. In addition, hydrogen in the vicinity of the oxygen vacancy is replaced by a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ H) and generate electrons that become carriers. Therefore, in the channel formation region, V Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0152] In addition, the source and drain regions of a transistor using an oxide semiconductor for a semiconductor layer have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of a transistor are n-type regions with a high carrier concentration and low resistance compared to the channel formation region, due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, and metal elements.

[0153] The band gap of the oxide semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using an oxide semiconductor with a wide band gap for a semiconductor layer, the off-state current of a transistor can be reduced. By using a transistor with a low off-state current for a memory cell, stored data can be retained for a long period of time. In other words, a refresh operation is not required or is performed very infrequently, and therefore the power consumption of the semiconductor device can be sufficiently reduced.

[0154] 14A and 14B, the semiconductor layer 530 is shown as a single layer, but the present invention is not limited to this. For example, the semiconductor layer 530 may have a stacked structure of two or more layers.

[0155] 14A , when an oxide semiconductor is used for the semiconductor layer 530, a region 543a may be formed as a low-resistance region at the interface with the conductive layer 542a of the semiconductor layer 530 or in its vicinity. Similarly, a region 543b may be formed as a low-resistance region at the interface with the conductive layer 542b of the semiconductor layer 530 or in its vicinity. In this case, the region 543a and the region 543b function as a source region and a drain region, respectively. Furthermore, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

[0156] Note that the semiconductor material that can be used for the semiconductor layer 530 is not limited to an oxide semiconductor. A semiconductor material other than an oxide semiconductor may be used for the semiconductor layer 530. Other semiconductor materials that can be used for the semiconductor layer 530 will be described in the section "Other Semiconductor Materials" below.

[0157] 14A, the conductive layers 542a and 542b each have a single-layer structure, but the present invention is not limited to this. For example, the conductive layers 542a and 542b each may have a stacked structure of two or more layers.

[0158] 14A and 14B, the conductive layer 560 and the conductive layer 503 each have a two-layer stacked structure, but the present invention is not limited to this. For example, the conductive layer 560 and the conductive layer 503 each may have a single-layer structure or a stacked structure of three or more layers.

[0159] The insulating layer 580 is provided over the conductive layers 542a and 542b with the insulating layer 544 interposed therebetween. The opening of the insulating layer 580 is formed to overlap the region between the conductive layers 542a and 542b. As a result, the conductive layer 560 is formed so as to be embedded in the opening of the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b.

[0160] When an oxide semiconductor is used for the semiconductor layer 530, the insulating layer 580 is preferably an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen). By performing heat treatment on the insulating layer 580 containing excess oxygen, oxygen is supplied from the insulating layer 580 to a channel formation region of the semiconductor layer 530, and oxygen vacancies and V Ｏ It is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor 500 and improve its reliability.

[0161] 14A and 14B, the insulating layer 545 is shown as a single layer, but the present invention is not limited to this. For example, the insulating layer 545 may have a stacked structure of two or more layers.

[0162] The insulating layer 544 is provided to cover the conductive layers 542a and 542b. The insulating layer 544 preferably has a barrier property against oxygen. With such a structure, the conductive layers 542a and 542b can be prevented from being oxidized.

[0163] An insulating layer 571a is disposed over the conductive layer 542a, and an insulating layer 571b is disposed over the conductive layer 542b. By providing the insulators 271a and 271b, it is possible to prevent the end portions of the conductive layers 242a and 242b from being excessively etched when the semiconductor film that becomes the semiconductor layer 530 and the conductive films that become the conductive layers 242a and 242b are collectively processed into island shapes. Therefore, it is possible to process minute transistors with high precision.

[0164] The insulating layer 574 preferably has a function of suppressing diffusion of impurities such as hydrogen. The insulating layer 574 also preferably has a function of capturing or fixing impurities such as hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 530 can be suppressed. Furthermore, the hydrogen concentration in the semiconductor layer 530 can be reduced.

[0165] A conductive layer 540a is disposed in openings formed in the insulating layers 581, 574, 580, 544, and 571a, and a conductive layer 540b is disposed in openings formed in the insulating layers 581, 574, 580, 544, and 571b. The conductive layers 540a and 540b are disposed opposite each other with the conductive layer 560 interposed therebetween. The conductive layers 540a and 540b function as vias, contact plugs, or wiring.

[0166] 14A, the conductive layer 540a and the conductive layer 540b each have a two-layer structure, but the present invention is not limited to this. For example, the conductive layer 540a and the conductive layer 540b each may have a single-layer structure or a stacked structure of three or more layers.

[0167] The transistor 500 illustrated in FIGS. 14A and 14B is an example, and the present invention is not limited to this configuration. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0168] 14A and 14B . For example, a transistor 500 having a structure shown in Fig. 14C may be used. The transistor 500 shown in Fig. 14C differs from the transistor 500 shown in Fig. 14A and 14B in that the conductive layers 542a and 542b each have a stacked structure and that an insulating layer 520 and an insulating layer 555 are provided.

[0169] 14C , the conductive layer 542a has a stacked structure of a conductive layer 542a1 and a conductive layer 542a2 over the conductive layer 542a1, and the conductive layer 542b has a stacked structure of a conductive layer 542b1 and a conductive layer 542b2 over the conductive layer 542b1. The conductive layers 542a1 and 542b1 in contact with the semiconductor layer 530 are preferably made of a conductor that is resistant to oxidation, such as a metal nitride. This can prevent the conductive layers 542a and 542b from being excessively oxidized by oxygen contained in the semiconductor layer 530. Furthermore, the conductive layers 542a2 and 542b2 are preferably made of a conductor having higher conductivity than the conductive layers 542a1 and 542b1. This allows the conductive layers 542a and 542b to function as highly conductive wirings or electrodes. In this manner, a semiconductor device in which the conductive layers 542a and 542b functioning as wirings or electrodes are provided in contact with the top surface of the semiconductor layer 530 can be provided.

[0170] 14C , in a cross-sectional view of the transistor 500 in the channel length direction, the distance between the conductive layer 542a1 and the conductive layer 542b1 is smaller than the distance between the conductive layer 542a2 and the conductive layer 542b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 500. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0171] The insulating layer 555 is provided in contact with the side surfaces of the conductive layer 542a2 and the conductive layer 542b2. The insulating layer 555 preferably has a function of suppressing oxygen diffusion. With such a structure, oxidation of the side surfaces of the conductive layer 542a2 and the conductive layer 542b2 can be suppressed.

[0172] The insulating layer 520 preferably has a barrier property against hydrogen, which can suppress diffusion of hydrogen into the semiconductor layer 530 and reduce the hydrogen concentration in the semiconductor layer 530.

[0173] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0174] Note that the transistor that can be used in the present invention is not limited to the transistor 500 shown in Figures 14A and 14C. Figures 15A to 15D describe structures different from those of the transistors shown in Figures 14A to 14C. Figure 15A is a plan view of a transistor 500A that can be used for the transistors M1 to M3. Figures 15B to 15D are cross-sectional views of the transistor 500A.

[0175] 15B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 15A, and is also a cross-sectional view of the transistor 500A in the channel width direction. FIG. 15C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 15A, and is also a cross-sectional view of the transistor 500A in the channel width direction. FIG. 15D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 15A, and is also a cross-sectional view of the transistor 500A in the channel length direction. Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of FIG. 15A, some elements are omitted and some elements are shown transparently for clarity.

[0176] The transistor 500A includes an insulating layer 516 over a substrate (not shown), an insulator 521 over the insulating layer 516, an insulating layer 522 over the insulator 521, a semiconductor layer 530 over the insulating layer 522, conductive layers 542a and 542b over the semiconductor layer 530 and the insulating layer 522, an insulating layer 545 over the semiconductor layer 530, and a conductive layer 560 (conductive layers 560a and 560b) over the insulating layer 545. Note that hereinafter, the conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0177] An insulator 575 is provided over the conductive layer 542, and an insulating layer 580 is provided over the insulator 575. The insulating layer 545 and the conductive layer 560 are disposed inside openings provided in the insulating layer 580 and the insulator 575. The openings reach the semiconductor layer 530, and the insulating layer 545 is in contact with the semiconductor layer 530 within the openings. An insulating layer 574 is provided over the insulating layer 580 and the conductive layer 560. An insulator 583 is provided over the insulating layer 574. An insulator 515 is provided under the insulating layer 516.

[0178] An insulator 541a is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540a is provided in contact with the side surface of the insulator 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulator 541b is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540b is provided in contact with the side surface of the insulator 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Note that hereinafter, the conductive layers 540a and 540b may be collectively referred to as the conductive layer 540. The insulators 541a and 541b may be collectively referred to as the insulator 541.

[0179] The semiconductor layer 530 has a region that functions as a channel formation region of the transistor 500A. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 500A. The insulating layer 545 has a region that functions as a first gate insulator of the transistor 500A.

[0180] The conductive layer 542a has a region functioning as one of the source electrode and the drain electrode of the transistor 500A. The conductive layer 540a functions as a plug connected to the conductive layer 542a. The conductive layer 542b has a region functioning as the other of the source electrode and the drain electrode of the transistor 500A. The conductive layer 540b functions as a plug connected to the conductive layer 542b.

[0181] The semiconductor layer 530 is formed on and in contact with the insulating layer 522. The semiconductor layer 530 has a shape with a high aspect ratio (a shape in which the length in the height direction (H) is equal to or greater than the length of the base side (W) (H≧W)) in a cross-sectional view in the channel width direction. The semiconductor layer 530 having a shape with a high aspect ratio is sometimes referred to as having a fin-like shape.

[0182] Here, the aspect ratio of the semiconductor layer 530 in a cross-sectional view in the channel width direction refers to the ratio of the width L of the semiconductor layer 530 to the height H of the semiconductor layer 530. The aspect ratio of the semiconductor layer 530 is preferably as large as possible without causing the semiconductor layer 530 to collapse during the manufacturing process of the transistor 500A. In the semiconductor layer 530, the height H of the semiconductor layer 530 is at least longer than the width L of the semiconductor layer 530. The height H of the semiconductor layer 530 may be greater than 1 time and less than 400 times, preferably 2 times to 100 times, more preferably 5 times to 40 times, and even more preferably 10 times to 20 times the width L of the semiconductor layer 530. Alternatively, for example, the height H may be 2 times to 10 times the width L. For example, the width L may be 5 nm to 100 nm, preferably 5 nm to 50 nm, and more preferably 10 nm to 30 nm. For example, the height H may be 50 nm or more and 2000 nm or less, and preferably 100 nm or more and 1000 nm or less.

[0183] In addition, in a cross-sectional view in the channel width direction, the angle formed between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably a right angle or a substantially right angle. For example, the angle formed between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably 80° to 100°, more preferably 85° to 95°.

[0184] An insulating layer 545, a conductive layer 560, and a conductive layer 542 are provided to cover the semiconductor layer 530 having such a high aspect ratio. In the transistor 500A, the insulating layer 545 and a part of the conductive layer 560 are provided so as to sandwich the semiconductor layer 530 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 530 and the conductive layer 560 are provided facing each other with the insulating layer 545 sandwiched between the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530. In other words, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530 each function as a channel formation region. Therefore, compared to when the semiconductor layer 530 is formed in a planar shape, the channel width of the transistor 500A is larger by the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 530.

[0185] By increasing the channel width as described above, the on-state current, transconductance, frequency characteristics, and the like of the transistor 500A can be improved. This makes it possible to provide a transistor with high operating speed. Furthermore, the operating speed of a memory device using the transistor can be increased. Furthermore, in the above structure, by providing the semiconductor layer 530, the channel width can be increased without increasing the area occupied by the transistor 500A. This enables miniaturization or high integration of the transistor. Furthermore, by using the above structure, the area where the conductive layer 560 and the semiconductor layer 530 face each other is increased, so that the transistor 500A can be made normally off by controlling the threshold voltage.

[0186] The upper portion of the semiconductor layer 530 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulating layer 545 and the conductive layer 542 near the upper portion of the semiconductor layer 530.

[0187] Because the semiconductor layer 530 has a high aspect ratio, it is preferably formed in the shape of a sidewall on the side surface of a pillar made of an insulator. Therefore, it is preferable to form the semiconductor layer 530 using the ALD method, which has good coverage. Furthermore, when the semiconductor layer 530 has a stacked structure, it is preferable to form at least one layer, preferably the layer in contact with the pillar, using the ALD method.

[0188] 15A , by forming the semiconductor layers 530 in a sidewall shape in contact with the side surfaces of the plurality of pillars, the plurality of semiconductor layers 530 can be formed simultaneously. By forming the plurality of semiconductor layers 530 in this manner, the distance between the semiconductor layers 530 can be set in accordance with the size and shape of the pillar. Therefore, the distance between the semiconductor layers 530 can be reduced, the area occupied by the transistor 500A can be reduced, and high integration of the transistors can be achieved.

[0189] Since the semiconductor layer 530 is formed in a sidewall shape in contact with the pillar, as shown in FIG. 15A , the top surface shape of the semiconductor layer 530 is a circumferential shape with both ends coinciding (which can also be called a frame shape, annular shape, doughnut shape, or closed curve shape). The semiconductor layer 530 can also be said to have a shape with an opening in the center. Note that in FIG. 15A , the top surface shape of the semiconductor layer 530 is line-symmetrical about A1-A2, but the present invention is not limited to this. For example, the top surface shape of the semiconductor layer 530 may be asymmetrical.

[0190] The structure shown in FIG. 15A has two pillars arranged in the A1-A2 direction, and a circumferential semiconductor layer 530 formed in contact with the side surface of each pillar. As shown in FIG. 15A , the semiconductor layer 530 preferably overlaps with the conductive layer 560 at two or more locations in a top view. That is, the semiconductor layer 530 has two or more overlapping regions with the conductive layer 560. With this structure, as shown in FIG. 15B , multiple fin-shaped semiconductor layers 530 are formed in a cross-sectional view in the channel width direction. Each of the multiple fin-shaped semiconductor layers 530 functions as a channel formation region. That is, the transistor 500A functions as a multi-channel transistor. Therefore, the channel width of the transistor 500A can be further increased.

[0191] 15A to 15D, the transistor 500A applicable to the transistors M1 to M3 may have a structure in which a conductive layer 503 is provided under an insulator 521, as illustrated in a transistor 500B shown in FIGS. 16A to 16D. The conductive layer 503 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 500B. The insulating layer 522 and the insulator 521 each have a region that functions as a second gate insulator of the transistor 500B. Here, FIGS. 16A to 16D correspond to FIGS. 15A to 15D, and therefore the above description can be referred to for detailed configurations.

[0192] In the transistor 500B, the conductive layer 503 is disposed so as to overlap with the semiconductor layer 530 and the conductive layer 560. Here, the conductive layer 503 is preferably provided so as to be embedded in an opening formed in the insulating layer 516. Furthermore, the conductive layer 503 is preferably provided so as to extend in the channel width direction as shown in FIGS. 16A and 16B. With such a structure, when a plurality of transistors are provided, the conductive layer 503 functions as a wiring.

[0193] 16B and 16D, the conductive layer 503 preferably includes a conductive layer 503a and a conductive layer 503b. The conductive layer 503a is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 503b is provided so as to fill a recess in the conductive layer 503a formed along the opening. Here, the height of the upper surface of the conductive layer 503 coincides with or approximately coincides with the height of the upper surface of the insulating layer 516.

[0194] Here, the conductive layer 503a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0195] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 503a, impurities such as hydrogen contained in the conductive layer 503b can be prevented from diffusing into the semiconductor layer 530 through the insulating layer 516 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 503a, oxidation of the conductive layer 503b and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 503a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 503a preferably contains titanium nitride.

[0196] The conductive layer 503b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0197] The conductive layer 503 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500B can be controlled by changing the potential applied to the conductive layer 503 independently of the potential applied to the conductive layer 560. In particular, applying a negative potential to the conductive layer 503 can increase the Vth of the transistor 500B and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 503 can reduce the drain current when the potential applied to the conductive layer 560 is 0 V compared to when a negative potential is not applied.

[0198] The electrical resistivity of the conductive layer 503 is designed in consideration of the potential applied to the conductive layer 503, and the film thickness of the conductive layer 503 is set to match the electrical resistivity. The film thickness of the insulating layer 516 is approximately the same as that of the conductive layer 503. Here, it is preferable to make the film thicknesses of the conductive layer 503 and the insulating layer 516 thin within the range permitted by the design of the conductive layer 503. By making the film thickness of the insulating layer 516 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 516 can be reduced, and therefore, the diffusion of the impurities into the semiconductor layer 530 can be suppressed.

[0199] Although the above describes a stacked structure of the conductive layer 503a and the conductive layer 503b, the present invention is not limited to this, and the conductive layer 503 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 503 has a three-layer stacked structure, a conductor made of the same material as the conductive layer 503a can be provided on the conductive layer 503b in the stacked structure of the conductive layer 503a and the conductive layer 503b. In this case, the conductor may be formed so that the top surface of the conductive layer 503b is lower than the top of the conductive layer 503a and fills the recess formed by the conductive layer 503a and the conductive layer 503b.

[0200] <Configuration Example of DOSRAM> Fig. 17 shows a cross-sectional configuration example when a DOSRAM circuit configuration is used. Fig. 17 illustrates a case where element layers UF[1] to UF[3] are stacked on an element layer LF. Fig. 18A shows an example of the cross-sectional structure of element layer UF[k]. Fig. 18B shows an equivalent circuit diagram of Fig. 18A.

[0201] 17, each of the multiple element layers UF has multiple memory cells 41. In each of the element layers UF[1] to UF[3] illustrated in FIG. 17, two memory cells 41 are connected to one bit line BL. The memory cell 41 illustrated in FIG. 17 includes a transistor M1 and a capacitor C1. In the memory cell 41 illustrated in FIG. 17, the capacitor C1 is provided below the transistor M1. An OS transistor can be used as the transistor M1.

[0202] Furthermore, conductive layers 363a, 363b, and 363c are embedded in the interlayer film between the element layer LF and the element layer UF[1]. Furthermore, in each of the multiple element layers UF, a conductive layer 365 is embedded in the insulating layer 180, which will be described later. Furthermore, in each of the multiple element layers UF, a conductive layer 366 is embedded in the insulating layer 180 and the insulating layer 280, which will be described later. Furthermore, in each of the multiple element layers UF, a conductive layer 367 is embedded in the semiconductor layer 270, the insulating layer 250, and the insulating layer 285, which will be described later. The conductive layers 363a, 363b, 363c, 365, 366, and 367 function as vias, contact plugs, or wiring.

[0203] Next, a configuration example of the memory cells 41 included in the plurality of element layers UF shown in FIG. 17 will be described.

[0204] Fig. 19A is a plan view showing an example of the configuration of a memory cell 41 and its periphery included in each of multiple element layers UF. Fig. 19B is a plan view in which some of the components shown in Fig. 19A are omitted. Fig. 19C is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 19A. Note that in Fig. 19A, some of the components of the transistor VM1, such as the insulating layer 250, are omitted. Furthermore, some of the components, such as the insulating layer, are omitted in the plan views of subsequent transistors as well.

[0205] 19A to 19C, the transistor VM1 corresponds to the transistor M1 in FIG. 17, and the capacitor VC1 corresponds to the capacitor C1 in FIG.

[0206] In FIG. 19C, insulating layer 160 is disposed on a substrate (not shown), insulating layer 180 is disposed on insulating layer 160, insulating layer 280 is disposed on insulating layer 180, and insulating layer 285 is disposed on insulating layer 280.

[0207] A conductive layer 110 is provided on the insulating layer 160. As an example, the conductive layer 110 can be a wiring PL extending in the Y direction.

[0208] An opening 601 is provided in a region of the insulating layer 180 that overlaps with the conductive layer 110. The conductive layer 115 is provided so as to be in contact with the bottom surface and sidewall of the opening 601. That is, the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 and a region in contact with the side surface of the insulating layer 180 in the opening 601. Note that in FIG. 19C , the conductive layer 115 has a region in contact with the top surface of the insulating layer 180.

[0209] An insulating layer 130 is provided on the insulating layer 180 and the conductive layer 115. A conductive layer 220 is provided on the insulating layer 130. The conductive layer 220 is provided so as to fill the opening 601.

[0210] The capacitor VC1 includes a conductive layer 115, a conductive layer 220, and an insulating layer 130.

[0211] In the capacitor VC1, the conductive layer 115 functions as one of a pair of electrodes, the conductive layer 220 functions as the other of the pair of electrodes, and the insulating layer 130 functions as a dielectric sandwiched between the pair of electrodes.

[0212] The transistor VM1 is provided above the capacitor VC1. The transistor VM1 includes a conductive layer 220, a conductive layer 240, a semiconductor layer 270, an insulating layer 250, and a conductive layer 260.

[0213] In the transistor VM1, the conductive layer 260 functions as a gate electrode, and the insulating layer 250 functions as a gate insulating film. The conductive layer 220 and the conductive layer 240 function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 220 also functions as the other of the pair of electrodes of the capacitor VC1.

[0214] The entire region of the semiconductor layer 270 that faces the gate electrode via the gate insulating film between the source electrode and the drain electrode functions as a channel formation region. The region of the semiconductor layer 270 that contacts the source electrode functions as a source region, and the region that contacts the drain electrode functions as a drain region.

[0215] The insulating layer 280 can function as an interlayer insulating layer. The interlayer insulating layer here can be an interlayer film for separating the source electrode and the gate electrode of the transistor VM1.

[0216] The conductive layer 240 is provided on the insulating layer 280. The insulating layer 280 has an opening 602 that reaches the conductive layer 220. The conductive layer 240 has an opening 603 that reaches the opening 602. That is, the opening 603 has a region that overlaps with the opening 602.

[0217] 19A shows conductive layers 220, 240, 260, and openings 602 and 603 as components of the transistor VM1. Here, FIG. 19B shows a configuration example in which the conductive layer 260 is omitted from the components shown in FIG. 19A. That is, FIG. 19B shows only the conductive layers 220, 240, and openings 602 and 603.

[0218] 19A and 19B show an example in which the shapes of the openings 602 and 603 are each circular in a plan view. By making the planar shapes of the openings 602 and 603 circular, the processing accuracy when forming the openings 602 and 603 can be improved, and the openings 602 and 603 can be formed in microscopic sizes. This allows for miniaturization or high integration of memory cells. Note that in this specification, a circle is not limited to a perfect circle. For example, the planar shapes of the openings 602 and 603 may be elliptical or may be a shape including curves. Alternatively, they may be polygonal, or may be polygonal with rounded corners.

[0219] The description of the shapes of the openings 602 and 603 can also be applied to the opening 601 .

[0220] The conductive layer 240 is preferably not provided inside the opening 602. In other words, the conductive layer 240 is preferably not in contact with the side surface of the insulating layer 280 on the opening 602 side. With this structure, the opening 603 and the opening 602 can be formed at the same time, thereby simplifying the process.

[0221] 19C shows an example in which the bottom edge of the conductive layer 240 in the opening 603 coincides with or roughly coincides with the top edge of the insulating layer 280 in the opening 602. In this specification and the like, the bottom surface of the conductive layer 240 refers to the surface on the insulating layer 280 side. The top surface of the insulating layer 280 refers to the surface on the conductive layer 240 side.

[0222] Incidentally, "the edges are aligned or approximately aligned" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, and when the planar shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, it is also said that the edges are approximately aligned or the planar shapes are approximately aligned.

[0223] Hereinafter, an opening including openings 602 and 603 may be referred to as opening 290. That is, opening 290 reaching conductive layer 220 is provided in insulating layer 280 and conductive layer 240. Opening 602 is a part of opening 290, and opening 603 is another part of opening 290.

[0224] At least a portion of the semiconductor layer 270 is disposed in the opening 290. In the opening 290, the semiconductor layer 270 has a region in contact with a side surface of the conductive layer 240, a region in contact with a side surface of the insulating layer 280, and a region in contact with the top surface of the conductive layer 220. The semiconductor layer 270 has a region in contact with the top surface of the conductive layer 240.

[0225] At least a portion of the insulating layer 250 is disposed in the opening 290. The insulating layer 250 is provided on the semiconductor layer 270 and the insulating layer 280. The insulating layer 250 has a region in contact with the top surface of the semiconductor layer 270, a region in contact with the side surface of the semiconductor layer 270, a region in contact with the side surface of the conductive layer 240, and a region in contact with the top surface of the insulating layer 280.

[0226] The conductive layer 260 is provided on the insulating layer 250, and has a region in contact with the upper surface of the insulating layer 250. The conductive layer 260 is provided so as to fill the opening 290. The conductive layer 260 is provided so as to fill a recess in the insulating layer 250 that reflects the shape of the opening 290. The conductive layer 260 has a region that overlaps with the semiconductor layer 270, with the insulating layer 250 interposed therebetween.

[0227] 19C shows an example in which the conductive layer 260 has a region overlapping with the conductive layer 240 with the insulating layer 250 and the semiconductor layer 270 interposed therebetween, but the present invention is not limited to this. For example, the conductive layer 260 may be provided so as not to overlap with the conductive layer 240. With such a structure, parasitic capacitance occurring between the conductive layer 260 and the conductive layer 240 can be reduced. Therefore, the operating speed of the memory cell can be improved.

[0228] The transistor VM1 is configured such that the direction of the channel length is not substantially parallel to the substrate (not shown) but is along the sidewall of an opening 602 provided in the insulating layer 280. In this specification and the like, such a transistor may be referred to as a vertical transistor.

[0229] In a vertical transistor, the source region, the channel formation region, and the drain region can at least partially overlap each other in a plan view, which allows the area occupied by the vertical transistor (also referred to as a footprint) to be reduced.Furthermore, the vertical transistor has a structure that allows the channel length to be reduced and the channel width to be increased, which allows the on-resistance to be reduced (the on-current to be increased).

[0230] FIG. 19A shows an example in which the conductive layer 240 extends in a direction perpendicular to the conductive layers 110 and 260 .

[0231] Here, an enlarged view of the semiconductor layer 270 and its vicinity in Fig. 19C is shown in Fig. 20A, and a cross-sectional view in the XY plane including the conductive layer 240 is shown in Fig. 20B.

[0232] As shown in FIG. 20A, the semiconductor layer 270 has a region 270i, and regions 270na and 270nb that are provided so as to sandwich the region 270i.

[0233] Region 270na is a region of semiconductor layer 270 that contacts conductive layer 220. Region 270nb is a region of semiconductor layer 270 that contacts conductive layer 240. Region 270na and region 270nb each function as a source region or a drain region of transistor VM1. As shown in FIG. 20B , conductive layer 240 contacts the entire periphery of semiconductor layer 270. Therefore, the source region or drain region of transistor VM1 can be formed around the entire periphery of a portion of semiconductor layer 270 that is formed in the same layer as conductive layer 240.

[0234] Region 270i is a region in the semiconductor layer 270 that is sandwiched between regions 270na and 270nb. Region 270i functions as a channel formation region of transistor VM1. That is, the channel formation region of transistor VM1 is formed in a part of the semiconductor layer 270 that is located in a region between the conductive layer 220 and the conductive layer 240. It can also be said that the channel formation region of transistor VM1 is located in a region in contact with the insulating layer 280 or in a region in the vicinity of the insulating layer 280 in the semiconductor layer 270.

[0235] The channel length of the transistor VM1 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor VM1 is determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 20A , the channel length L of the transistor VM1 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the edge of the region where the semiconductor layer 270 and the conductive layer 220 contact each other and the edge of the region where the semiconductor layer 270 and the conductive layer 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 602 side in a cross-sectional view.

[0236] In a planar transistor, the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor VM1 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor VM1, thereby improving the frequency characteristics. Therefore, a semiconductor device with high operating speed can be provided.

[0237] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. This allows the area occupied by the transistor VM1 to be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for a higher integration of the semiconductor device, thereby increasing the storage capacity per unit area.

[0238] Furthermore, in the XY plane including the channel formation region of the semiconductor layer 270, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are arranged concentrically, as in FIG. 20B . Therefore, the side surface of the centrally located conductive layer 260 faces the side surface of the semiconductor layer 270 via the insulating layer 250. In other words, in a top view, the entire periphery of the semiconductor layer 270 forms the channel formation region. In this case, for example, the channel width of the transistor VM1 is determined by the outer periphery of the semiconductor layer 270. In other words, the channel width of the transistor VM1 can be determined by the maximum width of the opening 602. In FIGS. 20A and 20B , the maximum width D of the opening 602 is indicated by a double-headed, dashed arrow. In FIG. 20B , the channel width W of the transistor VM1 is indicated by a double-headed, dashed arrow. Increasing the maximum width D of the opening 602 increases the channel width per unit area, thereby increasing the on-current.

[0239] When the opening 602 is formed using photolithography, the maximum width D of the opening 602 is set by the exposure limit of photolithography. The maximum width D of the opening 602 is set by the film thickness of each of the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 provided in the opening 602. The maximum width D of the opening 602 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 602 is circular in top view, the maximum width D of the opening 602 corresponds to the diameter of the opening 602, and the channel width W can be calculated as "D × π".

[0240] The maximum width D of the opening 602 may be calculated appropriately according to the shape of the opening 602 in a planar view. For example, if the opening 602 is rectangular in a planar view, the maximum width of the opening 602 may be the length of the diagonal of the rectangle. Alternatively, for example, if the opening 602 is elliptical, polygonal, or polygonal with rounded corners in a planar view, the maximum width of the opening 602 may be the diameter of the smallest circle (also referred to as the minimum encompassing circle) that encompasses the shape of the opening 602 in a planar view.

[0241] In the semiconductor device of one embodiment of the present invention, the channel length L of the transistor VM1 is preferably smaller than at least the channel width W of the transistor VM1. The channel length L of the transistor VM1 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor VM1. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0242] Furthermore, by forming the opening 602 so as to have a substantially circular shape in top view, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the semiconductor layer 270 substantially uniform, allowing a gate electric field to be applied to the semiconductor layer 270 substantially uniformly.

[0243] 20A and other drawings, the opening 602 is provided so that the side surface of the opening 602 is perpendicular to the upper surface of the conductive layer 220, but the present invention is not limited to this. For example, the side surface of the opening 602 may be tapered.

[0244] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface. For example, it is preferable that the structure has a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0245] 19C , a portion of insulating layer 250 is located outside opening 603, i.e., on insulating layer 280. In this case, insulating layer 250 preferably covers the side edges of conductive layer 240. This can prevent conductive layer 260 and conductive layer 240 from shorting out.

[0246] The semiconductor layer 270 can be a single layer or a stack of semiconductors that can be used for the semiconductor layer 530. For the structure of the semiconductor layer 270, the structure of the semiconductor layer 530 can also be referred to.

[0247] The semiconductor layer 270 preferably has layered crystals that are approximately parallel to the side surface of the insulating layer 280 in the opening 602. With this configuration, the layered crystals of the semiconductor layer 270 are formed approximately parallel to the channel length direction of the transistor VM1, thereby increasing the on-state current of the transistor.

[0248] When the semiconductor layer 270 and the conductive layer 220 come into contact with each other, a metal compound or oxygen vacancy is formed, and the resistance of a region 270na of the semiconductor layer 270 decreases. When the semiconductor layer 270 comes into contact with the conductive layer 220, the resistance of the semiconductor layer 270 and the conductive layer 220 decreases, thereby reducing the contact resistance between the semiconductor layer 270 and the conductive layer 220. Similarly, when the semiconductor layer 270 and the conductive layer 240 come into contact with each other, the resistance of a region 270nb of the semiconductor layer 270 decreases. Therefore, the contact resistance between the semiconductor layer 270 and the conductive layer 240 can be reduced.

[0249] The conductive layer 240 can have a stacked structure of a first conductive layer and a second conductive layer over the first conductive layer. In this case, the first conductive layer can be formed using a conductive material with high conductivity, and the second conductive layer can be formed using a conductive material containing oxygen. When an oxide semiconductor is used for the semiconductor layer 270, the contact resistance between the second conductive layer of the conductive layer 240 and the semiconductor layer 270 can be reduced by using a conductive material containing oxygen for the second conductive layer of the conductive layer 240 that is in contact with the semiconductor layer 270, thereby suppressing a decrease in the on-state current of the transistor VM1 due to the contact resistance. For example, tungsten can be used for the first conductive layer of the conductive layer 240, and indium tin oxide containing silicon can be used for the second conductive layer of the conductive layer 240.

[0250] The conductive layer 220 has a recessed portion at a position overlapping with the opening 602. The semiconductor layer 270 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220. Note that the recessed portion of the conductive layer 220 may be regarded as part of the opening 290.

[0251] By providing a recess in the position where the conductive layer 220 overlaps with the opening 602, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be made lower than the height of the top surface of the conductive layer 220 that is in contact with the insulating layer 280, with the top surface of the insulating layer 160 as the reference, compared to when the recess is not provided. Here, the height of each surface can be determined with the surface on which the memory cell or transistor is formed as the reference. Here, the top surface of the insulating layer 160 is used as the reference. The surface used as the reference is not particularly limited, and may be, for example, the top surface of a substrate on which the memory cell or transistor is provided as the reference.

[0252] This increases the contact area between the conductive layer 220 and the semiconductor layer 270, thereby reducing the contact resistance between the conductive layer 220 and the semiconductor layer 270. Therefore, a decrease in the on-state current of the transistor VM1 due to the contact resistance between the conductive layer 220 and the semiconductor layer 270 can be suppressed. Furthermore, a gate electric field is more easily applied to the channel formation region of the semiconductor layer 270, thereby improving the electrical characteristics of the transistor VM1. Furthermore, a gate electric field is more easily applied to the region of the semiconductor layer 270 that is in contact with the conductive layer 220, thereby increasing the on-state current of the transistor VM1. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor VM1 can be improved.

[0253] A conductive material containing oxygen is preferably used for the conductive layer 220. When an oxide semiconductor is used for the semiconductor layer 270, the use of a conductive material containing oxygen for the conductive layer 220 can reduce contact resistance between the semiconductor layer 270 and the conductive layer 220.

[0254] Alternatively, the conductive layer 220 may have a structure in which tungsten is stacked under a conductive material containing oxygen. By providing tungsten in this manner, the conductivity of the conductive layer 220 can be improved.

[0255] The insulating layers 280 and 285 preferably have a low dielectric constant because they function as interlayer films. By using a material with a low dielectric constant as the interlayer film, the capacitance value of parasitic capacitance generated between wirings can be reduced.

[0256] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 270.

[0257] An insulator containing excess oxygen is preferably used for the insulating layer 280. By performing heat treatment on the insulating layer 280 containing excess oxygen, oxygen is supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 270, and oxygen vacancies and V Ｏ It is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor VM1 and improve reliability.

[0258] Note that a transistor that can be used in the present invention is not limited to the transistor VM1 shown in Figure 19C. For example, a transistor VM2 having a structure shown in Figure 21 may be used. The transistor VM2 shown in Figure 21 differs from the transistor VM1 shown in Figure 19C in that a conductive layer 215 and an insulating layer 225 are provided.

[0259] The configuration shown in Fig. 21 corresponds to the memory cell 41A shown in Fig. 6A. In the memory cell 41A shown in Fig. 21, a transistor VM2 is provided above a capacitor VC1.

[0260] 21 , a conductive layer 215 is provided on an insulating layer 280. An insulating layer 281 is disposed on the insulating layer 280 and the conductive layer 215. A conductive layer 240 is provided on the insulating layer 281.

[0261] An opening 604 reaching the conductive layer 220 is provided in the insulating layer 280, the conductive layer 215, the insulating layer 281, and the conductive layer 240. The opening 604 includes an opening in the insulating layer 280, an opening in the conductive layer 215, an opening in the insulating layer 281, and an opening in the conductive layer 240. The sidewalls of the opening 604 include the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 215, the side surfaces of the insulating layer 281, and the side surfaces of the conductive layer 240.

[0262] Each of the insulating layer 225, the semiconductor layer 270, the insulating layer 250, and the conductive layer 220 is provided so that at least a portion thereof is located in the opening 604. Specifically, the insulating layer 225 is provided so as to cover a portion of the bottom and the sidewall of the opening 290, the semiconductor layer 270 is provided so as to cover another portion of the bottom of the opening 290 and the insulating layer 225, and the insulating layer 250 is provided so as to cover the semiconductor layer 270. Then, the conductive layer 260 is provided so as to fill a recess in the insulating layer 250 that reflects the shape of the opening 604.

[0263] Insulating layer 225 contacts part of the top surface of conductive layer 220 , the side surfaces of insulating layer 280 , conductive layer 215 , insulating layer 281 , and conductive layer 240 in opening 604 .

[0264] In the transistor VM2 shown in FIG. 21, the semiconductor layer 270 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating film, the conductive layer 215 functions as a second gate electrode, the insulating layer 225 functions as a second gate insulating film, and the conductive layer 220 and the conductive layer 240 function as a source electrode or a drain electrode, respectively.

[0265] The potential applied to the conductive layer 215 is changed independently of the potential applied to the conductive layer 260, and the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 215, the V ｔｈTherefore, when a negative potential is applied to the conductive layer 215, the drain current when the potential applied to the conductive layer 260 is 0 V can be made smaller than when a negative potential is not applied. Note that the conductive layer 260 may function as a second gate electrode, and the conductive layer 215 may function as a first gate electrode.

[0266] Alternatively, the conductive layer 215 may be connected to the conductive layer 260. Connecting the conductive layer 215 and the conductive layer 260 and applying the same potential to them makes it possible to increase the on-current, reduce variations in initial characteristics, suppress deterioration of electrical characteristics in a negative GBT (Gate Bias-Temperature) stress test, and suppress fluctuations in the on-current rise voltage at different drain voltages.

[0267] As described above, the transistor VM2 illustrated in FIG. 21 includes the first gate electrode and the second gate electrode, and therefore the electrical characteristics of the transistor included in the semiconductor device can be improved.

[0268] <Configuration Example 2 of NOSRAM> Figures 22A and 22B show an example of a transistor configuration applicable to a two-transistor NOSRAM circuit configuration. Figure 22A is an example of a perspective view of a semiconductor device in which multiple memory cells 41F, each having a stacked transistor VT1 and a transistor VT2, are arranged side by side. Transistors VT1 and VT2 are vertical transistors. Memory cell 41F is connected to conductive layer 220a, conductive layer 240a, conductive layer 240b, and conductive layer 210. Note that, for clarity, insulating layers such as interlayer films are not shown in Figure 22A, and the uppermost conductive layer 210 is indicated by a dashed line.

[0269] The conductive layer 220a shown in Fig. 22A functions as the read bit line RBL shown in Fig. 6F etc. The conductive layer 240a shown in Fig. 22A functions as the read word line RWL shown in Fig. 6F etc. The conductive layer 240b shown in Fig. 22A functions as the write bit line WBL shown in Fig. 6F etc. The conductive layer 210 shown in Fig. 22A functions as the write word line WWL shown in Fig. 6F etc.

[0270] In the memory cell 41F shown in Fig. 22A, a transistor VT2 is provided above a transistor VT1. The transistor VT2 shown in Fig. 22A corresponds to the transistor M1 of the memory cell 41F shown in Fig. 6F. The transistor VT1 shown in Fig. 22A corresponds to the transistor M2 of the memory cell 41F shown in Fig. 6F.

[0271] Although FIG. 22A shows an example in which the memory cells 41F are arranged at equal intervals in the X and Y directions, the memory cells 41F may be arranged in a staggered manner, with each memory cell 41F being shifted alternately.

[0272] The transistor VT1 includes a conductive layer 220a, a conductive layer 240a, and a conductive layer 260a as its components, and the transistor VT2 includes a conductive layer 260a, a conductive layer 240b, and a conductive layer 260b as its components.

[0273] Next, a configuration example of memory cell 41F will be described. Fig. 22B is a perspective view illustrating the configuration example of memory cell 41F. For clarity, insulating layers such as interlayer films are not shown, and conductive layer 220a, parts of conductive layer 240a and conductive layer 240b, and conductive layer 210 are shown by dashed lines.

[0274] The memory cell 41F shown in FIG. 22B has a configuration in which, in the transistor VT1, a semiconductor layer 270a is provided in an opening provided in a conductive layer 240a, and the side surface of the conductive layer 240a in the opening contacts the semiconductor layer 270a.

[0275] 23A is a plan view illustrating the transistor VT1, and FIG. 23B is a plan view illustrating the transistor VT2. Note that in the plan views, some elements are omitted for clarity.

[0276] Fig. 23C is a diagram corresponding to a cross section taken along line A1-A2 in Fig. 23A and Fig. 23B. Fig. 23D is a diagram corresponding to a cross section taken along line B1-B2 in Fig. 23A and Fig. 23B.

[0277] The memory cell 41F includes an insulating layer 160 on a substrate (not shown), a transistor VT1 provided on the insulating layer 160, and a transistor VT2 provided on the transistor VT1. Note that insulating layers 280a, 280b, 285, and the like that function as interlayer films can be provided between the transistors and between various wirings.

[0278] The transistor VT1 includes a conductive layer 220a, a conductive layer 240a, a semiconductor layer 270a, an insulating layer 250a, and a conductive layer 260a. In the transistor VT1, the semiconductor layer 270a functions as a semiconductor layer, the conductive layer 260a functions as a gate electrode, and the insulating layer 250a functions as a gate insulating film. The conductive layer 220a and the conductive layer 240a function as a source electrode and a drain electrode, respectively.

[0279] That is, the transistor VT1 has a structure corresponding to the structure of the transistor VM1 shown in FIG. 19C. Therefore, in the figure, the corresponding components in the transistor VM1 and the transistor VT1 are basically designated by the same three-digit numeral. Also, hereinafter, unless otherwise specified, the description of the transistor VM1 can be referred to for the transistor VT1.

[0280] The transistor VT2 includes a conductive layer 260a, a conductive layer 240b, a semiconductor layer 270b, an insulating layer 250b, and a conductive layer 260b. In the transistor VT2, the semiconductor layer 270b functions as a semiconductor layer, the conductive layer 260b functions as a gate electrode, and the insulating layer 250b functions as a gate insulating film. The conductive layers 260a and 260b function as source and drain electrodes.

[0281] That is, the transistor VT2 has a structure corresponding to the structure of the transistor VM1 shown in FIG. 19C. Therefore, in the figure, the corresponding components in the transistors VM1 and VT2 are basically designated by the same three-digit numeral. Also, hereinafter, unless otherwise specified, the description of the transistor VM1 can be referred to for the transistor VT2. The conductive layer 260a corresponds to the conductive layer 220 in the transistor VM1. Therefore, the description of the conductive layer 220 described above can be referred to for the conductive layer 260a.

[0282] The transistor VM1 shown in FIG. 21 may be applied to one or both of the transistors VT1 and VT2.

[0283] In other words, the conductive layer 260a has a region that shares the gate electrode of the transistor VT1 and one of the source electrode and drain electrode of the transistor VT2.

[0284] The conductive layer 260b is connected to the conductive layer 210 formed on the conductive layer 260b. The conductive layer 260b and the conductive layer 210 may be formed as the same element.

[0285] The conductive layers 260a and 260b preferably have a substantially circular top surface shape. Such a structure can increase the integration degree of the memory cell 41F. Note that the above description of the shape of the opening 602 and the like can be referred to for the top surface shapes of the conductive layers 260a and 260b.

[0286] In order to increase the overlapping area of ​​the transistors VT2 and VT1, it is preferable that the top surface shape of the opening 290b and the top surface shape of the opening 290a in which the transistor VT1 is formed are the same or similar.

[0287] <Constituent Materials of Semiconductor Device> Constituent materials that can be used in the semiconductor device will be described below.

[0288] [Substrate] Substrates that can be used in semiconductor devices include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate having elements provided thereon may be used, such as a capacitor, a resistor, a switch, a light-emitting element, a memory element, and the like.

[0289] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0290] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the capacitance value of the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the insulator's function. Note that materials with a low dielectric constant also have high dielectric strength.

[0291] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0292] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0293] Furthermore, a transistor using an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0294] An insulating layer, such as a gate insulating film, that is in contact with a semiconductor layer or that is provided near the semiconductor layer preferably has a region containing excess oxygen. For example, by providing an insulating layer having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0295] Examples of insulators having a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0296] Examples of insulators having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0297] An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be said to be an insulator having a barrier property against one or both of oxygen and hydrogen.

[0298] Furthermore, examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. These oxides preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. While these metal oxides preferably have an amorphous structure, they may also have crystalline regions formed in some parts.

[0299] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). The function of capturing or fixing (also referred to as gettering) a corresponding substance can be rephrased as barrier properties. When hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "barrier property against oxygen" refers to at least one of oxygen atoms, oxygen molecules, etc., which are difficult to diffuse.

[0300] [Conductor] As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the aforementioned metal element as a component, or an alloy combining the aforementioned metal elements, etc., may be used. As the alloy containing the aforementioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. may be used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0301] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and elsewhere, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0302] Furthermore, conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0303] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0304] When an oxide semiconductor is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0305] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the oxide semiconductor in which a channel is formed. Alternatively, the above-mentioned conductive materials containing the metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator may be captured.

[0306] [Other Semiconductor Materials] The semiconductor material that can be used for the semiconductor layer is not limited to an oxide semiconductor. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor layer. For example, it is preferable to use a semiconductor of a single element, a compound semiconductor, or a layered material (also called an atomic layer material, a two-dimensional material, or the like) as the semiconductor material.

[0307] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0308] Examples of semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0309] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure.

[0310] Layered materials include graphene, silicene, boron carbonitride, and chalcogenides. Boron carbonitride, a layered material, has carbon atoms, nitrogen atoms, and boron atoms arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0311] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to a semiconductor layer, a semiconductor device with a large on-current can be provided.

[0312] According to one embodiment of the present invention, a novel transistor and a novel semiconductor device can be provided. Alternatively, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, a semiconductor device with favorable frequency characteristics can be provided. Alternatively, a semiconductor device with high operating speed can be provided. Alternatively, a semiconductor device with favorable reliability can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, a semiconductor device with favorable electrical characteristics can be provided.

[0313] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0314] Embodiment 3 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0315] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0316] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0317] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0318] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0319] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0320] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0321] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0322] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0323] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0324] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0325] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0326] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0327] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0328] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed using at least two kinds of film formation methods may be referred to as a hybrid OS.

[0329] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by a first deposition method and then forming a metal oxide as a second layer on the first layer by a second deposition method. In this case, it is preferable to use a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the second deposition method as the first deposition method. By using a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the first deposition method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer, thereby increasing the crystallinity of the oxide semiconductor layer.

[0330] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). Examples of wet methods include spray coating. Compared to the sputtering method described below, the ALD and CVD methods are suitable as the first film formation method because they can suppress damage to the surface to be formed.

[0331] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0332] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling ultrathin film formation, film formation on high aspect ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs a high substrate temperature during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0333] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0334] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0335] Examples of the second film formation method include sputtering, pulsed laser deposition (PLD), etc. Metal oxides formed using the second film formation method tend to have a CAAC structure.

[0336] Note that the first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0337] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0338] For example, the oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide as a first layer by a first deposition method, forming a metal oxide as a second layer by a second deposition method, and forming a metal oxide as a third layer by the first deposition method. Specifically, an ALD method can be used as the first deposition method, and a sputtering method can be used as the second deposition method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the deposition method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0339] [Method for Manufacturing Oxide Semiconductor Layer] The oxide semiconductor 230, which is an oxide semiconductor layer, can be manufactured by, for example, forming an oxide semiconductor 230a over the layer 229, which is a surface to be formed, by an ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by a sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by an ALD method. After the oxide semiconductor 230 is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor 230. The heat treatment here is not limited to heat treatment. For example, heat applied during the manufacturing process may be used.

[0340] The oxide semiconductor 230 can be used for the semiconductor layer 530, the semiconductor layer 270, or the like described in the above embodiment. The layer 229 corresponds to the insulating layer 524, the insulating layer 280, the insulating layer 225, the conductive layer 220, or the like described in the above embodiment.

[0341] The layer 229 does not need to be crystalline. When the layer 229 is crystalline, the layer 229 may have a crystal structure with low lattice matching with a metal oxide included in the oxide semiconductor 230.

[0342] An example of a method for manufacturing the oxide semiconductor 230 will be described with reference to FIGS. 24A to 25D.

[0343] First, an oxide semiconductor 230a is formed on the layer 229 by ALD (FIG. 24A). Then, an oxide semiconductor 230b is formed on the oxide semiconductor 230a by sputtering (FIG. 24B).

[0344] When a metal oxide film is formed by a sputtering method, damage to the surface on which the metal oxide film is formed may cause alloying between components contained in the metal oxide film and components contained in the layer on which the metal oxide film is formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the metal oxide film is formed.

[0345] In the method for forming the oxide semiconductor layer of one embodiment of the present invention, the oxide semiconductor 230a is formed between the oxide semiconductor 230b and the layer 229 by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is formed. This prevents alloying of components contained in the oxide semiconductor 230 and components contained in the layer 229, thereby enabling the crystallinity of the oxide semiconductor 230 to be further improved.

[0346] By using the above structure, the thickness of the alloyed region can be reduced, or made so thin that the alloyed region is not observable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 24A and 24B show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor 230a.

[0347] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0348] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 230a being the depth direction. Next, in the profile of quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 230a contains In) that is the main component of the oxide semiconductor 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 230a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0349] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0350] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the oxide semiconductor 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0351] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0352] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor 230 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably between more than 0 nm and 2 nm, more preferably between 1 nm and 2 nm.

[0353] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of the oxide semiconductor 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0354] When the oxide semiconductor 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 24A , the oxide semiconductor 230a may have a region having lower crystallinity than the oxide semiconductor 230b.

[0355] The oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure.

[0356] When the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, sputtering particles or energy imparted to the substrate by the sputtering particles or the like during the formation of the oxide semiconductor 230b may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, causing at least a part of the oxide semiconductor 230a to crystallize.

[0357] In the formation of the oxide semiconductor 230b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, a metal oxide with high crystallinity can be formed in some cases.

[0358] Next, the oxide semiconductor 230c is formed on the oxide semiconductor 230b by ALD (FIG. 24C). The formation of the oxide semiconductor 230c by ALD can be performed by referring to the method for forming the oxide semiconductor 230a.

[0359] When the oxide semiconductor 230c is formed on the oxide semiconductor 230b having the CAAC structure by the ALD method, the oxide semiconductor 230c may grow epitaxially around the oxide semiconductor 230b as a nucleus. Therefore, when the oxide semiconductor 230c is formed, the oxide semiconductor 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 230c.

[0360] Next, a heat treatment step may be performed. This heat treatment step may enhance the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c. Furthermore, if the region is formed only below the oxide semiconductor 230c after film formation by the ALD method, this heat treatment step may cause the region to expand upward ( FIG. 24D ). That is, this heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 230c.

[0361] Furthermore, it is preferable that at least a portion of the oxide semiconductor 230a is converted into CAAC by the heat treatment ( FIG. 24D ). It is expected that the CAAC is easily generated because the mixed layer 231 formed in the oxide semiconductor 230a during the formation of the oxide semiconductor 230b serves as a nucleus or seed. It is preferable that the region in the oxide semiconductor 230a that is converted into CAAC is wide, and it is preferable that the CAAC is converted into CAAC up to the vicinity of the layer 229.

[0362] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 230a, the CAAC can be formed up to the vicinity of the layer 229 regardless of the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0363] 24A to 24D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 24A to 24D can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide film according to one embodiment of the present invention. As shown in FIGS. 24A to 24D , the oxide semiconductors 230a and 230c each have high crystallinity using the highly crystalline oxide semiconductor 230b as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor 230a can be increased by heat treatment during the formation of the oxide semiconductor 230b or after the formation of the oxide semiconductor 230c. The crystallinity of the oxide semiconductor 230c can be increased by heat treatment during the formation of the oxide semiconductor 230c or after the formation of the oxide semiconductor 230c. The heat treatment has an assisting effect of increasing the crystallinity.

[0364] As described above, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the oxide semiconductor 230a and the oxide semiconductor 230c here) can be increased by using the oxide semiconductor 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown by solid-phase growth using the oxide semiconductor 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, that is, a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC).

[0365] In the oxide semiconductor 230, it is preferable that a region having a CAAC structure is widely present throughout the entire layer. Fig. 25A shows the oxide semiconductors 230a, 230b, and 230c each being crystallized. At this time, the boundary between the oxide semiconductors 230a and 230b may not be observed. Also, the boundary between the oxide semiconductors 230b and 230c may not be observed. The oxide semiconductor 230 may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor 230 may be expressed as a single layer.

[0366] Furthermore, there are cases where a portion of the oxide semiconductor 230a or the oxide semiconductor 230c is not crystallized. The example shown in Fig. 25B illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a is not crystallized. Fig. 25C illustrates a state in which the vicinity of the surface in the oxide semiconductor 230c is not crystallized. Fig. 25D illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a and the vicinity of the surface of the oxide semiconductor 230c are not crystallized.

[0367] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0368] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 230, the boundaries between the stacked films of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0369] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the oxide semiconductors 230a and 230c, crystals that reflect the crystal orientation of the oxide semiconductor 230b are formed, thereby suppressing polycrystallization.

[0370] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 230b and the crystals of the oxide semiconductor 230a or the oxide semiconductor 230c is small. This allows the oxide semiconductor 230a or the oxide semiconductor 230c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 230b. In this case, for example, when a cross section of the oxide semiconductor 230 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the oxide semiconductor 230a or the oxide semiconductor 230c.

[0371] The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c is not particularly limited as long as the lattice mismatch between the crystal of the oxide semiconductor 230b and the crystal of the oxide semiconductor 230a or the oxide semiconductor 230c is small. The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0372] [Composition of Oxide Semiconductor Layer] As described above, the oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed by, for example, a sputtering method. The oxide semiconductor 230b preferably contains, for example, zinc. The inclusion of zinc results in a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 230b preferably contains the element M in addition to zinc. The inclusion of the element M in the oxide semiconductor 230b can, for example, prevent oxygen vacancies from being formed in the metal oxide. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved. Specifically, the oxide semiconductor 230b may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, or an atomic ratio of In:M:Zn = 1:3:4 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0373] The oxide semiconductor 230b may not contain the element M. For example, it may be an In—Zn oxide. Specifically, it may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, it may have a composition containing a trace amount of the element M. For example, it may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, it may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0374] The oxide semiconductor 230a and the oxide semiconductor 230c can be metal oxides having a high proportion of In. The oxide semiconductor 230a and the oxide semiconductor 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current and frequency characteristics can be increased.

[0375] Alternatively, the oxide semiconductors 230a and 230c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition of In:Zn=1:1 (atomic ratio) or a composition therearound, a composition of In:Zn=2:1 (atomic ratio) or a composition therearound, or a composition of In:Zn=4:1 (atomic ratio) or a composition therearound. Alternatively, indium oxide may be used. The oxide semiconductors 230a and 230c may contain a trace amount of the element M. Specifically, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition close thereto, In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition close thereto.

[0376] The oxide semiconductors 230a and 230c can be metal oxides containing a higher proportion of In than the oxide semiconductor 230b.

[0377] Alternatively, for example, metal oxides having a higher Ga content than the oxide semiconductor 230b may be used for the oxide semiconductors 230a and 230c. For example, the oxide semiconductors 230a and 230c may be metal oxides having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout, metal oxides having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout, or metal oxides having an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereabout. Increasing the Ga content may result in the band gaps of the oxide semiconductors 230a and 230c being larger than those of the oxide semiconductor 230b. As a result, the oxide semiconductor 230b is sandwiched between the oxide semiconductors 230a and 230c, which have larger band gaps, and the oxide semiconductor 230b mainly functions as a current path (channel). The oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c, whereby trap states at the interface of the oxide semiconductor 230b and in the vicinity thereof can be reduced, thereby realizing a buried channel transistor in which the channel is located away from the insulating layer interface, and thereby increasing the field-effect mobility.

[0378] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 230a and 230c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the oxide semiconductor 230b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor 230a and the oxide semiconductor 230c and the oxide semiconductor 230b.

[0379] In particular, even when the oxide semiconductor 230 a and the oxide semiconductor 230 c have a high In content, the oxide semiconductor layer can have suitable crystallinity for a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0380] The oxide semiconductor 230a and the oxide semiconductor 230c may have different compositions.

[0381] The oxide semiconductor 230a and the oxide semiconductor 230c may be made of a metal oxide having the same composition as the oxide semiconductor 230b.

[0382] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0383] The composition of the metal oxide used in the oxide semiconductor 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0384] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0385] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0386] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0387] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0388] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be a circle with a diameter of 1.0 nm, for example. Note that the region where FFT is performed is not limited to a circle.

[0389] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0390] The c-axis orientation rates of the region where the oxide semiconductor 230a is formed, the region where the oxide semiconductor 230b is formed, and the region where the oxide semiconductor 230c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0391] After the oxide semiconductor 230 is formed, the boundaries between the oxide semiconductors 230a, 230b, and 230c may not be clearly observed.

[0392] The oxide semiconductor 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region has a layer shape.

[0393] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rates of the second region and the third region are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0394] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor 230 .

[0395] Alternatively, the layer thickness in each region may be approximately the same, for example.

[0396] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0397] In this embodiment, electronic components, electronic devices, and large scale computers that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, and large scale computers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0398] [Electronic Component] FIG. 26A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 709 is mounted. The electronic component 709 shown in FIG. 26A has a semiconductor device 710 inside a mold 711. FIG. 26A omits some parts in order to show the interior of the electronic component 709. The electronic component 709 has lands 712 on the outside of the mold 711. The lands 712 are connected to electrode pads 713, and the electrode pads 713 are connected to the semiconductor device 710 via wires 714. The electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on the printed circuit board 702 to complete the mounting substrate 704.

[0399] The semiconductor device 710 also includes a layer 715 having an arithmetic core and a layer 716 having a memory. The layer 716 having the memory is configured by stacking multiple memory cell arrays. The stacked configuration of the layer 715 having the arithmetic core and the layer 716 having the memory can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the layer 715 having the arithmetic core and the layer 716 having the memory as a monolithic stack, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0400] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0401] Furthermore, it is preferable that the memory cell arrays included in the memory-containing layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used in the memory-containing layer 716, it is more difficult to achieve a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0402] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0403] 26B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.

[0404] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0405] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0406] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0407] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0408] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0409] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0410] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 26B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0411] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0412] 27A to 27D are diagrams illustrating configuration examples different from the electronic components 709 and 730 described above in Fig. 26A and Fig. 26B. Electronic components 730A to 730D illustrated in Fig. 27A to 27D have a configuration in which a layer 715 having an arithmetic core and a layer 716 having a memory are provided in a mold 711 on an interposer 731 provided with the above-described electrodes 733.

[0413] In the configuration of electronic component 730A shown in FIG. 27A , layer 715 having processor cores is provided on interposer 731 and connected to electrode pads (not shown) via wires 714. Layer 716 having memory formed on layer 715 having processor cores has the monolithic stack configuration described above. In the monolithic stack configuration, layer 716 having memory and layer 715 having processor cores are connected. Therefore, wires 714 between interposer 731 and layer 715 having processor cores can also serve as wiring between each layer having memory 716 and interposer 731, thereby reducing the number of wires.

[0414] While the configuration example of FIG. 27A illustrates a single monolithic stacked structure, a configuration in which an electronic component having a monolithic stacked structure is stacked with other electronic components is also possible. For example, as shown in FIG. 27B , a configuration in which a monolithic stacked structure is formed by stacking a layer 716A having memory and a layer 715A having an arithmetic core, and a layer 716B having memory and a layer 715B having an arithmetic core, are stacked together. The monolithic stacked structure stacked with other electronic components is fixed to a resin sheet 744 by an adhesive layer 743. This configuration allows for stacking multiple memory cell arrays with different circuit configurations. Having different circuit configurations allows for semiconductor devices with different memory bandwidths and memory access latencies, making it suitable for use in hierarchical structures such as cache memories.

[0415] The configuration example of FIG. 27A can also be stacked with other electronic components. For example, as shown in FIG. 27C , an electronic component having a layer 715C with an operational core such as a processor provided in a mold 711 between interposers 731A and 731B, and the above-described electronic component 730A can be stacked to form electronic component 730C. The circuit layers can be connected via conductors such as electrodes 733. This configuration enables the processor and memory interface to operate at high speed. Furthermore, a gap (space) can be provided between the mold including the operational core layer 715C and the electronic component 730A, thereby making it difficult for heat generated in the operational core layer 715C to be transmitted to the electronic component 730A.

[0416] 27C , a memory layer having an OS transistor may be provided on a layer 715C having an arithmetic core such as a processor. For example, as shown in FIG. 27D , a memory layer 716C may be provided on the arithmetic core layer 715C, and stacked with electronic components 730A. This configuration enables the high-speed operation of the interface between a so-called on-chip memory configuration in which memory is formed directly on a processor and a semiconductor device configuration having stacked memory layers.

[0417] [Electronic Device] Fig. 28A is an external view showing an example of a portable electronic device. Fig. 28B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0418] In the portable electronic device 595, the electronic component 709 can be provided on the printed circuit board 596. The portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by the speaker 597, the camera 598, the microphone 599, etc. using the electronic component 709. The portable electronic device 595 can also be used in systems that perform voice guidance, image search, etc.

[0419] The electronic component 709 performs arithmetic processing of the obtained image data using a neural network or the like, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0420] The portable game console 1100 shown in FIG. 29A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, the video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. The electronic component 709 can be incorporated into chips or the like provided on the substrates of the housings 1102 and 1103.

[0421] 29B shows a stick-shaped electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The electronic component 709 can be incorporated into the controller chip 1126 of the board 1124, etc.

[0422] 29C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the electronic component 709 described above.

[0423] [Mainframe] The electronic component 709 can be used in a system 3000 including a mainframe that communicates with the electronic device, instead of being built into the electronic device. In this case, the electronic device and the mainframe constitute a computing system. Fig. 30 shows an example of the configuration of the system 3000.

[0424] The system 3000 is configured by an electronic device 3001 and a mainframe computer 3002. Communication between the electronic device 3001 and the mainframe computer 3002 can be performed via an internet line 3003.

[0425] The mainframe 3002 has a plurality of racks 3004. A plurality of circuit boards 3005 are provided on the racks, and the electronic components 709 described in the above embodiment can be mounted on the circuit boards 3005. This forms a neural network in the mainframe 3002. The mainframe 3002 can then perform neural network calculations using data input from the electronic device 3001 via the Internet line 3003. The results of calculations by the mainframe 3002 can be transmitted to the electronic device 3001 via the Internet line 3003 as necessary. This reduces the calculation load on the electronic device 3001.

[0426] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0427] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0428] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0429] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0430] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0431] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0432] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0433] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0434] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0435] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0436] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0437] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0438] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0439] In this specification and the like, the channel length of a planar transistor refers to, for example, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap in a top view of the transistor, or a distance between a source and a drain in a region where a channel is formed.

[0440] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0441] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0442] In this specification, "A and B are connected" refers to an electrical connection between A and B. Here, "A and B are electrically connected" refers to a connection in which an electrical signal can be transmitted between A and B when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between A and B. Note that "A and B are electrically connected" also includes a case in which A and B are directly connected. Here, "A and B are directly connected" refers to a connection in which an electrical signal can be transmitted between A and B via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection refers to a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0443] BL: bit line, BLB: inverted bit line, CSE: column selection signal, CSEL: column line, DBL: data bit line, DBLB: inverted data bit line, DSA: data sense amplifier, GSA: global sense amplifier, MAC: product-sum operation circuit, 10: element layer, 11: functional circuit section, 12: data sense amplifier section, 13: global sense amplifier drive circuit, 14: column line side drive circuit, 15: word line side drive circuit, 20: global sense amplifier section, 30: product-sum operation circuit section, 40: element layer, 41: memory cell, 42: memory cell array

Claims

A memory cell; A first sense amplifier; A multiply-accumulate circuit; a second sense amplifier; the first sense amplifier, the second sense amplifier, and the product-sum operation circuit are provided in a first element layer; The memory cells are provided in a second element layer; the second element layer is provided above the first element layer, the memory cell is electrically connected to the first sense amplifier and the multiply-accumulate circuit via a first bit line; the second sense amplifier is electrically connected to the first sense amplifier and the multiply-accumulate circuit via a second bit line; the first sense amplifier has a function of outputting first data held in the memory cell to the multiplication and accumulation circuit and the second sense amplifier in response to a column selection signal; the multiply-and-accumulate circuit has a function of executing a multiply-and-accumulate operation on the first data and second data supplied from the second sense amplifier via the second bit line in response to the column selection signal; Semiconductor device. 　 In claim 1, The memory cell includes a first transistor; the first transistor has a first semiconductor layer having an oxide semiconductor in a channel formation region; Semiconductor device. 　 In claim 2, The first semiconductor layer has a fin-like shape. 　 In claim 1, the first bit line has a portion provided in parallel to a direction perpendicular to a substrate surface on which the first element layer is provided, between the memory cell and the first sense amplifier and between the memory cell and the product-sum operation circuit; Semiconductor device. 　 In claim 1, the first device layer includes a second transistor; the second transistor has a second semiconductor layer having silicon in a channel formation region; Semiconductor device. 　 In claim 1, a column line side driver circuit for outputting the column selection signal; the column line side driver circuit is electrically connected to a column line that supplies the column selection signal; the column lines are alternately connected to the first sense amplifier and the multiply-accumulate circuit in a direction in which the column lines extend; Semiconductor device.

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