Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component that is configured to handle squeaking and makes it easy to distinguish a mounting surface side and a non-mounting surface side.　This multilayer ceramic electronic component 10 comprises: a multilayer ceramic capacitor 10 that comprises a layered body 12 and two external electrodes 30a, 30b; a first spacer 52 that is connected to one external electrode 30a; a second spacer 54 that is connected to the other external electrode 30b; and a third spacer 56 that is provided between the first spacer 52 and the second spacer 54. The layered body 12 has a first surface 12a that is on a non-mounting surface side, and the first surface 12a is a different color from the third spacer 56.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] In recent years, multilayer ceramic capacitors, which are chip-type electronic components, have come to be widely used in electronic devices. As the performance of electronic devices using such multilayer ceramic capacitors continues to improve, the performance of multilayer ceramic capacitors, such as their miniaturization and increased capacitance, is also rapidly improving.

[0003] A multilayer ceramic capacitor has an inner layer portion in which dielectric layers and internal electrodes are alternately stacked. Dielectric layers are arranged on the top and bottom of the inner layer portion to form a rectangular parallelepiped laminate, which serves as an outer layer portion. External electrodes are provided on both longitudinal end faces of the laminate, forming a multilayer ceramic capacitor. In a multilayer ceramic capacitor, capacitance is generated when the internal electrodes face each other via the dielectric layers. It is known that vibrations occur in the multilayer ceramic capacitor due to the piezoelectric phenomenon, and when these vibrations are transmitted to the substrate, they cause what is known as "noise."

[0004] To suppress the occurrence of "squeak noise," for example, it is effective to separate the multilayer ceramic capacitor from the substrate. For this reason, for example, a multilayer ceramic electronic component is known that includes bumps (spacers) formed on the side of the multilayer ceramic capacitor that is mounted on the substrate so as to cover part of the external electrodes.

[0005] For example, Patent Document 1 describes a multilayer ceramic electronic component having bumps made of a substrate material such as alumina, which has high rigidity and a high Young's modulus. Also, Patent Document 2 describes a multilayer ceramic electronic component in which spacers are formed by applying a spacer-forming paste onto a multilayer ceramic capacitor and then performing a heat treatment.

[0006] U.S. Patent No. 10,542,626 International Publication No. 2018 / 101405

[0007] However, in the multilayer ceramic electronic components disclosed in Patent Document 1 and Patent Document 2, which are disclosed as multilayer ceramic electronic components with measures against acoustic noise, the mounting surface and the non-mounting surface have the same color, making it difficult to distinguish between the mounting surface and the non-mounting surface. In particular, when the external electrodes and spacers contain the same type of components, it is difficult to distinguish between the mounting surface and the non-mounting surface.

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic electronic component that has been designed to counteract acoustic noise and in which the mounting surface side and the non-mounting surface side can be easily distinguished from each other.

[0009] A multilayer ceramic electronic component according to the present invention comprises a multilayer ceramic capacitor having a laminate and two external electrodes, a first spacer connected to one of the external electrodes, a second spacer connected to the other external electrode, and a third spacer disposed between the first spacer and the second spacer, wherein the laminate has a second surface which is a non-mounting surface side, and the second surface and the third spacer have different hues.

[0010] According to the present invention, it is possible to provide a multilayer ceramic electronic component that has been designed to counteract acoustic noise and in which it is easy to distinguish between the mounting surface side and the non-mounting surface side.

[0011] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0012] Fig. 3 is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention. Fig. 4 is an external perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. Fig. 5 is a cross-sectional view taken along line III-III in Fig. 2. Fig. 6 is a cross-sectional view taken along line IV-IV in Fig. 2. Fig. 7 is a front view of a multilayer ceramic electronic component according to an embodiment of the present invention. Fig. 8 is a bottom view of a multilayer ceramic electronic component according to an embodiment of the present invention. Fig. 9 is a diagram showing a mounted state of a multilayer ceramic electronic component according to an embodiment of the present invention. Fig. 10 is a bottom view of a multilayer ceramic electronic component according to another embodiment of the present invention.

[0013] 1. Multilayer Ceramic Electronic Component A multilayer ceramic electronic component 1 according to the present invention will be described with reference to FIGS. 1 to 8. FIG. 1 is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 2 is an external perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a front view of a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 6 is a bottom view of a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 7 is a diagram showing a mounted state of a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 8 is a bottom view of a multilayer ceramic electronic component according to another embodiment of the present invention.

[0014] The multilayer ceramic electronic component 1 according to the present invention comprises a multilayer ceramic capacitor 10 having a laminate 12 and two external electrodes 30 a, 30 b, a first spacer 52 connected to one of the external electrodes 30 a, a second spacer 54 connected to the other external electrode 30 b, and a third spacer 56 disposed between the first spacer 52 and the second spacer 54.

[0015] (Laminate) The laminate 12 has a plurality of dielectric layers 14 stacked together and a plurality of internal electrodes 16 stacked on the dielectric layers 14. The laminate 12 has a first surface 12a and a second surface 12b facing in a height direction x, a third surface 12c and a fourth surface 12d perpendicular to the height direction x and facing in a length direction z, and a fifth surface 12e and a sixth surface 12f perpendicular to the height direction x and the length direction z and facing in a width direction y. In this embodiment, the first surface 12a side of the laminate 12 is the non-mounting surface side, and the second surface 12b side of the laminate 12 is the mounting surface side. The height direction x is a direction perpendicular to the mounting surface S. Alternatively, the width direction y, which is a direction connecting the fifth surface 12e and the sixth surface 12f of the laminate 12, may be the stacking direction.

[0016] The laminate 12 has a hexahedral shape. Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. The corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0017] The laminate 12 has an inner layer portion 18 in which a plurality of inner electrodes 16 face each other. In other words, in the inner layer portion 18, the first inner electrode 16a and the second inner electrode 16b face each other.

[0018] The laminate 12 is located on the first surface 12a side and has a first outer layer portion 20a formed from a plurality of dielectric layers 14 located between the first surface 12a and the outermost surface of the inner layer portion 18 on the first surface 12a side and an extension of that outermost surface.

[0019] Similarly, the laminate 12 has a second outer layer portion 20b located on the second surface 12b side and formed from a plurality of dielectric layers 14 located between the second surface 12b and the outermost surface of the inner layer portion 18 on the second surface 12b side and an extension of that outermost surface.

[0020] (Dielectric Layer) The ceramic material constituting the dielectric layer 14 may be, for example, a dielectric ceramic composed of a main component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, a material containing these main components and added with a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be used.

[0021] The thickness of the dielectric layer 14 is preferably 0.5 μm or more and 10 μm or less. The number of the dielectric layers 14, including the first outer layer portion 20 a and the second outer layer portion 20 b, is preferably 10 or more and 700 or less.

[0022] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b.

[0023] The first internal electrodes 16a are disposed on the plurality of dielectric layers 14 and are exposed on the third surface 12c.

[0024] The second internal electrodes 16b are disposed on the plurality of dielectric layers 14 and are exposed on the fourth surface 12d.

[0025] The first internal electrode 16a includes a first opposing electrode portion 26a that faces the second internal electrode 16b, and a first extraction electrode portion 28a that is extracted from the first opposing electrode portion 26a to the third surface 12c of the laminate 12. An end of the first extraction electrode portion 28a of the first internal electrode 16a is extracted to the surface of the third surface 12c of the laminate 12, forming an exposed portion.

[0026] The second internal electrode 16b includes a second opposing electrode portion 26b that faces the first internal electrode 16a, and a second extraction electrode portion 28b that is extracted from the second opposing electrode portion 26b to the fourth surface 12d of the laminate 12. The second extraction electrode portion 28b of the second internal electrode 16b has an end that is extracted to the surface of the fourth surface 12d of the laminate 12, forming an exposed portion.

[0027] The shapes of the first opposing electrode portion 26a of the first internal electrode 16a and the second opposing electrode portion 26b of the second internal electrode 16b are not particularly limited, but are preferably rectangular, although the corners may be rounded or angled (tapered).

[0028] The shapes of the first lead electrode portion 28a of the first internal electrode 16a and the second lead electrode portion 28b of the second internal electrode 16b are not particularly limited, but are preferably rectangular, although the corners may be rounded or angled (tapered).

[0029] The width of the first opposing electrode portion 26a of the first internal electrode 16a and the second opposing electrode portion 26b of the second internal electrode 16b may be the same as the width of the first extraction electrode portion 28a of the first internal electrode 16a and the second extraction electrode portion 28b of the second internal electrode 16b, or one of them may be formed to have a narrower width.

[0030] In this embodiment, the opposing electrode portions 26 of the internal electrodes 16 face each other via the dielectric layer 14, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0031] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0032] Furthermore, by including Sn in the first internal electrode 16a and the second internal electrode 16b, it is possible to alleviate the electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14, leading to an improvement in high-temperature load reliability. In this case, even if Sn is included in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b, it is possible to achieve a sufficient effect.

[0033] The thickness of each of the first internal electrode 16a and the second internal electrode 16b is preferably, for example, 0.2 μm or more and 2.0 μm or less. The number of internal electrodes 16 is preferably 10 or more and 700 or less.

[0034] (External Electrode) The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0035] The first external electrode 30a is connected to the first internal electrode 16a and is disposed on the third surface 12c. It may also be disposed on part of the first surface 12a, part of the second surface 12b, part of the fifth surface 12e, and part of the sixth surface 12f. In this embodiment, the first external electrode 30a extends from the third surface 12c to part of the first surface 12a, part of the second surface 12b, part of the fifth surface 12e, and part of the sixth surface 12f.

[0036] The second external electrode 30b is connected to the second internal electrode 16b and is disposed on the fourth surface 12d. It may also be disposed on a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f. In this embodiment, the second external electrode 30b extends from the fourth surface 12d to a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f.

[0037] The first external electrode 30 a and the second external electrode 30 b have an underlying electrode layer 32 disposed on the surface of the laminate 12 and a plating layer 34 disposed so as to cover the underlying electrode layer 32 .

[0038] (Base Electrode Layer) The base electrode layer 32 is disposed on the third surface 12c and the fourth surface 12d. Furthermore, on the first external electrode 30a side and the second external electrode 30b side, the base electrode layer 32 may also be disposed on parts of the first surface 12a and the second surface 12b, parts of the fifth surface 12e, and parts of the sixth surface 12f. In this embodiment, on the first external electrode 30a side and the second external electrode 30b side, the base electrode layer 32 is formed so as to extend from the third surface 12c and the fourth surface 12d to parts of the first surface 12a and the second surface 12b, parts of the fifth surface 12e, and parts of the sixth surface 12f.

[0039] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0040] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0041] (In the case of a baking layer) The baking layer contains a glass component and a metal. The glass component of the baking layer contains, for example, at least one selected from B, Si, Ba, Mg, Al, and Li. The metal of the baking layer contains, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc.

[0042] The baked layer may be a multi-layer. The baked layer is formed by applying and baking a conductive paste containing glass and metal to the laminate 12. The baked layer may be formed by simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 with the conductive paste applied to the laminated chip, or by firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 to obtain the laminate 12, and then applying and baking the conductive paste to the laminate 12. When simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 with the conductive paste applied to the laminated chip, it is preferable to form the baked layer by adding a dielectric material instead of the glass component and baking it.

[0043] The thickness in the length direction z connecting the third surface 12c and the fourth surface 12d at the center of the height direction x connecting the first surface 12a and the second surface 12b of the first baking layer located on the third surface 12c (i.e., the thickness of the base electrode layer at the center of the third surface 12c) is preferably, for example, 3 μm or more and 160 μm or less.

[0044] The thickness in the length direction z connecting the third surface 12c and the fourth surface 12d at the center of the height direction x connecting the first surface 12a and the second surface 12b of the second baking layer located on the fourth surface 12d (i.e., the thickness of the base electrode layer at the center of the fourth surface 12d) is preferably, for example, 3 μm or more and 160 μm or less.

[0045] Furthermore, it is preferable that the thickness in the height direction x connecting the first surface 12a and the second surface 12b at the center of the length direction z connecting the third surface 12c and the fourth surface 12d of the first baking layer located on a part of the first surface 12a and a part of the second surface 12b is, for example, 3 μm or more and 40 μm or less.

[0046] Furthermore, the thickness in the height direction x connecting the first surface 12a and the second surface 12b at the center of the length direction z connecting the third surface 12c and the fourth surface 12d of the second baking layer located on a part of the first surface 12a and a part of the second surface 12b is preferably, for example, 3 μm or more and 40 μm or less.

[0047] (In the case of conductive resin layer) When a conductive resin layer is provided as the base electrode layer 32, the conductive resin layer may be disposed so as to cover the baked layer. Alternatively, the conductive resin layer may be disposed directly on the laminate 12 without providing a baked layer. The conductive resin layer may completely cover the base electrode layer 32, or may cover only a portion of the base electrode layer 32. Alternatively, the conductive resin layer may be formed of multiple layers.

[0048] The conductive resin layer contains, for example, a thermosetting resin and a metal component.

[0049] Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0050] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent.

[0051] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. Alternatively, a metal powder with an Ag coating on its surface can be used. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the metal contained in the conductive resin layer is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. Furthermore, it is possible to use an inexpensive base metal while maintaining the above-mentioned properties of Ag. Furthermore, Cu or Ni that has been subjected to an oxidation prevention treatment can also be used as the metal contained in the conductive resin layer. Alternatively, a metal powder with an Sn, Ni, or Cu coating on its surface can also be used as the metal contained in the conductive resin layer. When using a metal powder with an Sn, Ni, or Cu coating on its surface, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0052] The metal contained in the conductive resin layer can be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder. The metal contained in the conductive resin layer is primarily responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between conductive fillers (metal contained in the conductive resin layer) forms an electrical path inside the conductive resin layer.

[0053] Since the conductive resin layer contains a thermosetting resin, it is more flexible than a base electrode layer made of, for example, a plating film or a fired conductive paste, and therefore functions as a buffer layer to prevent cracks in the multilayer ceramic capacitor even when the multilayer ceramic capacitor is subjected to a physical impact or an impact due to a thermal cycle.

[0054] The thickness of the thickest part of the conductive resin layer is preferably, for example, 10 μm or more and 150 μm or less.

[0055] (In the case of a thin film layer) The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0056] (Plating Layer) The plating layer 34 includes a first plating layer 34a and a second plating layer 34b. The first plating layer 34a is disposed so as to cover the first base electrode layer 32a. The second plating layer 34b is disposed so as to cover the second base electrode layer 32b.

[0057] The plating layer 34 contains at least one selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0058] The plating layer 34 may be formed of multiple layers. Preferably, it has a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic electronic component 1. The Sn plating layer also improves the wettability of the solder when mounting the multilayer ceramic electronic component 1, facilitating mounting.

[0059] The thickness of each plating layer 34 is preferably 2 μm or more and 15 μm or less.

[0060] The external electrode 30 may be formed using only the plating layer 34 without providing the base electrode layer 32. A structure in which the plating layer 34 is provided without providing the base electrode layer 32 will be described below.

[0061] For each of the first external electrode 30a and the second external electrode 30b, the plating layer 34 may be formed directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the multilayer ceramic capacitor 10 may have a structure including the plating layer 34 that is directly connected to the first internal electrode 16a and the second internal electrode 16b. In such a case, the plating layer 34 may be formed after a catalyst is disposed on the surface of the laminate 12 as a pretreatment.

[0062] When a plating layer is formed directly on the laminate 12 without providing the base electrode layer 32, the reduction in the thickness of the base electrode layer 32 can be converted into a lower profile, i.e., a thinner body, or into the thickness of the laminate 12, i.e., the thickness of the inner layer portion 18 (effective layer portion), thereby improving the design freedom of thin chips.

[0063] Furthermore, the plating layer 34 preferably includes a lower-layer plating electrode formed on the surface of the laminate 12 and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode.

[0064] The lower layer plating electrode and the upper layer plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal.

[0065] The lower layer plated electrode is preferably formed using Ni, which has solder barrier properties, and the upper layer plated electrode is preferably formed using Sn or Au, which has good solder wettability.

[0066] Furthermore, for example, when the first internal electrode 16 a and the second internal electrode 16 b are formed using Ni, it is preferable that the lower-layer plated electrode be formed using Cu, which has good bonding properties with Ni. Note that the upper-layer plated electrode may be formed as needed, and the first external electrode 30 a and the second external electrode 30 b may each be composed of only the lower-layer plated electrode.

[0067] The plating layer 34 may have an upper layer plating electrode as the outermost layer, or another plating electrode may be formed on the surface of the upper layer plating electrode.

[0068] The thickness of each plating layer 34, which is disposed without providing a base electrode layer 32, is preferably 1 μm or more and 15 μm or less. The plating layer 34 preferably does not contain glass. The metal content per unit volume of the plating layer 34 is preferably 99% by volume or more.

[0069] The dimension of the multilayer ceramic capacitor 10 in the length direction z is L M The dimensions are as follows: L MThe dimension of the multilayer ceramic capacitor 10 in the width direction y is preferably W M The dimensions are as follows: W M The dimension of the multilayer ceramic capacitor 10 in the height direction x is preferably T M The dimensions are as follows: T M The dimension is preferably 0.1 mm or more and 5 mm or less.

[0070] (Spacer) The multilayer ceramic electronic component 1 includes a multilayer ceramic capacitor 10 and a spacer 50. The spacer 50 includes a first spacer 52 covering at least a portion of the first external electrode 30a, a second spacer 54 covering at least a portion of the second external electrode 30b, and a third spacer 56 covering a portion of the laminate 12, a portion of the first spacer 52, and a portion of the second spacer 54. In this embodiment, the first spacer 52, the second spacer 54, and the third spacer 56 are described separately from one another, but there are cases in which the first spacer 52, the second spacer 54, and the third spacer 56 are integrated and cannot be distinguished from one another.

[0071] (First Spacer and Second Spacer) The first spacer 52 is disposed between the first external electrode 30a and the mounting surface S and is connected to the first external electrode 30a. The second spacer 54 is disposed between the second external electrode 30b and the mounting surface S and is connected to the second external electrode 30b.

[0072] The shapes of the first spacer 52 and the second spacer 54 are not particularly limited. In other words, the shapes of the first spacer 52 and the second spacer 54 may be, for example, a substantially hexahedral shape, a concave shape or an H-shape having opening regions that open to the third surface 12c and the fourth surface 12d of the laminate 12, or a four-legged shape in which the first spacer 52 and the second spacer 54 are discontinuously arranged. When the first spacer 52 and the second spacer 54 have opening regions that open to the third surface 12c and the fourth surface 12d of the laminate 12, some of the solder used during mounting enters the opening regions of the first spacer 52 and the second spacer 54. This reduces the amount of solder that wets onto the third surface 12c and the fourth surface 12d of the laminate 12, thereby suppressing squeal. However, the shapes may also be cloud-shaped, which has multiple protrusions and / or recesses when viewed from the bottom (mounting surface side). In the following description, the first spacer 52 and the second spacer 54 are assumed to have a hexahedral shape.

[0073] The first spacer 52 has a first surface 52a and a second surface 52b facing in the height direction x, a third surface 52c and a fourth surface 52d perpendicular to the height direction x and facing in the length direction z, and a fifth surface 52e and a sixth surface 52f perpendicular to the height direction x and the length direction z and facing in the width direction y. The first surface 52a of the first spacer 52 is connected to the first external electrode 30a. The second surface 52b of the first spacer 52 is connected to the mounting surface S. In addition, in the first spacer 52, an edge portion of the first spacer 52 facing the center of the multilayer ceramic capacitor 10 (a ridge portion where the first surface 52a and the fourth surface 52d intersect) may be located closer to the center of the multilayer ceramic capacitor 10 than the end portion of the first external electrode 30a facing the center of the multilayer ceramic capacitor 10.

[0074] The second spacer 54 has a first surface 54a and a second surface 54b facing in the height direction x, a third surface 54c and a fourth surface 54d perpendicular to the height direction x and facing in the length direction z, and a fifth surface 54e and a sixth surface 54f perpendicular to the height direction x and the length direction z and facing in the width direction y. The first surface 54a of the second spacer 54 is connected to the second external electrode 30b. The second surface 54b of the second spacer 54 is connected to the mounting surface S. In addition, in the second spacer 54, an edge portion of the second spacer 54 facing the center of the multilayer ceramic capacitor 10 (a ridge portion where the first surface 54a and the third surface 54c intersect) may be located closer to the center of the multilayer ceramic capacitor 10 than the end portion of the second external electrode 30b facing the center of the multilayer ceramic capacitor 10.

[0075] By arranging the first spacer 52 and the second spacer 54 between the multilayer ceramic capacitor 10 and the mounting surface S, the distance between the inner layer portion 18, which is the capacitance forming portion of the multilayer ceramic capacitor 10, and the mounting surface S can be increased, thereby suppressing "squeak".

[0076] At this time, the dimension L of the multilayer ceramic capacitor 10 in the height direction x is M The dimension T in the height direction x of the first spacer 52 and the second spacer 54 depends on S For example, the length L of the multilayer ceramic capacitor 10 is preferably 50 μm or more and 250 μm or less. M 1.6 mm, and the width W of the multilayer ceramic capacitor 10 M 0.8 mm, and the dimension T M is 0.8 mm, the dimension T of the first spacer 52 and the second spacer 54 in the height direction x is S It is preferable that the thickness T of the first spacer 52 and the second spacer 54 is about 160 μm. In addition, the first spacer 52 and the second spacer 54 may have a portion with unevenness. When the first spacer 52 and the second spacer 54 have a portion with unevenness due to their shape, the dimension T of the first spacer 52 and the second spacer 54 in the height direction x is S It is preferable that the minimum thickness is about 160 μm.

[0077] The first spacer 52 and the second spacer 54 contain metal powder. The metal powder may contain, for example, Sn and one of Cu, Ni, or an alloy of Cu and a metal component (e.g., Ni). In addition, Ag or a resin component (e.g., rosin) may be contained, and the Cu and Ni may be coated with Ag. This allows the multilayer ceramic electronic component 1 to have a melting point that does not melt even when soldered and does not deform due to heat, enabling the multilayer ceramic electronic component 1 to be mounted on a substrate while maintaining a desired shape even during soldering. Furthermore, the present invention is not limited to this, and the spacers may contain other metal components. Because the first spacer 52 and the second spacer 54 contain Sn and one of Cu, Ni, or an alloy of Cu and a metal component (e.g., Ni), metal bonding between the first spacer 52 and the second spacer 54 and the external electrodes 30a, 30b of the multilayer ceramic capacitor 10 is facilitated.

[0078] In addition to the above, the first spacer 52 and the second spacer 54 may contain phenolic resin as a resin component. In this case, the phenolic resin coats the metal powder particles and is scattered so as to fill the gaps between the particles. The inclusion of phenolic resin provides good heat resistance, so the amount of vaporization can be reduced during the heat treatment process when forming the spacers. This reduces voids within the spacers. Furthermore, without being limited to this, epoxy resin or rosin may also be contained in addition to phenolic resin.

[0079] The first spacer 52 and the second spacer 54 may also be configured to contain metal powder in resin. If the resin component is contained in a larger amount than the metal powder, the resin component can buffer vibrations of the multilayer ceramic capacitor 10, thereby reducing vibrations transmitted to the substrate. In this case, the surfaces of the first spacer 52 and the second spacer 54 may be plated.

[0080] The components of the first spacer 52 and the second spacer 54 can be detected, for example, as follows. The multilayer ceramic electronic component 1 is cross-polished perpendicular to the mounting surface S to 1 / 6 W of the width direction y, exposing a cross section (LT surface) in the height direction x and the length direction z. The components of the first spacer 52 and the second spacer 54 can be detected by qualitative analysis using EDX with an FE-SEM (SU8230, manufactured by Hitachi High-Technologies Corporation) obtained by cross-polishing. The cross section obtained by cross-polishing can be magnified 50 times with a microscope (BX-51, manufactured by Olympus Corporation) and photographed with a microscope digital camera (DP22, manufactured by Olympus Corporation). This allows the metal types in the first spacer 52 and the second spacer 54 to be observed, and, if plating is present on the first spacer 52 and the second spacer 54, the difference in the metal type of the plating. Furthermore, without being limited to this, by taking photographs using a microscope (Axio (registered trademark)-Imager-MAT manufactured by ZEISS) at a total magnification of 100 times or more and 500 times or less, it is also possible to observe the difference in the metal type within the first spacers 52 and the second spacers 54, or the difference in the metal type of plating if plating is present on the first spacers 52 and the second spacers 54. In addition to this, cross-section polishing may be performed up to ½W in the width direction y.

[0081] (Third Spacer) The third spacer 56 is connected to a portion of the laminate 12, a portion of the first spacer 52, and a portion of the second spacer 54. More specifically, the third spacer 56 covers the fourth surface 52d of the first spacer 52 and the third surface 54c of the second spacer 54. Preferably, the third spacer 56 covers 50% or more of the area of ​​the fourth surface 52d of the first spacer 52, and preferably covers 50% or more of the area of ​​the third surface 54c of the second spacer 54. In this case, the third spacer 56 preferably continuously covers the space between the first spacer 52 and the laminate 12 and the space between the second spacer 54 and the laminate 12. Furthermore, the third spacer 56 preferably continuously covers the surface of the laminate 12. However, this is not limited thereto, and the third spacer 56 may be arranged discontinuously in the longitudinal direction (length direction z) of the multilayer ceramic capacitor 10. This allows the distance between the center of the longitudinal direction z, which vibrates most, and the multilayer ceramic electronic component 1 to be increased, thereby reducing the possibility of contact between the mounting substrate and the multilayer ceramic electronic component 1.

[0082] The third spacer 56 may cover the fifth surface 52e and the sixth surface 52f of the first spacer 52 and the fifth surface 54e and the sixth surface 54f of the second spacer 54. Alternatively, the third spacer 56 may cover the fifth surface 52e and the sixth surface 52f of the first spacer 52 and the fifth surface 54e and the sixth surface 54f of the second spacer 54 continuously to the fifth surface 12e and the sixth surface 12f of the multilayer ceramic capacitor 10. This configuration provides insulation by the third spacer 56, allowing the multilayer ceramic electronic component 1 to be arranged in close proximity. The location of the multilayer ceramic capacitor 10 covered by the third spacer 56 is not particularly limited, but it is preferable that the third spacer 56 not cover the non-mounting surface (first surface 12a) of the multilayer ceramic electronic component 1 in order to identify the mounting surface (second surface 12b).

[0083] Here, the central region of the third spacer 56 is defined as a location 1 / 2L in the longitudinal direction z of the multilayer ceramic electronic component 1. The end regions of the third spacer 56 are defined as locations where the third spacer 56 contacts the first spacer 52 or the second spacer 54. In the longitudinal direction (longitudinal direction z) of the multilayer ceramic capacitor 10, the thickness t1 of the central region of the third spacer 56 is preferably thinner than the thicknesses t2 and t3 of the end regions of the third spacer 56. In other words, the third spacer 56 is preferably arranged so as to curve toward the mounting surface. In other words, the third spacer 56 is preferably shaped so as to be wetted by the first spacer 52 and the second spacer 54. This reduces the possibility of contact between the third spacer 56 and the mounting surface S when the multilayer ceramic capacitor 10 vibrates.

[0084] The method for measuring the thickness t1 of the central region of the third spacer 56 and the thicknesses t2 and t3 of the end regions of the third spacer 56 will be described below. The multilayer ceramic electronic component 1 is polished to ½W in the width direction y to expose the cross section (LT surface). A digital microscope (Keyence Corporation, VHX-6000) is used to measure the distance from the second surface 12b of the laminate 12 to the surface of the third spacer 56 on the mounting surface side of the exposed cross section.

[0085] 6 and 8, the length w1 in the width direction y of the central region of the third spacer 56 is preferably shorter than the lengths w2 and w3 in the width direction y of the end regions of the third spacer 56. By forming the third spacer 56 in this manner, the adhesive strength between the laminate 12 and the first spacer 52 and the second spacer 54 can be improved.

[0086] Furthermore, the third spacer 56 is preferably disposed between the laminate 12 and the first spacer 52 and between the laminate 12 and the second spacer 54. This fills the gap between the laminate 12 and the first spacer 52 and between the laminate 12 and the second spacer 54 with the third spacer 56, thereby reducing the possibility that the edge portion on the center side of the first spacer 52 (the ridge portion where the first surface 52a and the fourth surface 52d intersect) or the edge portion on the center side of the second spacer 54 (the ridge portion where the first surface 54a and the third surface 54c intersect) will come into contact with and damage the multilayer ceramic capacitor 10 when vibration occurs.

[0087] It is preferable that the color of the multilayer ceramic electronic component 1 be different when viewed from the bottom surface (mounting surface) than when viewed from the top surface (non-mounting surface). The different colors make it easier to select the direction when mounting on a substrate, and can reduce the number of times the multilayer ceramic electronic component 1 is mounted on a surface other than the surface on which it should be mounted.

[0088] The third spacer 56 includes, for example, carbon, Co, Al, or Cr. In addition, the third spacer 56 may include an epoxy resin, a hardener, or another organic solvent.

[0089] For example, when the third spacer 56 contains a large amount of carbon, the hue of the third spacer can be made closer to black. Also, when the third spacer 56 contains a large amount of Co, Al, or Cr, the hue of the third spacer 56 can be made closer to blue. In addition, the hue can be changed by using various other materials.

[0090] The content of the various materials for changing the hue is preferably 0.1 wt % to 5.0 wt % based on the solid content of the third spacer 56, i.e., the amount of solid content excluding solvent (epoxy resin, phenolic resin), additives (coupling agent, catalyst), and inorganic materials (silica, alumina)). If the weight ratio is too small, the hue change may be insufficient, and the image may not be correctly recognized during image processing. Furthermore, if the weight ratio is too large, the third spacer 56 may cause electrical conduction between the first external electrode 30a and the second external electrode 30b, or between the first spacer 52 and the second spacer 54. Depending on the distribution of the various materials, there may be areas with partially different hues. However, even in such cases, directional selection is possible as long as the hues are sufficiently different. It is preferable that the hue be different over at least half of the area of ​​the region between the first spacer 52 and the second spacer 54 on the mounting surface.

[0091] To distinguish between the portion where the third spacer 56 is present and the other portions, a method for measuring the hue of the mounting surface side and the non-mounting surface side of the multilayer ceramic electronic component 1 will be described. The first surface 12a, which is the non-mounting surface side, and the second surface 12b, which is the mounting surface side, of the multilayer ceramic electronic component 1 are measured (RGB measurement) using a digital microscope (Keyence Corporation, VHX-6000). The measurement conditions are brightness set to auto "100," gain set to auto "100," and ring removal set to "medium" for reflection removal. For the mounting surface side, measurements are taken on 1 / 2W of the multilayer ceramic electronic component 1, 1 / 2L of the multilayer ceramic electronic component 1, the contact point between the first spacer 52 and the laminate 12, and the contact point between the second spacer 54 and the laminate 12. Furthermore, on the non-mounting surface, measurements are made on 1 / 2 W of the multilayer ceramic electronic component 1, 1 / 2 L of the multilayer ceramic electronic component 1, near the contact points between the first external electrode 30a and the laminate 12, and near the contact points between the second external electrode 30b and the laminate 12. When the mounting surface and non-mounting surface of the multilayer ceramic electronic component 1 are measured, if any of the R, G, and B values ​​differ by 10 or more, the hues are defined as different. In this case, if the hue differs at even one of the measurement points, the hues are determined to be different.

[0092] 2. Method for Manufacturing the Multilayer Ceramic Electronic Component Next, a method for manufacturing the multilayer ceramic electronic component 1 will be described.

[0093] First, a conductive paste for the dielectric sheet and the internal electrodes is prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0094] Next, a dielectric sheet on which no internal electrode pattern is printed and a dielectric sheet on which a conductive paste for the internal electrodes is printed in a predetermined pattern by, for example, screen printing or gravure printing are prepared, thereby preparing a dielectric sheet on which a first internal electrode pattern is printed and a dielectric sheet on which a second internal electrode pattern is printed.

[0095] Next, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are laminated, and dielectric sheets on which the first internal electrode pattern and the second internal electrode pattern are printed are laminated in order thereon to form a portion that will become the inner layer portion 18. Furthermore, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are laminated on the portion that will become the inner layer portion 18 to produce a laminated sheet.

[0096] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0097] Next, the laminated block is cut to a predetermined size to cut out laminated chips, and at this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0098] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrodes 16, but is preferably 900°C or higher and 1400°C or lower.

[0099] Next, a conductive paste that will become the base electrode layer 32 is applied to the third surface 12c and the fourth surface 12d of the laminate 12 to form the base electrode layer 32. In this embodiment, a baked layer is formed as the base electrode layer 32. When forming the baked layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer 32. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0100] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0101] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate, followed by heat treatment at a temperature of 250°C to 550°C to thermally cure the thermosetting resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. To prevent scattering of the thermosetting resin and oxidation of the various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0102] When the base electrode layer 32 is formed as a thin film layer, the base electrode layer 32 can be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer is a layer of metal particles deposited to a thickness of 1 μm or less.

[0103] Furthermore, the plating layer 34 may be provided on the exposed portion of the internal electrode 16 of the laminate 12 without providing the base electrode layer 32. In this case, the plating layer 34 can be formed by the following method.

[0104] The third surface 12c and the fourth surface 12d of the laminate 12 are plated to form a base plated electrode on the exposed portion of the internal electrode 16. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating requires pretreatment using a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. If necessary, an upper plated electrode may be formed on the surface of the lower plated electrode in the same manner.

[0105] Thereafter, a plating layer 34 is formed on the surface of the base electrode layer 32, the surface of the conductive resin layer or the surface of the lower-layer plating electrode, and the surface of the upper-layer plating electrode. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, barrel plating.

[0106] In this manner, the multilayer ceramic capacitor 10 is manufactured.

[0107] Next, a method for arranging the first spacers 52 and the second spacers 54 in the multilayer ceramic capacitor 10 will be described.

[0108] A first spacer manufacturing paste used to manufacture the first spacer 52 and a second spacer manufacturing paste used to manufacture the second spacer 54 are prepared. The first spacer manufacturing paste and the second spacer manufacturing paste contain, for example, a metal including at least one of Cu, Ni, Sn, Ag, etc., and a resin component. However, this is not limited thereto, and the first spacer manufacturing paste and the second spacer manufacturing paste may be composed of a conductive paste. Next, the first spacer manufacturing paste and the second spacer manufacturing paste are placed on a holding substrate (e.g., an alumina plate) by screen printing, dispensing, or the like. Next, the multilayer ceramic capacitor 10 is placed on top of the spacer manufacturing paste in an orientation facing the holding substrate. At this time, the first external electrode 30a and the first spacer manufacturing paste, and the second external electrode 30b and the second spacer manufacturing paste are aligned, and the first spacer manufacturing paste and the second spacer manufacturing paste are applied to the multilayer ceramic capacitor 10. Thereafter, a heat treatment is performed to form the first spacers 52 and the second spacers 54 .

[0109] Alternatively, the first spacer 52 and the second spacer 54 can be disposed on the multilayer ceramic capacitor 10 by the following method: The multilayer ceramic capacitor 10 is disposed on a holding substrate (e.g., an alumina plate) using an adhesive. Each spacer manufacturing paste is disposed on the external electrodes 30 of the multilayer ceramic capacitor 10 disposed on the holding substrate by screen printing, dispensing, or the like. The first external electrode 30a and the first spacer manufacturing paste, and the second external electrode 30b and the second spacer manufacturing paste are aligned, and the first spacer manufacturing paste and the second spacer manufacturing paste are attached to the multilayer ceramic capacitor 10.

[0110] In the spacer placement step, the first spacers 52 and second spacers 54 can be formed in a desired shape and in a desired placement by changing the amount of paste or the design of the mask. After that, the first spacers 52 and second spacers 54 are formed by performing a heat treatment.

[0111] Next, a method for arranging the third spacer 56 in the multilayer ceramic capacitor 10 will be described.

[0112] The surface of the multilayer ceramic capacitor 10 on which the first spacers 52 and the second spacers 54 are disposed is cleaned with a solvent. After the cleaning is completed, the multilayer ceramic capacitor 10 on which the first spacers 52 and the second spacers 54 are disposed is aligned so that the first spacers 52 and the second spacers 54 face upward.

[0113] Next, a paste for manufacturing the third spacers 56 is prepared. The paste for manufacturing the third spacers 56 is composed of an insulating paste. The color of the third spacers 56 can be changed by adding various materials as additives.

[0114] Next, with respect to the multilayer ceramic capacitor 10 on which the first spacers 52 and second spacers 54 have been arranged, a dispenser or squeegee printing is used to form a third spacer 56 between the first spacer 52 and the second spacer 54. The amount of wetting of the first spacer 52 and the second spacer 54 can be changed by adjusting the amount of the paste for manufacturing the third spacer.

[0115] When the third spacer 56 is inserted between the laminate 12 and the first spacer 52, or between the laminate 12 and the second spacer 54, the third spacer 56 can be inserted by evacuating after placing the paste for manufacturing the third spacer. The amount of insertion can be controlled by changing the time and pressure of the evacuation.

[0116] Thereafter, the mixture is heated at a temperature of 100° C. to 200° C. for 20 minutes to 80 minutes.

[0117] Through the above steps, the multilayer ceramic electronic component 1 of this embodiment is manufactured.

[0118] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0119] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0120] <1> A multilayer ceramic electronic component comprising: a multilayer ceramic capacitor including a laminate and two external electrodes; a first spacer connected to one of the external electrodes; a second spacer connected to the other of the external electrodes; and a third spacer disposed between the first spacer and the second spacer, wherein the laminate has a first surface that is a non-mounting surface, and the first surface and the third spacer have different hues.

[0121] <2> The multilayer ceramic electronic component according to <1>, wherein a central region of the third spacer is thinner than end regions of the third spacer in the longitudinal direction of the multilayer ceramic capacitor.

[0122] <3> The multilayer ceramic electronic component according to <1> or <2>, wherein the third spacers are arranged discontinuously in the longitudinal direction of the multilayer ceramic capacitor.

[0123] <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the third spacer is disposed between the laminate and the first spacer or between the laminate and the second spacer.

[0124] <5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein the stacking direction of the laminate is perpendicular to the mounting surface.

[0125] <6> The multilayer ceramic electronic component according to any one of <1> to <5>, wherein, in the longitudinal direction of the multilayer ceramic capacitor, the length in the width direction of the central region of the third spacer is shorter than the length in the width direction of the end region of the third spacer.

[0126] <7> The multilayer ceramic electronic component according to any one of <1> to <6>, wherein the third spacer is disposed between the laminate and the first spacer and between the laminate and the second spacer.

[0127] <8> A multilayer ceramic electronic component comprising: a multilayer ceramic capacitor including a laminate and two external electrodes; a first spacer connected to one of the external electrodes; and a second spacer connected to the other of the external electrodes; wherein the laminate has a second surface that is a surface on the mounting side; and a first surface that is a surface on the non-mounting side and faces the second surface; and wherein the mounting surface and the non-mounting surface of the laminate have different hues in a direction connecting the first surface and the second surface.

[0128] <9> The multilayer ceramic electronic component according to any one of <1> to <8>, wherein the content of the material for changing the hue is 0.1 wt % or more and 5.0 wt % or less, based on the amount of solids excluding the solvent, additives, and inorganic materials.

[0129] REFERENCE SIGNS LIST 1 Multilayer ceramic electronic component 10 Multilayer ceramic capacitor 12 Laminate 12a First surface 12b Second surface 12c Third surface 12d Fourth surface 12e Fifth surface 12f Sixth surface 14 Dielectric layer 16 Internal electrode 16a First internal electrode 16b Second internal electrode 18 Internal layer portion 20a First outer layer portion 20b Second outer layer portion 26 Counter electrode portion 26a First counter electrode portion 26b Second counter electrode portion 28 Lead electrode portion 28a First lead electrode portion 28b Second lead electrode portion 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 50 Spacer 52 First spacer 52a First surface of first spacer 52b Second surface of first spacer 52c Third surface of first spacer 52d Fourth surface of first spacer 52e Fifth surface of first spacer 52f Sixth surface of first spacer 54 Second spacer 54a First surface of second spacer 54b Second surface of second spacer 54c Third surface of second spacer 54d Fourth surface of second spacer 54e Fifth surface of second spacer 54f Sixth surface of second spacer 56 Third spacer x Height direction y Width direction z Length direction (longitudinal direction) T M Height dimension of multilayer ceramic capacitor W M Width of the multilayer ceramic capacitor L M Length of the multilayer ceramic capacitor T S Height dimension S of the first spacer and the second spacer Mounting surface

Claims

1. A multilayer ceramic electronic component comprising: a multilayer ceramic capacitor having a laminate and two external electrodes; a first spacer connected to one of the external electrodes; a second spacer connected to the other of the external electrodes; and a third spacer disposed between the first spacer and the second spacer, wherein the laminate has a first surface which is a non-mounting surface, and the first surface and the third spacer have a different hue.

2. The multilayer ceramic electronic component according to claim 1, wherein a central region of said third spacer is thinner than end regions of said third spacer in the longitudinal direction of said multilayer ceramic capacitor.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein the third spacers are arranged discontinuously in the longitudinal direction of the multilayer ceramic capacitor.

4. A multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the third spacer is disposed between the laminate and the first spacer, or between the laminate and the second spacer.

5. The multilayer ceramic electronic component according to claim 1, wherein the lamination direction of said laminate is perpendicular to the mounting surface.

6. A multilayer ceramic electronic component according to any one of claims 1 to 5, wherein, in the longitudinal direction of the multilayer ceramic capacitor, the length in the width direction of the central region of the third spacer is shorter than the length in the width direction of the end regions of the third spacer.

7. A multilayer ceramic electronic component according to any one of claims 1 to 6, wherein the third spacer is disposed between the laminate and the first spacer, and between the laminate and the second spacer.

8. A multilayer ceramic electronic component comprising: a multilayer ceramic capacitor having a laminate and two external electrodes; a first spacer connected to one of the external electrodes; and a second spacer connected to the other of the external electrodes, wherein the laminate has a second surface which is a mounting surface side, and a first surface which is a non-mounting surface and faces the second surface, and wherein the mounting surface and the non-mounting surface of the laminate have different hues in a direction connecting the first surface and the second surface.

9. A monolithic ceramic electronic component according to any one of claims 1 to 8, wherein the content of the hue-changing material is 0.1 wt % or more and 5.0 wt % or less, based on the amount of solids excluding the solvent, additives, and inorganic materials.

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