Multi-layer ceramic capacitor and method for manufacturing multi-layer ceramic capacitor

Abstract

Provided is a multi-layer ceramic capacitor that makes it possible to ensure moisture resistance reliability by suppressing infiltration of moisture from the outside to the inside of the multi-layer ceramic capacitor, and to achieve lowering of ESR. A multi-layer ceramic capacitor 10 comprises: a layered body 12 in which ceramic layers 14 and internal electrode layers 16 are layered; a barrier film 28 that is disposed on the layered body 12; and an external electrode 24 that is disposed on the barrier film 28 at both end surfaces 12e and 12f of the layered body 12. The ceramic layer 14 is represented by the general formula ABO3, and contains a perovskite compound in which the A site is Ba. The barrier film 28 includes Ba and at least one of S and C. The barrier film 28 covers both principal surfaces 12a and 12b and both side surfaces 12c and 12d, and covers both end surfaces 12e and 12f except for an exposed surface 29 where the internal electrode layer 16 is exposed. The external electrode 24 is in contact with the internal electrode layer 16 at the exposed surface 29.

Description

Multilayer ceramic capacitor and method of manufacturing the same

[0001] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor.

[0002] In recent years, multilayer ceramic electronic components, such as multilayer ceramic capacitors, have come to be used in harsher environments than before. Such general multilayer ceramic capacitors include a capacitive element (component body) formed by stacking multiple ceramic layers and multiple internal electrode layers, with external electrodes formed on the outer surfaces of the capacitive element. The internal electrode layers are extended to the end faces or side surfaces of the capacitive element and connected to the external electrodes. The external electrodes are composed of, for example, a base electrode formed by applying and firing a conductive paste, and a plating layer formed on the outer surface of the base electrode. The plating layer may be composed of multiple layers, as needed.

[0003] For example, Patent Document 1 discloses a multilayer ceramic capacitor including a first electrode layer containing titanium nitride (TiN) formed by atomic layer deposition on the entire surface of a laminate including ceramic layers and internal electrode layers, and a second electrode layer disposed on the first electrode layer, in order to ensure moisture resistance reliability of the multilayer ceramic capacitor. The multilayer ceramic capacitor disclosed in Patent Document 1 can ensure sufficient moisture resistance reliability even when the external electrodes are thin by forming a thin and dense first electrode layer on the body, and can function to prevent moisture from penetrating into the internal electrode layers from the outside.

[0004] Meanwhile, focusing on the ESR problem, Patent Document 2 discloses a configuration in which a plurality of grooves are formed in the ceramic layer at the end surface of the laminate where the external electrode is formed, so that the ends of the internal electrode layer are exposed. The external electrode includes a conductive resin layer containing metal particles, resin, etc., and an electrode layer on the conductive resin layer. An intermetallic compound is formed in the grooves when the conductive resin layer is formed. This intermetallic compound ensures electrical conduction between the exposed ends of the internal electrode layer and the external electrode.

[0005] JP 2019-96862 A JP 2019-117942 A

[0006] In recent years, multilayer ceramic capacitors have been rapidly becoming smaller in size, and the required characteristics of multilayer ceramic capacitors are becoming higher, with higher reliability and lower resistance being required.

[0007] However, the multilayer ceramic capacitor disclosed in Patent Document 1 has a problem in that ESR (equivalent series resistance) increases in order to ensure moisture resistance reliability, resulting in a trade-off between the two. Furthermore, the configuration of Patent Document 2 may be able to suppress the ESR problem, but does not employ a configuration for ensuring moisture resistance reliability, resulting in problems with moisture resistance reliability. Therefore, there has been a demand for a multilayer ceramic capacitor that can stably achieve both high reliability and low resistance, even in a more miniaturized multilayer ceramic capacitor.

[0008] Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor that can ensure moisture resistance reliability by suppressing the penetration of moisture from the outside to the inside of the multilayer ceramic capacitor and further achieve a low ESR resistance.

[0009] The multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of laminated ceramic layers and a plurality of internal electrode layers, a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a barrier film disposed on the laminate; and external electrodes disposed on the barrier film at the first end surface and the second end surface. The ceramic layers contain a perovskite compound represented by the general formula ABO3, in which the A site is Ba. The barrier film contains Ba and at least one of S and C. The barrier film covers the first main surface, the second main surface, the first side surface, and the second side surface, and also covers the first end surface and the second end surface except for the exposed surfaces of the first end surface and the second end surface where the internal electrode layers are exposed in the laminate. The external electrodes are in contact with the internal electrode layers at the exposed surfaces.

[0010] According to the multilayer ceramic capacitor of the present invention, it is possible to achieve a low resistance ESR while ensuring reliability in moisture resistance.

[0011] A method for manufacturing a multilayer ceramic capacitor according to the present invention includes a preparation step of firing a laminate including a plurality of laminated ceramic layers and a plurality of internal electrode layers, each containing a perovskite compound represented by the general formula ABO3 and having Ba at the A site, a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction, a film formation step of immersing the laminate in a solution containing at least one of S ions and C ions to form a barrier film containing Ba and at least one of S and C ions on the laminate, and an external electrode formation step of forming external electrodes on the barrier film at the first end surface and the second end surface. The barrier film covers the first main surface, the second main surface, the first side surface, and the second side surface, and also covers the first end surface and the second end surface except for exposed surfaces of the first end surface and the second end surface where the internal electrode layers are exposed in the laminate. The external electrodes are in contact with the internal electrode layers at their exposed surfaces.

[0012] According to the method for manufacturing a multilayer ceramic capacitor of the present invention, it is possible to obtain a multilayer ceramic capacitor that can achieve low ESR resistance while ensuring moisture resistance reliability.

[0013] According to the present invention, it is possible to provide a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor that can ensure moisture resistance reliability by suppressing the penetration of moisture from the outside to the inside of the multilayer ceramic capacitor and further achieve a low ESR resistance.

[0014] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the invention, which proceeds with reference to the accompanying drawings.

[0015] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. 2 is a cross-sectional view taken along line II-II in FIG. 1. 3 is a cross-sectional view taken along line III-III in FIG. 1. 4 is an enlarged view of A in FIG. 2. 5 is a flow diagram showing a method for manufacturing the multilayer ceramic capacitor of FIG. 1, which is a method for forming a barrier film and external electrodes. 6(a) to 6(c) are schematic cross-sectional views showing a method for forming a barrier film and external electrodes of a multilayer ceramic capacitor according to an embodiment of the present invention. 7 is a schematic cross-sectional view of a multilayer ceramic capacitor according to a comparative example. 8 is a schematic explanatory view showing an experimental method for confirming conductivity.

[0016] 1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor according to a first embodiment of the present invention will be described. Fig. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to the embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is an enlarged view of A in Fig. 2.

[0017] As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12, a barrier film 28, and external electrodes 24.

[0018] The laminate 12 includes a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16. The laminate 12 further includes a first main surface 12a and a second main surface 12b that face each other in a height direction x, a first side surface 12c and a second side surface 12d that face each other in a width direction y that is perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f that face each other in a length direction z that is perpendicular to the height direction x and the width direction y. The corners and ridges of the laminate 12 are preferably rounded. The corners refer to the intersections of three adjacent surfaces of the laminate, and the ridges refer to the intersections of two adjacent surfaces of the laminate. Furthermore, unevenness may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. Furthermore, the dimension of the laminate 12 in the length direction z is not necessarily longer than the dimension in the width direction y.

[0019] The number of ceramic layers 14, including the outer layers, is preferably 15 to 700.

[0020] The laminate 12 has, in the lamination direction connecting the first main surface 12a and the second main surface 12b, an effective layer portion 15a where the internal electrode layers 16 face each other, a first outer layer portion 15b located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a, and a second outer layer portion 15c located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The first outer layer portion 15b is located on the first main surface 12a side of the laminate 12, and is an assembly of multiple ceramic layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. The second outer layer portion 15c is located on the second main surface 12b side of the laminate 12, and is an assembly of multiple ceramic layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The region sandwiched between the first outer layer portion 15b and the second outer layer portion 15c is the effective layer portion 15a.

[0021] The dimensions of the laminate 12 are not particularly limited, but it is preferable that the dimension in the length direction z is 0.2 mm or more and 10.0 mm or less, the dimension in the width direction y is 0.1 mm or more and 10.0 mm or less, and the dimension in the height direction x is 0.1 mm or more and 5.0 mm or less.

[0022] The ceramic layer 14 can be formed, for example, from a dielectric material as the ceramic material. Such a dielectric material includes a perovskite compound represented by the general formula ABO3, in which the A site is Ba. For example, a dielectric ceramic containing a component such as BaTiO3 can be used as the dielectric material. When the dielectric material is contained as the main component, a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be added in a smaller amount than the main component, depending on the desired characteristics of the laminate 12.

[0023] The thickness of the ceramic layer 14 after firing is preferably 0.4 μm or more and 10.0 μm or less.

[0024] 2 and 3, the laminate 12 has, for example, a plurality of substantially rectangular first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are embedded so as to be alternately arranged at equal intervals along the lamination direction of the laminate 12. The first internal electrode layers 16a and the second internal electrode layers 16b may be arranged parallel to or perpendicular to the mounting surface.

[0025] The first internal electrode layer 16a has a first opposing electrode portion 18a facing the second internal electrode layer 16b, and a first lead electrode portion 20a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. An end portion of the first lead electrode portion 20a is extended to and exposed at the first end face 12e. The second internal electrode layer 16b has a second opposing electrode portion 18b facing the first internal electrode layer 16a, and a second lead electrode portion 20b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the second end face 12f of the laminate 12. An end portion of the second lead electrode portion 20b is extended to and exposed at the second end face 12f.

[0026] The shapes of the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular. However, the corners may be rounded or obliquely (tapered). The shapes of the first extraction electrode portion 20a of the first internal electrode layer 16a and the second extraction electrode portion 20b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular. However, the corners may be rounded or obliquely (tapered). The width of the first opposing electrode portion 18a of the first internal electrode layer 16a and the width of the first extraction electrode portion 20a of the first internal electrode layer 16a may be the same, or one of them may be narrower. Similarly, the width of the second opposing electrode portion 18b of the second internal electrode layer 16b and the width of the second extraction electrode portion 20b of the second internal electrode layer 16b may be formed to be the same width, or one of them may be formed to be narrower.

[0027] The laminate 12 includes side portions (W gaps) 22a of the laminate 12 formed between one ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the first side surface 12c, and between the other ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the second side surface 12d. Furthermore, the laminate 12 includes end portions (L gaps) 22b of the laminate 12 formed between an end of the first internal electrode layer 16a opposite to the first extraction electrode portion 20a and the second end surface 12f, and between an end of the second internal electrode layer 16b opposite to the second extraction electrode portion 20b and the first end surface 12e.

[0028] The internal electrode layers 16 contain an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. The internal electrode layers 16 may further contain dielectric particles having the same composition as the ceramic contained in the ceramic layers 14.

[0029] The thickness of the internal electrode layers 16 is preferably 0.2 μm or more and 2.0 μm or less, and the number of the internal electrode layers 16 is preferably 15 or more and 200 or less.

[0030] The barrier film 28 is disposed on the laminate 12. Specifically, the barrier film 28 covers the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d, and also covers the first end surface 12e and the second end surface 12f except for exposed surfaces 29 of the first end surface 12e and the second end surface 12f where the internal electrode layer 16 is exposed in the laminate 12. The end of the first extraction electrode portion 20a is drawn and exposed at the first end surface 12e, and the end of the second extraction electrode portion 20b is drawn and exposed at the second end surface 12f, thereby providing the exposed surfaces 29. At the first end surface 12e and the second end surface 12f, the barrier film 28 does not cover the exposed surfaces 29, and the exposed surfaces 29 are covered by the external electrodes 24.

[0031] The barrier film 28 contains Ba and at least one of S and C. The barrier film 28 is, for example, BaSO4, BaCO3, etc. BaSO4 and BaCO3 are hardly soluble in water, so by forming the barrier film 28 from either of these, it is possible to further suppress the penetration of liquids such as moisture into the laminate 12 from the outside.

[0032] External electrodes 24 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12. The external electrodes 24 include a first external electrode 24a and a second external electrode 24b.

[0033] The external electrode 24 includes a base electrode layer 26 containing a metal component and a glass component, and a plating layer 30 formed on the surface of the base electrode layer 26 .

[0034] The first external electrode 24a is disposed on the surface of the barrier film 28 on the first end face 12e side, and is connected to the first internal electrode layer 16a at the exposed surface 29. The first external electrode 24a also extends from the first end face 12e side and is disposed on the surface of the barrier film 28 over a portion of the first main surface 12a side, a portion of the second main surface 12b side, and a portion of the first side surface 12c side, and a portion of the second side surface 12d side. In this case, the first external electrode 24a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0035] The second external electrode 24b is disposed on the surface of the barrier film 28 on the second end face 12f side, and is connected to the second internal electrode layer 16b at the exposed surface 29. The second external electrode 24b also extends from the second end face 12f side and is disposed on the surface of the barrier film 28 over a portion of the first main surface 12a side, a portion of the second main surface 12b side, and a portion of the first side surface 12c side, and a portion of the second side surface 12d side. In this case, the second external electrode 24b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0036] In the laminate 12, capacitance is formed by the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b facing each other via the ceramic layer 14. Therefore, capacitance can be obtained between the first external electrode 24a to which the first internal electrode layer 16a is connected and the second external electrode 24b to which the second internal electrode layer 16b is connected, and the characteristics of a capacitor are exhibited.

[0037] The base electrode layer 26 includes a first base electrode layer 26a and a second base electrode layer 26b.

[0038] The first base electrode layer 26a is disposed on the surface of the barrier film 28 on the first end face 12e side of the laminate 12 and is connected to the first internal electrode layer 16a at an exposed surface 29. At the exposed surface 29, as shown in FIG. 4 , an alloy layer 40 is formed by interdiffusion of Cu in the first base electrode layer 26a and Ni in the first internal electrode layer 16a. This alloy layer 40 is denser than the first internal electrode layer 16a and the first base electrode layer 26a themselves, thereby improving the bonding strength between the first base electrode layer 26a and the first internal electrode layer 16a. This further reduces the ESR. The first base electrode layer 26a extends from the first end face 12e side to cover portions of the surfaces of the barrier film 28 on the first main surface 12a side, the second main surface 12b side, the first side surface 12c side, and the second side surface 12d side. The second base electrode layer 26b is disposed on the surface of the barrier film 28 on the second end face 12f side of the laminate 12 and is connected to the second internal electrode layer 16b at an exposed surface 29. At the exposed surface 29, as shown in FIG. 4 , an alloy layer 40 is formed by interdiffusion of Cu in the second base electrode layer 26b and Ni in the second internal electrode layer 16b. This alloy layer 40 is denser than the second internal electrode layer 16b and the second base electrode layer 26b themselves, thereby improving the bonding strength between the second base electrode layer 26b and the second internal electrode layer 16b. This further reduces the ESR. The second base electrode layer 26b extends from the second end face 12f side to cover portions of the surfaces of the barrier film 28 on the first main surface 12a side, the second main surface 12b side, the first side surface 12c side, and the second side surface 12d side. The first base electrode layer 26a may be arranged only on the surface of the barrier film 28 on the first end face 12e side of the laminate 12, and the second base electrode layer 26b may be arranged only on the surface of the barrier film 28 on the second end face 12f side of the laminate 12.

[0039] Next, a configuration in which the base electrode layer 26 is the baked layer will be described.

[0040] The baking layer contains a glass component and a metal component. The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baking layer may be a multi-layered layer. The baking layer is formed by applying a conductive paste containing a glass component and a metal component to the laminate 12 and baking it. The baking layer may be formed by simultaneously baking a laminated chip having the internal electrode layer 16 and ceramic layer 14 before firing with the conductive paste applied to the laminated chip. Alternatively, the laminated chip having the internal electrode layer 16 and ceramic layer 14 before firing may be baked to obtain the laminate 12, and then the conductive paste may be applied to the laminate 12 and baked. Note that when the baking layer is formed by simultaneously baking a laminated chip having the internal electrode layer 16 and ceramic layer 14 with the conductive paste applied to the laminated chip, it is preferable to add a ceramic material instead of the glass component to form the baking layer.

[0041] The thicknesses of the first and second baked layers at the center in the height direction x of the first and second base electrode layers 26a, 26b located on the first end face 12e and the second end face 12f are preferably, for example, about 10 μm to 160 μm. Furthermore, when the base electrode layer 26 is provided on the first and second main faces 12a, 12b and the first and second side faces 12c, 12d, the thicknesses of the first and second baked layers at the center in the length direction z of the first and second base electrode layers 26a, 26b located on the first and second main faces 12a, 12b and the first and second side faces 12c, 12d are preferably, for example, about 5 μm to 40 μm.

[0042] The plating layer 30 includes a first plating layer 30a and a second plating layer 30b.

[0043] Next, the first plating layer 30a and the second plating layer 30b, which are plating layers 30 that can be disposed on the base electrode layer 26, will be described with reference to Figures 2 and 3. The first plating layer 30a and the second plating layer 30b contain, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, and the like.

[0044] The first plating layer 30a is disposed so as to cover the first base electrode layer 26a, and the second plating layer 30b is disposed so as to cover the second base electrode layer 26b.

[0045] The first plating layer 30 a and the second plating layer 30 b may be formed of multiple layers. In this case, the plating layer 30 preferably has a two-layer structure including a lower plating layer 32 formed by Ni plating on the base electrode layer 26 and an upper plating layer 34 formed by Sn plating on the lower plating layer 32.

[0046] That is, the first plating layer 30a has a first lower plating layer 32a and a first upper plating layer 34a located on the surface of the first lower plating layer 32a, and the second plating layer 30b has a second lower plating layer 32b and a second upper plating layer 34b located on the surface of the second lower plating layer 32b.

[0047] The lower plating layer 32 made of Ni plating is used to prevent the base electrode layer 26 from being eroded by solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer 34 made of Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each plating layer is preferably 2.0 μm or more and 15.0 μm or less.

[0048] The dimension of the multilayer ceramic capacitor 10 in the length direction z, including the laminate 12, the first external electrode 24a, and the second external electrode 24b, is defined as dimension L. The dimension of the multilayer ceramic capacitor 10 in the height direction x, including the laminate 12, the first external electrode 24a, and the second external electrode 24b, is defined as dimension T. The dimension of the multilayer ceramic capacitor 10 in the width direction y, including the laminate 12, the first external electrode 24a, and the second external electrode 24b, is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are not particularly limited, but are preferably L in the length direction z between 0.2 mm and 7.5 mm, W in the width direction y between 0.1 mm and 3.5 mm, and T in the height direction x between 0.2 mm and 3.5 mm. Note that the L dimension in the length direction z is not necessarily longer than the W dimension in the width direction y. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0049] In the multilayer ceramic capacitor 10 shown in FIG. 1 , the first and second principal surfaces 12a, 12b and the first and second side surfaces 12c, 12d of the laminate 12 are covered with a barrier film 28. The first and second end surfaces 12e, 12f of the laminate 12 are also covered with the barrier film 28, except for the exposed surfaces 29 of the internal electrode layers 16. The exposed surfaces 29 are also covered with the first and second external electrodes 24a, 24b. In other words, the laminate 12 is covered with the barrier film 28 and the first and second external electrodes 24a, 24b. Therefore, the barrier film 28 and the first and second external electrodes 24a, 24b prevent the intrusion of liquids such as moisture into the laminate 12 from the outside, thereby improving moisture resistance reliability. For example, if grain boundaries are formed within the ceramic layers 14, they may become vulnerable to the intrusion of moisture, potentially damaging the ceramic layers 14. Grain boundaries are the boundaries between particles of glass or the like that constitute the ceramic layers 14. However, the above-described configuration can prevent moisture and the like from penetrating into the laminate 12, thereby preventing damage to the ceramic layers 14.

[0050] Furthermore, according to the above configuration, a barrier film 28 is also provided between the external electrode 24 and the laminate 12, so that even if the external electrode 24 has a hole or the like and is damaged, the barrier film 28 can prevent moisture and the like from passing through the external electrode 24 and entering the laminate 12.

[0051] Furthermore, according to the above configuration, since the barrier film 28 is not formed on the exposed surface 29, the internal electrode layer 16 and the external electrode 24 are directly connected to each other on the exposed surface 29. Therefore, the conductivity between the internal electrode layer 16 and the external electrode 24 is ensured, and the ESR (Equivalent Series Resistance) can be reduced.

[0052] As described above, the above configuration makes it possible to achieve a low ESR resistance while ensuring moisture resistance reliability.

[0053] Furthermore, even if the base electrode layer 26 contains a glass component that is sensitive to moisture, the barrier film 28 is formed on almost the entire laminate 12 except for the exposed surface 29, so that it is possible to prevent liquids such as moisture from penetrating into the laminate 12 from the outside.

[0054] 2. Method for Manufacturing a Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0055] First, a ceramic paste containing ceramic powder is applied in the form of a sheet by, for example, screen printing, and then dried to produce a ceramic green sheet.

[0056] Next, a conductive paste for forming internal electrodes is prepared, and the conductive paste for forming internal electrodes is applied to the ceramic green sheets in a predetermined pattern, for example, by screen printing or gravure printing, to prepare ceramic green sheets on which a conductive pattern for forming internal electrodes is formed and ceramic green sheets on which a conductive pattern for forming internal electrodes is not formed.

[0057] The ceramic paste and the conductive paste for forming the internal electrodes may contain, for example, a known organic binder or solvent.

[0058] Next, a predetermined number of ceramic green sheets for outer layers on which no conductive pattern for forming internal electrodes is formed are laminated, and then ceramic green sheets on which a conductive pattern for forming internal electrodes is formed are laminated in order thereon, and then a predetermined number of ceramic green sheets on which no conductive pattern for forming internal electrodes is formed are laminated to produce a mother laminate. At this time, a plurality of ceramic green sheets on which a conductive pattern for forming internal electrodes is printed are laminated so that the lead portions of the conductive pattern for forming internal electrodes are staggered to produce a laminate sheet.

[0059] The laminated sheets are pressed together in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0060] The laminated block is then cut into a predetermined shape and size to produce raw laminated chips, which may have rounded corners and ridges by barrel polishing or the like.

[0061] The cut raw laminate chip is then fired, and the first internal electrode layer and the second internal electrode layer are disposed inside the laminate, and the first internal electrode layer is extended to the first end face, and the second internal electrode layer is extended to the second end face, to produce the laminate 12. The firing temperature for the raw laminate chip depends on the ceramic material and the material of the conductive paste for forming the internal electrodes, but is preferably 900°C or higher and 1300°C or lower.

[0062] Next, a barrier film 28 is formed on the resulting laminate 12. However, a process of treating the end faces 12e, 12f of the laminate 12 may be added before forming the barrier film 28. Because the firing temperatures for the conductive paste for forming the internal electrodes and the ceramic paste are different, shrinkage may occur at different times during the firing process. As a result, in the fired laminate 12, the ends of the ceramic layers 14 and the ends of the internal electrode layers 16 are not flush with each other at the first and second end faces 12e, 12f in the longitudinal direction z. Instead, the ends of the internal electrode layers 16 are located more inward than the ends of the ceramic layers 14 (toward the interior of the laminate 12 in the longitudinal direction z). In other words, a step occurs between the ends of the internal electrode layers 16 and the ends of the ceramic layers 14. If such a step remains, the degree of contact between the external electrode 24 and the internal electrode layers 16 may be reduced when forming external electrodes 24 on the ends of the internal electrode layers 16 and the ends of the ceramic layers 14 at the first and second end faces 12e, 12f. Therefore, the fired laminate 12 may be subjected to a method such as blasting to remove the ends of the ceramic layers 14 at the first and second end faces 12e, 12f of the laminate 12, thereby reducing the above-mentioned step, or the ends of the internal electrode layers 16 and the ends of the ceramic layers 14 may be processed to be flush with each other.

[0063] Next, a barrier film 28 is formed on the laminate 12. Fig. 5 is a flow diagram showing a method for forming the barrier film and external electrodes in a method for manufacturing the multilayer ceramic capacitor of Fig. 1. In Fig. 6, (a) to (c) are schematic cross-sectional views showing a method for forming the barrier film and external electrodes of the multilayer ceramic capacitor according to an embodiment of the present invention.

[0064] First, after the laminate 12 is produced (S11), the laminate 12 is immersed in a solution (S12). The solution contains at least one of S ions and C ions. For example, the entire laminate 12 is immersed in the solution at room temperature and left to stand for 15 minutes. The solution may be stirred. Preferably, the solution does not dissolve the internal electrode layers and the laminate and remains liquid. Examples of solutions containing S ions include Na2SO4, K2SO4, CuSO4, NiSO4, Al2(SO4)3, and MnSO4. Examples of solutions containing C ions include Na2CO3, K2CO3, CuCO3, NiCO3, Al2(CO3)3, and MnCO3. The concentration of the solution is, for example, 50 g / l.

[0065] 6(a), a barrier film 28 is formed on the laminate 12. When the solution contains S ions, Ba in the ceramic layers 14 of the laminate 12 reacts with the S ions, forming a barrier film 28 made of BaSO4 on the laminate 12. When the solution contains C ions, Ba in the ceramic layers 14 of the laminate 12 reacts with the C ions, forming a barrier film 28 made of BaCO3 on the laminate 12. However, since the solution does not react with the internal electrode layers 16, the barrier film 28 is not formed on the exposed surfaces 29 of the internal electrode layers 16.

[0066] After immersion in the solution, the laminate 12 is removed from the solution and dried (S13). For example, the solution adhering to the laminate 12 is drained using a DSC (vacuum suction machine). This makes it possible to remove droplets from the barrier film 28. As a drying method, for example, heat treatment using a dryer at about 100°C can also be used.

[0067] Next, external electrodes 24 are formed on the laminate 12. A conductive paste for external electrodes is applied to both end surfaces of the laminate 12 on which the barrier film 28 has been formed (S14). The applied conductive paste for external electrodes is then fired to form baked layers as the first base electrode layer 26a of the first external electrode 24a and the second base electrode layer 26b of the second external electrode 24b, as shown in FIG. 6(b) (S15). At this time, on the exposed surface 29, the first and second base electrode layers 26a, 26b are in direct contact with and electrically connected to the first and second internal electrode layers 16a, 16b. Furthermore, on the exposed surface 29, as shown in FIG. 4, for example, an alloy layer 40 is formed by Cu in the first and second base electrode layers 26a, 26b and Ni in the first and second internal electrode layers 16a, 16b.

[0068] When forming the baked layer, a conductive paste containing a glass component and a metal component is applied by, for example, dipping or other methods, and baked to form the baked layer as the base electrode layer 26. The baking temperature is preferably 700°C or higher and 900°C or lower.

[0069] 6(c), a lower plating layer 32 is formed on the surface of the base electrode layer 26 (S16), and an upper plating layer 34 is formed on the surface of the lower plating layer 32 (S17). This process forms the external electrode 24. In the multilayer ceramic capacitor 10 shown in FIG. 1, a Ni plating layer is formed as the lower plating layer 32 on the base electrode layer 26, and a Sn plating layer is formed as the upper plating layer 34. The lower plating layer 32 and the upper plating layer 34 are formed by electrolytic plating, electroless plating, or the like. Preferably, the plating layers are formed in multiple layers.

[0070] In the manner described above, the multilayer ceramic capacitor 10 shown in FIG. 1 is manufactured.

[0071] 3. Experimental Example Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitors were manufactured and subjected to a humidity resistance reliability test and an ESR measurement test.

[0072] (1) Specifications of Samples in Examples First, multilayer ceramic capacitors according to the examples having the following specifications were fabricated according to the above-described method for manufacturing a multilayer ceramic capacitor.

[0073] (Example) Structure of multilayer ceramic capacitor: two terminals (see Figures 1 to 3) Dimensions of multilayer ceramic capacitor L x W x T (including design values): 1.0 mm x 0.5 mm x 0.5 mm Ceramic layer material: BaTiO3 Capacitance: 10 μF Rated voltage: 6.3 V Structure of internal electrode layer Metal component: Cu Structure of barrier film Component: BaSO4 Structure of external electrode Base electrode layer Metal component: Ni Plating layer: two-layer structure of Ni plating layer and Sn plating layer

[0074] (2) Specifications of Sample in Comparative Example Next, a multilayer ceramic capacitor 10A according to a comparative example was fabricated with the following specifications. Fig. 7 is a schematic cross-sectional view of the multilayer ceramic capacitor according to the comparative example. The multilayer ceramic capacitor 10A according to the comparative example has the same specifications as the multilayer ceramic capacitor 10 according to the example, except that the barrier film 28 is not formed, unlike the multilayer ceramic capacitor 10 according to the example.

[0075] (3) Test Methods (a) Moisture Resistance Reliability Test Samples according to the examples and samples according to the comparative examples were mounted on a substrate, and the substrate was placed in a high-temperature, high-humidity chamber. A voltage of 4 V was applied to each sample for 200 hours under an environment of 85°C and 85% RH. Subsequently, the insulation resistance value of each sample after the moisture resistance reliability test was measured. The insulation resistance values ​​of each sample before and after the moisture resistance reliability test were compared, and samples that did not show a decrease in insulation resistance value by one digit or more were considered good. The number of samples for each test was 20. In Table 2, if 10% or more of each sample were found to be defective, the sample was judged as NG and indicated by "X," and the rest were indicated by "O."

[0076] (b) ESR Measurement Test: A cross section of each sample was processed, and when a probe was applied to the internal electrode layer and the Sn plating layer, an ESR value of 100 Ω or less was deemed good. Seven samples were used for each test. In Table 2, if two or more of the seven samples were defective, the test was judged as NG and indicated with an "x." Otherwise, the test was indicated with an "o." To confirm conductivity, each sample was polished to expose the LT cross section, and then a measuring device including a voltmeter 41 and an ammeter 42 was attached to positions P1, P2, P3, and P4 shown in Figure 8. The resistance between P1 and P3 (2-3 cm) was measured using the four-terminal method. For example, a digital multimeter (PC7000, manufactured by Sanwa Electric Instruments Co., Ltd.) was used to measure the voltage between P1 and P2 and the current between P3 and P4. When the measurement voltage is 100 mV, if the internal electrode layer and the external electrode are electrically connected, it is possible to measure a current of, for example, several hundred mA according to Ohm's law. On the other hand, if the electrical connection between the internal electrode layer and the external electrode is poor, the current will be several tens of mA or less.

[0077] The evaluation results are shown in Table 1.

[0078]

[0079] (4) Experimental Results According to Table 1, the multilayer ceramic capacitor 10, a sample according to the example, has a barrier film formed on both end faces, both main faces, and both side faces to cover the surface of the laminate, and both end faces are covered with external electrodes. Therefore, moisture penetration from the outside can be suppressed, and the capacitor was judged as good in the moisture resistance reliability test. Furthermore, according to Table 1, the multilayer ceramic capacitor 10, a sample according to the example, ensures conductivity between the external electrodes and the internal electrode layers through the exposed surfaces, and the capacitor was judged as good in the ESR measurement test. The ESR measurement test of the multilayer ceramic capacitor 10, a sample according to the example, was good, similar to the ESR measurement test of the multilayer ceramic capacitor 10A, a sample according to the comparative example. This indicates that the presence of the barrier film 28 does not inhibit the reduction of ESR resistance. From the above, it is clear that the multilayer ceramic capacitor 10, a sample according to the example, can maintain a low ESR resistance.

[0080] On the other hand, the sample multilayer ceramic capacitor 10A according to the comparative example was judged as defective in the moisture resistance reliability test because it did not have a barrier film formed thereon, and the sample multilayer ceramic capacitor 10A according to the comparative example was judged as good in the ESR measurement test because it ensured conductivity between the internal electrode layers and the plating layers because it did not have a barrier film formed thereon.

[0081] As described above, the multilayer ceramic capacitor 10 according to the present invention has a barrier film formed on both end faces, both main faces, and both side faces so as to cover the surface of the laminate, and both end faces are covered with external electrodes. Furthermore, conductivity between the external electrodes and the internal electrode layers is ensured via the exposed surfaces. Therefore, it has become clear that it is possible to suppress the intrusion of moisture from the outside, improve moisture resistance reliability, and maintain low ESR resistance.

[0082] Although a barrier film is formed between the external electrode and the laminate, since moisture resistance reliability and low ESR resistance have been achieved, it is believed that the external electrode and the barrier film are firmly attached and that the presence of the barrier film has not caused peeling of the external electrode.

[0083] As described above, although the embodiments of the present invention have been disclosed in the above description, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0084] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated ceramic layers and a plurality of internal electrode layers, the laminate including first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height and width directions; a barrier film disposed on the laminate; and external electrodes disposed on the barrier film at the first end surface and the second end surface, wherein the ceramic layers contain a perovskite compound represented by the general formula ABO3 and in which the A site is Ba, the barrier film contains Ba and at least one of S and C, the barrier film covers the first main surface, the second main surface, the first side surface, and the second side surface, and also covers the first end surface and the second end surface except for exposed surfaces of the first end surface and the second end surface where the internal electrode layer is exposed in the laminate, and the external electrodes are in contact with the internal electrode layer at the exposed surfaces.

[0085] <2> The multilayer ceramic capacitor according to <1>, wherein the barrier film is made of at least one of barium sulfate and barium carbonate.

[0086] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the internal electrode layers contain Ni as a main component, and the external electrodes have a base electrode layer containing Cu as a main component and a plating layer on the base electrode layer, and the internal electrode layers and the base electrode layer are in contact with each other at the exposed surfaces.

[0087] <4> The multilayer ceramic capacitor according to <3>, wherein the base electrode layer contains a glass component and a metal component.

[0088] <5> A method for manufacturing a semiconductor device, comprising: a preparation step of firing a laminate including a plurality of laminated ceramic layers and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a film formation step of immersing the laminate in a solution containing at least one of S ions and C ions to form a barrier film containing Ba and at least one of S and C on the laminate; and an external electrode formation step of forming external electrodes on the barrier film at the first end surface and the second end surface, the barrier film covers the first principal surface, the second principal surface, the first side surface, and the second side surface, and also covers the first end surface and the second end surface except for exposed surfaces of the first end surface and the second end surface where the internal electrode layers are exposed in the laminate, and the external electrodes are in contact with the internal electrode layers at the exposed surfaces.

[0089] <6> The method for producing a multilayer ceramic capacitor according to <5>, wherein the barrier film is made of at least one of barium sulfate and barium carbonate.

[0090] <7> The method for manufacturing a multilayer ceramic capacitor according to <5> or <6>, wherein the internal electrode layer contains Ni as a main component, and the external electrode has a base electrode layer containing Cu as a main component and a plating layer on the base electrode layer, and the internal electrode layer and the base electrode layer are in contact with each other at the exposed surface.

[0091] <8> The method for producing a multilayer ceramic capacitor according to <7>, wherein the base electrode layer contains a glass component and a metal component.

[0092] REFERENCE SIGNS LIST 10 Multilayer ceramic capacitor 12 Laminate 12a First main surface 12b Second main surface 12c First side surface 12d Second side surface 12e First end surface 12f Second end surface 14 Ceramic layer 15a Effective layer portion 15b First outer layer portion 15c Second outer layer portion 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18a First opposing electrode portion 18b Second opposing electrode portion 20a First lead electrode portion 20b Second lead electrode portion 22a Side portion (W gap) 22b End portion (L gap) 24 External electrode 24a First external electrode 24b Second external electrode 26 Base electrode layer 26a First base electrode layer 26b Second base electrode layer 28 Barrier film 29 Exposed surface 30: Plating layer 30a: First plating layer 30b: Second plating layer 32: Underlayer plating layer 32a: First underlayer plating layer 32b: Second underlayer plating layer 34: Upper layer plating layer 34a: First upper layer plating layer 34b: Second upper layer plating layer x: Height direction y: Width direction z: Length direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated ceramic layers and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a barrier film disposed on the laminate; and an external electrode disposed on the barrier film at the first end surface and the second end surface, wherein the ceramic layers comprise a perovskite compound represented by the general formula ABO3 and in which the A site is Ba, the barrier film comprises Ba and at least one of S and C, the barrier film covers the first main surface, the second main surface, the first side surface and the second side surface, and also covers the first end surface and the second end surface except for exposed surfaces of the first end surface and the second end surface where the internal electrode layer is exposed in the laminate, and the external electrode is in contact with the internal electrode layer at the exposed surface.

2. The multilayer ceramic capacitor according to claim 1, wherein the barrier film is at least one of barium sulfate and barium carbonate.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the internal electrode layer contains Ni as a main component, the external electrode has a base electrode layer containing Cu as a main component and a plating layer on the base electrode layer, and the internal electrode layer and the base electrode layer are in contact with each other at the exposed surface.

4. The multilayer ceramic capacitor according to claim 3, wherein the base electrode layer contains a glass component and a metal component.

5. A method for manufacturing a semiconductor device comprising: a preparation step of firing a laminate including a plurality of laminated ceramic layers and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface opposed to each other in a height direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the height direction and the width direction; a film formation step of forming a barrier film containing Ba and at least one of S and C on the laminate by immersing the laminate in a solution containing at least one of S ions and C ions; and an external electrode formation step of forming external electrodes on the barrier film at the first end surface and the second end surface, a first main surface, a second main surface, a first side surface, and a second side surface, and also covers the first end surface and the second end surface except for exposed surfaces of the first end surface and the second end surface where the internal electrode layer is exposed in the laminate, and the external electrode is in contact with the internal electrode layer at the exposed surfaces.

6. The method for producing a multilayer ceramic capacitor according to claim 5, wherein the barrier film is at least one of barium sulfate and barium carbonate.

7. A method for manufacturing a multilayer ceramic capacitor as set forth in claim 5 or 6, wherein the internal electrode layer contains Ni as a main component, the external electrode has a base electrode layer containing Cu as a main component and a plating layer on the base electrode layer, and the internal electrode layer and the base electrode layer are in contact with each other at the exposed surface.

8. The method for producing a multilayer ceramic capacitor according to claim 7, wherein the base electrode layer contains a glass component and a metal component.

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