Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor in which occurrence of "singing" is suppressed and which is reduced in size and increased in capacity.　This multilayer ceramic capacitor comprises a plurality of dielectric layers 20 and a plurality of inner electrode layers 30 which are alternately layered in a layering direction T, and a first side face WS1 and a second side face WS2 which face each other in a width direction W, wherein the distance L1 between the first side face WS1 and an end E1L which is the closest to the first side face WS1 of the ends of the plurality of inner electrode layers 30 on the first side face WS1 side is smaller than the distance L2 between the second side face WS2 and an end E2L which is the closest to the second side face WS2 of the ends of the plurality of inner electrode layers 30 on the second side face WS2 side, and a distance L3 which is the maximum of the distances in the width direction W between the ends of the plurality of inner electrode layers 30 in the width direction W that are side by side on the first side face WS1 side is smaller than a distance L4 which is the maximum of the distances in the width direction W between the ends of the plurality of inner electrode layers 30 in the width direction W that are side by side on the second side face WS2.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, multilayer ceramic capacitors widely used in various electronic devices, such as mobile terminal devices such as mobile phones and personal computers, have a structure comprising a rectangular parallelepiped laminate including inner layer portions in which dielectric layers and internal electrode layers are alternately stacked, outer layer portions formed above and below the inner layer portions, and external electrodes on both longitudinal end faces of the laminate. With the recent development of electronic devices, further miniaturization and higher capacitance are required for such multilayer ceramic capacitors.

[0003] On the other hand, when a multilayer ceramic capacitor is mounted on a substrate, it is prone to generating vibration noise, known as "squeak." To suppress the generation of "squeak," a multilayer ceramic capacitor is known that includes a spacer formed to cover part of the external electrode on the side where the multilayer ceramic capacitor is mounted on the substrate.

[0004] Japanese Patent Application Laid-Open No. 2015-216337

[0005] However, multilayer ceramic capacitors equipped with spacers have had problems with the cost of arranging the spacers and the precision with which the spacers are arranged.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that is small in size and has a high capacitance, while suppressing the occurrence of "squeak noise."

[0007] The inventors discovered that by adjusting the arrangement of the ends aligned along one side surface and the arrangement of the ends aligned along the other side surface of a plurality of widthwise ends of internal electrode layers aligned along two opposing side surfaces of a laminate, it is possible to suppress the occurrence of "noise" in a multilayer ceramic capacitor while achieving miniaturization and high capacitance, and have completed the present invention.

[0008] That is, the present invention provides a laminate having a substantially rectangular parallelepiped shape, including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and having first and second main surfaces opposing each other in the stacking direction, first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction, and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; and a pair of external electrodes arranged at both ends in the length direction of the laminate so as to cover at least the first end surface and the second end surface, respectively, and connected to the internal electrode layers, wherein the distance between an end closest to the first side surface among ends in the width direction on the first side surface side of the plurality of internal electrode layers and the first side surface is smaller than the distance between an end closest to the second side surface among ends in the width direction on the second side surface side of the plurality of internal electrode layers and the second side surface, The multilayer ceramic capacitor is such that the maximum distance in the width direction between the ends of the plurality of internal electrode layers aligned on the first side surface side is smaller than the maximum distance in the width direction between the ends of the plurality of internal electrode layers aligned on the second side surface side.

[0009] According to the present invention, it is possible to reduce the size and increase the capacitance of a multilayer ceramic capacitor while suppressing the occurrence of "squeak noise."

[0010] 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view (LT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II; FIG. 3 is a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 taken along line III-III; FIG. 4 is a cross-sectional view (WT cross-section) showing a mounted state of the multilayer ceramic capacitor shown in FIG. 5; FIG. 6 is an enlarged view of an end of an internal electrode layer of the multilayer ceramic capacitor shown in FIG. 6; FIG. 7 is a perspective view showing a laminate chip which is a precursor of the laminate constituting the multilayer ceramic capacitor shown in FIG. 7; FIG. 8 is a view showing a state in which a side covering portion is attached to the laminate chip shown in FIG.

[0011] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0012] (Multilayer Ceramic Capacitor) Fig. 1 is a perspective view showing a multilayer ceramic capacitor according to this embodiment, Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II, and Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line III-III. The multilayer ceramic capacitor 1 shown in Figs. 1 to 3 includes a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0013] 1 to 3 show an XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10. Therefore, the cross section shown in FIG. 2 is also referred to as an LT cross section, and the cross section shown in FIG. 3 is also referred to as a WT cross section.

[0014] The length direction L, width direction W, and stacking direction T do not necessarily have to be perpendicular to each other, and may intersect each other.

[0015] The laminate 10 has a substantially rectangular parallelepiped shape, and has a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in the width direction W, and a first end surface LS1 and a second end surface LS2 that face each other in the length direction L. The surface of each surface may be uneven or may be roughened.

[0016] It is preferable that the corners and ridges of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate 10 intersect, and a ridge is a portion where two surfaces of the laminate 10 intersect.

[0017] 2 and 3 , the laminate 10 has a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in a stacking direction T. The laminate 10 also has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 101 and a second outer layer portion 102 arranged to sandwich the inner layer portion 100.

[0018] The internal layer portion 100 includes some of the dielectric layers 20 and a plurality of internal electrode layers 30. In the internal layer portion 100, the plurality of internal electrode layers 30 are arranged opposite each other with the dielectric layers 20 interposed therebetween. The internal layer portion 100 is a portion that generates capacitance and essentially functions as a capacitor.

[0019] The first outer layer portion 101 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 102 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 101 is disposed between the first main surface TS1 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the first main surface TS1, and the second outer layer portion 102 is disposed between the second main surface TS2 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the second main surface TS2. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30.

[0020] The material of the dielectric layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ A dielectric ceramic containing, as a main component, a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like may be added as a secondary component to the material of the dielectric layer 20.

[0021] The thickness of the dielectric layers 20 is not particularly limited, but is preferably 0.40 μm or more and 0.50 μm or less, and more preferably 0.40 μm or more and 0.45 μm or less. The number of dielectric layers 20 is not particularly limited, but is preferably 100 or more and 2000 or less. The number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion and the dielectric layers in the outer layer portion.

[0022] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the stacking direction T of the laminate 10.

[0023] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312 , and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322 .

[0024] The opposing electrode portions 311 and 321 face each other via the dielectric layer 20 in the stacking direction T of the laminate 10. The shapes of the opposing electrode portions 311 and 321 are not particularly limited and may be, for example, approximately rectangular. The opposing electrode portions 311 and 321 are portions that generate electrostatic capacitance and essentially function as capacitors.

[0025] The lead electrode portion 312 extends from the counter electrode portion 311 toward the first end surface LS1 of the laminate 10 and is exposed at the first end surface LS1. The lead electrode portion 322 extends from the counter electrode portion 321 toward the second end surface LS2 of the laminate 10 and is exposed at the second end surface LS2. The lengths in the width direction W of the counter electrode portion 311 and the lead electrode portion 312 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed first end surface LS1. The lengths in the width direction W of the counter electrode portion 321 and the lead electrode portion 322 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed second end surface LS2.

[0026] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end surface LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end surface LS1 of the laminate 10, i.e., the first external electrode 41.

[0027] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a main component, or as a component other than the main component, at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a component other than the main component, particles of a dielectric material having the same composition as the ceramic contained in the dielectric layer 20. In this specification, the term "main component metal" refers to the metal component with the highest weight percentage.

[0028] The thicknesses of the first internal electrode layers 31 and the second internal electrode layers 32 are not particularly limited, but are preferably, for example, 0.30 μm or more and 0.40 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layers 31 and the second internal electrode layers 32 is not particularly limited, but is preferably, for example, 10 to 1,000.

[0029] The thicknesses of the dielectric layers 20 and the internal electrode layers 30 may be measured by, for example, observing the LT cross section of the laminate exposed by polishing near the center in the width direction with a scanning electron microscope. Each value may be an average value of measurements taken at multiple locations in the length direction, or may be an average value of measurements taken at multiple locations in the stacking direction.

[0030] As shown in Fig. 3, the laminate 10 has, in the width direction W, an electrode facing portion W30 where the internal electrode layers 30 face each other, and a first side gap WG1 and a second side gap WG2 arranged to sandwich the electrode facing portion W30. The first side gap WG1 is located between the electrode facing portion W30 and the first side surface WS1, and the second side gap WG2 is located between the electrode facing portion W30 and the second side surface WS2. More specifically, the first side gap WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap WG1 and the second side gap WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are also called W gaps.

[0031] There may be segregation of Si at the end in the width direction W on the first side face WS1 side of the internal electrode layer 30, and the presence of segregation of Si improves the flexural strength of the multilayer ceramic capacitor 1. The amount of segregation of Si in the width direction W on the second side face WS2 side of the internal electrode layer 30 may be smaller than that at the end in the width direction W on the first side face WS1 side.

[0032] 2 , the laminate 10 has, in the longitudinal direction L, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap LG1, and a second end gap LG2. The first end gap LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second end gap LG2 is located between the electrode facing portion L30 and the second end face LS2. More specifically, the first end gap LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap LG1 does not include the second internal electrode layer 32 but includes the first internal electrode layer 31 and the dielectric layer 20, and the second end gap LG2 does not include the first internal electrode layer 31 but includes the second internal electrode layer 32 and the dielectric layer 20. The first end gap LG1 is a portion that functions as a lead electrode portion to the first end surface LS1 of the first internal electrode layer 31, and the second end gap LG2 is a portion that functions as a lead electrode portion to the second end surface LS2 of the second internal electrode layer 32. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0033] The electrode opposing portion L30 is located with the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32. The first end gap portion LG1 is located with the lead-out electrode portion 312 of the first internal electrode layer 31, and the second end gap portion LG2 is located with the lead-out electrode portion 322 of the second internal electrode layer 32.

[0034] The thickness of the laminate 10 can be measured, for example, by observing an LT cross section near the center of the width of the laminate exposed by polishing, or a WT cross section near the center of the length of the laminate exposed by polishing, using a scanning electron microscope. Each value may also be the average of measurements taken at multiple locations in the length or width direction. Similarly, the length of the laminate 10 can be measured, for example, by observing an LT cross section near the center of the width of the laminate exposed by polishing, using a scanning electron microscope. Each value may also be the average of measurements taken at multiple locations in the stacking direction. Similarly, the width of the laminate 10 can be measured, for example, by observing a WT cross section near the center of the length of the laminate exposed by polishing, using a scanning electron microscope. Each value may also be the average of measurements taken at multiple locations in the stacking direction.

[0035] The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0036] The first external electrode 41 is disposed on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. Alternatively, the first external electrode 41 may extend from the first end face LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0037] The second external electrode 42 is disposed on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2. The second external electrode 42 may also extend from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0038] The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may be composed of only the first plating layer 416, and the second external electrode 42 may be composed of only the second plating layer 426.

[0039] The first base electrode layer 415 and the second base electrode layer 425 may be fired layers containing a metal and glass. The glass may be a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, etc. A specific example is borosilicate glass. The metal may contain Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, as a main component or as a component other than the main component.

[0040] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0041] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layers may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0042] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the layer. The resin layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The resin layer may also be a multi-layered layer.

[0043] The thickness of each of the first base electrode layer 415 and the second base electrode layer 425 as a fired layer or a resin layer is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0044] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition, on which metal particles are deposited.

[0045] First plating layer 416 covers at least a portion of first base electrode layer 415, and second plating layer 426 covers at least a portion of second base electrode layer 425. First plating layer 416 and second plating layer 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag—Pd alloys.

[0046] The first plating layer 416 and the second plating layer 426 may each be formed of multiple layers. Preferably, they have a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, facilitating mounting. The first plating layer 416 and the second plating layer 426 may each have a three-layer structure, for example, by stacking Sn plating, Ni plating, and Sn plating. The outermost layer may be Au plating.

[0047] The thickness of each of first plating layer 416 and second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0048] As shown in FIG. 4, the multilayer ceramic capacitor 1 is mounted on the circuit board CB with the second side surface WS2 facing the circuit board CB.

[0049] (Internal electrode layers) Next, a further description will be given of the internal electrode layers 30, i.e., the first internal electrode layers 31 and the second internal electrode layers 32. Fig. 5 is an enlarged view of the ends of the internal electrode layers of the multilayer ceramic capacitor shown in Fig. 4, and schematically shows variations in the arrangement of the ends of the internal electrode layers 30, i.e., the first internal electrode layers 31 and the second internal electrode layers 32, in the width direction W.

[0050] 5, the distance L1 between the first side surface WS1 and an end E1L closest to the first side surface WS1 among the ends in the width direction W on the first side surface WS1 side of the internal electrode layer 30 is smaller than the distance L2 between the second side surface WS2 and an end E2L closest to the second side surface WS2 among the ends in the width direction W on the second side surface WS2 side of the internal electrode layer 30. In addition, the maximum distance L3 in the width direction W between the ends in the width direction W aligned on the first side surface WS1 side of the internal electrode layer 30 is smaller than the maximum distance L4 in the width direction W between the ends in the width direction W aligned on the second side surface WS2 side of the internal electrode layer 30.

[0051] Here, the maximum distance L3 in the width direction W between the ends in the width direction W aligned on the first side face WS1 side of the internal electrode layer 30 corresponds to the distance in the width direction W between the end E1L closest to the first side face WS1 and the end E1S closest to the second side face WS2 among the ends in the width direction W aligned on the first side face WS1 side of the internal electrode layer 30. Also, the maximum distance L4 in the width direction W between the ends in the width direction W aligned on the second side face WS2 side of the internal electrode layer 30 corresponds to the distance in the width direction W between the end E2L closest to the second side face WS2 and the end E2S closest to the first side face WS1 among the ends in the width direction W aligned on the second side face WS2 side of the internal electrode layer 30.

[0052] In the multilayer ceramic capacitor 1 in which the ends of the internal electrode layers 30 in the width direction W are arranged in this manner, by mounting the multilayer ceramic capacitor 1 on the circuit board CB with the second side surface WS2 facing the circuit board CB, the part that forms the capacitance can be separated from the mounting surface, thereby suppressing the occurrence of "sound". This eliminates the need to provide spacers or dielectric ceramic layers that have conventionally been arranged to provide a space between the internal electrode layers 30 and the circuit board CB, and makes it possible to reduce the size of the multilayer ceramic capacitor 1 and increase its capacitance while suppressing the occurrence of "sound".

[0053] The end portions of the internal electrode layers 30 in the width direction W on the second side surface WS2 side can be disposed at any position in the stacking direction T, appropriately shifted in the width direction W. For example, if the end portions of the internal electrode layers 30 in the width direction W on the second side surface WS2 side are disposed at the center of the stacking direction T of the laminate 10, shifted toward the center of the width direction W, the area of ​​contact between adjacent dielectric layers 20 in the stacking direction T increases, thereby suppressing the occurrence of delamination, cracks, and the like at the center of the stacking direction T of the laminate 10. Furthermore, if the end portions of the internal electrode layers 30 in the width direction W on the second side surface WS2 side located above or below the center of the stacking direction T of the laminate 10 are disposed at the center of the width direction W, the intrusion of moisture from the outside can be suppressed, and the moisture resistance of the multilayer ceramic capacitor 1 can be improved.

[0054] 5, in the multilayer ceramic capacitor 1 of the present invention, a distance L5 between the first side surface WS1 and an end E1S closest to the second side surface WS2 among the ends in the width direction W on the first side surface WS1 side of the internal electrode layer 30 is smaller than a distance L6 between the second side surface WS2 and an end E2S closest to the first side surface WS1 among the ends in the width direction W on the second side surface WS2 side of the internal electrode layer 30. Also, a maximum distance L3 in the width direction W between the ends in the width direction W of the internal electrode layers 30 aligned on the first side surface WS1 side is smaller than a maximum distance L4 in the width direction W between the ends in the width direction W of the internal electrode layers 30 aligned on the second side surface WS2 side of the internal electrode layers 30.

[0055] In the multilayer ceramic capacitor 1 in which the ends of the internal electrode layers 30 in the width direction W are arranged in this manner, by mounting the multilayer ceramic capacitor 1 on the circuit board CB with the second side surface WS2 facing the circuit board CB, the part that forms the capacitance can be separated from the mounting surface, thereby suppressing the occurrence of "sound". Furthermore, there is no need to provide a spacer or a dielectric ceramic layer to provide a space between the internal electrode layers 30 and the circuit board CB as in the conventional case, and the multilayer ceramic capacitor 1 can be made smaller and have a higher capacitance while suppressing the occurrence of "sound".

[0056] The maximum distance L3 in the width direction W between the ends of the internal electrode layers 30 aligned on the first side surface WS1 side is preferably 10 μm or less. By arranging the ends of the internal electrode layers 30 on the first side surface WS1 side in the width direction W relatively evenly, the internal electrode layers 30 can be positioned closer to the first side surface WS1 side, and the ends of the internal electrode layers 30 aligned on the second side surface WS2 side can be positioned away from the mounting surface. This achieves the effect of suppressing acoustic noise without reducing the capacitance of the multilayer ceramic capacitor 1.

[0057] The arrangement of the ends of the internal electrode layers 30 in the width direction W and the distance relationship can be observed or measured, for example, by the following method.

[0058] First, the multilayer ceramic capacitor 1 is polished in the length direction L to expose WT cross sections that are 1 / 3 and 1 / 2 of the dimension in the length direction L of the multilayer ceramic capacitor 1. Then, for the obtained cross sections, the regions between the ends in the width direction W of the first internal electrode layer 31 and the second internal electrode layer 32 and the side surfaces of the laminate 10 are observed or measured using a VHX5000 manufactured by Keyence Corporation at a magnification that allows observation of the outermost internal electrode layers in the lamination direction T and also allows observation of the ends in the width direction of each layer.

[0059] Si is precipitated at the end portions in the width direction W aligned on the first side face WS1 side of the internal electrode layer 30, and Si is precipitated at a second side gap portion WG2 between the second side face WS2 and the end portion E2L that is closest to the second side face WS2 among the end portions in the width direction aligned on the second side face WS2 side of the internal electrode layer 30. Si may also be precipitated at the end portions in the width direction aligned on the second side face WS2 side of the internal electrode layer 30.

[0060] The presence of Si segregation at the end portions in the width direction W of the internal electrode layers 30 improves the flexural strength of the multilayer ceramic capacitor 1. The amount of Si segregation in the width direction W on the second side surface WS2 side of the internal electrode layers 30 may be smaller than that on the end portions in the width direction W on the first side surface WS1 side.

[0061] (Manufacturing Method) Next, an example of a manufacturing method for the above-mentioned multilayer ceramic capacitor 1 will be described. First, a dielectric sheet for the dielectric layers 20 and a conductive paste for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. Known materials can be used as the binder and the solvent.

[0062] Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0063] Next, a predetermined number of dielectric sheets for the second outer layer portion 102, on which no internal electrode pattern is printed, are stacked. On top of these, dielectric sheets for the inner layer portion 100, on which internal electrode patterns are printed, are stacked in sequence. On top of these, a predetermined number of dielectric sheets for the first outer layer portion 101, on which no internal electrode pattern is printed, are stacked. In this way, a laminated sheet is produced.

[0064] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block, which is then cut to a predetermined size to cut out the laminated chip 10T.

[0065] As shown in Figure 6, the laminate chip 10T is formed by alternately stacking multiple material sheets on the surface of the laminate ceramic green sheet 120, which becomes the dielectric layer 20, with a conductive pattern 131 that becomes the first internal electrode layer 31 printed on it and a conductive pattern 132 that becomes the second internal electrode layer 32 printed on it, and then cutting and cutting out the material sheets along the stacking direction T to form an approximately rectangular parallelepiped shape as shown in the figure.

[0066] Of the pair of end faces 10Ta of the laminated chip 10T, a conductive pattern 131 is exposed on one end face, and a conductive pattern 132 is exposed on the other end face.

[0067] On the first side surface 10Tb1 of the laminate chip 10T, all ends in the width direction W of the laminated conductive patterns 131 and 132 are aligned along the lamination direction T on the cut-out exposed first side surface 10Tb1. This allows the ends in the width direction W of the multiple internal electrode layers 30 on the first side surface WS1 side of the multilayer ceramic capacitor 1 to be aligned within a range of 10 μm in the width direction W. On the other hand, on the second side surface 10Tb2 of the laminate chip 10T, the ends in the width direction W of the laminated conductive patterns 131 and 132 are not cut and are not exposed on the second side surface 10Tb2, so the ends in the width direction W of the conductive patterns 131 and 132 are not aligned as compared to the first side surface 10Tb1 side. Therefore, as shown in Figure 5, the maximum distance L3 in the width direction W between the ends in the width direction W that are aligned on the first side surface WS1 side of the internal electrode layer 30 is smaller than the maximum distance L4 in the width direction W between the ends in the width direction W that are aligned on the second side surface WS2 side.

[0068] Ceramic green sheets for covering the first side surface 10Tb1 and the second side surface 10Tb2 of the laminate chip 10T are attached to form the first side gap WG1 and the second side gap WG2, respectively, to cover the first side surface 10Tb1 and the second side surface 10Tb2 of the laminate chip 10T, thereby forming the side surface covering portion SC. As a result, the ends of the conductive patterns 131 and 132 exposed on the first side surface 10Tb1 of the laminate chip 10T in the width direction W are covered by the side surface covering portion SC.

[0069] By making the thickness of the covering ceramic green sheet attached to the first side surface 10Tb1 and the second side surface 10Tb2 of the laminate chip 10T sufficiently thin, the thickness of the first side gap portion WG1 and the second side gap portion WG2 can be narrowed.

[0070] The distance L1 between the first side surface WS1 and an end E1L of the internal electrode layer 30 in the width direction W that is closest to the first side surface WS1 is preferably 5 μm or more and 40 μm or less, and particularly preferably 5 μm or more and 15 μm or less. This makes it possible to increase the distance between the electrode opposing portion W30 and the mounting surface, thereby suppressing the occurrence of "noise" without reducing capacitance.

[0071] Furthermore, on the second side 10Tb2 of the laminated chip 10T, the ends of the conductive patterns 131 and 132 in the width direction W are not exposed, so there is no need to protect the ends, and it is not necessarily necessary to attach a covering ceramic green sheet.

[0072] The coating ceramic green sheets have a different composition from the lamination ceramic green sheets 120 that will become the dielectric layers 20, and differences in the concentrations of specific elements can be provided, or multiple regions with different concentrations of specific elements can be provided in the coating ceramic green sheets. For example, if the concentration of Ba contained in the lamination ceramic green sheets 120 is made higher than the concentration of Ba in the coating ceramic green sheets, it is possible to suppress moisture penetration into the inner layer portion 100 of the multilayer ceramic capacitor 1. In particular, in the embodiment of the present invention, since the thickness of the first side gap portion WG1 in the width direction W is thin, this is an effective means for suppressing moisture penetration and improving reliability.

[0073] As a result of the above, an unsintered laminate chip 10S with side covering portion SC is formed, as shown in Fig. 7. Next, the unsintered laminate chip 10S with side covering portion SC is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric and internal electrodes, but is preferably 900°C or higher and 1400°C or lower.

[0074] Next, the first end surface LS1 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply a conductive paste for the first base electrode layer 415 to the first end surface LS1. Similarly, the second end surface LS2 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply a conductive paste for the second base electrode layer 425 to the second end surface LS2. These conductive pastes are then fired to form the first base electrode layer 415 and the second base electrode layer 425, which are fired layers. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0075] As described above, the first base electrode layer 415 and the second base electrode layer 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and then firing it, or the first base electrode layer 415 and the second base electrode layer 425, which are thin films, may be formed by a thin film formation method such as a sputtering method or a vapor deposition method.

[0076] Thereafter, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form the second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 described above is obtained.

[0077] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 First opposing electrode portion 312 First lead electrode portion 32 Second internal electrode layer 321 Second opposing electrode portion 322 Second lead electrode portion 40 External electrode 41 First external electrode 415 First base electrode layer 416 First plating layer 42 Second external electrode 425 Second base electrode layer 426 Second plating layer 100 Internal layer portion 101 First external layer portion 102 Second external layer portion L30 Electrode opposing portion LG1 First end gap portion LG2 Second end gap portion W30 Electrode opposing portion WG1 First side gap portion WG2 Second side gap portion L Length direction T Stacking direction W Width direction LS1 First end surface LS2 Second end surface TS1 First main surface TS2 Second main surface WS1 First side surface WS2 Second side surface

Claims

1. A laminate having a substantially rectangular parallelepiped shape including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and having first and second main faces opposing each other in the stacking direction, a first side face and a second side face opposing each other in a width direction perpendicular to the stacking direction, and a first end face and a second end face opposing each other in a length direction perpendicular to the stacking direction and the width direction; and a pair of external electrodes connected to the internal electrode layers and arranged at both ends in the length direction of the laminate so as to cover at least the first end face and the second end face, respectively; wherein the distance between an end closest to the first side face among the ends in the width direction on the first side face side of the plurality of internal electrode layers and the first side face is smaller than the distance between an end closest to the second side face among the ends in the width direction on the second side face side of the plurality of internal electrode layers and the second side face, a maximum distance in the width direction between ends of the plurality of internal electrode layers aligned on the first side surface side of the plurality of internal electrode layers is smaller than a maximum distance in the width direction between ends of the plurality of internal electrode layers aligned on the second side surface side of the plurality of internal electrode layers.

2. A laminate having a substantially rectangular parallelepiped shape, including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and having first and second main faces opposing each other in the stacking direction, a first side face and a second side face opposing each other in a width direction perpendicular to the stacking direction, and a first end face and a second end face opposing each other in a length direction perpendicular to the stacking direction and the width direction; and a pair of external electrodes connected to the internal electrode layers, arranged at both ends in the length direction of the laminate so as to cover at least the first end face and the second end face, respectively; wherein the distance between an end closest to the second side face among the ends in the width direction on the first side face side of the plurality of internal electrode layers and the first side face is smaller than the distance between an end closest to the first side face among the ends in the width direction on the second side face side of the plurality of internal electrode layers and the second side face, a maximum distance in the width direction between ends of the plurality of internal electrode layers aligned on the first side surface side of the plurality of internal electrode layers is smaller than a maximum distance in the width direction between ends of the plurality of internal electrode layers aligned on the second side surface side of the plurality of internal electrode layers.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the maximum distance in the width direction between ends of the plurality of internal electrode layers aligned on the first side surface side in the width direction is within 10 μm.

4. A multilayer ceramic capacitor as described in claim 1 or 2, wherein Si is precipitated at ends in the width direction aligned on the first side surface side of the plurality of internal electrode layers, and Si is precipitated between an end closest to the second side surface among the ends in the width direction aligned on the second side surface side of the plurality of internal electrode layers and the second side surface.

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