Processor and computer system for alignment process

Abstract

A processor (core A3) according to the present invention comprises a first source operand, a second source operand, a third source operand, a fourth source operand, a fifth source operand, and a sixth source operand. The processor (core A3) also comprises: a first adder / subtractor for calculating the first intermediate sum of an element of the first source operand and an element of the second source operand; a second adder / subtractor for calculating the second intermediate sum of an element of the third source operand and an element of the fourth source operand element; and a third adder / subtractor for calculating the third intermediate sum of sixth resultant data obtained on the basis of an element of the fifth source operand and an element of the sixth source operand. The processor (core A3) further comprises a selector for selecting the maximum value and / or the minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum. Thereby, a processor suitable for an alignment process can be provided.

Description

Processor, alignment processing computer system

[0001] The present invention relates to a processor that is applied to a computer system for alignment processing, etc.

[0002] The human genome is a set of genetic information that a person possesses, and the material that carries this information is DNA (deoxyribonucleic acid), which is a string of approximately 3 billion pairs of bases. The bases are adenine (A), guanine (G), cytosine (C), and thymine (T). In other words, a person's genetic information is determined by the arrangement (sequence) of these bases.

[0003] A device called a sequencer is used to read the human genome. The sequencer reads the sample human genome, cuts it into a predetermined upper limit (about a few hundred base pairs), amplifies it, and outputs a huge data sequence consisting of hundreds of millions of pieces of genetic information. Current sequencers can read one human genome in about an hour.

[0004] The individual data fragments read by the sequencer are compared with the human genome reference sequence, which is defined as the standard genome sequence for humans, and then reconstructed into the original length of the human genome sequence and analyzed. For example, the position of each data fragment relative to the human genome reference sequence is examined (mapped). After mapping is complete, analysis is performed to determine what mutations are present.

[0005] For mapping data fragments, a programming tool such as BWA (Burrow-Wheeler Aligner) is used. BWA consists of three algorithms: BWA-backtrack, BWA-SW, and BWA-MEM. Of these, BWA-MEM is widely used as a high-speed algorithm that supports indels (insertion deletions). BWA-MEM is an algorithm that creates an index using a suffix sequence for the portion of a query string based on the read data fragment that repeatedly appears in the human genome reference sequence, and performs mapping.

[0006] The mapped data fragment (matching string) is matched with a partial sequence (matched string) at the same position in the human genome reference sequence, and the presence of any mutations is analyzed. For example, an alignment algorithm is used to match the partial sequence of the human genome reference sequence with the data fragment. In an alignment algorithm, a similar string is identified while calculating the degree of mutation (similarity) for each element of a sequence called an alignment table according to dynamic programming. Examples of alignment algorithms include the Smith-Waterman algorithm, the Smith-Waterman-Gotoh algorithm, and the Needleman-Wunsch algorithm (see, for example, U.S. Pat. No. 1,550,584).

[0007] In a computer processor that runs the above-mentioned alignment algorithm, multiple instructions are executed when calculating the degree of variation (similarity) of each element (cell) of the alignment table (alignment array), which results in a corresponding decrease in processing speed. Furthermore, when multiple instructions are executed, access to an external memory is required, and the processing speed of the processor is limited by the time it takes to access the memory.

[0008] An object of the present invention is to provide a processor suitable for alignment processing. Another object of the present invention is to provide, for example, a technique for performing alignment processing at high speed and / or efficiently.

[0009] In relation to the above object, the present invention provides a processor comprising: a first source operand, a second source operand, a third source operand, a fourth source operand, a fifth source operand, a sixth source operand; a first adder / subtractor that calculates a first intermediate sum of elements of the first source operand and elements of the second source operand; a second adder / subtractor that calculates a second intermediate sum of elements of the third source operand and elements of the fourth source operand; a third adder / subtractor that calculates a third intermediate sum of sixth cause data obtained based on the elements of the fifth source operand and elements of the sixth source operand; and a selector that selects a maximum and / or minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0010] The processor may be characterized in that the first source operand, the third source operand, and the fifth source operand are stored in a general-purpose register file, and the second source operand, the fourth source operand, and the sixth source operand are stored in a dedicated register file.

[0011] The processor may further include a seventh source operand and a second selection unit, and the sixth cause data may be data selected by the second selector from at least elements of the sixth source operand and the seventh source operand.

[0012] The processor may further include an eighth source operand, and the selector may select a maximum value and / or a minimum value from among elements of at least the first intermediate sum, the second intermediate sum, the third intermediate sum, and the eighth source operand.

[0013] The processor may further include an instruction decoder that decodes instructions, and a single instruction decoded by the instruction decoder may cause the first adder-subtractor to calculate the first intermediate sum, the second adder-subtractor to calculate the second intermediate sum, the third adder-subtractor to calculate the third intermediate sum, and the selector to select the maximum value and / or the minimum value.

[0014] The present invention, which relates to the above object, provides a left-upward variance source operand, the element of which is a variance in the left-upward direction relative to the current position of an alignment matrix used in alignment processing between a first character string and a second character string; a true-left variance source operand, the element of which is a variance in the true-left direction relative to the current position of the alignment matrix; a penalty source operand, the element of which is a linear gap penalty value in the alignment processing; a true-upward variance source operand, the element of which is a variance relative to the current position of the alignment matrix; a first adder-subtractor that calculates a first intermediate sum of elements of the true-left variance source operand and elements of the penalty source operand; a second adder-subtractor that calculates a second intermediate sum of elements of the diagonal-up variance source operand and a score function value based on a match / mismatch between elements of the first string and elements of the second string corresponding to the current position; and a variance selector that selects a maximum and / or minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0015] The processor may include a match score source operand, a mismatch score source operand, a first string character source operand whose elements are characters in a first string corresponding to the current position, a second string character source operand whose elements are characters in a second string corresponding to the current position, and a score function selector that selects an element of the match score source operand when an element of the first string character source operand matches an element of the second string character source operand, and that selects an element of the mismatch score source operand and outputs the element as the score function value when an element of the first string character source operand does not match an element of the second string character source operand.

[0016] The processor may include a score function source operand, the score function value being stored in the score source operand.

[0017] In the above processor, the left diagonal-upward variance source operand, the directly-above variance source operand, and the directly-left variance source operand may be stored in a general-purpose register file, and the gap source operand may be stored in a dedicated register file.

[0018] The processor may further include a restricted constant source operand having a restricted constant as an element, and the variability selector may select a maximum value and / or a minimum value from at least the first intermediate sum, the second intermediate sum, the third intermediate sum, and elements of the restricted constant source operand.

[0019] The processor may further include an instruction decoder that decodes instructions, and a single variability calculation instruction from the instruction decoder may collectively execute the calculation of the first intermediate sum by the first adder-subtractor, the calculation of the second intermediate sum by the second adder-subtractor, the calculation of the third intermediate sum by the third adder-subtractor, and the selection of the maximum value and / or the minimum value by the variability selector.

[0020] The present invention, which relates to the above-mentioned object, is a computer device for alignment processing, which has a memory device in which a first character string and a second character string are stored, and a processor, and which performs alignment processing using alignment matrices of the first character string and the second character string, wherein the processor is one of those described above, and the processor calculates the degree of variation of the current position of the alignment matrix based on an alignment program stored in the memory device.

[0021] According to the present invention, the alignment process can be performed quickly and / or efficiently by a processor suitable for the alignment process.

[0022] 1 is a block diagram showing an example of a schematic configuration of a computer system according to an embodiment of the present invention. FIG. 2 is a flowchart illustrating an example of an outline of approximate string matching processing by the computer system. FIG. 3 is a flowchart illustrating an example of an alignment processing procedure by the computer system. FIG. 4 is a block diagram illustrating an example of functional blocks of an alignment processing computer system realized by the computer system. FIG. 5 is a diagram showing the data structure of an alignment matrix used in alignment processing by the computer system. FIG. 6 is a diagram showing partition division of the alignment matrix and the order of calculation of the variation of each partition. FIG. 7 is a diagram showing a modified example of partition division of the alignment matrix and the order of calculation of the variation of each partition. FIG. 8 is a diagram showing a modified example of partition division of the alignment matrix and the order of calculation of the variation of each partition. FIG. 9 is a diagram showing a concept of calculation of variation and return path flag in a data cell of the alignment matrix. FIG. 10 is a diagram showing backtrack data in the alignment matrix. FIG. 11 is a diagram showing a specific example of variation calculation using the alignment matrix. FIG. 12 is a diagram showing a specific example of variation calculation using the alignment matrix. FIG. 13 is a diagram showing a specific example of backtrack data using the alignment matrix. FIG. 14 is a diagram showing the data structure of a score matrix used in alignment processing by the computer system. FIG. 15 is a diagram showing an example of the hardware configuration of the computer system. FIG. 16 is a block diagram showing an example of a processor module in the hardware configuration of the computer system. FIG. 1 is a block diagram showing the internal configuration of a core of the processor module. FIG. 2 is a block diagram showing the internal configurations of a general-purpose register file, a dedicated register file, and a mutation-dedicated arithmetic logic unit of the core. FIG. 3 is a block diagram showing a modified internal configuration of the core. FIG. 4 is a block diagram showing a modified internal configuration of the core. FIG. 5 is a block diagram showing a modified internal configuration of the core. FIG. 6 is a block diagram showing a modified internal configuration of the core. FIG. 7 is a block diagram showing a modified internal configuration of the core.

[0023] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are merely examples, and are not intended to exclude various modifications or applications of techniques not explicitly described below. The present invention can be implemented in various modifications (e.g., by combining the various embodiments) without departing from the spirit of the present invention. Furthermore, in the following description of the drawings, identical or similar parts are denoted by identical or similar reference numerals. The drawings are schematic and do not necessarily correspond to actual dimensions, ratios, etc. Parts in the drawings may have different dimensional relationships or ratios.

[0024] FIG. 1 is a block diagram illustrating an example of a schematic configuration of a computer system according to an embodiment of the present invention. As shown in the figure, the computer system 1 includes, for example, a host computer 10, multiple subordinate computers 20(1) to 20(n), and a database 30. The host computer 10 and the subordinate computers 20(1) to 20(n) are communicatively connected via a predetermined interface. In this disclosure, the computer system 1 is configured as a centralized computer system in which the host computer 10 comprehensively controls the multiple subordinate computers 20(1) to 20(n). However, the present disclosure is not limited to this, and the computer system 1 may also be configured as, for example, a distributed computer system. In a distributed computer system, each computer can operate cooperatively through parallel distributed processing, but a specific process may be performed by only one representative computer.

[0025] The computing hardware common to the upper computer 10 and the lower computer 20 is a computing device 100, as exemplified in Fig. 15. The computing device 100 includes a memory module 102 serving as a main storage device such as a DRAM, a processor module 104 serving as a central computer, a chipset 106 serving as a bridge between the processor module 104 and external devices, an internal storage device 108 such as an HDD or SSD, an I / O controller 110, an output interface 112, an input / output interface 114, a communication interface 116, and an external storage device 118 such as an external HDD.

[0026] 16, the processor module 104 includes multiple cores A, B, C, and D that execute independent computational processes, first cache memories (L1 cache memories) L1a, L1b, L1c, and L1d and second cache memories (L2 cache memories) L2a, L2b, L2c, and L2d, which are internal storage functions provided for each core A, B, C, and D, and a third cache memory (L3 cache memory) L3n, which is internal storage function shared by all cores A, B, C, and D. The access latency of cores A, B, C, and D is shortest for the L1 cache memories L1a, L1b, L1c, and L1d, followed by the L2 cache memories L2a, L2b, L2c, and L2d, and longest for the L3 cache memory L3n. Meanwhile, the access latency of the L1, L2, and L3 cache memories is significantly shorter than that of the memory module (main memory) 102. These structures allow the multiple cores A, B, C, and D in the processor module 104 to process tasks in parallel. For example, each of the multiple cores A, B, C, and D can perform analysis processing by comparing a given query string with a reference string. While the cache memory is divided into three levels here, the present invention is not limited to this configuration and may be divided into one, two, or four or more levels. Hereinafter, the first cache memory (L1 cache memory) L1a, L1b, L1c, and L1d, the second cache memory (L2 cache memory) L2a, L2b, L2c, and L2d, and the third cache memory (L3 cache memory) L3n may be collectively referred to as "cache memory." In the present invention, the number of cores in the processor module 104 is not particularly limited. The number of cores can be selected from a few to tens of thousands.

[0027] 15 and 16 illustrate examples of general-purpose hardware structures, but the present invention is not limited to these. Furthermore, all or part of these hardware structures may employ individually customized (programmed) hardware using an FPGA or the like. Furthermore, hereinafter, the memory module 102, the internal storage device 108, the external storage device 118, the first cache memories (L1 cache memories) L1a, L1b, L1c, and L1d, the second cache memories (L2 cache memories) L2a, L2b, L2c, and L2d, and the third cache memory (L3 cache memory) L3n, which are hardware capable of storing data, may be collectively referred to as a "storage device."

[0028] 1 , in the present disclosure, the lower-level computers 20 process tasks in parallel under the control of the upper-level computer 10. For example, each of the multiple lower-level computers 20 performs analysis processing by comparing a given query string with a reference string. Hereinafter, the lower-level computers 20(1) to 20(n) may be simply referred to as "lower-level computers 20" unless there is a need to particularly distinguish between them.

[0029] The database 30 stores various data, such as reference strings, under the control of the host computer 10. As an example, the database 30 stores a human genome reference sequence. The human genome reference sequence is data indicating a base pair sequence defined as a standard human genome sequence. The database 30 also stores an index created based on the reference string. The index is a type of data array structure used to search for the reference string. Note that in the figure, the database 30 is configured to be connected so as to be accessible only to the host computer 10, but this is not limited thereto; the database 30 may also be connected so as to be accessible to the lower-level computer 20. The lower-level computer 20 may also have a similar database. Here, an example is shown in which a human genome reference sequence is used, but a metagenomic reference sequence that compiles multiple organisms (animals), plants, etc., may also be used.

[0030] 2 is a flowchart outlining an example of approximate string matching processing by a computer system 1 according to an embodiment of the present invention. This processing is realized, for example, by the host computer 10 and the multiple lower-level computers 20 executing an approximate string matching program in the processor module 104 in cooperation with other hardware components. As a result, the computer system 1, the host computer 10, or the multiple lower-level computers 20 function as the approximate string matching computer system 200 shown in FIG. 4. The approximate string matching program has multiple processing blocks (subroutines). As a result, the approximate string matching computer system 200, in more detail, includes an index creation computer system 201, a mapping computer system 202, a string pair creation computer system 203, and an alignment processing computer system 204.

[0031] As shown in FIG. 2 , first, the host computer 10 reads the reference string stored in the database 30 and creates an index based on the read reference string (index creation process: S201). Specifically, the host computer 10 creates an index having a predetermined data array structure by expanding and / or sorting substrings of the reference string according to predetermined conditions. The data array structure is a hierarchical tree structure. In this disclosure, such an index is referred to as a hierarchical index. The host computer 10 stores the created index based on the reference string in the database 30. Details of the process for creating a hierarchical index based on the reference string will be described later. Note that if a hierarchical index based on the reference string has already been created and stored in the database 30, the index creation process S201 can be omitted. This allows the computer system 1 to function as an index creation computer system 201.

[0032] Next, the host computer 10 receives a query string from an external device (not shown), references the hierarchical index based on the received query string, and performs a mapping process of the query string to the reference string (mapping process: S202). In one example, the external device is a sequencer that reads the human genome, and the query string is a data fragment of, for example, approximately 150 to 200 base pairs output from the sequencer. The query string may be temporarily stored in the database 30. The number of characters in the query string is preferably 50 or more, more preferably 100 or more. On the other hand, the number of characters in the query string is preferably 1,000 or less, desirably 300 or less, and more preferably 200 or less. In the present disclosure, the lower-level computer 20 also performs mapping by reference to the hierarchical index based on the assigned query string under the control of the higher-level computer 10. This allows the computer system 1 to function as a mapping computer system 202.

[0033] Mapping is a process for identifying substrings (matching strings) in the reference string that match at least a portion of the query string. That is, mapping identifies the starting position and length (number of characters) of substrings in the reference string that match at least a portion of the query string. In the mapping process according to the present disclosure, the starting position of the query string in the reference string is identified by searching or traversing a hierarchical index for the query string. To speed up processing, the created hierarchical index is preferably loaded into a high-speed memory such as a cache memory in memory module 102 or processor module 104.

[0034] In the above example, the upper computer 10 and the lower computer 20 each perform mapping according to the assigned query string, but this is not limited to this. For example, only the upper computer 10 may perform a search by referring to a hierarchical index based on the assigned query string.

[0035] Next, the host computer 10 and the lower computer 20 each create a string pair for approximate string matching (described later) (string pair creation process: S203). A string pair consists of a matched string in the reference string and a match string in the query string, including a matching string identified by mapping. This allows the computer system 1 to function as a string pair creation computer system 203.

[0036] Specifically, the host computer 10 and the lower computer 20 create a matched string by adding a corresponding character string of a predetermined length in the reference string to the beginning and end of the matching string identified by mapping. In other words, the matched string is a character string in the vicinity of the matching string identified in the reference string, including the matching string. For example, if the reference string is "CCGATCTGTATACCCTACGA" and the matching string is "TACC," the string to be matched is "TATACCCT," which is obtained by adding two characters to the beginning and two characters to the end. In the case of human genome analysis, the length of bases added to the beginning and end of the matching string for the reference string may be, for example, about 50 bases each.

[0037] Furthermore, the host computer 10 creates a matching string by adding a corresponding character string of a predetermined length in the query string to the end of the matching string. In the case of analyzing the human genome, the length of the character string added to the end of the matching string for the query string is, for example, about 50 bases.

[0038] In the present disclosure, for a reference string, a character string of a predetermined length is added to the beginning and end of the matching string, but this is not limited to this, and for example, a character string of a predetermined length may be added to only one of the beginning or end. Furthermore, for a query string, a character string of a predetermined length may be added to the beginning and end of the matching string, or the matching string itself may be treated as a matching string without adding any character string.

[0039] Next, the host computer 10 and the lower computer 20 derive at least one approximate string based on a string pair consisting of a matched string based on the reference string and a match string based on the query string (alignment process: S204). A predetermined alignment using dynamic programming is applied to derive the approximate string. Alignment is a method of comparing two sequences (strings) while allowing substitution, insertion, and deletion between their elements, and calculating the degree of variation (similarity) according to a defined score / penalty. Known algorithms for achieving alignment include the Smith-Waterman algorithm and the Needleman-Wunsch algorithm. Dynamic programming is a method of calculating the optimal solution for the next stage based on the optimal solution obtained at a given stage. In other words, in calculating the degree of variation, a score is calculated for each element in an array-like alignment table according to dynamic programming, and the element with the highest score is determined, thereby deriving at least one approximate string. This allows the computer system 1 to function as an alignment processing computer system 204.

[0040] As described above, in the approximate string matching process of this embodiment, a hierarchical index based on a reference string is created, and then a matching string (and its length) is identified by searching the hierarchical index according to a given query string. An approximate string is derived by performing approximate string matching on a string pair consisting of a matched string and a match string based on the identified matching string. In other words, the approximate string matching program of this embodiment includes an index creation program based on the reference string, a mapping program that searches the hierarchical index according to the query string, a program that creates string pairs consisting of a matched string and a match string, and an alignment program that performs approximate string matching using the string pairs to derive an approximate string. The index creation program, mapping program, and string pair creation program can be publicly known programs, so detailed description thereof will be omitted.

[0041] <Alignment Processing> First, the alignment processing will be described. In this embodiment, the alignment processing is performed using dynamic programming. The alignment processing is a technique for comparing two sequences (strings), namely, a string (matched string) near an identified appearance start position in a reference string and a query string (matching string), while allowing substitutions, insertions, and deletions between their elements, and calculating the degree of variation (similarity) according to a defined score / penalty. For example, in a comparison between a matched string X (i.e., a matched string based on a reference string) and a string Y (i.e., a matching string based on a query string), if some characters in the matching string Y are substituted, inserted, or deleted, the matching string Y is determined to not match the matched string X. In other words, the relationship between the characters at each position in the matched string X and the matching string Y can be said to be one of the following: a match (match), a mismatch (mismatch), or one of the characters is absent (gap). In this disclosure, the Needleman-Wunsch algorithm, an example of global alignment, will be described for calculating the degree of variation. For ease of understanding, the following example illustrates the case where alignment processing is performed between an extremely short eight-character string X to be matched and a matching string Y. However, it should be noted that the actual number of strings is approximately 150 to 200, or even more.

[0042] In the alignment process, a data group of a matrix (grid) alignment matrix V (alignment table) shown in Figure 5 is generated using the matched string X and the matching string Y. In the table, "φ" means a null character. Here, the matched string X is defined as X = x1x2...xi, the matching string Y is defined as Y = y1y2...yj, and a specific position (i, j) in the alignment matrix V is defined as data storage cell v(i, j).

[0043] 17, the internal configuration of each of the cores A, B, C, and D used in the alignment process in the host computer 10 and the lower computer 20 will be described. Note that since the internal configurations of the cores A, B, C, and D that are processed in parallel are the same, only core A will be described here, and descriptions of the other cores B, C, and D will be omitted.

[0044] Core A has a program counter 800, a decoder 804, a general-purpose register file 806, a dedicated register file 808, and an execution unit 830. The program counter 800 is a register that holds the address of the instruction currently being executed by Core A. Core A uses the value of this register to reference the memory device and obtain the instruction stored at the corresponding address. When execution of an instruction is completed, the address of the next instruction to be executed is set in the program counter depending on the execution result.

[0045] The decoder 804 examines the bit string of the instruction and analyzes the type of instruction and the operands required for the operation. Based on the analysis results, the decoder 804 reads the required operands from the general-purpose register file 806 and / or the dedicated register file 808. The decoder 804 also selects an appropriate arithmetic unit within the execution unit 830 and switches the data path so that signals read from the general-purpose register file 806 and / or the dedicated register file 808 are sent to the selected arithmetic unit. The general-purpose register file 806 and the dedicated register file 808 serve as areas for temporarily storing data required for the operation. The general-purpose register file 806 and the dedicated register file 808 are composed of multiple registers, and one piece of data is generally stored in one register. Note that the dedicated register file 808 in this embodiment differs from a register file for system control in that it is a file dedicated to storing only specific data among the data required for the operation. Data in the storage device is written to the general-purpose register file 806 and the dedicated register file 808 when a load instruction is executed. It is also written back to the main storage device when a store instruction is executed.

[0046] The execution unit 830 incorporates various arithmetic units, such as an adder / subtractor 832, a multiplier 834, and a floating-point arithmetic unit 836. In particular, the execution unit 830 of this embodiment includes a mutation-dedicated arithmetic logic unit 840 that is selected to calculate the mutation in the alignment process. The calculation results of the execution unit 830 are written to the designated general-purpose register file 806 and / or dedicated register file 808.

[0047] These cores A, B, C, and D are controlled by an alignment processing kernel, which is included as part of an alignment program described later.

[0048] <Register File> Figure 18 shows the detailed configuration of the general-purpose register file 806 and dedicated register file 808 of core A. The general-purpose register file 806 stores an upper array character source operand 806A, a left array character source operand 806B, a left-diagonal-upward variance source operand 806C, a directly-above variance source operand 806D, a directly-left variance source operand 806E, and an output destination operand 806F. The upper array character source operand 806A receives the matched character string xi corresponding to the data storage cell v(i,j). The left array character source operand 806B receives the matched character string yj corresponding to the data storage cell v(i,j). The left-diagonal-upward variance source operand 806C receives the variance (score) F(i-1,j-1) of the cell v(i-1,j-1) diagonally above and to the left of the data storage cell v(i,j). The directly above variation source operand 806D receives the variation (score) of the cell v(i,j-1) directly above the data storage cell v(i,j). The directly left variation source operand 806E receives the variation (score) of the cell v(i-1,j) directly to the left of the data storage cell v(i,j). The output data of the variation-dedicated arithmetic logic unit 840, which will be described later, is received as the output destination operand 806F.

[0049] The dedicated register file 808 stores a match score source operand 808A, a mismatch score source operand 808B, a gap score source operand 808C, and a penalty source operand 808D. The match score source operand 808A receives the match score (e.g., "+2") of a pair of character pairs (xj, yj) selected from a matched string X and a match string Y. The mismatch score source operand 808B receives the mismatch score (e.g., "-1") of a pair of character pairs (xj, yj). The gap score source operand 808C receives the gap score (e.g., "-2") of a pair of character pairs (xj, yj). The penalty source operand 808D receives the gap penalty value (e.g., "-2").

[0050] <Variation-dedicated arithmetic logic unit 840> The variation-dedicated arithmetic logic unit 840 includes a score function selector 841B, a first adder / subtractor 840A, a second adder / subtractor 840B, a third adder / subtractor 840C, and a variation selector 841A. The score function selector 841B is a multiplexer that references each element of the upper array character source operand 806A, the left array character source operand 806B, the match score source operand 808A, the mismatch score source operand 808B, and the gap score source operand 808C and outputs a score based on a score function s (described below). The third adder / subtractor 840C adds the element of the left-diagonally-above variation source operand 806C and the output element of the score function selector 841B. The first adder / subtractor 840A adds the element of the directly-above variation source operand 806D and the element of the penalty source operand 808D. The second adder-subtractor 840B adds the elements of the true-left variability source operand 806E and the elements of the penalty source operand 808D. The variability selector 841A is a multiplexer that selects the maximum or minimum value (here, the maximum value) of the output elements of the first adder-subtractor 840A, the output elements of the second adder-subtractor 840B, and the output elements of the third adder-subtractor 840C. In particular, the variability selector 841A can be configured to select the maximum and / or minimum values ​​of three or more elements by connecting individual selectors (multiplexers) in multiple stages, each selecting the larger and / or smaller value of a pair of elements.

[0051] <Alignment Program> Next, the alignment program will be described. The alignment program executes alignment processing using dynamic programming. Using the alignment program, the host computer 10 and the lower-level computer 20 estimate the degree of variation (variation degree) between a string pair consisting of a string (string to be matched) near the identified appearance start position in the reference string and a query string (string to be matched).

[0052] Fig. 3 is a flowchart illustrating an example of an alignment processing procedure performed by a computer system according to this embodiment. Specifically, Fig. 3 shows details of the alignment processing (S204) in the approximate string matching process shown in Fig. 2. Fig. 4 also shows a functional block configuration of the alignment processing computer system 204. The alignment processing computer system 204 includes an alignment matrix creation means 602, a constant setting means 604, a filling region selection means 606, a filling route setting means 608, a filling cell selection means 610, a variation / path calculation means 612, a backtrack processing means 620, and an approximate string derivation means 622.

[0053] (Alignment matrix creation means 602 / alignment matrix creation step S602) In alignment matrix creation step S602, the alignment matrix creation means 602 generates a data group of an (m+1) x (n+1) matrix-shaped alignment matrix V (alignment table) shown in FIG. 5 using the matched string X and the matching string Y. In the table, "φ" means a null character. Here, the matched string X is defined as X = x1x2...xi...xm, the matching string Y is defined as Y = y1y2...yj...n, and a specific position (i, j) in the alignment matrix V is defined as data storage cell v(i, j). Note that the alignment matrix creation means 602 is equivalent to the process of selecting a string pair of the matched string X and the matching string Y for which alignment processing is to be performed (storing them at a specified address in a storage device).

[0054] (Constant Setting Means 604 / Constant Setting Step S604) In the constant setting step S604, the constant setting means 604 sets constants required for the alignment process. Specifically, it sets scores for match, mismatch, and gap between a pair of characters (xj, yj) selected from the matched string X and the matched string Y, as well as gap penalties between the top and bottom and the left and right of the cells. In this embodiment, the score for a match between the character pairs is set to, for example, "+2," the score for a mismatch to, for example, "-1," the score for a gap to, for example, "-2," and the gap penalty to, for example, "-2." Based on this constant setting means 604, the alignment process kernel loads these values ​​into a match score source operand 808A, a mismatch score source operand 808B, a gap score source operand 808C, and a penalty source operand 808D of the dedicated register file 808.

[0055] (Filling Area Selecting Means 606 / Filling Area Selecting Step S606) In the filling area selecting step S606, the filling area selecting means 606 divides the alignment matrix V into a plurality of (p) sections, as shown in FIG. 6, to generate a plurality of array areas V1V2...Vk...Vp, and sequentially selects the array area Vk for calculation in accordance with the arrangement order. In FIG. 6, the alignment matrix V is divided vertically into a plurality of sections, thereby forming the array area Vk into a group of cells that are continuous in the left-right direction. There are various division methods other than that shown in FIG. 6. For example, in FIG. 7, the alignment matrix V is divided horizontally into a plurality of sections, thereby forming the array area Vk into a group of cells that are continuous in the up-down direction. For example, in FIG. 8, the alignment matrix V is divided into a plurality of sections in a lattice pattern, thereby forming the array area Vk into a group of cells that are continuous in the up-down and left-right directions. The order of the multiple array regions V1V2...Vk...Vp is set so that, for the data storage cell v(i,j) to be operated on, the calculations of the cell v(i-1,j-1) diagonally above to the left, the cell v(i,j-1) directly above, and the cell v(i-1,j) directly to the left are always executed first.

[0056] Specifically, to determine the array area Vk, a substring pair consisting of a substring {xs...xi...xe} of the target string X and a substring {ys...yi...ye} of the matching string Y is extracted from the string pair X-Y, which is the target string X and the matching string Y, and stored at a predetermined address in the storage device as the array area Vk. Note that (xs, ys) denotes the start character of the substring pair, and (xe, ye) denotes the end character of the substring pair. Selection of substrings in the target string X must be performed sequentially from left to right, while selection of substrings in the matching string Y must be performed sequentially from top to bottom. The size of the array area Vk is preferably a size that can fit into a cache memory. In this embodiment, a size that can fit into the L1 cache memory is preferred, a size that can fit into the L2 cache memory is more preferred, and a size that can fit into the L3 cache memory is even more preferred. Here, an example has been given in which the alignment matrix V is divided into multiple (p) sections, but the present invention is not limited to this. The filling area selection means 606 may extract one sequence area that will become part of the alignment matrix V (in other words, exclude excess sequences) and calculate the degree of variation only within that extracted range.

[0057] (Filling Route Setting Means 608 / Filling Route Setting Step S608) In filling route setting step S608, filling route setting means 608 defines a calculation order (calculation route) Rk for data storage cell v(i,j) in array area Vk. Setting of this calculation order Rk takes into account the selection order of array area Vk in filling area selection step S606. For example, as shown by the arrows in FIG. 6, for the data storage cell v(i,j) to be calculated, the calculations of the cell v(i-1,j-1) diagonally above to the left, the cell v(i,j-1) directly above, and the cell v(i-1,j) directly to the left are always performed first. Here, a calculation order moving from left to right is selected. However, a calculation order Rk moving from top to bottom, as shown in FIG. 7, may also be selected, or a calculation order Rk moving diagonally, as shown in FIG. 8, may also be selected.

[0058] 9, in the fill cell selection step S610, the fill cell selection means 610 selects the data storage cell v(i, j) to be operated on in the order set by the fill route setting means 608. Based on this fill cell selection means 610, the alignment processing kernel loads the character set (xi, yj) corresponding to the data storage cell v(i, j) into the upper array character source operand 806A and the left array character source operand 806B of the general-purpose register file 806. Furthermore, the alignment processing kernel takes into the left-upward variation source operand 806C the variation (score) F(i-1, j-1) that has been pre-calculated (pre-saved in a storage device) for the cell v(i-1, j-1) diagonally above, takes into the directly above variation source operand 806D the variation (score) F(i, j-1) that has been pre-calculated (pre-saved in a storage device) for the cell v(i, j-1) directly above, and takes into the directly left variation source operand 806E the variation (score) F(i-1, j) that has been pre-calculated (pre-saved in a storage device) for the cell v(i-1, j) to the directly left.

[0059] (Variation and path calculation means 612 / Variation and path calculation step S612) In variation and path calculation step S612, the variation and path calculation means 612 calculates the variation F(i, j) of the data storage cell v(i, j) that is the object of calculation. Specifically, for example, in a comparison between a character string X = x1x2...xi...ym and a character string Y = y1y2...yj...yn, the variation F(i, j) between character xi and character yj is defined as in the following equation 1: Here, max is a function that outputs the maximum value among the values ​​of the given expression (m1, m2, m3), s is a score function (match: s = 2, mismatch: s = -1, gap: s = -2), and d is the penalty due to the gap (d = 2).

[0060] Specifically, the calculation of Equation 1 is performed by an alignment processing kernel based on the variation / path calculation means 612. The alignment processing kernel causes the decoder 804 to retrieve a single dedicated instruction (variation calculation instruction) for calculating the variation F(i, j). As a result, the decoder 804 reads operands required for the variation calculation instruction from the general-purpose register file 806 and / or the dedicated register file 808. Furthermore, the decoder 804 switches the data path so that the elements of these operands are sent to the variation-dedicated arithmetic logic unit 840.

[0061] (Variation Calculation Instruction) In the variation-dedicated arithmetic and logic unit 840, if the element (character xi) of the top array character source operand 806A and the element (character yj) of the left array character source operand 806B match, the score function selector 841B outputs the value ("+2") of the match score source operand 808A. If the element (character xi) of the top array character source operand 806A and the element (character yj) of the left array character source operand 806B do not match, the score function selector 841B outputs the value ("-1") of the mismatch score source operand 808B. If at least one of the element (character xi) of the top array character source operand 806A and the element (character yj) of the left array character source operand 806B is missing, the score function selector 841B outputs the value ("-2") of the gap score source operand 808C. This output corresponds to the calculation of the score function s(i, j) described above.

[0062] Furthermore, in the variability-dedicated arithmetic and logic unit 840, the first adder / subtractor 840A adds the element (F(i,j-1)) of the directly above variability source operand 806D to the element ("-2") of the penalty source operand 808D, the second adder / subtractor 840B adds the element (F(i-1,j)) of the directly left variability source operand 806E to the element ("-2") of the penalty source operand 808D, and the third adder / subtractor 840C adds the element (F(i-1,j-1)) of the diagonally above-left variability source operand 806C to the output element of the score function selector 841B. These outputs correspond to the operations m1, m2, and m3 in Equation 1.

[0063] Furthermore, in the variation-dedicated arithmetic and logic unit 840, the variation selector 841A selects the maximum or minimum value (here, the maximum value) of the output elements of the first adder-subtractor 840A, the second adder-subtractor 840B, and the third adder-subtractor 840C. This output corresponds to the operation of the max function in Equation 1, i.e., the result data of the variation F(i,j). This output (variation F(i,j)) is recorded in the output destination operand 806F.

[0064] After the mutation calculation command is completed, the variation / path calculation means 612 calculates the return path flag B(i,j) of the data storage cell v(i,j) to be calculated. The return path flag B is path information that links the data storage cell v(i,j) to the upstream data storage cells corresponding to m1, m2, and m3 selected as the maximum values ​​in Equation 1. For example, if m1 is selected as the maximum value, the data storage cell v(i,j) is linked to the cell v(i,j-1) directly above. For example, if m2 is selected as the maximum value, the data storage cell v(i,j) is linked to the cell v(i-1,j) directly to the left. For example, if m3 is selected as the maximum value, the data storage cell v(i,j) is linked to the cell v(i-1,j-1) diagonally above and to the left. In other words, the return path flag B(i,j) is a combination of three types of information: a path going directly upward, a path going directly left, and a path going diagonally upward and to the left. For example, in this embodiment, the return path flag B(i, j) is defined as 1 when m1, m2, and m3 are selected as the maximum values ​​in that order, and as 0 when they are not selected. As a result, the return path flag B(i, j) becomes ([1 or 0], [1 or 0], [1 or 0]).

[0065] (Remaining Filling Cell Determination Step S614) Once the variation / path calculation step S612 is completed, the process proceeds to the filling cell determination step S614, where it is determined, according to the calculation order R, whether or not any uncalculated data storage cells v(i,j) remain. If any remain, the process returns to the filling cell selection step S610, where the filling cell selection means 610 selects the data storage cell v(i,j) to be the next calculation target. As a result, in the variation / path calculation step S612, the variation F(i,j) of the next data storage cell v(i,j) is output. On the other hand, if no uncalculated data storage cells v(i,j) remain in the filling cell determination step S614, the process proceeds to the unprocessed filling area determination step S616.

[0066] (Unprocessed Filling Area Determination Step S616) In the unprocessed filling area determination step S616, it is determined whether or not any unprocessed array areas Vn remain. If so, the process returns to the filling area selection step S606, where the filling area selection means 606 selects the array area Vn to be the next calculation target. Thereafter, the above-mentioned filling route setting step S608, filling cell selection step S610, variation / path calculation step S612, and remaining filling cell determination step S614 are repeated. On the other hand, if no unprocessed array areas Vn remain in the unprocessed filling area determination step S616, this means that filling of the alignment matrix V with the variation F has been completed, and the process proceeds to the backtracking process S620.

[0067] (Backtracking Process S620) In the backtracking process S620, the backtracking processing means 620 selects the data storage cell v with the highest mutation degree as the starting cell vs, as shown in FIG. 10, and then selects the data storage cell v(i,j) with the highest mutation degree F(i,j) from all data storage cells v(i,j) linked upstream by the return path flag B(i,j). This makes it possible to trace back to, for example, a data storage cell (end cell ve) where one of the element positions (i,j) is 0. Here, the information on the group of element positions (element position array) that forms the path from the element position (is,js) of the starting cell vs to the element position (ie,je) of the end cell ve is defined as backtracking data BT. Once the backtracking data BT is generated, the process proceeds to the approximate string derivation process S622.

[0068] (Approximate Character String Derivation Process S622) In the approximate character string derivation process S622, the approximate character string derivation means 622 derives an approximate character string by referencing the backtrack data BT from the end position (ie, je) toward the start position (is, js). In the reference path, a movement diagonally downward to the right means "the presence (match or replacement) of both the matched character xi and the collation character yi at the destination position," a movement directly to the right means "the loss of the collation character yi for the matched character xi at the destination position," and a movement directly downward means "the insertion of the collation character yi for the matched character xi at the destination position." Note that in a path meaning "the presence (match or replacement) of both the matched character xi and the collation character yi at the destination position," the matched character xi and the collation character yi at the destination position may or may not match. A mismatch means that the matched character xi has been "replaced" by the collation character yi.

[0069] For example, in the case of the backtrack data BT of FIG. 10, the approximate character strings are as follows: X: (x1) (x2) (x3) - (x4) <x5> (y6) (y7) Y: (y1) (y2) (y3) <y4> (y5) - (y6) (y7) Note that the symbol "( )" indicates the presence of both, and if the matched character xi and the matching character yi are the same, it is a match, and if they are different, it is a substitution. Furthermore, the symbol "< >" indicates the insertion of a character. The symbol "-" indicates the loss of a character. In other words, the approximate character string is a data set that indicates the correlation of the matched character string Y with the matched character string X.

[0070] 10, the same applies when the backtrack data BT branches midway, generating multiple backtrack data BT2, or when there are multiple data storage cells v (starting cells vs) with the maximum degree of variation, generating other backtrack data BT3. In this case, there will be multiple approximate character strings corresponding to each backtrack data. After going through all of the above steps, the derivation of an approximate character string using the Needleman-Wunsch algorithm is completed.

[0071] <Specific Example of Alignment Processing> Next, as a specific example, a case where alignment processing is performed between a matched string X "GCCTCGCT" and a matched string Y "GCCATTGA" will be described. In the alignment matrix creation step S602, the alignment matrix V shown in FIG. 11 is generated. In the alignment matrix V, "φ" in the table is a null character, and F(0,0)=0 is defined. Also, in Equation 1, if at least one of the arguments (i,j) that determine the degree of variation F(i,j) is a negative value, it is outside the range of the calculation, so the calculation is omitted (output is Null). The alignment matrix V is expanded on a storage device as a kind of lattice-like data structure and is made available for use by the processor.

[0072] In the constant setting step S604, the score for a matched character pair is set to "+2", the score for a mismatch to "-1", and the score for a gap to "-2", and the gap penalty is set to "-2". In the filling region selection step S606, the sequence region V1 for which calculations are to be performed first is selected. In the filling route setting step S608, a route R1 is defined in the sequence region V1.

[0073] In the fill cell selection step S610, first, the data storage cell v(0,0) to be operated on is selected, but since its mutation rate F(0,0) is predefined as 0, subsequent operations are omitted, and v(1,0) is selected as the next data storage cell.

[0074] In the variation / path calculation step S61, m1, m2, and m3 in the max function of Equation 1 that calculates the variation F(1,0) are as follows: m1 = F(1,-1) - d = Null m2 = F(0,0) - d = 0 - 2 = -2 m3 = F(0,-1) + s(x1,y0) = Null As a result, the max function selects m2, and F(1,0) = -2. Then, the return path flag B(1,0) is as follows: B(1,0) = (0,1,0) (i.e., only "direct left")

[0075] When the variation / path calculation step S612 is completed, the process proceeds to the fill cell determination step S614, where it is determined according to the calculation order R1 whether or not any uncalculated data storage cells v(i,j) remain. Since there are, the process returns to the fill cell selection step S610, where the fill cell selection means 610 selects the data storage cell v(2,0) to be the next calculation target. Next, in the variation / path calculation step S612, F(2,0) and B(2,0) are calculated as follows: F(2,0) = F(1,0) - d = -4 B(2,0) = (0,1,0) (i.e., only "direct left")

[0076] After that, through the fill cell determination step S614 and fill cell selection step S610, the data storage cell v(3,0) to be the next calculation target is selected, and in the variation and path calculation step S612, F(3,0) and B(3,0) are calculated as follows: F(3,0) = F(2,0) - d = -4 B(3,0) = (0,1,0) (i.e., only "direct left")

[0077] By repeating these steps n times, F(n,0) and B(n,0) are calculated for the data storage cell v(n,0) as follows: F(n,0) = -nd B(n,0) = (0,1,0) (i.e., only the "true left")

[0078] As a result of the above, the mutation degree F and return path flag B of array area V1 are as shown in Figure 11. In fill cell determination step S614, it is determined that no uncalculated data storage cells v(i, j) remain in accordance with calculation order R1, so the process then proceeds to unprocessed fill area determination step S616, where it is determined whether or not an unprocessed array area Vk remains. Since an unprocessed array area Vk remains, the process returns to fill area selection step S606, where fill area selection means 606 selects array area V2 as the next calculation target.

[0079] The m1, m2, and m3 in the max function of formula 1 for the first data storage cell v(0,1) in array area V2 are as follows: m1 = F(0,0) - d = 0 - 2 = -2 m2 = F(-1,1) - d = Null m3 = F(-1,0) + s(x0,y1) = Null As a result, the max function selects m1, and the mutation degree F(0,1) = -2. The return path flag B(0,1) is then as follows: B(1,0) = (1,0,0) (i.e., only "directly above")

[0080] Next, m1, m2, and m3 in the max function of formula 1 in the next selected data storage cell v(1,1) are as follows: m1 = F(1,0) - d = -2 - 2 = -4 m2 = F(0,1) - d = -2 - 2 = -4 m3 = F(0,0) + s(x1,y1) = 0 + 2 = 2 As a result, the max function selects m3, and the mutation degree F(1,1) = 2. Then, the return path flag B(1,1) is as follows: B(1,1) = (0,0,1) (i.e., only "upper left")

[0081] Next, m1, m2, and m3 in the max function of formula 1 in the selected data storage cell v(2,1) are as follows: m1 = F(2,0) - d = -4 - 2 = -6 m2 = F(1,1) - d = 2 - 2 = 0 m3 = F(1,0) + s(x2,y1) = -2 - 1 = -3 As a result, the max function selects m2, and the mutation degree F(2,1) = 0. Then, the return path flag B(2,1) is as follows: B(2,1) = (0,1,0) (i.e., only "direct left")

[0082] Next, m1, m2, and m3 in the max function of formula 1 in the selected data storage cell v(3,1) are as follows: m1 = F(3,0) - d = -6 - 2 = -8 m2 = F(2,1) - d = 0 - 2 = -2 m3 = F(2,0) + s(x3,y1) = -4 - 1 = -5 As a result, the max function selects m2, and the mutation degree F(3,1) = -2. Then, the return path flag B(3,1) is as follows: B(3,1) = (0,1,0) (i.e., only "direct left")

[0083] : Without going into detail about some of the subsequent calculations, m1, m2, and m3 in the max function of formula 1 in data storage cell v(6,1) are as follows: m1 = F(6,0) - d = -12 - 2 = -14 m2 = F(5,1) - d = -6 - 2 = -8 m3 = F(5,0) + s(x6,y1) = -10 + 2 = -8 As a result, the max function selects m2 or m3, resulting in a mutation degree F(6,1) = -8. The return path flag B(6,1) is then as follows: B(6,1) = (0,1,1) (i.e., a combination of "direct left" and "diagonally up left") As with this return path flag B(6,1), the return path flag B may select multiple paths.

[0084] When the above repeated calculations are performed on array area V2, the result is as shown in Figure 12. Similarly, when the calculations are performed on all array areas V1 to V9 in order, the alignment matrix V shown in Figure 13 is completed. In step S616 for determining unprocessed filling areas, since no unprocessed array areas remain, the process proceeds to backtracking processing S620.

[0085] In the backtracking process S620, since the mutation degree F(6,7) of the data storage cell v(6,7) has the maximum value of "7," this is selected as the starting cell vs. Therefore, from among the routes linked by arrows indicating the return path flag B from the data storage cell v(6,7) to the data storage cell v(0,0), the route with the maximum mutation degree F is selected. By performing this backtracking, the backtrack data BT {(6,7) → (5,6) → (4,5) → (3,4) → (3,3) → (2,2) → (1,1) → (0,0)} colored in gray is selected. Once the acquisition of the backtrack data BT is complete, the process proceeds to the approximate string derivation process S622.

[0086] In the approximate character string derivation process S622, the backtrack data BT is referenced from the end position (0,0) toward the start position (6,7) to derive an approximate character string. Here, (0,0) → (1,1) = "G (match)", (1,1) → (2,2) = "C (match)", (2,2) → (3,3) = "C (match)", (3,3) → (3,4) = "A (insertion)", (3,4) → (4,5) = "T (match)", (4,5) → (5,6) = "T (replacement)", (5,6) → (6,7) = "T (match)".

[0087] This derives the following approximate strings: X: "GCC - T C G" Y: "GCCT[T]G" where the symbol "< >" indicates an insertion between characters, the symbol "-" indicates a deletion, and the symbol "[ ]" indicates a substitution. In other words, in this example, the referenced string X is "GCCTCG," and an "A" has been inserted between the "C" and "T" in the referenced string X, indicating a correlation in which the "C" in the referenced string "TCG" has been replaced with a "T."

[0088] As described above, by identifying the element position in the aligned sequence where the degree of variation is the maximum according to the Needleman-Wunsch algorithm, an approximate character string can be derived therefrom.

[0089] (Introduction of a First Variation) In the core A shown in FIG. 18 , the variability-dedicated arithmetic logic unit 840 includes a score function selector 841B, and the score function s is calculated simultaneously in a single variability calculation instruction. However, the present invention is not limited to this example. For example, as shown in FIG. 19 , the score function selector 841B can be placed in the score function-dedicated arithmetic logic unit 842, which is executed by an instruction independent of the variability-dedicated arithmetic logic unit 840, to execute the calculation of the score function s. In this case, by storing a score source operand 806S in the general-purpose register file 806, the output data of the score function-dedicated arithmetic logic unit 842 (score function selector 841B) can be incorporated into the score source operand 806S. The third adder / subtractor 840C of the variability-dedicated arithmetic logic unit 840 simply adds the elements of the score source operand 806S and the elements of the upper left variability source operand 806C.

[0090] Furthermore, while Figure 18 illustrates an example in which the score source operand 806S directly imports the output data of the score function-dedicated arithmetic and logic unit 842, the present invention is not limited to this. The alignment program may use the score function-dedicated arithmetic and logic unit 842 to generate a data group of an (m+1) x (n+1) matrix-shaped score matrix S (score table) using the matched string X and the matched string Y, as shown in Figure 14, and collectively calculate score values ​​and store them in a storage device. In this case, it is preferable that the score source operand 806S imports the desired score value s(i, j) from the score matrix S stored in the storage device.

[0091] 18 and 19 illustrate an example in which the mutation selector 841A of the mutation-dedicated arithmetic logic unit 840 selects the maximum or minimum value (here, the maximum value) of the output element of the first adder-subtractor 840A, the output element of the second adder-subtractor 840B, and the output element of the third adder-subtractor 840C. This is suitable for so-called global alignment processing such as the Needleman-Wunsch algorithm. However, the present invention is not limited to this and can also be applied to so-called local alignment processing. In this case, for example, as in core A2 of a second modified example in Figure 20, which is a further modification of the first modified example in Figure 19, the dedicated register file 808 may further store a limiting constant operand 808E, and the mutation selector 841A may select the maximum or minimum value (here, the maximum value) of the output elements of the first adder-subtractor 840A, the output elements of the second adder-subtractor 840B, the output elements of the third adder-subtractor 840C, and the element of the limiting constant operand 808E. The limiting constant operand 808E holds data (e.g., "0") for restricting the mutation F(i, j) value selected by the mutation selector 841A so that it does not become smaller than a predetermined value.

[0092] For example, in local alignment processing using the Smith-Waterman algorithm, when comparing a string X = x1x2...xi...ym with a string Y = y1y2...yj...yn, the degree of variation F(i, j) between character xi and character yj is defined as in the following equation 2: Here, max is a function that outputs the maximum value from the values ​​of the given formula (m1, m2, m3, z), s is a score function (match: s=2, mismatch: s=-1, gap: s=-2), d is the penalty for gaps (d=2), and z is a limiting constant (here, "0") that limits the degree of variation so that it does not become smaller than a predetermined value.

[0093] (Introduction of the third variant) In the cores A, A1, and A2 shown in Figures 18 to 20, an example is shown in which the dedicated register file 808 stores a match score source operand 808A, a mismatch score source operand 808B, and a gap score source operand 808C, and the values ​​of these elements are selectively output by the score function selector 841B, but the present invention is not limited to this.

[0094] 21, the match score, mismatch score, and gap score can be stored as arguments in the variability calculation instruction itself processed by the decoder 804. In this case, a general-purpose or dedicated comparator 807 compares in advance whether the element (character xi) of the upper array character source operand 806A matches or mismatches the element (character yj) of the left array character source operand 806B, and records the match / mismatch determination result in a flag register 809. The score function selector 841B references the determination result recorded in the flag register 809. If an element (character xi) of the upper array character source operand 806A matches an element (character yj) of the left array character source operand 806B, the score function selector 841B masks the variability calculation instruction using a mask register to extract and output the argument: match score ("+2"); if an element (character xi) of the upper array character source operand 806A does not match an element (character yj) of the left array character source operand 806B, the score function selector 841B masks the variability calculation instruction using a mask register to extract and output the argument: mismatch score ("-1"). This reduces the number of operands. In other words, by storing the arguments, instruction-dedicated registers such as the decoder 804 can also serve as the dedicated register file 808 (dedicated operands). In addition, regarding the defect determination as to whether or not at least one of the elements (character xi) of the upper array character source operand 806A and the elements (character yj) of the left array character source operand 806B is defective, the defect determination is performed by reloading the data into the comparator 807, and the defect determination result is recorded in the flag register 809. This allows the score function selector 841B to mask the variability calculation instruction with the mask register and extract and output the argument: gap score ("-2"). Of course, by providing two or more comparators 807 and flag registers 809, a configuration may be adopted in which match / mismatch determination and defect determination are performed simultaneously.

[0095] (Fourth Modification: Introduction of Generalized Examples)

[0096] 18 to 21 illustrate examples in which alignment processing is customized by providing a general-purpose register file 806 and a dedicated register file 808, but the present invention is not limited to this, and all operand groups may be stored in the general-purpose register file 806. A core A3 according to a third modified example in which the core A shown in FIG. 18 is generalized is shown in FIG.

[0097] Core A3 includes a general-purpose register file 806-H3, a dedicated register file 808-H3, and a general-purpose arithmetic and logic unit 840-H3. The general-purpose register file 806-H3 stores a ninth source operand 806A-H3, a tenth source operand 806B-H3, a fifth source operand 806C-H3, a first source operand 806D-H3, a third source operand 806E-H3, and an output destination operand 806F-H3.

[0098] The dedicated register file 808-H3 stores a sixth source operand 808A-H3, a seventh source operand 808B-H3, an eighth source operand 808C-H3, a second source operand 808D-H3a, and a fourth source operand 808D-H3b. Note that the second source operand 808D-H3a and the fourth source operand 808D-H3b are generalized versions of the penalty source operand 808D in FIG. 18, which are separated into two independent operands, allowing different elements to be added to the first adder-subtractor 840A-H3 and the second adder-subtractor 840B-H3.

[0099] The general-purpose arithmetic logic unit 840-H3 includes a second selector 841B-H3, a first adder-subtractor 840A-H3, a second adder-subtractor 840B-H3, a third adder-subtractor 840C-H3, and a first selector 841A-H3. The second selector 841B-H3 is a multiplexer that references each element of the ninth source operand 806A-H3, the tenth source operand 806B-H3, the sixth source operand 808A-H3, the seventh source operand 808B-H3, and the eighth source operand 808C-H3 and outputs a score based on a score function s. The third adder-subtractor 840C-H3 adds the element of the fifth source operand 806C-H3 to the output element of the second selector 841B-H3. The first adder-subtractors 840A-H3 add the elements of the first source operands 806D-H3 and the elements of the second source operands 808D-H3a. The second adder-subtractors 840B-H3 add the elements of the third source operands 806E-H3 and the elements of the fourth source operands 808D-H3b. The first selectors 841A-H3 are multiplexers that select the maximum or minimum value (here, the maximum value) of the output elements of the first adder-subtractors 840A-H3, the output elements of the second adder-subtractors 840B-H3, and the output elements of the third adder-subtractors 840C-H3. It goes without saying that the first selector 841A-H3 can be realized in a general-purpose manner, for example, by combining a first comparator that compares two of these three elements (for example, the output element of the first adder-subtractor 840A-H3 and the output element of the second adder-subtractor 840B-H3) and a second comparator that compares the output of the first comparator with the remaining one (for example, the output element of the third adder-subtractor 840C-H3).

[0100] The reference numerals given to the generalized parts and members in the core A3 in Fig. 22 are the same as the reference numerals given to the dedicated parts and members of the core A shown in Fig. 18 with "-H3" added. Due to this reference numeral correspondence, a detailed description of the functions of the core A3 in Fig. 22 will be omitted.

[0101] As described above, the core A3 in FIG. 21 includes a first source operand 806D-H3, a second source operand 808D-H3a, a third source operand 806E-H3, a fourth source operand 808D-H3b, a fifth source operand 806C-H3, a sixth source operand 808A-H3, a first adder / subtractor 840A-H3 that calculates a first intermediate sum of the elements of the first source operand 806D-H3 and the elements of the second source operand 808D-H3a, and a second adder / subtractor 840B-H3 that calculates a first intermediate sum of the elements of the third source operand 806E-H3. and the elements of the fourth source operand 808D-H3b; a third adder-subtractor 840C-H3 for calculating a third intermediate sum of sixth causing data (here, the output elements of the second selector 841B-H3) obtained based on the elements of the fifth source operand 806C-H3 and the elements of the sixth source operand 808A-H3; and a first selector 841A-H3 for selecting the maximum and / or minimum values ​​from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0102] The function executed by a single instruction in this core A3 can be generalized as in the following equation 3. Here, L is the output element of the first selector 841A-H3, a is the element of the first source operand 806D-H3, b is the element of the second source operand 808D-H3a, c is the element of the third source operand 806E-H3, d is the element of the fourth source operand 808D-H3b, e is the element of the fifth source operand 806C-H3, and f is the sixth cause data obtained based on the element of the sixth source operand 808A-H3.

[0103] The core A3 in Fig. 22 can be suitably used for alignment processing similar to that of the core A in Fig. 18, but can also be used for other general-purpose applications. Note that, although an example is shown here in which the registers are divided into a general-purpose register file 806-H3 and a dedicated register file 808-H3, versatility may be further enhanced by storing all operands in the general-purpose register file 806-H3.

[0104] (Fifth Modification: Introduction of a Generalized Example) Figure 23 shows a core A4 according to a fifth modification, which is a generalized version of the core A1 according to the first modification shown in Figure 19. The core A4 includes a general-purpose register file 806-H4, a dedicated register file 808-H4, a first general-purpose arithmetic and logic unit 840-H4, and a second general-purpose arithmetic and logic unit 842-H4. The general-purpose register file 806-H4 stores a tenth source operand 806A-H4, an eleventh source operand 806B-H4, a sixth source operand 806S-H4, a fifth source operand 806C-H4, a first source operand 806D-H4, a third source operand 806E-H4, and an output destination operand 806F-H4.

[0105] The dedicated register file 808-H4 stores a seventh source operand 808A-H4, an eighth source operand 808B-H4, a ninth source operand 808C-H4, a second source operand 808D-H4a, and a fourth source operand 808D-H4b. Note that the second source operand 808D-H4a and the fourth source operand 808D-H4b are generalized versions of the penalty source operand 808D in FIG. 19 that are separated into two independent operands, allowing different elements to be added to the first adder-subtractor 840A-H4 and the second adder-subtractor 840B-H4.

[0106] The second general-purpose arithmetic logic unit 842-H4 includes a second selector 841B-H4. The second selector 841B-H4 is a multiplexer that references each element of the tenth source operand 806A-H4, the eleventh source operand 806B-H4, the seventh source operand 808A-H4, the eighth source operand 808B-H4, and the ninth source operand 808C-H4 and outputs a score based on the score function s. The output data of the second selector 841B-H4 can be taken into the sixth source operand 806S-H4.

[0107] The first general-purpose arithmetic logic unit 840-H4 includes a first adder-subtractor 840A-H4, a second adder-subtractor 840B-H4, a third adder-subtractor 840C-H4, and a first selector 841A-H4. The third adder-subtractor 840C-H4 adds elements of a fifth source operand 806C-H4 and elements of a sixth source operand 806S-H4. The first adder-subtractor 840A-H4 adds elements of a first source operand 806D-H4 and elements of a second source operand 808D-H4a. The second adder-subtractor 840B-H4 adds elements of a third source operand 806E-H4 and elements of a fourth source operand 808D-H4b. The first selector 841A-H4 is a multiplexer that selects the maximum or minimum value (here, the maximum value) of the output elements of the first adder-subtractor 840A-H4, the output elements of the second adder-subtractor 840B-H4, and the output elements of the third adder-subtractor 840C-H4.

[0108] The reference numerals given to the generalized parts and members in the core A4 in Fig. 23 are the same as the reference numerals given to the dedicated parts and members of the core A1 in Fig. 19 with "-H4" added. Due to this correspondence between the reference numerals, a detailed description of the functions of the core A4 in Fig. 23 will be omitted.

[0109] As described above, the core A4 in FIG. 23 includes a first source operand 806D-H4, a second source operand 808D-H4a, a third source operand 806E-H4, a fourth source operand 808D-H4b, a fifth source operand 806C-H4, a sixth source operand 806S-H4, a first adder-subtractor 840A-H4 that calculates a first intermediate sum of the elements of the first source operand 806D-H4 and the elements of the second source operand 808D-H4a, and a second adder-subtractor 840B-H4 that calculates a first intermediate sum of the elements of the third source operand 806E-H4 and the fourth source operand 808D-H4b. The multiplication unit 806 includes a second adder / subtractor 840B-H4 that calculates a second intermediate sum of the elements of the source operand 808D-H4b, a third adder / subtractor 840C-H4 that calculates a third intermediate sum of sixth cause data (here, the elements of the sixth source operand 806S-H4 themselves) obtained based on the elements of the fifth source operand 806C-H4 and the elements of the sixth source operand 806S-H4, and a first selector 841A-H4 that selects the maximum and / or minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0110] The function executed by a single instruction in this core A4 can be generalized to the following equation 4. Here, L is the output element of the first selector 841A-H4, a is the element of the first source operand 806D-H4, b is the element of the second source operand 808D-H4a, c is the element of the third source operand 806E-H4, d is the element of the fourth source operand 808D-H4b, e is the element of the fifth source operand 806C-H4, and f' is the element of the sixth source operand 806S-H4.

[0111] The core A4 in Fig. 23 can be suitably used for alignment processing similar to that of the core A1 in Fig. 19, but can also be used for other general-purpose applications. Note that, although an example is shown here in which the registers are divided into a general-purpose register file 806-H4 and a dedicated register file 808-H4, versatility may be further enhanced by storing all operands in the general-purpose register file 806-H4.

[0112] (Sixth Modification: Introduction of Generalized Example) FIG. 24 shows a core A5 according to a sixth modification, which is a generalized version of the core A2 of the second modification shown in FIG.

[0113] Core A5 includes a general-purpose register file 806-H5, a dedicated register file 808-H5, a first general-purpose arithmetic logic unit 840-H5, and a second general-purpose arithmetic logic unit 842-H5. The general-purpose register file 806-H5 stores a twelfth source operand 806A-H5, a thirteenth source operand 806B-H5, a sixth source operand 806S-H5, a fifth source operand 806C-H5, a first source operand 806D-H5, a third source operand 806E-H5, and an output destination operand 806F-H5.

[0114] The dedicated register file 808-H5 stores a ninth source operand 808A-H5, a tenth source operand 808B-H5, an eleventh source operand 808C-H5, a second source operand 808D-H5a, a fourth source operand 808D-H5b, and an eighth source operand 808E-H5. Note that the second source operand 808D-H5a and the fourth source operand 808D-H5b are generalized versions of the penalty source operand 808D in FIG. 20 that are separated into two independent operands, allowing different elements to be added to the first adder-subtractor 840A-H5 and the second adder-subtractor 840B-H5.

[0115] The second general-purpose arithmetic logic unit 842-H5 includes a second selector 841B-H5. The second selector 841B-H5 is a multiplexer that references each element of the twelfth source operand 806A-H5, the thirteenth source operand 806B-H5, the ninth source operand 808A-H5, the tenth source operand 808B-H5, and the eleventh source operand 808C-H5 and outputs a score based on the score function s. The output data of the second selector 841B-H5 can be taken into the sixth source operand 806S-H5.

[0116] The first general-purpose arithmetic logic unit 840-H5 includes first adder-subtractors 840A-H5, second adder-subtractors 840B-H5, third adder-subtractors 840C-H5, and first selectors 841A-H5. The third adder-subtractor 840C-H5 adds elements of the fifth source operand 806C-H5 and elements of the sixth source operand 806S-H5. The first adder-subtractor 840A-H5 adds elements of the first source operand 806D-H5 and elements of the second source operand 808D-H5a. The second adder-subtractor 840B-H5 adds elements of the third source operand 806E-H5 and elements of the fourth source operand 808D-H5b. The first selector 841A-H5 is a multiplexer that selects the maximum or minimum value (here, the maximum value) of the output elements of the first adder-subtractor 840A-H5, the output elements of the second adder-subtractor 840B-H5, the output elements of the third adder-subtractor 840C-H5, and the elements of the eighth source operand 808E-H5.

[0117] The reference numerals given to the generalized parts and members in the core A5 in Fig. 24 are the same as the reference numerals given to the dedicated parts and members of the core A2 in Fig. 20 with "-H5" added. Due to this reference numeral correspondence, a detailed description of the functions of the core A5 in Fig. 24 will be omitted.

[0118] As described above, the core A5 in FIG. 24 includes a first source operand 806D-H5, a second source operand 808D-H5a, a third source operand 806E-H5, a fourth source operand 808D-H5b, a fifth source operand 806C-H5, a sixth source operand 806S-H5, an eighth source operand 808E-H5, a first adder / subtractor 840A-H5 that calculates a first intermediate sum of the elements of the first source operand 806D-H5 and the elements of the second source operand 808D-H5a, and a fourth adder / subtractor 840B-H5 that calculates a second intermediate sum of the elements of the third source operand 806E-H5 and the elements of the fourth source operand 808D-H5b. a second adder-subtractor 840B-H5 that calculates a second intermediate sum of the elements of the fifth source operand 806C-H5 and the sixth source operand 806S-H5; a third adder-subtractor 840C-H5 that calculates a third intermediate sum of sixth causing data (here, the elements of the sixth source operand 806S-H5 themselves) obtained based on the elements of the fifth source operand 806C-H5 and the elements of the sixth source operand 806S-H5; and a first selector 841A-H5 that selects the maximum and / or minimum values ​​from among the elements of the eighth source operand 808E-H5 of at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

[0119] The function executed by a single instruction in this core A5 can be generalized to the following equation 5. Here, L is the output element of the first selector 841A-H5, a is the element of the first source operand 806D-H5, b is the element of the second source operand 808D-H5a, c is the element of the third source operand 806E-H5, d is the element of the fourth source operand 808D-H5b, e is the element of the fifth source operand 806C-H5, f' is the element of the sixth source operand 806S-H5, and g is the element of the eighth source operand 808E-H5.

[0120] The core A5 in Fig. 24 can be suitably used for alignment processing similar to the core A2 in Fig. 20, but can also be used for other general-purpose applications. Note that, although an example is shown here in which the registers are divided into a general-purpose register file 806-H5 and a dedicated register file 808-H5, versatility may be further enhanced by storing all operands in the general-purpose register file 806-H5.

[0121] (Seventh Modification: Introduction of a Generalized Example) FIG. 25 shows a core A6 according to a seventh modification, which is a further simplification of the general-purpose core A3 shown in FIG. 22. This core A6 omits the sixth source operand 808A-H3, seventh source operand 808B-H3, and eighth source operand 808C-H3 stored in the general-purpose register file 806-H3 of the core A3. Instead, the core A6 stores the values ​​of these elements (sixth source r1, seventh source r2, and eighth source r3) on the argument side of the general-purpose arithmetic instruction processed by the decoder 804-H6. The core A6 may further include a comparator 807-H6 and a flag register 809-H6. The comparator 807-H6 compares the ninth source operand 806A-H6 with the tenth source operand 806B-H6 to determine whether they match, mismatch, or are missing, and records the comparison result in the flag register 809-H6. The second selector 841B-H6 is a multiplexer that uses a mask register to extract and output one of the sixth source r1, seventh source r2, and eighth source r3, which serve as arguments, based on the result recorded in the flag register 809-H6. In other words, by holding the arguments, instruction-dedicated registers such as the decoder 804 can also serve as part of the operands stored in the dedicated register file 808-H6 and the general-purpose register file 806-H6. In the core A6, the reference numerals of devices similar to the dedicated parts and components of the core A3 in FIG. 22 are replaced with "-H6" instead of "-H3" in the reference numerals of the core A3, and detailed descriptions of the functions of the core A6 are omitted.

[0122] The function executed by a single instruction in this core A6 can be generalized to the following equation 6. Here, L is the output element of the first selector 841A-H3, a is the element of the first source operand 806D-H3, b is the element of the second source operand 808D-H3a, c is the element of the third source operand 806E-H3, d is the element of the fourth source operand 808D-H3b, e is the element of the fifth source operand 806C-H3, and r1, r2, and r3 are the sixth, seventh, and eighth sources stored as arguments in the instruction register (decoder 804).

[0123] In addition, in the cores A4, A5, A6, and A7, which are generalized examples, we have exemplified the case where both element b of the second source operand 808D-H3a and element d of the fourth source operand 808D-H3b are used, but if necessary, either element b or element d may be omitted, which is suitable for the Smith-Waterman-Gotoh algorithm, etc.

[0124] In the alignment processing computer system 204 of this embodiment, the processor module 104 includes cores A to D, so that the variability F(i, j) of the current position of the alignment matrix V can be calculated for cores A to D with a single instruction. This reduces the number of accesses to the memory module (main memory) 102 and increases the hit rate of the L1 to L3 cache memories, thereby achieving extremely fast variability calculations. As a result, an approximate string can be derived in a short time for a string pair consisting of a matched string and a matching string. Furthermore, in the alignment processing computer system 204, the constant setting means 604 stores constant data such as gap penalties in a dedicated register file 808, allowing it to be shared across multiple variability calculations performed by the variation / path calculation means 612. This also reduces the number of accesses to the memory module (main memory) 102, thereby increasing the calculation speed.

[0125] Furthermore, in the alignment processing computer system 204, the filling area selection means 606 extracts array areas V1V2...Vk...Vp that are part of the entire alignment matrix V, and the variation / path calculation means 612 calculates the variation within that range, which further increases the hit rate of the L1 to L3 cache memories and therefore increases the calculation speed.

[0126] The above-described embodiments are merely examples for explaining the present invention, and are not intended to limit the present invention to these embodiments. The present invention can be embodied in various forms without departing from the spirit of the present invention.

[0127] For example, in the above embodiment, an example was given in which core A performs alignment processing for a string pair consisting of a matched string and a matching string. However, multiple cores A to D may be used in parallel to perform alignment processing for a common string pair. In this case, the alignment processing kernel may employ, for example, a single instruction, multiple data (Single Instruction, Multiple Data) method to manage the calculation order of cores A to D, or may further employ a pipeline processing method. Furthermore, the alignment processing kernel may employ a single instruction, multiple threads (Single Instruction, Multiple Threads) method. Also, while four cores A to D are illustrated here, the number of cores is not particularly limited.

[0128] For example, in the methods disclosed herein, steps, operations, or functions may be performed in parallel or in a different order unless the results are inconsistent. The steps, operations, and functions described are provided merely as examples, and some of the steps, operations, and functions may be omitted or combined into one, or other steps, operations, or functions may be added, without departing from the spirit of the invention.

[0129] The above-described embodiments are merely examples for explaining the present invention, and are not intended to limit the present invention to these embodiments. The present invention can be implemented in various forms without departing from the spirit of the present invention. For example, in this embodiment, an example is given of performing alignment processing on reference character strings that are genetic information, but the present invention is not limited to this and can be applied to cases where alignment processing is performed on character string pairs other than genetic information.

[0130] Furthermore, in the above embodiment, the hardware configuration of the computing device is a general-purpose structure, but the present invention is not limited to this. For example, individually customized hardware such as an FPGA (Field Programmable Gate Array) may be used.

[0131] Furthermore, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment can be added to or substituted for specific features in other embodiments, with appropriate modifications, and such forms are also included in the spirit of the present invention.

[0132] A, B, C, D Core 1 Computer system 10 Host computer 20 Sub-computer 30 Database 100 Computing device 102 Memory module 104 Processor module 106 Chipset 108 Internal storage device 112 Output interface 114 Input / output interface 116 Communication interface 118 External storage device 200 Computer system for approximate string matching 201 Computer system for index creation 202 Computer system for mapping 203 Computer system for string pair creation 204 Computer system for alignment processing 602 Alignment matrix creation means 604 Constant setting means 606 Filling area selection means 608 Filling route setting means 610 Filling cell selection means 612 Variation / path calculation means 620 Backtrack processing means 622 Approximate string derivation means 800 Program counter 804 Decoder 806 General-purpose register file 806A Upper array character source operand 806B Left array character source operand 806C Upper variation source operand 806D Directly above variation source operand 806E Directly left variation source operand 806F Output destination operand 806S Score source operand 808 Dedicated register file 808A Match score source operand 808B Mismatch score source operand 808C Gap score source operand 808D Penalty source operand 808E Restriction constant operand 830 Execution unit 832 Adder / subtractor 834 Multiplier 836 Floating point arithmetic unit 840 Variation dedicated arithmetic logic unit 840A First adder / subtractor 840B Second adder / subtractor 840C Third adder / subtractor 841A Variation selector 841B Score function selector 841B Arithmetic logic unit dedicated to score function 842 Arithmetic logic unit dedicated to score function

Claims

1. A processor comprising: a first source operand, a second source operand, a third source operand, a fourth source operand, a fifth source operand, a sixth source operand, a first adder / subtractor for calculating a first intermediate sum of elements of the first source operand and elements of the second source operand, a second adder / subtractor for calculating a second intermediate sum of elements of the third source operand and elements of the fourth source operand, a third adder / subtractor for calculating a third intermediate sum of sixth cause data obtained based on the elements of the fifth source operand and elements of the sixth source operand, and a selector for selecting a maximum and / or minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

2. The processor according to claim 1, wherein the first source operand, the third source operand, and the fifth source operand are stored in a general-purpose register file, and the second source operand, the fourth source operand, and the sixth source operand are stored in a dedicated register file.

3. The processor according to claim 1, further comprising: a seventh source operand; and a second selection unit, wherein the sixth causal data is data selected by the second selector from at least an element of the sixth source operand and the seventh source operand.

4. The processor of claim 1, further comprising an eighth source operand, wherein the selector selects maximum and / or minimum values ​​from among elements of at least the first intermediate sum, the second intermediate sum, the third intermediate sum, and the eighth source operand.

5. A processor according to any one of claims 1 to 5, further comprising an instruction decoder for decoding instructions, wherein a single instruction decoded by said instruction decoder executes the calculation of the first intermediate sum by said first adder / subtractor, the calculation of the second intermediate sum by said second adder / subtractor, the calculation of the third intermediate sum by said third adder / subtractor, and the selection of the maximum value and / or the minimum value by said selector.

6. a left-upward variation source operand having as its element the variation to the left diagonally upward based on the current position of an alignment matrix used in an alignment process between a first string and a second string; a true-left variation source operand having as its element the variation to the left based on the current position of the alignment matrix; a penalty source operand having as its element the linear gap penalty value of the alignment process; a true-upward variation source operand having as its element the variation based on the current position of the alignment matrix; a first adder / subtractor that calculates a first intermediate sum of the elements of the true-upward variation source operand and the elements of the penalty source operand; a second adder / subtractor that calculates a second intermediate sum of the elements of the true-left variation source operand and the elements of the penalty source operand; a third adder / subtractor that calculates a third intermediate sum of the elements of the diagonal-upward variation source operand and a score function value based on a match / mismatch between an element of the first string and an element of the second string corresponding to the current position; a mutation selector that selects a maximum value and / or a minimum value from at least the first intermediate sum, the second intermediate sum, and the third intermediate sum.

7. The processor according to claim 6, comprising: a match score source operand; a mismatch score source operand; a first string character source operand having as its element a character in a first string corresponding to the current position; a second string character source operand having as its element a character in a second string corresponding to the current position; and a score function selector which selects an element of the match score source operand when an element of the first string character source operand matches an element of the second string character source operand, and which selects an element of the mismatch score source operand and outputs the result as the score function value when an element of the first string character source operand does not match an element of the second string character source operand.

8. The processor of claim 6, further comprising a score function source operand, said score function value being stored in said score source operand.

9. The processor of claim 6, wherein the left diagonal-upper mutation source operand, the directly above mutation source operand, and the directly left mutation source operand are stored in a general-purpose register file, and the gap source operand is stored in a dedicated register file.

10. The processor of claim 6, further comprising a restriction constant source operand having a restriction constant as an element, wherein the mutation selector selects a maximum value and / or a minimum value from among at least the first intermediate sum, the second intermediate sum, the third intermediate sum, and the elements of the restriction constant source operand.

11. A processor as claimed in any one of claims 6 to 10, further comprising an instruction decoder for decoding instructions, characterized in that a single mutation calculation instruction by said instruction decoder collectively executes the calculation of the first intermediate sum by said first adder-subtractor, the calculation of the second intermediate sum by said second adder-subtractor, the calculation of the third intermediate sum by said third adder-subtractor, and the selection of the maximum value and / or the minimum value by said mutation selector.

12. A computer device for alignment processing, comprising a storage device in which a first character string and a second character string are stored, and a processor, and which executes alignment processing using an alignment matrix of the first character string and the second character string, wherein the processor is one as defined in any one of claims 1 to 10, and wherein the processor calculates a degree of deviation of a current position of the alignment matrix based on an alignment program stored in the storage device.

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