Display device and display method

Abstract

[Problem] To prevent deterioration in display quality even if a light emission duty is low. [Solution] This display device comprises: a pixel array part that has a plurality of pixels arranged in a first direction and a second direction crossing each other; a pixel group drive circuit that, with a pixel group including two or more pixels arranged along the second direction as a unit, sequentially drives a plurality of pixel groups arranged along the second direction; and a gradation signal supply circuit that supplies a signal voltage corresponding to a gradation signal to the two or more pixels belonging to the pixel group in synchronization with the driving by the pixel group drive circuit. Each of the plurality of pixels has a self-luminous element that emits light with a brightness corresponding to the gradation signal, and the gradation signal supply circuit controls the signal voltage to be supplied to the pixel group such that the respective light emission patterns and / or light emission duties in two or more continuous display frames are different.

Description

Display device and display method

[0001] The present disclosure relates to a display device and a display method.

[0002] With the advancement of semiconductor process technology, high-resolution display devices using microstructured self-luminous elements such as organic electroluminescence (EL) elements have been attracting attention (see, for example, Patent Document 1). One example of this type of display device is a microdisplay. Each pixel constituting the microdisplay uses a microstructured organic EL element or liquid crystal display element.

[0003] Japanese Patent Application Laid-Open No. 2010-145664

[0004] In a display device, a plurality of pixel rows are typically scanned in sequence, and the self-luminous elements of each pixel are controlled to emit light for each pixel row. If the light-emitting duty, which represents the proportion of pixel rows that are to emit light among all pixel rows, is equal to or less than a predetermined value (e.g., 20%), there is a risk of a deterioration in display quality due to a large difference in current flowing through a node (e.g., a cathode electrode) to which the self-luminous elements are connected between the pixel rows that are to emit light and the pixel rows that are not to emit light.

[0005] Therefore, the present disclosure provides a display device and a display method that prevent degradation of display quality even when the light emission duty is low.

[0006] In order to solve the above problems, according to the present disclosure, there is provided a display device comprising: a pixel array section having a plurality of pixels arranged in a first direction and a second direction that intersect with each other; a pixel group drive circuit that sequentially drives a plurality of pixel groups arranged along the second direction, each pixel group including two or more of the pixels arranged along the second direction; and a gradation signal supply circuit that supplies a signal voltage corresponding to a gradation signal to the two or more pixels belonging to the pixel group in synchronization with driving by the pixel group drive circuit, wherein each of the plurality of pixels has a self-luminous element that emits light at a luminance corresponding to the gradation signal, and the pixel group drive circuit controls the emission start timing and the extinction timing of the plurality of pixels so that at least one of the emission pattern or the emission duty in each of two or more consecutive display frames is different.

[0007] The pixel group drive circuit may control the emission start timing and extinction timing of the plurality of pixels so that a plurality of emission forms, each having different emission patterns or different emission duties, are selected in rotation or randomly for each display frame.

[0008] The pixel group drive circuit may control the emission start timing and extinction timing of the plurality of pixels so that the light emission duty is the same for each display frame and the plurality of different light emission patterns are selected in rotation or randomly.

[0009] The pixel group drive circuit may set the light emitting duty for each display frame to be the same, and may set the light emitting pattern for each of two or more adjacent display frames to be different.

[0010] The different light emission patterns may differ in at least one of the number of pixel groups that emit light simultaneously or their locations, and the different light emission duties may differ in the proportion of the number of pixel groups that emit light simultaneously out of the total number of the plurality of pixel groups arranged along the second direction.

[0011] The light emission pattern may move from a first end to a second end in the second direction in synchronization with the pixel group drive circuit sequentially driving the plurality of pixel groups for each display frame.

[0012] The areas of the light emitting patterns in the second direction in two or more consecutive display frames may be different from one another.

[0013] At least some of the light emitting patterns selected in turn or randomly may include the pixel groups that emit light and the pixel groups that do not emit light.

[0014] Of the plurality of light-emitting patterns selected in sequence or randomly, at least two of the light-emitting patterns have a first pixel block to be illuminated, a second pixel block not to be illuminated, and a third pixel block to be illuminated, which are arranged adjacent to each other in the second direction, the second pixel block being arranged between the first pixel block and the third pixel block, and the width of the second pixel block in the second direction may be different for each of the at least two light-emitting patterns.

[0015] Each of the first pixel block, the second pixel block, and the third pixel block may have the same width as the pixel group in the first direction and the width of one or more of the pixel groups in the second direction.

[0016] The first pixel block and the third pixel block may have the same width in the second direction.

[0017] The first direction is the horizontal direction of the display area, the second direction is the vertical direction of the display area, the pixel group is a pixel row extending horizontally and vertically in the display area, and the pixel group drive circuit may make at least one of the light emission pattern or the light emission duty different in each of two or more consecutive display frames.

[0018] The pixel group drive circuit may vary at least one of the light emission pattern and the light emission duty for each display frame when the light emission duty is equal to or less than a predetermined value.

[0019] The pixel group driving circuit may make at least one of the light emission pattern or the light emission duty different in each of two or more consecutive display frames when the brightness of a first partial region that is located inside both ends in the first direction is made higher than the brightness of a second partial region that is located closer to both ends in the first direction than the first partial region.

[0020] The self-luminous element may be an organic EL (Electroluminescence) element.

[0021] According to the present disclosure, there is provided a display method, in a pixel array section having a plurality of pixels arranged in a first direction and a second direction intersecting each other, comprising: sequentially driving a plurality of pixel groups arranged along the second direction, each pixel group including two or more of the pixels arranged along the second direction; supplying a signal voltage corresponding to a gradation signal to the two or more pixels belonging to the pixel group in synchronization with the driving of the plurality of pixel groups; causing a self-luminous element provided in each of the plurality of pixels to emit light at a luminance corresponding to the gradation signal; and controlling the emission start timing and extinction timing of the plurality of pixels so that at least one of an emission pattern or an emission duty in each of two or more consecutive display frames is different.

[0022] 3C 。 FIG. 3D is a block diagram showing a schematic configuration of a display system including a display device and a host device according to an embodiment. FIG. 3E is a diagram showing an image displayed on a display device according to an embodiment. FIG. 3F is a diagram showing how an emission pattern of a first example moves in conjunction with scanning of pixel rows. FIG. 3G is a diagram showing how an emission pattern of a second example moves in conjunction with scanning of pixel rows. FIG. 3H is a diagram showing how an emission pattern of a third example moves in conjunction with scanning of pixel rows. FIG. 3I is a diagram showing a killer image of the emission pattern of FIG. 3C. FIG. 3I is a diagram showing an example of a plurality of emission patterns that a display device according to an embodiment switches for each display frame. 10 is an external view of an HMD which is a third application example of the electronic device; an external view of smart glasses; an external view of a TV which is a fourth application example of the electronic device; and an external view of a smartphone which is a fifth application example of the electronic device.

[0023] Hereinafter, embodiments of a display device and a display method will be described with reference to the drawings. The following description will focus on the main components of the display device, but the display device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0024] Fig. 1 is a block diagram showing a schematic configuration of a display system 3 according to one embodiment, which includes a display device 1 and a host device 2. As shown in Fig. 1, the display device 1 according to one embodiment includes a display unit 4, a display controller 5, a timing controller 6, and an interface (hereinafter, referred to as I / F) unit 7.

[0025] The display unit 4 includes a pixel array unit 11 .

[0026] The pixel array unit 11 has a plurality of pixels arranged in a first direction (e.g., horizontal direction) X and a second direction (e.g., vertical direction) Y that intersect with each other. As will be described later, each pixel has a self-emitting element and a pixel circuit. The self-emitting element is, for example, an organic EL element or an LED (Light Emitting Diode). The following mainly describes an example in which the first direction X is the horizontal (horizontal) direction and the second direction Y is the vertical (vertical) direction.

[0027] The display controller 5 includes a gate driver 12 and a source driver 13. The gate driver 12 includes a V-Logic unit 12a and a V-Analog unit 12b. The V-Logic unit 12a is a transfer circuit unit, such as a shift register, and is configured with the voltage amplitude and minimum transistor size required for transfer. The V-Analog unit 12b is a circuit unit for driving the pixel unit. It incorporates a level shift circuit to achieve the voltage amplitude required for pixel drive and is configured with serially connected inverter circuits to expand the transistors to account for the charging and discharging of scan line loads (e.g., resistors and capacitors) within the pixel area. The gate driver 12 outputs multiple selection signals to drive each pixel group (e.g., pixel rows) including two or more pixels arranged in a first direction (horizontal direction) X. More specifically, the gate driver 12 is connected to multiple row selection lines to drive each of the multiple pixel rows arranged vertically. The gate driver 12 outputs multiple selection signals to the multiple row selection lines, each of which goes high at different times. As a result, the gate driver 12 drives the multiple pixel rows line-sequentially, one pixel row at a time. In principle, the same selection signal is supplied to multiple pixels in the same pixel row. Therefore, typically, multiple pixels in the same pixel row are driven at the same timing. As will be described later, the gate driver 12 performs control to change at least one of the light-emitting pattern and light-emitting duty in each of two or more consecutive display frames.

[0028] The source driver 13 has an H-Logic unit 13a and an H-Analog unit 13b. The source driver 13 drives multiple signal lines that supply pixel data to each pixel included in a group of pixels (hereinafter referred to as a pixel row) arranged in a first direction (horizontal direction) X. Hereinafter, the signal lines will be referred to as vertical signal lines. The multiple vertical signal lines extend in a second direction (vertical direction) Y and are provided corresponding to multiple groups of pixels (hereinafter referred to as pixel columns) arranged in the first direction X. The source driver 13 outputs multiple pixel data in parallel to the multiple vertical signal lines. Each pixel data is supplied to one of the pixels in the corresponding pixel column via the corresponding vertical signal line.

[0029] As will be described later, the gate driver 12 performs control to change at least one of the light-emitting pattern and the light-emitting duty in each of two or more consecutive display frames. More specifically, the gate driver 12 specifies rows to which pixel data supplied from the source driver 13 is written, and controls the light-emission start and end timings of the specified rows. The different light-emitting patterns differ in at least one of the number of pixel rows that emit light simultaneously and their locations. The different light-emission duties differ in the proportion of the number of pixel rows that emit light simultaneously out of the total number of pixel rows arranged along the second direction Y.

[0030] More specifically, the gate driver 12 controls the emission start timing and extinction timing of each pixel row so that a plurality of emission forms, each differing in at least one of the emission pattern and the emission duty, are selected in rotation or randomly for each display frame.

[0031] For example, the gate driver 12 controls the emission start timing and extinction timing of each pixel row so that the light emission duty is the same for each display frame and a plurality of different light emission patterns are selected in sequence or randomly. In other words, the gate driver 12 controls the light emission duty for each display frame and different light emission patterns for two or more adjacent display frames.

[0032] As will be described later, the light-emitting pattern moves from a first end (e.g., the top end) to a second end (e.g., the bottom end) in the second direction (vertical direction) Y in synchronization with the gate driver 12 sequentially driving the plurality of pixel rows for each display frame. The areas of the light-emitting patterns in the second direction (vertical direction) Y in two or more consecutive display frames may be different from one another. At least some of the light-emitting patterns selected in sequence or randomly may include light-emitting pixel rows and non-light-emitting pixel rows.

[0033] The timing controller 6 includes a clock generator 21 , a timing generator 22 , and an image processing unit 23 .

[0034] The clock generator 21 generates a vertical synchronization clock and a horizontal synchronization clock for the display unit 4 and supplies them to the source driver 15. The timing generator 22 generates a signal that controls the operation timing of the display controller 5 and supplies it to the display controller 5. The image processing unit 23 performs various image processing on image data input from the host device 2 via the I / F unit 7, and supplies the processed image data to the gate driver 12. The specific content of the image processing performed by the image processing unit 23 is not important. The image data supplied to the gate driver 12 includes a plurality of pixel data to be supplied to a plurality of pixels.

[0035] The I / F unit 7 includes an image I / F unit 25 , a clock control unit 26 , an H / V synchronization unit 27 , and a data S / P conversion unit 28 .

[0036] The image I / F unit 25 receives image data transmitted from the host device 2. The image data is serial digital data. The clock control unit 26 generates a clock that matches the display frequency of the display device 1 and supplies it to the clock generator 21. The H / V synchronization unit 27 determines the horizontal synchronization timing and vertical synchronization timing of the display device 1 and transmits them to the timing generator 22. The data S / P conversion unit 28 converts the image data into parallel data and supplies it to the image processing unit 23.

[0037] The host device 2 sends image data and display control signals to the image I / F unit 25. The host device 2 does not necessarily have to be located near the display device 1. For example, the host device 2 may be located at a location far from the display device 1 and send image data and display control signals to the display device 1 via a wired or wireless network line.

[0038] 1 is a device that sends a video signal to the display device 1, such as a computer, a camera, or a TV. In the display device 1 according to one embodiment, an example will be mainly described in which an organic EL element (hereinafter, referred to as OLED) is used as an example of a self-luminous element.

[0039] Fig. 2 is a diagram schematically showing an image displayed on the display device 1 according to one embodiment. Display of an image on the display unit 4 of the display device 1 is controlled by the gate driver 12 shown in Fig. 1 sequentially selecting and driving a plurality of pixel rows extending in the horizontal direction and arranged in the vertical direction of the display unit 4, and supplying grayscale signals to a plurality of pixels included in the selected pixel row from the source driver 13. The sequential selection and driving of a plurality of pixel rows by the gate driver 12 is called pixel row scanning.

[0040] 2A is a diagram showing image IG1 that should be displayed. Image IG1 has a white rectangular image IG0 placed in part of a gray background image. The vertical width of rectangular image IG0 is 20% of the vertical width of the display area of ​​display unit 4, and the light emission duty of rectangular image IG0 is 20%. The light emission duty is the ratio of the number of pixel rows that are simultaneously illuminated to the total number of pixel rows arranged vertically in the display area.

[0041] The width of rectangular image IG0 is shorter than the width of the display area, and both horizontal edges of rectangular image IG0 are positioned inside both horizontal edges of the display area. In other words, the background image is positioned outside both horizontal edges of rectangular image IG0. In this way, rectangular image IG0 is surrounded by the background image in both the horizontal and vertical directions.

[0042] When the image IG1 is displayed on the display unit 4, the gate driver 12 sequentially selects and drives each pixel row, and the source driver 13 supplies a grayscale signal to each pixel in the pixel row being driven.

[0043] 2B to 2D are diagrams showing first to third examples of displaying an image IG1 using different illumination patterns IP1 to IP3. Each of the illumination patterns IP1 to IP3 differs in at least one of the number of pixel rows that are simultaneously illuminated and their locations. An illumination pattern may include only one pixel row or multiple pixel rows. When an illumination pattern includes multiple pixel rows, the pixel rows may be vertically adjacent or spaced apart. For example, when two pixel rows included in an illumination pattern are vertically spaced apart, one or more pixel rows that are not to be illuminated are disposed between the two pixel rows. As the gate driver 12 scans each pixel row, the illumination range corresponding to the illumination pattern moves from the top to the bottom of the display area.

[0044] This embodiment is characterized in that multiple light emission patterns are switched for each display frame. At least some of the multiple light emission patterns include light-emitting pixel rows and non-light-emitting pixel rows. Of the multiple light emission patterns selected in sequence or randomly, at least two or more light emission patterns have, for example, two pixel blocks to be light-emitting arranged adjacent to each other in the second direction Y and a pixel block to be non-light-emitting arranged between these two pixel blocks. The vertical widths in the second direction Y of the two pixel blocks to be light-emitting may be the same. For each of the at least two or more light emission patterns, the widths in the second direction Y of the pixel blocks to be non-light-emitting are different.

[0045] 2 is provided near the vertical center of the display area. When the gate driver 12 drives pixel rows overlapping with the image IG1, the source driver 13 supplies a signal voltage of a gradation signal corresponding to white to the signal lines at the pixel positions of the image IG1, and a signal voltage of a gradation signal corresponding to gray to the signal lines at the pixel positions of the background image.

[0046] In this way, while the light-emitting range corresponding to the light-emitting pattern moves from the top to the bottom of the display area, the light-emitting mode of each pixel row is controlled according to the luminance and color of the image IG1 in the display area. The control of the light-emitting mode of each pixel row is performed by the gate driver 12.

[0047] Fig. 2B shows a first example in which image IG1 is displayed using illumination pattern IP1, and the viewer sees image IG2. Fig. 2C shows a second example in which image IG1 is displayed using illumination pattern IP2, and the viewer sees image IG3. Fig. 2D shows a third example in which image IG1 is displayed using illumination pattern IP3, and the viewer sees image IG4.

[0048] 2B to 2D, the upper side shows light emission patterns IP1 to IP3 and OLED light emission current waveforms w1 to w3, and the lower side shows images IG2 to IG4.

[0049] The light emission duties of the light emission patterns IP1 to IP3 in the first to third examples are all 20%.

[0050] The first example of the illumination pattern IP1 in FIG. 2B has the vertical width of the rectangular image IG0 and multiple pixel rows (first pixel block B1) to be illuminated. As the gate driver 12 sequentially scans the multiple pixel rows, the illumination pattern IP1 moves from the top to the bottom of the display area. When the illumination pattern IP1 approaches the rectangular image IG0, the cathode current begins to increase to display the rectangular image IG0, as shown by the cathode current waveform w1 in FIG. 2B. The cathode current reaches its maximum when the illumination pattern IP1 overlaps the vertical width of the rectangular image IG0. Thereafter, as the illumination pattern IP1 moves toward the bottom of the display area, the cathode current begins to decrease.

[0051] When image IG1 is displayed using light-emitting pattern IP1, a noticeable drop in brightness of the background image on both sides of rectangular image IG0 in the horizontal direction is visible, as in image IG2. This drop in brightness is caused by IR drop occurring in the cathode electrode due to the light-emitting current flowing through the OLED of each pixel in the pixel row that overlaps rectangular image IG0. The drop in brightness on both sides of rectangular image IG0 in the horizontal direction is more noticeable when the light-emitting duty is small.

[0052] The second example of the illumination pattern IP2 in FIG. 2C includes a plurality of pixel rows (second pixel block B2) that are to be illuminated and have a vertical width that is half the vertical width of the rectangular image IG0, a plurality of pixel rows (third pixel block B3) that are adjacent to the second pixel block B2 and are not to be illuminated and have a vertical width that is one-quarter the vertical width of the rectangular image IG0, and a plurality of pixel rows (fourth pixel block B4) that are adjacent to the third pixel block B3 and are to be illuminated and have a vertical width that is half the vertical width of the rectangular image IG0. The illumination pattern IP2 is composed of second to fourth pixel blocks B2 to B4, and the sum of the vertical widths of the second pixel block B2 and the fourth pixel block B4 is the same as the vertical width of the rectangular image IG0. The combined vertical width of the second to fourth pixel blocks B2 to B4 is greater than the vertical width of the rectangular image IG0.

[0053] As the light-emitting pattern IP2 moves from the top to the bottom of the display area, the cathode current of the OLED begins to increase when the bottom edge of the fourth pixel block B4 approaches the rectangular image IG0. The cathode current of the OLED increases stepwise due to the presence of the third pixel block B3, which is not a light-emitting target. The cathode current reaches its maximum when the bottom edge of the fourth pixel block B4 coincides with the bottom edge of the rectangular image IG0. Thereafter, the cathode current begins to decrease stepwise as the light-emitting pattern IP2 moves toward the bottom edge of the display area.

[0054] As described above, the vertical width of the light-emitting pattern IP2 (second to fourth pixel blocks B2 to B4) in the second example is greater than the vertical width of the rectangular image IG0, so the cathode current when the light-emitting pattern overlaps with the rectangular image IG0 is smaller than in the first example, and the peak of the cathode current in the second example is lower than the peak of the cathode current (dashed line) in the first example. Therefore, the decrease in brightness of the background image on both horizontal sides of the rectangular image IG0 in the second example is smaller than in the first example. However, because the vertical width of the light-emitting pattern IP2 is greater than the vertical width of the rectangular image IG0, a slight decrease in brightness occurs in the background image on both vertical sides of the rectangular image IG0.

[0055] The third example of the illumination pattern IP3 shown in FIG. 2D includes a plurality of pixel rows (fifth pixel block B5) that are to be illuminated and have a vertical width half that of the rectangular image IG0, a plurality of pixel rows (sixth pixel block B6) that are adjacent to the fifth pixel block B5 and are not to be illuminated and have a vertical width half that of the rectangular image IG0, and a plurality of pixel rows (seventh pixel block B7) that are adjacent to the sixth pixel block B6 and are to be illuminated and have a vertical width half that of the rectangular image IG0. The illumination pattern IP3 is composed of fifth to seventh pixel blocks B5 to B7, and the sum of the vertical widths of the fifth pixel block B5 and the seventh pixel block B7 is the same as the vertical width of the rectangular image IG0. The combined vertical width of the fifth to seventh pixel blocks B5 to B7 is greater than the vertical width of the rectangular image IG0 and is greater than the vertical width of the illumination pattern of the second example (second to fourth pixel blocks B2 to B4).

[0056] As the light emitting pattern IP3 moves from the top to the bottom of the display area, the cathode current of the OLED starts to increase when the bottom edge of the seventh pixel block B7 reaches the rectangular image IG0. The cathode current of the OLED changes in a trapezoidal shape.

[0057] As described above, the vertical width of the light-emitting pattern IP3 (fifth to seventh pixel blocks B5 to B7) in the third example is greater than the vertical widths of the rectangular image IG0 and the light-emitting pattern IP2. Therefore, the cathode current when the light-emitting pattern overlaps the rectangular image IG0 is smaller than in the second example, and the peak of the cathode current in the third example is lower than the peak of the cathode current (dashed line) in the second example. Therefore, the reduction in brightness of the background image on both horizontal sides of the rectangular image IG0 in the third example is smaller than in the second example. However, because the vertical width of the light-emitting pattern IP3 is greater than the vertical width of the light-emitting pattern IP2, the reduction in brightness occurs over a wider range on both vertical sides of the rectangular image IG0 than in the second example, but the degree of the reduction in brightness is smaller than in the second example.

[0058] Thus, although the light emission patterns IP1 to IP3 have the same light emission duty, the degree of brightness reduction of the background image that occurs around the rectangular image IG0 differs. In the case of light emission pattern IP1, which has the same vertical width as the rectangular image IG0, the brightness reduction of the background image on both sides of the rectangular image IG0 in the horizontal direction is significant. By mixing pixel blocks that are to be illuminated and pixel blocks that are not to be illuminated in the light emission pattern, as in light emission pattern IP2 or IP3, and making the combined vertical width of these pixel blocks larger than the vertical width of the rectangular image IG0, the maximum value of the cathode current can be suppressed and brightness reduction can be suppressed, but on the other hand, the range in which brightness reduction occurs expands.

[0059] FIG. 3A shows how the light-emitting pattern IP1 of the first example moves in conjunction with the scanning of pixel rows. For simplicity's sake, FIG. 3A illustrates an example in which the entire display area is displayed with the same brightness (light-emitting duty of 20%). As shown in FIG. 3A, the gate driver 12 performs scanning control to drive multiple pixel rows arranged vertically in the display area, starting from the top pixel row. As the pixel rows are scanned sequentially, the light-emitting pattern IP1 also moves pixel row by pixel row from the top to the bottom of the display area. In FIG. 3A, pixel rows to be illuminated are shown in white, and pixel rows not to be illuminated are shown in black. In reality, the pixel rows to be illuminated include multiple pixels with different light-emitting modes depending on the brightness and color of the image displayed in the display area. Meanwhile, the OLEDs of the pixels in the pixel rows not to be illuminated are turned off.

[0060] FIG. 3A shows an example in which the display area is made up of 20 pixel rows 1H to 20H, and the times t at which the gate driver 12 drives (scans) each pixel row are designated as t0, t1h, t2h, . . . , t20h.

[0061] At time t0, all pixel rows are not subject to light emission, and the OLEDs of all pixels are off. At time t1h, pixel row 1H at the top of the display area is scanned, causing the OLEDs of each pixel in pixel row 1H to emit light. At time t2h, pixel row 2H is scanned, causing the OLEDs of each pixel in pixel row 2H to emit light. At this time, the OLEDs of each pixel in pixel row 1H also continue to emit light. Thereafter, pixel row 3H and subsequent pixel rows are scanned in a similar manner, causing the OLEDs of each pixel in each pixel row to emit light.

[0062] 3A shows an example in which the vertical width of rectangular image IG0 is equal to the vertical width of four pixel rows, i.e., an example in which the light emission duty is 20%. In this case, when pixel row 4H is scanned, not only do the OLEDs of each pixel in pixel row 4H emit light, but the OLEDs of each pixel in pixel rows 1H to 3H also continue to emit light. Therefore, when pixel row 4H is scanned, four pixel rows with the same vertical width as the rectangular image IG0 are simultaneously illuminated.

[0063] After time t5h, a new pixel row is illuminated so that four vertically consecutive pixel rows are illuminated simultaneously, and one of the four pixel rows closest to the top end is switched from an illuminated target to a non-illuminated target and turned off.

[0064] When pixel row 20H at the bottom of the display area is scanned at time t20h, the OLEDs of the pixels in pixel row 20H emit light, and the OLEDs of the pixels in pixel rows 17H to 19H also continue to emit light.

[0065] The period from time t0 to t20h is the display period of the first frame, and the display period of the second frame begins from time t21h onwards.

[0066] 3B is a diagram showing how the light-emitting pattern IP2 of the second example moves in conjunction with the scanning of pixel rows. The second example has the same light-emitting duty as the first example, but differs from the first example in that a third pixel block B3, which is not to be illuminated, is placed between the second pixel block B2 and the fourth pixel block B4, which are to be illuminated. The vertical width of the first pixel block B1, which is to be illuminated in the first example, is equal to the sum of the vertical widths of the second pixel block B2 and the fourth pixel block B4 in the second example.

[0067] As shown in Figure 3B, as scanning of each pixel row begins at time t0, the number of pixel rows to be illuminated gradually increases. At time t5h, the two pixel rows constituting the second pixel block B2 and the two pixel rows constituting the fourth pixel block B4 are illuminated simultaneously. The third pixel block B3, located between the second pixel block B2 and the fourth pixel block B4, has a vertical width equivalent to one pixel row.

[0068] After time t5h, the remaining pixel rows are scanned sequentially while simultaneously emitting light across the vertical width of the second to fourth pixel blocks B2 to B4. At time t20h, the pixel row at the bottom of the display area is scanned, and the bottom edge of the fourth pixel block B4 becomes the bottom edge of the display area, completing the display of the display area in the first frame. After time t21h, scanning of each pixel row in the second frame is performed.

[0069] 3C is a diagram showing how the illumination pattern IP3 of the third example moves in conjunction with the scanning of pixel rows. The third example has the same illumination duty as the first example, but differs from the second example in that a sixth pixel block B6, which is not an illumination target and has the same vertical width as the fifth and seventh pixel blocks B5 and B7, is disposed between the fifth and seventh pixel blocks B5 and B7. In the second example, the sum of the vertical widths of the second and fourth pixel blocks B2 and B4, which are illumination targets, is equal to the sum of the vertical widths of the fifth and seventh pixel blocks B5 and B7, which are illumination targets, in the third example. In the second example, the vertical width of the third pixel block B3, which is disposed between the second and fourth pixel blocks B2 and B4, is equal to the vertical width of one pixel block, whereas in the third example, the vertical widths of the fifth to seventh pixel blocks B5 to B7 are equal to the vertical widths of two pixel blocks.

[0070] 3C, as scanning of each pixel row begins at time t0, the number of pixel rows to be illuminated gradually increases. At time t6h, the fifth pixel block B5 and the seventh pixel block B7 that constitute the illumination pattern IP3 are illuminated simultaneously. The sixth pixel block B6, which is not to be illuminated and is located between the fifth pixel block B5 and the seventh pixel block B7, has a vertical width equivalent to two pixel rows.

[0071] From time t6h onwards, the fifth to seventh pixel blocks B5 to B7 simultaneously emit light over their vertical widths, while the remaining pixel rows are scanned sequentially. At time t20h, the pixel row at the bottom of the display area is scanned, and the bottom edge of the seventh pixel block B7 becomes the bottom edge of the display area, completing the display of the display area for the first frame. From time t21h onwards, scanning of each pixel row in the second frame is performed.

[0072] 3A to 3C show an example in which each pixel row is displayed at the same brightness for the sake of simplicity, but when a rectangular image IG0 is displayed at a brightness higher than that of a background image of the same brightness as part of the background image as in FIG. 2A, the OLED emission brightness of two or more pixel rows that overlap with the rectangular image IG0 needs to be changed depending on whether it is the rectangular image IG0 or the background image. More specifically, the OLED emission brightness of pixels at pixel positions that overlap with the rectangular image IG0 needs to be higher than that of pixels at pixel positions that overlap with the background image.

[0073] The light emission patterns IP1, IP2, and IP3 shown in FIGS. 3A to 3C are examples, and light emission forms of the light emission patterns may be other than those shown in FIGS. 3A to 3C.

[0074] Images of various shapes and sizes are displayed in the display area. For each of the multiple light-emitting patterns, there is an image of a shape and size in which a decrease in brightness is most easily perceived. For example, in the case of the rectangular image IG0 in FIG. 2A, when each pixel row is scanned with a light-emitting pattern having the same vertical width as the rectangular image IG0, a significant decrease in brightness is perceived on both sides of the rectangular image IG0 in the horizontal direction. In this specification, for convenience, the image of a shape and size in which a decrease in brightness is most easily perceived for each light-emitting pattern is referred to as a killer image.

[0075] Fig. 4 is a diagram showing a killer image of the illumination pattern IP3 of Fig. 3C. In the illumination pattern IP3 of Fig. 3C, a sixth pixel block B6 that is not to be illuminated is placed between a fifth pixel block B5 and a seventh pixel block B7 that are to be illuminated, and the fifth to seventh pixel blocks B5 to B7 have a common vertical width (for example, the vertical width of two pixel columns).

[0076] With light emission pattern IP3, when image IG5, which has the same vertical width as the fifth to seventh pixel blocks B5 to B7, is displayed in the display area, the drop in brightness perceived around image IG5 is greatest, and a killer image such as image IG6 is actually perceived. The cathode current waveform w4 when a killer image is displayed with light emission pattern IP3 reaches its peak when the two rectangular images included in the killer image overlap with the fifth pixel block B5 and the seventh pixel block B7 in light emission pattern IP3.

[0077] In the case of the image of Figure 2A, the degree of brightness reduction can be suppressed by scanning each pixel row with the illumination pattern of Figure 3C, but on the other hand, when the image of Figure 4 is displayed with the illumination pattern of Figure 3C, a significant reduction in brightness occurs around the image.

[0078] From the above, it can be seen that in order to display an image of any shape and size, it is desirable to display a plurality of different illumination patterns by switching between them for each display frame, rather than using a single illumination pattern.

[0079] Fig. 5 is a diagram showing an example of a plurality of light emission patterns that are switched for each display frame by the display device 1 according to this embodiment. Fig. 5 shows an example in which three types of light emission patterns IP2, IP3, and IP4 are switched in turn for each display frame. The switching control of the light emission patterns IP2 to IP4 is performed by the gate driver 12 controlling the light emission start timing and light extinction timing of pixel data supplied from the source driver 13 to each signal line.

[0080] The upper part of Fig. 5A illustrates an emission pattern IP2 and an OLED cathode current waveform w2. The lower part of Fig. 5A illustrates an image IG3 that is actually viewed when pixel IG1 is illuminated using emission pattern IP2. The upper part of Fig. 5B illustrates an emission pattern IP3 and an OLED cathode current waveform w3. The lower part of Fig. 5B illustrates an image IG4 that is actually viewed when pixel IG1 is illuminated using emission pattern IP3. The upper part of Fig. 5C illustrates an emission pattern IP4 and an OLED cathode current waveform w5. The lower part of Fig. 5C illustrates an image IG7 that is actually viewed when pixel IG3 is illuminated using emission pattern IP2.

[0081] Light emission pattern IP2 includes the second to fourth pixel blocks B2 to B4 in Fig. 3B. Light emission pattern IP3 includes the fifth to seventh pixel blocks B5 to B7 in Fig. 3C. Light emission pattern IP4 includes an eighth pixel block B8 that is an emission target and has the same vertical width as the third pixel block B3, a ninth pixel block B9 that is a non-emission target and has the same vertical width as the third pixel block B3, a tenth pixel block B10 that is an emission target and has the same vertical width as the second pixel block B2, an eleventh pixel block B11 that is a non-emission target and has the same vertical width as the third pixel block B3, and a twelfth pixel block B12 that is an emission target and has the same vertical width as the third pixel block B3.

[0082] When light emission pattern IP2 is selected, the cathode current of the OLED increases stepwise and then decreases stepwise, as shown in cathode current waveform w2. When light emission pattern IP3 is selected, the cathode current of the OLED changes in a trapezoidal shape, as shown in cathode current waveform w3. When light emission pattern IP4 is selected, the cathode current of the OLED increases stepwise and reaches a peak, then decreases once, reaches a second peak, and then decreases stepwise, as shown in cathode current waveform w5.

[0083] In this embodiment, for example, light emission patterns IP2 to IP4 are selected in turn for each display frame. As a result, the OLED cathode current becomes a waveform that is an average of the cathode current waveforms w1 to w3, as shown in cathode current waveform w4. Furthermore, the brightness reductions visible around images IG6 to IG13 in Figure 5 are averaged, and as shown in image IG14, the brightness reduction is barely visible across the entire display area.

[0084] It should be noted that the three light emission patterns IP2 to IP4 shown in Fig. 5 are merely examples, and light emission patterns other than those shown in Fig. 5 may be included. The order in which the multiple light emission patterns are selected is arbitrary, and n (n is 2 or more) types of light emission patterns may be selected in rotation or randomly. Increasing the number of random selections averages out the light emission brightness, making the decrease in brightness around the image less noticeable.

[0085] In the above-described embodiment, an example in which the light emission pattern is switched for each display frame has been described, but the light emission duty may also be switched for each display frame. When the light emission duty is high, the light emission brightness of the entire display area increases, making the decrease in brightness around the periphery of the image less noticeable. Therefore, the need to switch the light emission duty arises when the light emission duty is equal to or less than a predetermined value (e.g., 20%).

[0086] Alternatively, a plurality of combinations of different light emission patterns and different light emission duties may be prepared, and the plurality of combinations may be selected in rotation or randomly for each display frame.

[0087] The above-described control of switching the light emission pattern or light emission duty for each display frame may be performed only when the luminance of the rectangular image IG0 displayed in the display area is higher than the luminance of the background image. That is, when the gate driver 12 sets the luminance of a first partial area (e.g., rectangular image IG0) located inside both ends in the first direction X to be higher than the luminance of a second partial area (e.g., background image) located closer to both ends in the first direction X than the first partial area, the gate driver 12 may set at least one of the light emission pattern or the light emission duty in each of two or more consecutive display frames to be different.

[0088] (Specific Circuit Configuration of Pixel Circuit) Each pixel PX arranged in the pixel array section 11 of the display device 1 according to this embodiment has a pixel circuit that drives an organic EL element, which is a self-luminous element. The specific circuit configuration of the pixel circuit is arbitrary. Representative circuit configurations will be described below in order.

[0089] FIG. 6A is a circuit diagram of a pixel circuit 10 according to a first example. As shown in FIG. 6A, the pixel circuit 10 according to the first example includes NMOS transistors Q11 and Q12 and a capacitor C11. The gate of the transistor Q1 is connected to a control line WSL that supplies a write control signal for a grayscale voltage, the drain is connected to a signal line SGL, and the source is connected to the gate of the transistor Q12. The drain of the transistor Q12 is connected to a power supply line VCCP. A capacitor C11 is connected between the gate and source of the transistor Q12. The source of the transistor Q12 is connected to the anode of the light-emitting element EL, and the cathode is connected to the power supply line Vcat. The power supply line VCCP supplies a voltage for light emission quenching control, and the voltage level of the power supply line VCCP is switched appropriately to a first voltage or a second voltage lower than the first voltage.

[0090] In FIG. 6A , when the transistor Q11 is turned on, the voltage across the capacitor C11 is set based on the pixel signal supplied from the signal line SGL. During a period when the voltage of the power supply line VCCP is at a first voltage, the transistor Q12 passes a current corresponding to the voltage across the capacitor C11 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor Q12. In this manner, the pixel PX emits light at a luminance corresponding to the pixel signal. During a period when the power supply line VCCP is at a second voltage, the light-emitting element EL is turned off. In FIG. 6A , for example, at least one of the light-emitting pattern and the light-emitting duty can be controlled by controlling the voltage of the power supply line VCCP. Specifically, during light emission, the power supply line VCCP is set higher than the cathode voltage Vcath of the light-emitting element EL, and during light-off, VCCP≦Vcath.

[0091] FIG. 6B is a circuit diagram of a pixel circuit 10 according to a second example. As shown in FIG. 6B, the pixel circuit 10 according to the second example includes PMOS transistors Q11 to Q14 and capacitors C11 and C12. The gate of transistor Q11 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor Q12. Capacitors C11 and C12 are connected in series between the drain of transistor Q11 (the gate of transistor Q12) and a power supply line VCCP. The drain of transistor Q13 is connected to the source of transistor Q12. The source of transistor Q13 is connected to the power supply line VCCP, and its gate is connected to a control line DSL. The voltage level of the control line DSL switches between when the light-emitting element EL is emitting light and when it is not emitting light. The control line DSL is also used to control a correction voltage. The control line WSL is used to control the writing of grayscale voltages. The drain of transistor Q12 is connected to the anode of the light-emitting element EL and the source of transistor Q14. The drain of transistor Q14 is connected to the power supply line VSS, and the gate is connected to control line AZSL. The control line AZSL controls whether the anode of the light-emitting element EL is set to a reset voltage.

[0092] When the transistor Q11 is turned on, the voltage across the capacitor C11 is set based on the pixel signal supplied from the signal line SGL. The transistor Q13 is turned on and off based on the signal on the control line DSL. While the transistor Q13 is in the on state, the transistor Q12 passes a current corresponding to the voltage across the capacitor C11 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor Q12. In this way, the pixel PX emits light at a luminance corresponding to the pixel signal. The transistor Q14 is turned on and off based on the signal on the control line AZSL. While the transistor Q14 is in the on state, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0093] 6C is a circuit diagram of a pixel circuit 10 according to the third example. As shown in FIG. 6C, the pixel circuit 10 according to the third example includes NMOS transistors Q11 to Q14 and a capacitor C11. The gate of transistor Q11 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor Q12. The drain of transistor Q12 is connected to the source of transistor Q13. The gate of transistor Q13 is connected to a control line DSL, and the drain is connected to a power supply line VCCP. The source of transistor Q12 is connected to the anode of the light-emitting element EL and the drain of transistor Q14. The source of transistor Q14 is connected to the power supply line VSS, and the gate is connected to a control line AZSL.

[0094] When the transistor Q13 is turned on, the voltage across the capacitor C11 is set based on the pixel signal supplied from the signal line SGL. The transistor Q13 is turned on and off based on the signal on the control line DSL. While the transistor Q13 is on, the transistor Q12 passes a current corresponding to the voltage across the capacitor C11 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor Q12. In this way, the pixel PX emits light at a luminance corresponding to the pixel signal. The transistor Q14 is turned on and off based on the signal on the control line AZSL. While the transistor Q14 is on, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0095] FIG. 6D is a circuit diagram of a pixel circuit 10 according to a fourth example. As shown in FIG. 6D, the pixel circuit 10 according to the fourth example includes PMOS transistors Q11, Q12, Q14, Q15, and Q16, and a capacitor C13. The gate of transistor Q11 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor Q12 and the source of transistor Q15. The source of transistor Q12 is connected to a power supply line VCCP, and its drain is connected to the drain of transistor Q15 and the source of transistor Q16. Capacitor C13 is connected between the gate of transistor Q12 and the power supply line VCCP. The gate of transistor Q15 is connected to a control line AXSL1. The gate of transistor Q16 is connected to a control line DSL, and its drain is connected to the anode of the light-emitting element EL and the source of transistor Q14. The gate of transistor Q14 is connected to a control line AZSL2, and its drain is connected to the power supply line VSS.

[0096] When transistor Q11 is turned on, the voltage across capacitor C13 is set based on the pixel signal supplied from signal line SGL. Transistor Q16 is turned on and off based on the signal on control line DSL. While transistor Q16 is on, transistor Q12 passes a current corresponding to the voltage across capacitor C13 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor Q12. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistor Q15 is turned on and off based on the signal on control line AZSL1. While transistor Q15 is on, the drain and gate of transistor Q12 are connected to each other. Transistor Q14 is turned on and off based on the signal on control line AZSL2. While transistor Q14 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0097] 6E is a circuit diagram of a pixel circuit 10 according to a fifth example. The pixel circuit 10 according to the fifth example includes PMOS transistors Q11, Q13, Q14, Q15, Q16, and Q17, and capacitors C13, C14, and C15. The gate of transistor Q11 is connected to a control line WSL1, its source is connected to a signal line SGL2, and its drain is connected to the gate of transistor Q13. The source of transistor Q13 is connected to a power supply line VCCP, and its drain is connected to the drain of transistor Q15 and the source of transistor Q16. Capacitor C13 is connected between the gate of transistor Q13 and the power supply line VCCP. The gate of transistor Q15 is connected to a control line AZSL1. Capacitors C14 and C15 are connected in series between the source of transistor Q15 and the power supply line VSS. The gate of transistor Q16 is connected to a control line DSL, and its drain is connected to the anode of the light-emitting element EL and the source of transistor Q14. The gate of the transistor Q14 is connected to the control line AZSL2, and the drain is connected to the power supply line VSS.

[0098] When transistor Q11 is turned on, the voltage across capacitor C13 is set based on the pixel signal supplied from signal line SGL1 via capacitor C14. Transistor Q16 is turned on and off based on the signal on control line DSL. While transistor Q16 is on, transistor Q13 passes a current corresponding to the voltage across capacitor C13 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor Q13. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistor Q15 is turned on and off based on the signal on control line AZSL1. While transistor Q15 is on, the drain of transistor Q13 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor Q16 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0099] 6F is a circuit diagram of a pixel circuit 10 according to a sixth example. The pixel circuit 10 according to the sixth example is disposed between a first control unit 40 and a second control unit 41. The first control unit 40 and the second control unit 41 are shared by a plurality of pixels PX in the pixel array unit 11.

[0100] The pixel circuit 10 of each pixel PX includes PMOS transistors Q11, Q15, Q16, and Q18, and a capacitor C13. The gate of the PMOS transistor Q11 is connected to a control line WSL, its source is connected to a signal line 43, and its drain is connected to the gate of transistor Q13. The capacitor C13 is connected between the gate of transistor Q13 and a power supply line Vel. The drain of transistor Q13 is connected to the drain of transistor Q15 and the source of transistor Q16. The source of transistor Q15 is connected to the signal line 43. The gate of transistor Q16 is connected to a control line DSL, and its drain is connected to the anode of the display element EL and the drain of transistor Q18. The gate of transistor Q18 is connected to the gate of transistor Q15 and control line AZSL. The source of transistor Q18 is connected to the power supply line Vorst.

[0101] The first control unit 40 has transfer gates TG11 and TG12, PMOS transistors Q19 and Q20, and a capacitor C16. The transfer gate TG11 switches whether or not a pixel signal is transmitted to a signal line 42. The transfer gate TG12 switches whether or not a signal line 43 is connected to the source of transistor Q18. The gate of transistor Q19 is connected to a control line INIL, its source is connected to a power supply line Vini, and its drain is connected to the signal line 43. The gate of transistor Q20 is connected to a control line ELL, its source is connected to a power supply line Vel, and its drain is connected to the signal line 43.

[0102] The second control unit 41 has a transfer gate TG13, a PMOS transistor Q21, and a capacitor C17. The transfer gate TG13 switches whether or not the signal line 42 is connected to one end of the capacitor C17. The gate of the transistor Q21 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to one end of the capacitor C17. The other end of the capacitor C17 is connected to the signal line 43.

[0103] When transistor Q11 is turned on, the voltage across capacitor C13 is set based on the pixel signal supplied via transmission gate TG11, signal line 42, transmission gate TG13, capacitor C17, and signal line 43. Transistor Q16 is turned on and off based on the signal on control line DSL. While transistor Q16 is on, transistor Q13 passes a current corresponding to the voltage across capacitor C13 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor Q13. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistors Q15 and Q18 are turned on and off based on the signal on control line AZSL. While transistor Q15 is on, the drain of transistor Q13 and the source of transistor Q16 are connected to signal line 43. While transistor Q18 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor Q19 is turned on and off based on the signal on control line INIL, transistor Q20 is turned on and off based on the signal on control line ELL, and transistor Q21 is turned on and off based on the signal on control line REFL. When transistor Q19 is turned on, signal line 43 is set to the voltage of power supply line Vini, and when transistor Q20 is turned on, signal line 43 is set to the voltage of power supply line Vel. When transistor Q21 is turned on, one end of capacitor C17 is initialized by being set to the voltage of power supply line Vref.

[0104] FIG. 6G is a circuit diagram of a pixel circuit 10 according to a seventh example. The pixel circuit 10 according to the seventh example includes PMOS transistors Q11, Q13, Q14, Q16, Q22, Q23, Q24, Q24, and Q26, and a capacitor C18. The gate of transistor Q11 is connected to a control line WSL, its source is connected to a control line SGL, and its drain is connected to the drain of transistor Q13 and the source of transistor Q22. The source of transistor Q13 is connected to a power supply line VCCP, and its gate is connected to a control line DSL. The gate of transistor Q22 is connected to the sources of transistors Q23, Q25, and one end of capacitor C18. The other end of capacitor C18 is connected to power supply line VCCP. The drain of transistor Q22 is connected to the source of transistor Q16 and the drain of transistor Q26. The drain of transistor Q23 is connected to the source of transistor Q24. The gates of transistors Q23 and Q24 are connected to a control line AZSL1. The drain of transistor Q24 is connected to the power supply line VSS. The gates of transistors Q25 and Q26 are connected to the control line WSL. The drain of transistor Q16 is connected to the anode of the light-emitting element EL and the source of transistor Q14. The gate of transistor Q14 is connected to the control line AZSL2, and the drain is connected to the power supply line VSS.

[0105] When transistors Q11, Q22, Q26, and Q25 are turned on, the voltage across capacitor C18 is set based on the pixel signal supplied from signal line SGL. Transistors Q13 and Q16 are turned on and off based on the signal on control line DSL. While transistors Q13 and Q16 are on, transistor Q22 passes a current corresponding to the voltage across capacitor C18 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor Q22. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistors Q23 and Q24 are turned on and off based on the signal on control line AZSL1. While transistors Q23 and Q24 are on, the gate voltage of transistor Q22 is initialized by being set to the voltage of power supply line VSS. Transistor Q14 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor Q14 is in the on state, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0106] FIG. 6H is a circuit diagram of a pixel circuit 10 according to an eighth example. The pixel circuit 10 according to the eighth example includes NMOS transistors Q13, Q14, and Q16, capacitors C19 and C20, and a transfer gate TG14. The transfer gate TG14 includes an NMOS transistor Q27 and a PMOS transistor Q28 connected in parallel. The transfer gate TG14 switches between connecting and disconnecting the control line SGL and the gate of transistor Q13. One end of each of capacitors C19 and C20 is connected to the gate of transistor Q13, and the other end is connected to a power supply line VSS2. The drain of transistor Q13 is connected to a power supply line VCCP, and the source is connected to the drains of transistors Q14 and Q16. The gate of transistor Q14 is connected to a control line AZL, and the source is connected to a power supply line VSS1. The gate of transistor Q16 is connected to a control line DSL, and the source is connected to the anode of the light-emitting element EL. The gate of the transistor Q27 constituting the transfer gate TG14 is connected to a control line WSNL, and the gate of the transistor Q28 is connected to a control line WSPL.

[0107] When at least one of transistors Q27 and Q28 is turned on, the voltage across capacitors C19 and C20 is set based on the pixel signal supplied from signal line SGL. Transistor Q16 is turned on and off based on the signal on control line DSL. While transistor Q16 is on, transistor Q13 passes a current corresponding to the voltage across capacitors C19 and C20 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor Q13. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor Q14 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors Q13 and Q14 form a so-called source follower circuit.

[0108] The pixel circuits 10 according to the first to eighth examples shown in Figures 6A to 6H are representative examples of pixel circuits 10 according to the present disclosure, and the display device 1 according to the present disclosure can be applied to pixel circuits 10 having circuit configurations other than those shown in Figures 6A to 6H.

[0109] In this manner, in this embodiment, when each pixel row is scanned in sequence to display the display area, at least one of the light emission pattern and the light emission duty is made different in two or more consecutive display frames, so that it is possible to suppress a decrease in brightness around the image displayed in the display area and improve display quality. Although the light emission pattern in which a decrease in brightness is more noticeable varies depending on the shape and size of the image displayed in the display area, by, for example, switching the light emission pattern for each display frame, it is possible to suppress a decrease in brightness around the image, regardless of the shape and size of the image.

[0110] (Application examples of the display device 1 and electronic device according to the present disclosure) (First application example) The display device 1 and electronic device 50 according to the present disclosure can be used for various purposes. Figures 7A and 7B are diagrams showing the internal configuration of a vehicle 100, which is a first application example of an electronic device 50 equipped with a display device 1 according to the present disclosure. Figure 7A is a diagram showing the interior of the vehicle 100 from the rear to the front of the vehicle 100, and Figure 7B is a diagram showing the interior of the vehicle 100 from diagonally rear to diagonally front of the vehicle 100.

[0111] The vehicle 100 of FIGS. 7A and 7B includes a center display 101, a console display 102, a head-up display 103, a digital rearview mirror 104, a steering wheel display 105, and a rear entertainment display 106.

[0112] The center display 101 is disposed on the dashboard 107 in a position facing the driver's seat 108 and the passenger's seat 109. FIG. 7 shows an example of a horizontally elongated center display 101 extending from the driver's seat 108 to the passenger's seat 109, but the screen size and location of the center display 101 are arbitrary. The center display 101 can display information detected by various sensors. As a specific example, the center display 101 can display an image captured by an image sensor, a distance image to obstacles in front of or on the side of the vehicle measured by a ToF sensor, and the body temperature of a passenger detected by an infrared sensor. The center display 101 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0113] The safety-related information includes information such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger has been abandoned. For example, this information is detected by a sensor disposed on the rear side of the center display 101. The operation-related information is obtained by detecting gestures related to passenger operations using a sensor. The detected gestures may include operations of various equipment within the vehicle 100. For example, operations of the air conditioning system, navigation system, AV system, lighting system, etc. are detected. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior while on board. By acquiring and storing the life log, the condition of the passenger at the time of the accident can be confirmed. The health-related information is obtained by detecting the passenger's body temperature using a temperature sensor and inferring the passenger's health condition based on the detected body temperature. Alternatively, the passenger's face may be captured using an image sensor and the passenger's health condition may be inferred from the facial expression captured in the image. Furthermore, the passenger may be spoken to by an automated voice and the passenger's health condition may be inferred based on the passenger's responses. The authentication / identification-related information includes a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes a function that uses a sensor to detect operation information of an AV device by an occupant, a function that recognizes the occupant's face with a sensor and provides content suitable for the occupant via the AV device, etc.

[0114] The console display 102 can be used to display, for example, life log information. The console display 102 is disposed near a shift lever 111 on a center console 110 between a driver's seat 108 and a passenger seat 109. Information detected by various sensors can also be displayed on the console display 102. In addition, the console display 102 may display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0115] The head-up display 103 is virtually displayed behind the windshield 112 in front of the driver's seat 108. The head-up display 103 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 103 is often virtually located in front of the driver's seat 108, it is suitable for displaying information directly related to the operation of the vehicle 100, such as the speed of the vehicle 100 and the remaining fuel (battery) level.

[0116] The digital rearview mirror 104 can not only display the rear of the vehicle 100 but also display the status of passengers in the rear seats. Therefore, by placing a sensor on the back side of the digital rearview mirror 104, it can be used to display life log information, for example.

[0117] The steering wheel display 105 is disposed near the center of the steering wheel 113 of the vehicle 100. The steering wheel display 105 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 105 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information regarding the operation of AV equipment, air conditioning equipment, etc.

[0118] The rear entertainment display 106 is attached to the back side of the driver's seat 108 and the passenger seat 109 and is intended for viewing by rear seat passengers. The rear entertainment display 106 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 106 is located directly in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 106. For example, the rear entertainment display 106 may display information related to the operation of an AV device or an air conditioning system, or may display the results of measurements such as the body temperature of the rear seat passengers using a temperature sensor.

[0119] As described above, by arranging a sensor on the rear side of the display device 1, the distance to surrounding objects can be measured. Optical distance measurement methods are broadly divided into passive and active types. Passive types measure distance by receiving light from an object without projecting light from the sensor onto the object. Passive types include the lens focusing method, the stereo method, and the monocular vision method. Active types measure distance by projecting light onto an object and receiving reflected light from the object with a sensor. Active types include the optical radar method, the active stereo method, the photometric stereo method, the moire topography method, and the interferometry method. The display device 1 according to the present disclosure can be applied to any of these distance measurement methods. By using a sensor arranged on the rear side of the display device 1 according to the present disclosure, the above-mentioned passive or active distance measurement can be performed.

[0120] Second Application Example The display device 1 according to the present disclosure is not only applicable to various displays used in vehicles, but also to displays mounted on various electronic devices 50 .

[0121] Fig. 8A is a front view of a digital camera 120 that is a second application example of electronic device 50, and Fig. 8B is a rear view of digital camera 120. Digital camera 120 in Fig. 8A and Fig. 8B shows an example of a single-lens reflex camera with an interchangeable lens 121, but the present invention is also applicable to cameras in which lens 121 is not interchangeable.

[0122] 8A and 8B, when the photographer holds the grip 123 of the camera body 122, looks through the electronic viewfinder 124, decides on the composition of the shot, adjusts the focus, and presses the shutter 125, the photographed data is saved in the camera's internal memory. As shown in Fig. 8B, the rear side of the camera is provided with a monitor screen 126 that displays photographed data, live images, etc., and the electronic viewfinder 124. In addition, a sub-screen that displays setting information such as shutter speed and exposure value may be provided on the top surface of the camera.

[0123] By arranging a sensor on the back side of a monitor screen 126, an electronic viewfinder 124, a sub-screen, or the like used in a camera, it can be used as a display device 1 according to the present disclosure.

[0124] (Third Application Example) The display device 1 according to the present disclosure can also be applied to a head-mounted display (hereinafter referred to as an HMD). The HMD can be used for virtual reality (VR), augmented reality (AR), mixed reality (MR), substitutional reality (SR), or the like.

[0125] Fig. 9A is an external view of an HMD 130, which is a third application example of the electronic device 50. The HMD 130 in Fig. 9A has a mounting member 131 for being worn over a person's eyes. This mounting member 131 is secured by hooking it onto a person's ear, for example. A display device 132 is provided inside the HMD 130, and the wearer of the HMD 130 can view a 3D image or the like on this display device 132. The HMD 130 is equipped with, for example, a wireless communication function and an acceleration sensor, and can switch the 3D image or the like displayed on the display device 132 depending on the posture, gestures, etc. of the wearer.

[0126] Alternatively, a camera may be provided in the HMD 130 to capture an image of the wearer's surroundings, and an image obtained by combining the image captured by the camera with an image generated by a computer may be displayed on the display device 132. For example, a camera may be placed on the back side of the display device 132 that is viewed by the wearer of the HMD 130, and the camera may capture an image of the area around the wearer's eyes. The captured image may then be displayed on another display provided on the outer surface of the HMD 130, allowing people around the wearer to grasp the wearer's facial expressions and eye movements in real time.

[0127] Various types of HMD 130 are possible. For example, as shown in FIG. 9B , the display device 1 according to the present disclosure can also be applied to smart glasses 130a that display various information on glasses 134. The smart glasses 130a in FIG. 9B include a main body 135, an arm 136, and a lens barrel 137. The main body 135 is connected to the arm 136. The main body 135 is detachable from the glasses 134. The main body 135 incorporates a control board and a display unit for controlling the operation of the smart glasses 130a. The main body 135 and the lens barrel 137 are connected to each other via the arm 136. The lens barrel 137 emits image light emitted from the main body 135 via the arm 136 toward the lenses 138 of the glasses 134. This image light enters the human eye through the lens 138. A wearer of the smart glasses 130a in FIG. 9B can visually recognize not only the surrounding situation but also various pieces of information emitted from the lens barrel portion 137, just like with regular glasses.

[0128] (Fourth Application Example) The display device 1 according to the present disclosure can also be applied to a television device (hereinafter referred to as a TV). Recent TVs tend to have as small a frame as possible from the viewpoints of miniaturization and design. For this reason, when a camera for photographing viewers is installed in a TV, it is desirable to place the camera on the back side of the TV's display panel.

[0129] Fig. 10 is an external view of a TV 140, which is a fourth application example of electronic device 50. The TV 140 in Fig. 10 has a minimized frame, and almost the entire front side is the display area. The TV 140 may have a built-in sensor such as a camera for capturing images of viewers.

[0130] (Fifth Application Example) The display device 1 according to the present disclosure can also be applied to smartphones and mobile phones. FIG. 11 is an external view of a smartphone 150, which is a fifth application example of the electronic device 50. In the example of FIG. 11 , the display surface 1z extends to nearly the outer size of the electronic device 50, and the width of the bezel 1y surrounding the display surface 1z is set to a few millimeters or less. Typically, a front camera is mounted on the bezel 1y. However, in FIG. 11 , as shown by the dashed line, an image sensor module functioning as a front camera is disposed on the rear side of the display surface 1z, for example, in the approximate center thereof. By providing the front camera on the rear side of the display surface 1z in this manner, there is no need to place the front camera in the bezel 1y, and the width of the bezel 1y can be narrowed.

[0131] The present technology can be configured as follows:

[0132] (1) A display device comprising: a pixel array unit having a plurality of pixels arranged in a first direction and a second direction that intersect with each other; a pixel group drive circuit that sequentially drives a plurality of pixel groups arranged along the second direction, with each pixel group including two or more of the pixels arranged along the second direction as a unit; and a gradation signal supply circuit that supplies a signal voltage corresponding to a gradation signal to the two or more pixels belonging to the pixel group in synchronization with driving by the pixel group drive circuit, wherein each of the plurality of pixels has a self-luminous element that emits light at a luminance corresponding to the gradation signal, and the pixel group drive circuit controls the emission start timing and extinction timing of the plurality of pixels so that at least one of the emission pattern or the emission duty differs in each of two or more consecutive display frames. (2) The display device according to (1), wherein the pixel group drive circuit controls the emission start timing and extinction timing of the plurality of pixels so that a plurality of emission forms, each differing in at least one of the emission pattern or the emission duty, are selected in sequence or randomly for each display frame. (3) The display device according to (2), wherein the pixel group drive circuit controls the emission start timing and the extinction timing of the plurality of pixels so that the light emission duty is the same for each display frame and the plurality of different light emission patterns are selected in sequence or randomly. (4) The display device according to (3), wherein the pixel group drive circuit controls the light emission duty for each display frame and makes the light emission pattern different for each of two or more adjacent display frames. (5) The display device according to (3) or (4), wherein the different light emission patterns differ in at least one of the number or arrangement location of the pixel groups that emit light simultaneously, and the different light emission duties differ in the proportion of the number of pixel groups that emit light simultaneously out of the total number of the plurality of pixel groups arranged along the second direction. (6) The display device according to any one of (3) to (5), wherein the light emission pattern moves from a first end to a second end in the second direction in synchronization with the pixel group drive circuit sequentially driving the plurality of pixel groups for each display frame.(7) The display device according to any one of (3) to (6), wherein areas in the second direction of the light emission patterns in two or more consecutive display frames are different from each other. (8) The display device according to any one of (3) to (7), wherein at least some of the light emission patterns selected in a cyclic or random manner include the pixel groups that emit light and the pixel groups that do not emit light. (9) The display device according to (8), wherein at least two or more of the light emission patterns selected in a cyclic or random manner have a first pixel block to be light-emitted, a second pixel block to be non-light-emitted, and a third pixel block to be light-emitted that are arranged adjacent to each other in the second direction, the second pixel block being arranged between the first pixel block and the third pixel block, and the width in the second direction of the second pixel block is different for each of the at least two or more light emission patterns. (10) The display device according to (9), wherein each of the first pixel block, the second pixel block, and the third pixel block has the same width as the pixel group in the first direction and the same width as one or more of the pixel groups in the second direction. (11) The display device according to (9) or (10), wherein the widths of the first pixel block and the third pixel block in the second direction are equal. (12) The display device according to any one of (1) to (11), wherein the first direction is a horizontal direction of a display area, the second direction is a vertical direction of the display area, the pixel group is a pixel row extending in the horizontal direction of the display area and corresponding to one vertical row, and the pixel group drive circuit changes at least one of the light emission pattern or the light emission duty in each of two or more consecutive display frames. (13) The display device according to any one of (1) to (12), wherein the pixel group drive circuit changes at least one of the light emission pattern or the light emission duty for each display frame when the light emission duty is equal to or less than a predetermined value.(14) The display device according to any one of (1) to (13), wherein the pixel group drive circuit, when setting a luminance of a first partial region arranged inside both end portions in the first direction higher than a luminance of a second partial region arranged on both end sides of the first partial region in the first direction, makes at least one of the light emission pattern or the light emission duty different in each of two or more consecutive display frames. (15) The display device according to any one of (1) to (14), wherein the self-luminous elements are organic electroluminescence (EL) elements. (16) A display method comprising: in a pixel array unit having a plurality of pixels arranged in a first direction and a second direction intersecting each other, sequentially driving a plurality of pixel groups arranged along the second direction, each pixel group including two or more of the pixels arranged along the second direction; supplying a signal voltage corresponding to a gradation signal to the two or more pixels belonging to the pixel group in synchronization with the driving of the plurality of pixel groups; causing a self-luminous element provided in each of the plurality of pixels to emit light at a luminance corresponding to the gradation signal; and controlling light emission start timing and light extinction timing of the plurality of pixels so that at least one of a light emission pattern or a light emission duty in each of two or more consecutive display frames is different.

[0133] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0134] 1 Display device, 1y Bezel, 1z Display surface, 2 Host device, 3 Display system, 4 Display unit, 5 Display controller, 6 Timing controller, 7 I / F unit, 10 Pixel circuit, 11 Pixel array unit, 12 Gate driver, 12a V-Logic unit, 12b V-Analog unit, 13 Source driver, 13a H-Logic unit, 13b H-Analog unit, 20 Light emitting duty, 20H Pixel row, 21 Clock generator, 22 Timing generator, 23 Image processing unit, 25 Image I / F unit, 26 Clock control unit, 27 H / V synchronization unit, 28 Data S / P conversion unit, 40 First control unit, 41 Second control unit, 42 Signal line, 43 Signal line, 50 Electronic device, 100 Vehicle, 101 Center display, 102 Console display, 103 Head-up display, 104 Digital rearview mirror, 105 Steering wheel display, 106 Rear entertainment display, 107 Dashboard, 108 Driver's seat, 109 Passenger seat, 110 Center console, 111 Shift lever, 112 Windshield, 113 Steering wheel, 120 Digital camera, 121 Lens, 122 Camera body, 123 Grip, 124 Electronic viewfinder, 125 Shutter, 126 Monitor screen, 130a Smart glasses, 131 Mounting member, 132 Display device, 134 Glasses, 135 Main body, 136 Arm, 137 Lens barrel, 138 Lens, 150 Smartphone

Claims

1. A display device comprising: a pixel array section having a plurality of pixels arranged in a first direction and a second direction which intersect with each other; a pixel group drive circuit which sequentially drives a plurality of pixel groups arranged along the second direction, each pixel group including two or more of the pixels arranged along the second direction; and a gradation signal supply circuit which supplies a signal voltage corresponding to a gradation signal to the two or more pixels belonging to the pixel group in synchronization with driving by the pixel group drive circuit, wherein each of the plurality of pixels has a self-luminous element which emits light at a luminance corresponding to the gradation signal, and the pixel group drive circuit controls the emission start timing and the extinction timing of the plurality of pixels so that at least one of the emission pattern or the emission duty in each of two or more consecutive display frames is different.

2. The display device according to claim 1, wherein the pixel group drive circuit controls the emission start timing and extinction timing of the plurality of pixels so that a plurality of emission forms, each differing in at least one of the emission pattern and the emission duty, are selected in sequence or randomly for each display frame.

3. The display device according to claim 2, wherein the pixel group drive circuit controls the emission start timing and extinction timing of the plurality of pixels so that the light emission duty is the same for each display frame and the plurality of different light emission patterns are selected in sequence or randomly.

4. The display device according to claim 3, wherein said pixel group drive circuit makes said light emission duty the same for each display frame, and makes said light emission pattern different for each of two or more adjacent display frames.

5. The display device described in claim 3, wherein the different emission patterns differ in at least one of the number or location of the pixel groups that emit light simultaneously, and the different emission duties differ in the proportion of the number of pixel groups that emit light simultaneously out of the total number of the plurality of pixel groups arranged along the second direction.

6. The display device according to claim 3, wherein the light emission pattern moves from a first end to a second end in the second direction in synchronization with the pixel group drive circuit sequentially driving the plurality of pixel groups for each display frame.

7. The display device according to claim 3, wherein the areas of the light-emitting patterns in the second direction in two or more consecutive display frames are different from each other.

8. The display device according to claim 3, wherein at least some of the plurality of light emission patterns selected in sequence or randomly include the pixel groups that emit light and the pixel groups that do not emit light.

9. The display device of claim 8, wherein at least two of the plurality of emission patterns selected in sequence or randomly have a first pixel block to be illuminated, a second pixel block to be not illuminated, and a third pixel block to be illuminated, which are arranged adjacent to each other in the second direction, the second pixel block being arranged between the first pixel block and the third pixel block, and the width of the second pixel block in the second direction differs for each of the at least two emission patterns.

10. The display device of claim 9, wherein each of the first pixel block, the second pixel block, and the third pixel block has the same width as the pixel group in the first direction and the width of one or more of the pixel groups in the second direction.

11. The display device according to claim 9, wherein the first pixel block and the third pixel block have the same width in the second direction.

12. The display device of claim 1, wherein the first direction is a horizontal direction of a display area, the second direction is a vertical direction of the display area, the pixel group extends in the horizontal direction of the display area and is one vertical row of pixels, and the pixel group drive circuit makes at least one of the light emission pattern or the light emission duty different in each of two or more consecutive display frames.

13. The display device according to claim 1, wherein said pixel group drive circuit changes at least one of said light emission pattern or said light emission duty for each display frame when said light emission duty is equal to or less than a predetermined value.

14. The display device according to claim 1, wherein the pixel group driving circuit, when making the luminance of a first partial region arranged inside both ends in the first direction higher than the luminance of a second partial region arranged on both end sides of the first direction relative to the first partial region, makes at least one of the emission pattern or the emission duty different in each of two or more consecutive display frames.

15. The display device according to claim 1, wherein the self-luminous element is an organic EL (Electroluminescence) element.

16. A display method comprising the steps of: in a pixel array section having a plurality of pixels arranged in a first direction and a second direction intersecting each other, sequentially driving a plurality of pixel groups arranged along the second direction, each pixel group including two or more of the pixels arranged along the second direction; supplying a signal voltage corresponding to a gradation signal to the two or more pixels belonging to the pixel group in synchronization with the driving of the plurality of pixel groups; causing self-luminous elements provided in each of the plurality of pixels to emit light at a luminance corresponding to the gradation signal; and controlling the emission start timing and extinction timing of the plurality of pixels so that at least one of the emission pattern or the emission duty in each of two or more consecutive display frames is different.

Images