Multilayer ceramic capacitor, production method for multilayer ceramic capacitor, and production method for mounting structure for multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor (1) according to the present invention comprises a capacitor body (10), a first external electrode (20A), and a second external electrode (20B). A first principal surface (101) is on one side in the layering direction (DS) of the capacitor body (10). The first external electrode (20A) includes a first base electrode layer (21A) and a first surface electrode layer (22A). The first base electrode layer (21A) is provided on the first surface (101) so as to cover a first via conductor (13A). The first surface electrode layer (22A) directly covers the first base electrode layer (21A). The second external electrode (20B) is provided on the first principal surface (101) at a gap from the first external electrode (20A) so as to cover a second via conductor (13B). An outer surface (221A) of the first surface electrode layer (22A) extends away from the first principal surface (101) from an end edge (21AE) of the first base electrode layer (21A) on the first principal surface (101).

Description

Multilayer ceramic capacitor, method for manufacturing multilayer ceramic capacitor, and method for manufacturing mounting structure of multilayer ceramic capacitor

[0001] The present invention relates to a multilayer ceramic capacitor, a method for manufacturing a multilayer ceramic capacitor, and a method for manufacturing a mounting structure of a multilayer ceramic capacitor.

[0002] 2. Description of the Related Art Multilayer ceramic capacitors are known that include a plurality of via conductors and a plurality of external terminals electrically connected to the via conductors, respectively.

[0003] For example, the multilayer capacitor disclosed in Japanese Patent Laid-Open No. 7-201651 (Patent Document 1) is characterized in that external electrodes are formed on at least a portion of each of the front and rear main surfaces of a laminate consisting of a dielectric and internal electrodes, the internal electrodes and external electrodes of the same polarity are connected to each other by a plurality of columnar connecting members, and the columnar connecting members (via conductors) are arranged at locations where magnetic fields caused by currents flowing through the internal electrodes cancel each other out.

[0004] For example, Japanese Patent Laid-Open Publication No. 2006-135333 (Patent Document 2) discloses a multilayer capacitor array including a capacitor body, first and second internal electrodes arranged alternately and facing each other with laminated dielectric layers sandwiched therebetween, first and second external terminals formed on at least one of the upper and lower surfaces of the body, and first and second conductive via holes formed in the stacking direction of the body and connected to the first and second external terminals, respectively.

[0005] Japanese Patent Application Laid-Open No. 7-201651 Japanese Patent Application Laid-Open No. 2006-135333

[0006] The multilayer ceramic capacitors described in Patent Documents 1 and 2 are said to be capable of reducing equivalent series inductance (ESL). However, there is room for further improvement in reducing the ESL of such multilayer ceramic capacitors.

[0007] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a multilayer ceramic capacitor, a method for manufacturing a multilayer ceramic capacitor, and a method for manufacturing a mounting structure of a multilayer ceramic capacitor, which can further reduce the equivalent series inductance (ESL) of the multilayer ceramic capacitor.

[0008] A multilayer ceramic capacitor according to one aspect of the present invention includes a capacitor body, a first external electrode, and a second external electrode. The capacitor body includes a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor. The plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in the stacking direction with the dielectric layer sandwiched between them. The first via conductor is electrically connected to the plurality of first internal electrode layers. The first via conductor extends from the interior of the capacitor body to the first main surface. The first main surface is one side of the capacitor body in the stacking direction. The second via conductor is electrically connected to the plurality of second internal electrode layers. The second via conductor extends from the interior of the capacitor body to the first main surface. The first external electrode includes a first base electrode layer and a first surface electrode layer. The first base electrode layer is provided on the first main surface so as to cover the first via conductor. The first surface electrode layer directly covers the first base electrode layer. The second external electrode is provided on the first principal surface at a distance from the first external electrode so as to cover the second via conductor, and the outer surface of the first surface electrode layer extends from an edge of the first base electrode layer on the first principal surface so as to be away from the first principal surface.

[0009] A method for manufacturing a multilayer ceramic capacitor according to another aspect of the present invention includes: preparing a capacitor body including a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the dielectric layer sandwiched between them, the first via conductor is electrically connected to the plurality of first internal electrode layers and extends from the interior of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction, and the second via conductor is electrically connected to the plurality of second internal electrode layers and extends from the interior of the capacitor body to the first main surface; providing a first external electrode including a first base electrode layer provided on the first main surface so as to cover the first via conductor and a first surface electrode layer directly covering the first base electrode layer; and providing a second external electrode on the first main surface at a distance from the first external electrode so as to cover the second via conductor. Providing the first external electrode includes forming a first base electrode layer, forming a first plating layer on the first base electrode layer by plating, heating and melting the first plating layer, and cooling the heated and melted first plating layer to form a first surface electrode layer.

[0010] A multilayer ceramic capacitor according to another aspect of the present invention includes a capacitor body, a first external electrode, and a second external electrode. The capacitor body includes a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor. The plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in the stacking direction with the dielectric layer sandwiched between them. The first via conductor is electrically connected to the plurality of first internal electrode layers and extends from the interior of the capacitor body to the first main surface. The first main surface is one side of the capacitor body in the stacking direction. The second via conductor is electrically connected to the plurality of second internal electrode layers. The second via conductor extends from the interior of the capacitor body to the first main surface. The first external electrode is provided on the first main surface to cover the first via conductor. The second external electrode is provided on the first main surface at a distance from the first external electrode to cover the second via conductor. The outer surface of the first external electrode extends away from the edge of the first via conductor on the first principal surface.

[0011] A method for manufacturing a multilayer ceramic capacitor according to another aspect of the present invention includes preparing a capacitor body including a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in the stacking direction with the dielectric layer sandwiched between them, the first via conductor is electrically connected to the plurality of first internal electrode layers and extends from the interior of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction, and the second via conductor is electrically connected to the plurality of second internal electrode layers and extends from the interior of the capacitor body to the first main surface; providing a first external electrode on the first main surface to cover the first via conductor; and providing a second external electrode on the first main surface at a distance from the first external electrode to cover the second via conductor. Providing the first external electrode includes forming a first plating layer 30 by plating on the first via conductor on the first main surface, heating and melting the first plating layer, and cooling the heated and melted first plating layer to form the first external electrode.

[0012] According to the present invention, the equivalent series inductance (ESL) of the multilayer ceramic capacitor can be further reduced.

[0013] 1 is a cross-sectional view showing a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 as viewed in the direction of the arrows along line II-II. FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 as viewed in the direction of the arrows along line III-III. FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 as viewed in the direction of the arrows along line IV-IV. FIG. 2 is a partial cross-sectional view showing a first external electrode and its periphery of the multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a partial cross-sectional view showing a first external electrode and its periphery of the multilayer ceramic capacitor according to a first modified example. FIG. 4 is a partial cross-sectional view showing a first external electrode and its periphery of the multilayer ceramic capacitor according to a second modified example. FIG. 5 is a partial cross-sectional view showing a first external electrode and its periphery of the multilayer ceramic capacitor according to a third modified example. FIG. 6 is a partial cross-sectional view showing a first external electrode and its periphery of the multilayer ceramic capacitor according to a fourth modified example. FIG. 7 is a cross-sectional view of a multilayer ceramic capacitor according to a fifth modified example, taken along a cross section passing through the first internal electrode layer. FIG. 8 is a cross-sectional view of a ceramic capacitor according to the fifth modified example, taken along a cross section passing through the second internal electrode layer. FIG. 9 is a cross-sectional view of a multilayer ceramic capacitor according to a sixth modified example, taken along a cross section passing through the first internal electrode layer. FIG. 10 is a cross-sectional view of a ceramic capacitor according to the sixth modified example, taken along a cross section passing through the second internal electrode layer. FIG. 11 is a flow diagram showing a method for manufacturing the multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 1 is a schematic cross-sectional view showing a state immediately after a first plating layer is formed in a manufacturing method of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a cross-sectional SEM image of a state immediately after a first plating layer is formed in an experimental example of manufacturing a ceramic capacitor according to a first embodiment of the present invention. FIG. 3 is a cross-sectional SEM photograph of a state after a first surface electrode layer is formed in an experimental example of manufacturing a ceramic capacitor according to a first embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing a state in which a multilayer ceramic capacitor according to a first embodiment of the present invention and an electronic component are prepared. FIG. 5 is a schematic cross-sectional view showing a mounting structure of the multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 6 is a cross-sectional view of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 7 is a cross-sectional view of a multilayer ceramic capacitor according to a third embodiment of the present invention. FIG. 8 is a cross-sectional view of a multilayer ceramic capacitor according to a fourth embodiment of the present invention.Fig. 1 is a partial cross-sectional view showing a first external electrode and its periphery of the multilayer ceramic capacitor according to embodiment 4 of the present invention. Fig. 2 is a flow diagram showing a method for manufacturing the multilayer ceramic capacitor according to embodiment 4 of the present invention. Fig. 3 is a schematic cross-sectional view showing a state immediately after a first plating layer is formed in the method for manufacturing the multilayer ceramic capacitor according to embodiment 4 of the present invention. Fig. 4 is a schematic cross-sectional view showing a state in which the multilayer ceramic capacitor according to embodiment 4 of the present invention and an electronic component are prepared. Fig. 5 is a schematic cross-sectional view showing a mounting structure of the multilayer ceramic capacitor according to embodiment 4 of the present invention.

[0014] Hereinafter, a multilayer ceramic capacitor, a method for manufacturing a multilayer ceramic capacitor, and a method for manufacturing a mounting structure of a multilayer ceramic capacitor according to each embodiment of the present disclosure will be described with reference to the drawings. In the following description of the embodiments, the same or corresponding parts in the drawings will be designated by the same reference numerals, and description thereof will not be repeated.

[0015] (Embodiment 1) [Multilayer Ceramic Capacitor] Fig. 1 is a cross-sectional view showing a multilayer ceramic capacitor according to embodiment 1 of the present invention. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1 as seen in the direction of the arrows II-II. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1 as seen in the direction of the arrows III-III. Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1 as seen in the direction of the arrows IV-IV.

[0016] As shown in FIGS. 1 to 4, the multilayer ceramic capacitor 1 includes a capacitor body 10, a first external electrode 20A, and a second external electrode 20B.

[0017] The capacitor body 10 may have any shape. In this embodiment, the capacitor body 10 has a rectangular parallelepiped shape as a whole. The rectangular parallelepiped shape as a whole refers to a shape that is not a perfect rectangular parallelepiped shape, such as a shape in which the corners and ridges of a rectangular parallelepiped are rounded, but has six surfaces and can be regarded as a rectangular parallelepiped as a whole.

[0018] The capacitor body 10 has a first main surface 101, a second main surface 102, and a peripheral side surface 103. The first main surface 101 is a surface on one side of the capacitor body 10 in the stacking direction DS. The second main surface 102 is a surface of the capacitor body 10 opposite to the first main surface 101. The first main surface 101 and the second main surface 102 may have a rectangular outer shape when viewed in the stacking direction DS. The peripheral side surface 103 connects the first main surface 101 and the second main surface 102.

[0019] The dimensions of the capacitor body 10 are arbitrary, but for example, when viewed from the first main surface 101 side, the vertical dimension of the rectangle can be 0.3 mm or more and 3.0 mm or less, the horizontal dimension can be 0.3 mm or more and 3.0 mm or less, and the dimension in the stacking direction DS can be 50 μm or more and 200 μm or less.

[0020] The capacitor body 10 includes a plurality of dielectric layers 11, a plurality of first internal electrode layers 12A, a plurality of second internal electrode layers 12B, a plurality of first via conductors 13A, and a plurality of second via conductors 13B.

[0021] The plurality of dielectric layers 11 include a first outer layer portion 111 and a second outer layer portion 112. The first outer layer portion 111 is the dielectric layer 11 located closest to the first main surface 101 among the plurality of dielectric layers 11. The first outer layer portion 111 forms a part of the first main surface 101. The second outer layer portion 112 is the dielectric layer 11 located closest to the second main surface 102 among the plurality of dielectric layers 11. The second outer layer portion 112 forms the entire second main surface 102. The entire peripheral side surface 103 is formed of the plurality of dielectric layers 11 including the first outer layer portion 111 and the second outer layer portion 112.

[0022] The dielectric layer 11 may be made of any material, and may be made of, for example, a ceramic material containing BaTiO3, CaTiO3, SrTiO3, SrZrO3, CaZrO3, etc. as a main component. A minor component selected from the group consisting of Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may be added to these main components in a smaller amount than the main component.

[0023] The plurality of first internal electrode layers 12A and the plurality of second internal electrode layers 12B are alternately stacked one layer at a time in the stacking direction DS with the dielectric layer 11 sandwiched therebetween. In the multilayer ceramic capacitor 1, the first internal electrode layers 12A and the second internal electrode layers 12B face each other via the dielectric layer 11, thereby forming a capacitance. By stacking the plurality of first internal electrode layers 12A and the plurality of second internal electrode layers 12B as described above, the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a high capacitance density in which a plurality of capacitor function sections are arranged side by side at high density.

[0024] In this embodiment, each of the first internal electrode layers 12A is integrally formed within the same layer (see FIG. 3). The first internal electrode layer 12A has a rectangular outer shape when viewed from the stacking direction DS. Each of the first internal electrode layers 12A has a plurality of first through holes 12Ah formed therein for inserting a plurality of second via conductors 13B therethrough.

[0025] In this embodiment, each of the second internal electrode layers 12B is integrally formed within the same layer (see FIG. 4). The second internal electrode layer 12B has substantially the same rectangular outer shape as the first internal electrode layer 12A when viewed from the stacking direction DS. A plurality of second through holes 12Bh are formed in each of the second internal electrode layers 12B to allow insertion of a plurality of first via conductors 13A (described later).

[0026] The material of the first internal electrode layer 12A and the second internal electrode layer 12B is arbitrary, and may contain, for example, a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing these metals, as a main component. The first internal electrode layer 12A and the second internal electrode layer 12B may contain, as a common material, the same ceramic material as the dielectric ceramic contained in the dielectric layer 11. In this case, the proportion of the common material contained in the first internal electrode layer 12A and the second internal electrode layer 12B is, for example, 20 vol % or less.

[0027] The thickness of each of the first internal electrode layers 12A and the second internal electrode layers 12B is arbitrary, but can be, for example, about 0.3 μm or more and 1.0 μm or less. The number of layers of the first internal electrode layers 12A and the second internal electrode layers 12B is arbitrary, but can be, for example, about 10 layers or more and 150 layers or less in total.

[0028] Each of the plurality of first via conductors 13A is electrically connected to at least one of the plurality of first internal electrode layers 12A. In this embodiment, each of the plurality of first via conductors 13A is electrically connected to each of the plurality of first internal electrode layers 12A.

[0029] The multiple first via conductors 13A extend from the inside of the capacitor body 10 to the first main surface 101. The multiple first via conductors 13A extend along the stacking direction DS. The first via conductors 13A are not exposed from the second main surface 102. The multiple first via conductors 13A pass through second through holes 12Bh formed in each of the multiple second internal electrode layers 12B. Therefore, the multiple first via conductors 13A are insulated from the multiple second internal electrode layers 12B.

[0030] Each of the plurality of second via conductors 13B is electrically connected to at least one of the plurality of second internal electrode layers 12B. In the present embodiment, each of the plurality of second via conductors 13B is electrically connected to each of the plurality of second internal electrode layers 12B.

[0031] The multiple second via conductors 13B extend from the inside of the capacitor body 10 to the first main surface 101. The multiple second via conductors 13B extend along the stacking direction DS. The second via conductors 13B are not exposed from the second main surface 102. The multiple second via conductors 13B pass through second through holes 12Bh formed in each of the multiple first internal electrode layers 12A. Therefore, the multiple second via conductors 13B are insulated from the multiple first internal electrode layers 12A.

[0032] The first and second via conductors 13A and 13B may have any shape, such as a cylindrical shape. In this case, the diameter of each of the first and second via conductors 13A and 13B is, for example, about 20 μm to 150 μm. The distance between adjacent first and second via conductors 13A and 13B, more specifically, the distance between the center of each first and second via conductor 13A and 13B, is, for example, about 50 μm to 500 μm.

[0033] The first via conductor 13A and the second via conductor 13B may be made of any material, such as a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing these metals. In this embodiment, the first via conductor 13A and the second via conductor 13B are preferably made of Ni or an alloy containing Ni.

[0034] 5 is a partial cross-sectional view showing a first external electrode and its periphery in the multilayer ceramic capacitor according to the first embodiment of the present invention. As shown in FIGS. 1 and 5, the plurality of first external electrodes 20A are provided on the first main surface 101 so as to cover the corresponding first via conductors 13A, respectively. More specifically, the plurality of first external electrodes 20A each cover the edge of the corresponding first via conductor 13A and the dielectric layer 11 (first outer layer portion 111) on the first main surface 101.

[0035] Each of the multiple first external electrodes 20A includes a first base electrode layer 21A and a first surface electrode layer 22A. The first base electrode layer 21A is provided on the first main surface 101 so as to cover the corresponding first via conductor 13A. Specifically, the first base electrode layer 21A covers the boundary between the corresponding first via conductor 13A and the dielectric layer 11 (first outer layer portion 111) on the first main surface 101.

[0036] The specific internal configuration of the first base electrode layer 21A is not particularly limited. In the present embodiment, the first base electrode layer 21A includes a baked electrode layer 211A and a first base plating layer 212A and a second base plating layer 213A as base plating layers.

[0037] The fired electrode layer 211A is provided on the first main surface 101 so as to directly cover the first via conductor 13A. Specifically, the fired electrode layer 211A covers the boundary between the corresponding first via conductor 13A and the dielectric layer 11 (first outer layer portion 111) on the first main surface 101. The fired electrode layer 211A preferably contains the same type of metal as the metal contained in the first via conductor 13A. In this embodiment, the material of the fired electrode layer 211A is preferably Ni or an alloy containing Ni. A ceramic material is further added to the fired electrode layer 211A as a co-material to improve the bonding strength with the dielectric layer 11.

[0038] The underplating layer covers the entire surface of the baked electrode layer 211A that is not in contact with the first main surface 101. Specifically, the first underplating layer 212A directly covers the entire surface of the baked electrode layer 211A that is not in contact with the first main surface 101. The second underplating layer 213A covers the side of the first underplating layer 212A opposite to the baked electrode layer 211A.

[0039] Examples of materials that can be used to form the underplating layer include Cu, Ni, and Au. In this embodiment, the first underplating layer 212A contains Cu, and the second underplating layer 213A contains Ni.

[0040] The shape of the first base electrode layer 21A when viewed in the stacking direction DS is not particularly limited. The shape of the first base electrode layer 21A when viewed in the stacking direction DS may be, for example, circular. If the shape of the first base electrode layer 21A when viewed in the stacking direction DS is circular, the shapes of the baked electrode layer 211A, the first base plating layer 212A, and the second base plating layer 213A when viewed in the stacking direction DS are also circular. Furthermore, the thickness of each of the baked electrode layer 211A, the first base plating layer 212A, and the second base plating layer 213A is, for example, 1 μm or more and 10 μm or less.

[0041] The first surface electrode layer 22A directly covers the first base electrode layer 21A. The first surface electrode layer 22A covers the entire portion of the first base electrode layer 21A that is not in contact with the first major surface 101.

[0042] An outer surface 221A of the first surface electrode layer 22A extends from an edge 21AE of the first base electrode layer 21A on the first main surface 101 so as to be away from the first main surface 101. The outer surface 221A of the first surface electrode layer 22A includes a first region 221Ap and a second region 221Aq in the stacking direction DS.

[0043] The first region 221Ap is in contact with the edge 21AE. The second region 221Aq is located on the opposite side of the first region 221Ap from the first main surface 101. The first region 221Ap extends such that the cross-sectional area of ​​the first external electrode 20A when viewed in the stacking direction DS increases with increasing distance from the first main surface 101. The second region 221Aq extends such that the cross-sectional area of ​​the first external electrode 20A when viewed in the stacking direction DS decreases with increasing distance from the first main surface 101.

[0044] More specifically, the outer surface 221A of the first surface electrode layer 22A extends in a substantially curved shape. When the first base electrode layer 21A has a circular shape when viewed from the stacking direction DS, the outer surface 221A of the first surface electrode layer 22A extends in a substantially spherical shape.

[0045] The thickness T1 in the stacking direction DS of a central portion of the first surface electrode layer 22A in a plane direction DP parallel to the first main surface 101 is greater than the average thickness of the first surface electrode layer 22A, which is the average thickness from the inner surface 222A, which is the surface of the first surface electrode layer 22A that contacts the first base electrode layer 21A, to the outer surface 221A. In this embodiment, the central portion of the first surface electrode layer 22A in the plane direction DP refers to the center portion (center of gravity) of the first surface electrode layer 22A when viewed from the stacking direction DS. Furthermore, the thickness from the inner surface 222A to the outer surface 221A when viewed from an arbitrary point on the inner surface 222A refers to the thickness of the first surface electrode layer 22A on a virtual normal line drawn to the inner surface 222A at that point. The average thickness from the inner surface 222A to the outer surface 221A is obtained by, for example, averaging the thicknesses measured from five different points on the inner surface 222A.

[0046] The height dimension H of the first surface electrode layer 22A in the stacking direction DS from the first main surface 101 is, for example, approximately 10 μm or more and 20 μm or less. The larger the height dimension H of the first surface electrode layer 22A, the greater the distance between the capacitor body 10 and the electronic component when the first surface electrode layer 22A is reflow soldered to the electronic component. Therefore, by setting the height dimension H to 10 μm or more, it is possible to easily inject an underfill resin into the gap between the capacitor body 10 and the electronic component. However, the height dimension H of the first surface electrode layer 22A is not limited to the above range.

[0047] The width dimension W, which is the maximum dimension in the plane direction DP of the first surface electrode layer 22A, is appropriately set to correspond to the dimension in the plane direction DP of the first via conductor 13A. If the outer shape of the first surface electrode layer 22A when viewed in the stacking direction DS is approximately circular, the width dimension W is the diameter of the first surface electrode layer 22A when viewed in the stacking direction DS. The width dimension W of the first surface electrode layer 22A is, for example, 120 μm or less, preferably 100 μm or less, and more preferably 75 μm or less. The smaller the width dimension W of the first surface electrode layer 22A, the smaller the center distance between the first external electrode 20A and the second external electrode 20B (described later) in the plane direction DP can be designed. The lower limit of the width dimension W of the first surface electrode layer 22A is not particularly limited, but the width dimension W of the first surface electrode layer 22A may be, for example, 30 μm or more or 50 μm or more.

[0048] The ratio (W / H) of the first surface electrode layer 22A, which is the value obtained by dividing the width dimension W by the height dimension H, is preferably, for example, 3.0 or less, and more preferably 1.5 or less. The smaller the ratio (W / H), the smaller the center distance between the first external electrode 20A and the second external electrode 20B (described later) in the planar direction DP can be designed to be, and the larger the distance between the capacitor body 10 and the electronic component when the first surface electrode layer 22A is reflow soldered to the electronic component can be.

[0049] The first surface electrode layer 22A is preferably formed of a material having a melting point lower than that of the material constituting the first base electrode layer 21A. This allows the shape of the first base electrode layer 21A to be easily maintained when the first surface electrode layer 22A is reflow soldered to an electronic component. This also makes it easier to form the first surface electrode layer 22A into the above-described shape (details will be described later). The first surface electrode layer 22A is preferably formed of, for example, Sn or an alloy containing a metal such as Sn and Ag.

[0050] 1 , the second external electrodes 20B are provided at intervals from the first external electrodes 20A. The second external electrodes 20B are provided on the first main surface 101 so as to cover the corresponding second via conductors 13B, respectively. More specifically, the second external electrodes 20B each cover the boundary between the corresponding second via conductor 13B and the dielectric layer 11 (first outer layer portion 111) on the first main surface 101. When viewed from the corresponding second via conductor 13B, the second external electrode 20B may have the same configuration as the first external electrode 20A when viewed from the corresponding first via conductor 13A.

[0051] Each of the multiple second external electrodes 20B includes a second base electrode layer 21B and a second surface electrode layer 22B. The second base electrode layer 21B is provided on the first principal surface 101 so as to cover the corresponding second via conductor 13B. Specifically, the second base electrode layer 21B covers the boundary between the corresponding second via conductor 13B and the dielectric layer 11 (first outer layer portion 111) on the first principal surface 101. The second base electrode layer 21B in the second external electrode 20B may have a configuration similar to that of the first base electrode layer 21A in the first external electrode 20A. In this embodiment, the second base electrode layer 21B has a baked electrode layer, a first base plating layer, and a second base plating layer (not shown) similar to those of the first base electrode layer 21A.

[0052] The second surface electrode layer 22B directly covers the second base electrode layer 21B. The second surface electrode layer 22B covers the entire portion of the second base electrode layer 21B that is not in contact with the first major surface 101.

[0053] An outer surface 221B of the second surface electrode layer 22B extends from an edge 21BE of the second base electrode layer 21B on the first main surface 101 so as to be away from the first main surface 101. Furthermore, the second surface electrode layer 22B when viewed from the corresponding second base electrode layer 21B and second via conductor 13B can have the same configuration as the first surface electrode layer 22A when viewed from the corresponding first base electrode layer 21A and first via conductor 13A.

[0054] In this embodiment, the height dimension H of the first surface electrode layer 22A (and the second surface electrode layer 22B) can take various values. Furthermore, in this embodiment, the first base electrode layer 21A (and the second base electrode layer 21B) can also have various layer structures. Here, multilayer ceramic capacitors according to various modifications of this embodiment will be described. In the description of each modification, the same configuration as in embodiment 1 will not be repeated.

[0055] 6A is a partial cross-sectional view showing the first external electrode and its periphery of the multilayer ceramic capacitor 1 w according to the first modification of the first preferred embodiment of the present invention. As shown in FIG. 6A, the multilayer ceramic capacitor 1 w according to the first modification of the first preferred embodiment of the present invention has a larger height dimension H than the first surface electrode layer 22A (see FIG. 5 ) according to the present preferred embodiment.

[0056] 6B is a partial cross-sectional view showing a first external electrode and its periphery of a multilayer ceramic capacitor according to a second modification. As shown in FIG. 6B, in a multilayer ceramic capacitor 1x according to a second modification of Preferred Embodiment 1 of the present invention, the base plating layer in the first base electrode layer 21A is composed only of a first base plating layer 212A. In this modification, a first surface electrode layer 22A directly covers the first base plating layer 212A.

[0057] 6C is a partial cross-sectional view showing a first external electrode and its periphery of a multilayer ceramic capacitor according to a third modification. As shown in FIG. 6C , in a multilayer ceramic capacitor 1y according to a third modification of Preferred Embodiment 1 of the present invention, the first base electrode layer 21A does not include a fired electrode layer. In this modification, the first base electrode layer 21A includes only a first base plating layer 212A and a second base plating layer 213A. In this modification, the first base plating layer 212A is provided on the first main surface 101 so as to directly cover the first via conductors 13A.

[0058] 6D is a partial cross-sectional view showing a first external electrode and its periphery of a multilayer ceramic capacitor according to a fourth modification. As shown in FIG. 6D , in a multilayer ceramic capacitor 1z according to a fourth modification of Preferred Embodiment 1 of the present invention, the first base electrode layer 21A is composed only of a first base plating layer 212A. Therefore, in this modification, the first base plating layer 212A is provided on the first main surface 101 so as to directly cover the first via conductors 13A, and the first surface electrode layer 22A directly covers the first base plating layer 212A.

[0059] Furthermore, in this embodiment, the first via conductors 13A and the second via conductors 13B are arranged alternately in both one direction and a direction perpendicular to that one direction when viewed from the stacking direction DS (see Figures 3 and 4), but the arrangement of the first via conductors 13A and the second via conductors 13B when viewed from the stacking direction DS is not limited to the above arrangement.

[0060] 6E is a cross-sectional view of a multilayer ceramic capacitor according to a fifth modified example, taken along a line passing through the first internal electrode layer. FIG. 6F is a cross-sectional view of a multilayer ceramic capacitor according to a fifth modified example, taken along a line passing through the second internal electrode layer. As shown in FIGS. 6E and 6F , in the multilayer ceramic capacitor 1m according to the fifth modified example, when viewed from the stacking direction DS, a plurality of first via conductors 13Am are adjacent to one another in one direction, and a plurality of second via conductors 13Bm are adjacent to one another in one direction. Furthermore, the first internal electrode layer 12Am includes a plurality of first internal electrode portions 121A, 122A that are spaced apart from one another within the same layer. In this modified example, only one second internal electrode layer 12Bm is located within the same layer, but the second internal electrode layer 12Bm may also include a plurality of second internal electrode layers that are spaced apart from one another within the same layer.

[0061] 6G is a cross-sectional view of a multilayer ceramic capacitor according to a sixth modification, taken along a line passing through the first internal electrode layer. Fig. 6H is a cross-sectional view of a multilayer ceramic capacitor according to a sixth modification, taken along a line passing through the second internal electrode layer. As shown in Figs. 6G and 6H , in the multilayer ceramic capacitor In according to the sixth modification, when viewed from the stacking direction DS, the direction in which the first via conductors 13An and the second via conductors 13Bn are arranged intersects with one side of the rectangular peripheral side surface 103.

[0062] [Method for Manufacturing Multilayer Ceramic Capacitor] Next, a method for manufacturing the multilayer ceramic capacitor according to the first embodiment of the present invention will be described. Fig. 7 is a flow chart showing the method for manufacturing the multilayer ceramic capacitor according to the first embodiment of the present invention. As shown in Fig. 7, the method for manufacturing the multilayer ceramic capacitor according to the first embodiment of the present invention includes a step S1 of preparing a capacitor body, a step S2 of providing a first external electrode, and a step S3 of providing a second external electrode.

[0063] In the capacitor body preparation step S1, the capacitor body 10 shown in FIG. 1 is prepared. The specific method for preparing the capacitor body 10 is not particularly limited. In this embodiment, for example, in the capacitor body preparation step S1, a laminate is formed by stacking a plurality of ceramic green sheets corresponding to the plurality of dielectric layers 11 and conductive paste layers corresponding to the plurality of first internal electrode layers 12A and the plurality of second internal electrode layers 12B in a predetermined pattern. A plurality of through holes penetrating the laminate in the stacking direction are formed by laser irradiation. These through holes are then filled with conductive paste. As a result, a plurality of columnar conductive pastes corresponding to the plurality of first via conductors 13A and the plurality of second via conductors 13B of the capacitor body 10 are provided in the laminate. Furthermore, an outer layer ceramic green sheet corresponding to at least a portion of the second outer layer portion 112 is further stacked on the laminate so as to cover one side of the columnar conductive pastes. As a result, the columnar conductive pastes are not exposed on one surface (the surface corresponding to the second main surface 102) of the laminate.

[0064] The laminate having the plurality of columns of conductive paste and the outer ceramic green sheets is then fired to form the capacitor body 10.

[0065] 1 and 5 is provided on the first main surface 101 of the capacitor body 10. As shown in Fig. 7, the step S2 of providing the first external electrode includes a step S21 of forming a first base electrode layer, a step S22 of forming a first plating layer, a step S23 of heating and melting the first plating layer, and a step S24 of cooling the first plating layer to form a first surface electrode layer.

[0066] 1 and 5 is provided on the main surface of the capacitor body 10. First, a conductive paste surface layer corresponding to the fired electrode layer 211A is provided on the first main surface 101 of the capacitor body 10 so as to cover the first via conductors 13A, and then fired to form the fired electrode layer 211A. The conductive paste surface layer may be provided on the laminate before firing the capacitor body 10. In this case, firing of the laminate and firing of the conductive paste surface layer may be performed simultaneously.

[0067] After the baked electrode layer 211A is formed, the baked electrode layer 211A is plated to form a first undercoat plating layer 212A. Then, the first undercoat plating layer 212A is plated to form a second undercoat plating layer 213A. These plating processes may be, for example, plating processes using a rotary plating method. Note that in the third modified example (see FIG. 6C ) and the fourth modified example (see FIG. 6D ) of this embodiment, the first undercoat plating layer 212A is formed by plating the first via conductors 13A. In this case, the first undercoat plating layer 212A also grows in the planar direction DP during the plating process. Therefore, the first undercoat plating layer 212A is provided so as to cover the boundary between the dielectric layer 11 (first outer layer portion 111) and the first via conductors 13A.

[0068] 8 is a schematic cross-sectional view showing a state immediately after the first plating layer is formed in the manufacturing method of the multilayer ceramic capacitor according to the first embodiment of the present invention. As shown in FIG. 8, in the step S22 of forming the first plating layer, the first plating layer 30A is formed on the first base electrode layer 21A by plating. Specifically, the first plating layer 30A is formed by plating the first base electrode layer 21A.

[0069] The first plating layer 30A is formed to cover the entire portion of the first base electrode layer 21A that is not in contact with the first main surface 101. The outer surface 301A, which is the surface of the first plating layer 30A exposed to the outside, is located away from the edge 21AE of the first base electrode layer 21A on the first main surface 101. Furthermore, the thickness Tp1 of the central portion of the first plating layer 30A in the planar direction DP in the stacking direction DS is approximately equal to the average thickness of the first plating layer 30A, which is the average thickness from the inner surface 302A, which is the surface of the first plating layer 30A that is in contact with the first base electrode layer 21A, to the outer surface 301A. Because the first plating layer 30A is formed by plating to grow from the first base electrode layer 21A, the thickness from the inner surface 302A to the outer surface 301A is approximately uniform. The average thickness of the first plating layer 30A is, for example, 3 μm or more and 50 μm or less. The average thickness of the first plating layer 30A can be appropriately designed taking into account the distance between the center of the first via conductor 13A in the planar direction DP and the center of the second via conductor 13B in the planar direction DP, and the separation distance between the first via conductor 13A and the second via conductor 13B.

[0070] In step S23 of heating and melting the first plating layer, the first plating layer 30A formed as described above is heated and melted. As a result, the surface tension of the melted first plating layer 30A causes the outer surface 301A to deform into a curved shape, more specifically, a substantially spherical shape, so that the area of ​​the outer surface 301A approaches the minimum area of ​​the volume of the first plating layer 30A. This deformation increases the thickness Tp1 at the central portion of the first plating layer 30A and also increases the height dimension Hp of the first plating layer 30A in the stacking direction DS. Meanwhile, this deformation reduces the width dimension Wp, which is the maximum dimension of the first plating layer 30A in the planar direction DP. Furthermore, the bonding strength between the first plating layer 30A and the first outer layer portion 111 is relatively low, while the bonding strength between the first plating layer 30A and the first base electrode layer 21A is relatively high. As a result, outer surface 301A of first plating layer 30A is deformed so as to extend from edge 21AE of first base electrode layer 21A on first main surface 101 toward first main surface 101.

[0071] Then, in step S24 of forming the first surface electrode layer by cooling the first plating layer, the melted and deformed first plating layer 30A is cooled and solidified, thereby forming the first surface electrode layer 22A as shown in Figures 1 and 5. Therefore, the average thickness, thickness T1 at the central portion, height dimension H, width dimension W, etc. of the first surface electrode layer 22A can be controlled by adjusting the average thickness of the first plating layer 30A.

[0072] Here, the first plating layer 30A and the first surface electrode layer 22A will be described while showing an experimental example of the multilayer ceramic capacitor according to this embodiment. Fig. 9 is a cross-sectional SEM image of the state immediately after the first plating layer is formed in an experimental example of the manufacture of the multilayer ceramic capacitor according to embodiment 1 of the present invention. Fig. 10 is a cross-sectional SEM photograph of the state after the first surface electrode layer is formed in an experimental example of the manufacture of the multilayer ceramic capacitor according to embodiment 1 of the present invention. In Figs. 9 and 10, reference numerals corresponding to the reference numerals used in the description of the multilayer ceramic capacitor 1 according to embodiment 1 of the present invention are used.

[0073] As also shown in Figures 9 and 10, when the first plating layer 30A melts, the outer surface 301A of the first plating layer 30A is deformed into an approximately spherical shape, and further, when the molten first plating layer 30A cools and solidifies, a first surface electrode layer 22A having an outer surface 221A of an approximately spherical shape is formed.

[0074] Therefore, in this embodiment, the width dimension W of the first surface electrode layer 22A is smaller than the width dimension Wp of the first plating layer 30A before heat melting. The height dimension H of the first surface electrode layer 22A is larger than the height dimension Hp of the first plating layer 30A before heat melting. The thickness T1 of the central portion of the first surface electrode layer 22A is larger than the thickness Tp1 of the central portion of the first plating layer 30A before heat melting. The ratio (W / H) of the first surface electrode layer 22A is smaller than the ratio (Wp / Hp) obtained by dividing the width dimension Wp by the height dimension Hp of the first plating layer 30A before heat melting.

[0075] The smaller the dimension of the first base electrode layer 21A in the plane direction DP, the greater the difference between the height dimension H of the first surface electrode layer 22A and the height dimension Hp of the first plating layer 30A. The greater the thickness Tp1 of the central portion of the first plating layer 30A before heating and melting, the greater the height dimension H of the first surface electrode layer 22A. The heating and cooling conditions in steps S33 and S34 can be adjusted appropriately depending on the material of the first plating layer 30A (first surface electrode layer 22A). The heating and cooling conditions can be similar to the solder reflow conditions in accordance with IPC / J-STD. The peak temperature in step S33 is, for example, 260°C.

[0076] In step S3 of providing a second external electrode, the second external electrode 20B shown in Fig. 1 is provided on the first main surface 101 of the capacitor body 10. As shown in Fig. 7, step S3 of providing a second external electrode includes step S31 of forming a second base electrode layer, step S32 of forming a second plating layer, step S33 of heating and melting the second plating layer, and step S34 of cooling the second plating layer to form a second surface electrode layer.

[0077] The step S3 of providing the second external electrode may be carried out simultaneously with the step S2 of providing the first external electrode. Specifically, the step S31 of forming the second base electrode layer is carried out simultaneously with the step S21 of forming the first base electrode layer. The step S32 of forming the second plating layer is carried out simultaneously with the step S22 of forming the first plating layer. The step S33 of heating and melting the second plating layer is carried out simultaneously with the step S23 of heating and melting the first plating layer. The step S34 of cooling the second plating layer to form the second surface electrode layer is carried out simultaneously with the step S24 of cooling the first plating layer to form the first surface electrode layer.

[0078] 1 and 5 is provided on the main surface of the capacitor body 10. The method for forming the second base electrode layer 21B as viewed from the corresponding second via conductor 13B can be the same as the method for forming the first base electrode layer 21A as viewed from the first via conductor 13A.

[0079] In step S32 of forming the second plating layer, the second plating layer can be formed on the second base electrode layer 21B by the same method as the method of forming the first plating layer 30A on the first base electrode layer 21A. The heating conditions in step S33 of heating and melting the second plating layer may be the same as the heating conditions in step S23 of heating and melting the first plating layer. This causes the second plating layer to deform in the same way as the first plating layer 30A. The conditions for cooling the heated and melted second plating layer in step S34 of cooling the second plating layer to form the second surface electrode layer 22B may be the same as the cooling conditions in step S24 of cooling the first plating layer to form the first surface electrode layer 22A.

[0080] The multilayer ceramic capacitor 1 according to the first embodiment of the present invention is manufactured by the above-described manufacturing method. However, the manufacturing method of the multilayer ceramic capacitor 1 according to the first embodiment of the present invention is not limited to the above-described manufacturing method.

[0081] [Method for manufacturing a multilayer ceramic capacitor mounting structure] Next, a method for manufacturing a multilayer ceramic capacitor mounting structure according to the first embodiment of the present invention will be described. Fig. 11 is a schematic cross-sectional view showing a state in which the multilayer ceramic capacitor according to the first embodiment of the present invention and an electronic component are prepared. Fig. 12 is a schematic cross-sectional view showing the multilayer ceramic capacitor mounting structure according to the first embodiment of the present invention.

[0082] 11 and 12 , the method for manufacturing a multilayer ceramic capacitor mounting structure includes the steps of preparing a multilayer ceramic capacitor 1 manufactured by the above-described manufacturing method, and reflow soldering the plurality of first surface electrode layers 22A of the multilayer ceramic capacitor 1 to the electronic component 500 to electrically connect the plurality of first surface electrode layers 22A to the electronic component 500. In this way, a multilayer ceramic capacitor mounting structure 1000 is manufactured.

[0083] The manufacturing method for a mounting structure of a multilayer ceramic capacitor in this embodiment further includes a step of reflow soldering the second surface electrode layers 22B to the electronic component 500, thereby electrically connecting the second surface electrode layers 22B to the electronic component 500. This step can be performed simultaneously with the step of reflow soldering the first surface electrode layers 22A.

[0084] As described above, the first surface electrode layers 22A and the second surface electrode layers 22B manufactured by the manufacturing method of the multilayer ceramic capacitor according to this embodiment are formed so that the thickness of the central portion in the planar direction DP is relatively large. This facilitates reflow soldering of the first surface electrode layers 22A and the second surface electrode layers 22B. This allows the multilayer ceramic capacitor 1 to be easily mounted on the electronic component 500, and the multilayer ceramic capacitor mounting structure 1000 can be more easily manufactured.

[0085] As described above, the multilayer ceramic capacitor 1 according to the first embodiment of the present invention includes a capacitor body 10, a first external electrode 20A, and a second external electrode 20B. The capacitor body 10 includes a dielectric layer 11, a plurality of first internal electrode layers 12A and a plurality of second internal electrode layers 12B, a first via conductor 13A, and a second via conductor 13B. The first internal electrode layers 12A and the second internal electrode layers 12B are alternately stacked in the stacking direction DS with the dielectric layer 11 sandwiched therebetween. The first via conductor 13A is electrically connected to the plurality of first internal electrode layers 12A. The first via conductor 13A extends from the interior of the capacitor body 10 to a first main surface 101. The first main surface 101 is one surface of the capacitor body 10 in the stacking direction DS. The second via conductor 13B is electrically connected to the plurality of second internal electrode layers 12B. The second via conductors 13B extend from the interior of the capacitor body 10 to the first principal surface 101. The first external electrode 20A includes a first base electrode layer 21A and a first surface electrode layer 22A. The first base electrode layer 21A is provided on the first principal surface 101 so as to cover the first via conductors 13A. The first surface electrode layer 22A directly covers the first base electrode layer 21A. The second external electrode 20B is provided on the first principal surface 101 at a distance from the first external electrode 20A so as to cover the second via conductors 13B. An outer surface 221A of the first surface electrode layer 22A extends away from the first principal surface 101 from an edge 21AE of the first base electrode layer 21A on the first principal surface 101.

[0086] According to the above configuration, the thickness of the first surface electrode layer 22A in the plane direction DP perpendicular to the stacking direction DS is relatively small near the edge 21AE of the first base electrode layer 21A. This allows the center-to-center distance between the first external electrode 20A and the second external electrode 20B in the plane direction DP to be designed to be small, thereby reducing the distance between the first via conductor 13A and the second via conductor 13B. Reducing the distance between the first via conductor 13A and the second via conductor 13B makes it easier for the magnetic fields induced by the current flowing through the first via conductor 13A and the magnetic fields induced by the current flowing through the second via conductor 13B to cancel each other out.

[0087] Therefore, with the above configuration, the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1 can be reduced.

[0088] In addition, in this embodiment, the thickness T1 in the stacking direction DS of the central portion of the first surface electrode layer 22A in the plane direction DP parallel to the first main surface 101 is greater than the average thickness of the first surface electrode layer 22A, which is the average thickness from the inner surface 222A, which is the surface of the first surface electrode layer 22A that contacts the first base electrode layer 21A, to the outer surface 221A.

[0089] According to the above configuration, the thickness T1 of the first surface electrode layer 22A in the stacking direction DS is relatively large. When mounting such a multilayer ceramic capacitor 1 on an electronic component 500, the distance between the capacitor body 10 and the electronic component 500 can be relatively large when the first surface electrode layer 22A is reflow soldered to the electronic component 500. Therefore, an underfill resin for filling the gap between the capacitor body 10 and the electronic component 500 can be easily provided in the gap.

[0090] In this embodiment, the outer surface 221A of the first surface electrode layer 22A includes a first region 221Ap and a second region 221Aq in the stacking direction DS. The first region 221Ap is in contact with the edge 21AE. The second region 221Aq is located on the opposite side of the first region 221Ap from the first main surface 101. The first region 221Ap extends such that the cross-sectional area of ​​the first external electrode 20A when viewed in the stacking direction DS increases with increasing distance from the first main surface 101. The second region 221Aq extends such that the cross-sectional area of ​​the first external electrode 20A when viewed in the stacking direction DS decreases with increasing distance from the first main surface 101.

[0091] According to the above configuration, the thickness of the first surface electrode layer 22A from the inner surface 222A to the outer surface 221A in the first region 221Ap can be prevented from becoming too small, thereby ensuring the strength of the first surface electrode layer 22A. Furthermore, in the second region 221Aq, the dimension of the first surface electrode layer 22A in the planar direction DP can be reduced. This further reduces the center-to-center distance between the first external electrode 20A and the second external electrode 20B in the planar direction DP. This in turn further reduces the distance between the first via conductor 13A and the second via conductor 13B, thereby further reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1.

[0092] In this embodiment, the first via conductors 13A and the second via conductors 13B are not exposed from the second main surface 102 of the capacitor body 10 , which is the surface opposite to the first main surface 101 .

[0093] According to the above configuration, it is possible to prevent short circuits from occurring between the multilayer ceramic capacitor 1 and other electronic components disposed on the second main surface 102 side of the multilayer ceramic capacitor 1 .

[0094] Furthermore, the method for manufacturing the multilayer ceramic capacitor according to the first embodiment of the present invention includes a capacitor body 10 including a dielectric layer 11, a plurality of first internal electrode layers 12A and a plurality of second internal electrode layers 12B, a first via conductor 13A, and a second via conductor 13B, wherein the plurality of first internal electrode layers 12A and the plurality of second internal electrode layers 12B are alternately stacked in a stacking direction DS with the dielectric layer 11 sandwiched therebetween, the first via conductor 13A is electrically connected to the plurality of first internal electrode layers 12A, and a ... a first surface of the capacitor body 10 on one side in the stacking direction DS from the inside of the capacitor body 10. The method includes preparing a capacitor body 10, in which a first via conductor 13A extends to the main surface 101, and a second via conductor 13B is electrically connected to a plurality of second internal electrode layers 12B and extends from the inside of the capacitor body 10 to the first main surface 101; providing a first external electrode 20A including a first base electrode layer 21A provided on the first main surface 101 so as to cover the first via conductor 13A and a first surface electrode layer 22A directly covering the first base electrode layer 21A; and providing a second external electrode 20B on the first main surface 101 at a distance from the first external electrode 20A so as to cover the second via conductor 13B. Providing the first external electrode 20A includes forming a first base electrode layer 21A, forming a first plating layer 30A on the first base electrode layer 21A by plating, heating and melting the first plating layer 30A, and cooling the heated and melted first plating layer 30A to form a first surface electrode layer 22A.

[0095] According to the above configuration, by heating and melting the first plating layer 30A, the outer surface of the first plating layer 30A is deformed into a substantially spherical shape. By cooling the first plating layer 30A deformed by heating and melting to form the first surface electrode layer 22A, the dimension of the first surface electrode layer 22A in the plane direction DP becomes smaller than the dimension of the first plating layer 30A in the plane direction DP. Therefore, the center distance between the first external electrode 20A and the second external electrode 20B in the plane direction DP can be designed to be small, and thus the spacing between the first via conductor 13A and the second via conductor 13B can be reduced. If the spacing between the first via conductor 13A and the second via conductor 13B can be reduced, the magnetic field induced by the current flowing through the first via conductor 13A and the magnetic field induced by the current flowing through the second via conductor 13B are more likely to cancel each other out.

[0096] Therefore, with the above configuration, the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1 can be reduced.

[0097] Furthermore, by cooling the first plating layer 30A deformed by heating and melting to form the first surface electrode layer 22A, the thickness T1 of the first surface electrode layer 22A at the center portion becomes greater than the thickness Tp1 of the first plating layer 30A at the center portion. When mounting the multilayer ceramic capacitor 1 manufactured using the above configuration on an electronic component 500, the distance between the capacitor body 10 and the electronic component 500 can be made relatively large when the first surface electrode layer 22A is reflow soldered to the electronic component 500. Therefore, an underfill resin for filling the gap between the capacitor body 10 and the electronic component 500 can be easily provided in the gap.

[0098] The manufacturing method of the mounting structure of the multilayer ceramic capacitor according to the first embodiment of the present invention includes preparing the multilayer ceramic capacitor 1 manufactured by the above-described manufacturing method, and electrically connecting the first surface electrode layer 22A of the multilayer ceramic capacitor 1 to the electronic component 500 by reflow soldering the first surface electrode layer 22A to the electronic component 500.

[0099] According to the above configuration, the underfill resin for filling the gap between the capacitor body 10 and the electronic component 500 can be easily provided in the gap.

[0100] (Embodiment 2) Next, a multilayer ceramic capacitor according to embodiment 2 of the present invention will be described. The multilayer ceramic capacitor according to embodiment 2 of the present invention differs from multilayer ceramic capacitor 1 according to embodiment 1 of the present invention in that it further includes a third external electrode and a fourth external electrode. Therefore, description of the same configuration and effects as those of the multilayer ceramic capacitor according to embodiment 1 of the present invention will not be repeated.

[0101] 13 is a cross-sectional view showing a multilayer ceramic capacitor according to Preferred Embodiment 2 of the present invention. As shown in FIG. 13, the multilayer ceramic capacitor 1a further includes a third external electrode 20Ca and a fourth external electrode 20Da. The first via conductor 13Aa extends from the inside of the capacitor body 10 to the second main surface 102. The second via conductor 13Ba extends from the inside of the capacitor body 10 to the second main surface 102.

[0102] The third external electrode 20Ca includes a third base electrode layer 21Ca and a third surface electrode layer 22Ca. The third base electrode layer 21Ca is provided on the second principal surface 102 so as to cover either the first via conductors 13Aa or the second via conductors 13Ba. The third surface electrode layer 22Ca directly covers the third base electrode layer 21Ca.

[0103] The fourth external electrode 20Da is provided on the second main surface 102 at a distance from the third external electrode 20Ca so as to cover the other of the first via conductors 13Aa and the second via conductors 13Ba.

[0104] An outer surface 221Ca of the third surface electrode layer 22Ca extends from an edge 21CEa of the third base electrode layer 21Ca on the second major surface 102 so as to move away from the second major surface 102.

[0105] According to the above configuration, even when an external electrode is provided on the second main surface 102 side, the center distance between the third external electrode 20Ca and the fourth external electrode 20Da in the planar direction DP can be designed to be small, and ultimately, the distance between the first via conductor 13Aa and the second via conductor 13Ba can be reduced to reduce the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1a.

[0106] Specifically, the multilayer ceramic capacitor 1a according to this embodiment includes a plurality of third external electrodes 20Ca and a plurality of fourth external electrodes 20Da. The third external electrodes 20Ca are provided on the second main surface 102 so as to cover the respective first via conductors 13Aa. The third base electrode layer 21Ca is provided on the second main surface 102 so as to cover the corresponding first via conductors 13Aa. In this embodiment, the third external electrodes 20Ca when viewed from the second main surface 102 may have the same configuration as the first external electrodes 20A when viewed from the first main surface 101.

[0107] The plurality of fourth external electrodes 20Da are provided on the second principal surface 102 so as to cover the plurality of second via conductors 13Ba. The fourth external electrode 20Da includes a fourth base electrode layer 21Da and a fourth surface electrode layer 22Da. The fourth base electrode layer 21Da is provided on the second principal surface 102 so as to cover the second via conductors 13Ba. The fourth surface electrode layer 22Da directly covers the fourth base electrode layer 21Da.

[0108] An outer surface 221Da of the fourth surface electrode layer 22Da also extends from an edge 21DEa of the fourth base electrode layer 21Da on the second main surface 102 so as to be away from the second main surface 102. In the present embodiment, the fourth external electrode 20Da when viewed from the second main surface 102 may have a configuration similar to that of the second external electrode 20B when viewed from the first main surface 101.

[0109] The method for manufacturing a multilayer ceramic capacitor according to this embodiment further includes the steps of providing the third external electrode 20Ca and providing the fourth external electrode 20Da. When viewed from above the second main surface 102, the step of providing the third external electrode 20Ca may have the same configuration as step S2 of providing the first external electrode 20A when viewed from above the first main surface 101. The step of providing the third external electrode 20Ca may be performed simultaneously with step S2 of providing the first external electrode 20A. When viewed from above the second main surface 102, the step of providing the fourth external electrode 20Da may have the same configuration as step S3 of providing the second external electrode 20B when viewed from above the first main surface 101. The step of providing the fourth external electrode 20Da may be performed simultaneously with step S3 of providing the second external electrode 20B.

[0110] In the present embodiment, the steps of providing the third external electrode 20Ca and the fourth external electrode 20Da may be performed, for example, by clamping the capacitor body 10 with a jig so that the components for the third external electrode 20Ca and the fourth external electrode 20Da are not grounded. Furthermore, in the step S1 of preparing the capacitor body in the present embodiment, the outer layer ceramic green sheets are not stacked on the laminate so that both sides of the columnar conductive paste in the stacking direction DS are not covered by the outer layer portions.

[0111] (Embodiment 3) Next, a multilayer ceramic capacitor according to embodiment 3 of the present invention will be described. The multilayer ceramic capacitor according to embodiment 3 of the present invention differs from the multilayer ceramic capacitor according to embodiment 2 of the present invention in the shapes of the third surface electrode layer and the fourth surface electrode layer. Therefore, description of the same configuration and effects as those of the multilayer ceramic capacitor according to embodiment 2 of the present invention will not be repeated.

[0112] 14 is a cross-sectional view showing a multilayer ceramic capacitor according to Preferred Embodiment 3 of the present invention. As shown in Fig. 14, in the multilayer ceramic capacitor 1b according to Preferred Embodiment 3 of the present invention, the thickness T3 in the stacking direction DS of a central portion of the third surface electrode layer 22Cb in the plane direction DP parallel to the first main surface 101 is smaller than the thickness T1 in the stacking direction DS of a central portion of the first surface electrode layer 22A in the plane direction DP parallel to the first main surface 101. This configuration allows the overall dimension of the multilayer ceramic capacitor 1b in the stacking direction DS to be relatively small.

[0113] Furthermore, in this embodiment, the thickness T4 in the stacking direction DS of the central portion of the fourth surface electrode layer 22Db in the surface direction DP is smaller than the thickness T1 in the stacking direction DS of the central portion of the first surface electrode layer 22A in the surface direction DP parallel to the first main surface 101.

[0114] In the manufacturing method of the multilayer ceramic capacitor 1b according to this embodiment, in the step of heating and melting the plating layers provided on the respective base electrode layers to form the third surface electrode layer 22Cb and the fourth surface electrode layer 22Db, the plating layers can be heated and melted while the orientation of the capacitor body 10 is fixed so that the second main surface 102 of the capacitor body 10 faces upward in the vertical direction. This causes the heated and melted plating layers to be crushed and deformed by their own weight, resulting in the formation of the third surface electrode layer 22Cb and the fourth surface electrode layer 22Db having a relatively small thickness in their central portions. Alternatively, in the step of heating and melting the plating layers provided on the respective base electrode layers to form the third surface electrode layer 22Cb and the fourth surface electrode layer 22Db, the third surface electrode layer 22Cb and the fourth surface electrode layer 22Db can be formed by sucking up a portion of the heated and melted plating layers.

[0115] (Embodiment 4) Next, a multilayer ceramic capacitor according to embodiment 4 of the present invention, a manufacturing method thereof, and a manufacturing method of a mounting structure of a multilayer ceramic capacitor will be described. The multilayer ceramic capacitor according to embodiment 4 of the present invention differs from the multilayer ceramic capacitor 1 according to embodiment 1 of the present invention in the configurations of the first external electrodes and the second external electrodes. In the following description of embodiment 4, the same configurations and effects as those of the multilayer ceramic capacitor 1 according to embodiment 1 of the present invention, a manufacturing method thereof, and a manufacturing method of a mounting structure of a multilayer ceramic capacitor will not be described repeatedly.

[0116] [Multilayer Ceramic Capacitor] Fig. 15 is a cross-sectional view showing a multilayer ceramic capacitor according to Preferred Embodiment 4 of the present invention. Fig. 16 is a partial cross-sectional view showing a first external electrode and its periphery of the multilayer ceramic capacitor according to Preferred Embodiment 4 of the present invention.

[0117] As shown in Figures 15 and 16, in the multilayer ceramic capacitor 1c according to embodiment 4 of the present invention, the outer surface 201Ac of the first external electrode 20Ac extends away from the edge 13AE of the first via conductor 13A on the first main surface 101.

[0118] According to the above configuration, while the first external electrode 20Ac covers the first via conductor 13A, the dimension of the first external electrode 20Ac in the planar direction DP can be reduced near the edge 13AE of the first via conductor 13A. This allows the center-to-center distance between the first external electrode 20Ac and the second external electrode 20Bc in the planar direction DP to be reduced, thereby reducing the distance between the first via conductor 13A and the second via conductor 13B. Reducing the distance between the first via conductor 13A and the second via conductor 13B makes it easier for the magnetic fields induced by the current flowing through the first via conductor 13A and the magnetic fields induced by the current flowing through the second via conductor 13B to cancel each other out.

[0119] Therefore, with the above configuration, the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1c can be reduced.

[0120] In this embodiment, the outer surface 201Ac of the first external electrode 20Ac includes a first region 201Acp and a second region 201Acq in the stacking direction DS. The first region 201Acp is in contact with the edge 13AE. The second region 201Acq is located on the opposite side of the first region 201Acp from the first main surface 101. The first region 201Acp extends such that the cross-sectional area of ​​the first external electrode 20Ac when viewed in the stacking direction DS increases with increasing distance from the first main surface 101. The second region 201Acq extends such that the cross-sectional area of ​​the first external electrode 20Ac when viewed in the stacking direction DS decreases with increasing distance from the first main surface 101.

[0121] According to the above configuration, the dimension of the first external electrode 20Ac in the plane direction DP in the first region 201Acp can be prevented from becoming too small, thereby ensuring the strength of the first external electrode 20Ac. Furthermore, the dimension of the first external electrode 20Ac in the plane direction DP can be reduced in the second region 201Acq. This further reduces the center-to-center distance between the first external electrode 20Ac and the second external electrode 20Bc in the plane direction DP. This further reduces the distance between the first via conductor 13A and the second via conductor 13B, thereby further reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1c.

[0122] The first external electrode 20Ac and the second external electrode 20Bc according to the fourth embodiment of the present invention will be described in detail.

[0123] More specifically, the outer surface 201Ac of the first external electrode 20Ac extends in a generally curved shape, and even more specifically, in a generally spherical shape. The height dimension Hc of the first external electrode 20Ac in the stacking direction DS is, for example, approximately 10 μm or more and 20 μm or less. The larger the height dimension Hc of the first external electrode 20Ac, the greater the distance between the capacitor body 10 and the electronic component when the first external electrode 20Ac is reflow soldered to the electronic component. Therefore, by setting the height dimension Hc to 10 μm or more, it is possible to easily inject an underfill resin into the gap between the capacitor body 10 and the electronic component. The upper limit of the height dimension Hc of the first external electrode 20Ac is not particularly limited. However, the height dimension Hc of the first external electrode 20Ac is not limited to the above range.

[0124] The width dimension Wc, which is the maximum dimension of the first external electrode 20Ac in the plane direction DP, is appropriately set to correspond to the dimension of the first via conductor 13A in the plane direction DP. The width dimension Wc is, for example, 120 μm or less, preferably 100 μm or less, and more preferably 75 μm or less. The smaller the width dimension Wc of the first external electrode 20Ac, the smaller the center distance between the first external electrode 20Ac and the second external electrode 20Bc in the plane direction DP can be designed to be. There is no particular lower limit for the width dimension Wc of the first external electrode 20Ac, but the width dimension Wc may be, for example, 30 μm or more, or 50 μm or more.

[0125] The ratio (Wc / Hc), which is the value obtained by dividing the width dimension Wc by the height dimension Hc of the first external electrode 20Ac, is preferably, for example, 3.0 or less, and more preferably 1.5 or less. The smaller the ratio (Wc / Hc), the shorter the center-to-center distance between the first external electrode 20Ac and the second external electrode 20Bc in the planar direction DP can be designed to be, and the longer the distance between the capacitor body 10 and the electronic component when the first external electrode 20Ac is reflow soldered to the electronic component can be.

[0126] Each of the first external electrodes 20Ac is preferably made of a single material. The first external electrodes 20Ac are preferably made of a material with a melting point lower than that of the material constituting the first via conductors 13A. This facilitates forming the first surface electrode layer 22A into the above-described shape (details will be described later). The first external electrodes 20Ac are preferably made of, for example, Sn or an alloy containing a metal such as Sn and Ag.

[0127] The outer surface 201Bc of the second external electrode 20Bc extends from the edge 13BE of the corresponding second via conductor 13B on the first main surface 101 so as to be away from the first main surface 101. In this way, the second external electrode 20Bc when viewed from the corresponding second via conductor 13B can have the same configuration as the first external electrode 20Ac when viewed from the corresponding first via conductor 13A.

[0128] [Method for manufacturing a multilayer ceramic capacitor] Next, a method for manufacturing a multilayer ceramic capacitor according to embodiment 4 of the present invention will be described. Fig. 17 is a flow diagram showing a method for manufacturing a multilayer ceramic capacitor according to embodiment 4 of the present invention. Fig. 18 is a schematic cross-sectional view showing a state immediately after a first plating layer is formed in the method for manufacturing a multilayer ceramic capacitor according to embodiment 4 of the present invention.

[0129] As shown in Figures 17 and 18, in the manufacturing method of the multilayer ceramic capacitor of embodiment 4 of the present invention, providing a first external electrode 20Ac (S2c) includes forming a first plating layer 30Ac by plating on the first via conductor 13A on the first main surface 101 (S22c), heating and melting the first plating layer 30Ac (S23c), and cooling the heated and melted first plating layer 30Ac to form the first external electrode 20Ac (S24c).

[0130] According to the above configuration, by heating and melting the first plating layer 30Ac, the outer surface of the first plating layer 30Ac is deformed into a substantially spherical shape. By cooling the first plating layer 30Ac deformed by heating and melting to form the first external electrode 20Ac, the width dimension Wc of the first external electrode 20Ac becomes smaller than the width dimension Wpc, which is the maximum dimension of the first plating layer 30Ac in the planar direction DP. This allows the center distance between the first external electrode 20Ac and the second external electrode 20Bc in the planar direction DP to be designed to be small, thereby reducing the spacing between the first via conductor 13A and the second via conductor 13B. Reducing the spacing between the first via conductor 13A and the second via conductor 13B makes it easier for the magnetic fields induced by the current flowing through the first via conductor 13A and the magnetic fields induced by the current flowing through the second via conductor 13B to cancel each other out.

[0131] Therefore, with the above configuration, the distance between the first via conductor 13A and the second via conductor 13B can be reduced, and the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1c can be reduced.

[0132] Furthermore, by cooling the first plating layer 30Ac deformed by heating and melting to form the first external electrode 20Ac, the height Hc of the first external electrode 20Ac becomes greater than the height Hpc of the first plating layer 30A. When mounting the multilayer ceramic capacitor 1c manufactured using the above configuration on an electronic component, the distance between the capacitor body 10 and the electronic component can be made relatively large when the first external electrode 20Ac is reflow soldered to the electronic component. Therefore, underfill resin can be easily provided in the gap between the capacitor body 10 and the electronic component.

[0133] The method for manufacturing the multilayer ceramic capacitor according to the fourth embodiment of the present invention will now be described in more detail. As shown in Fig. 17 , in this embodiment, the step S2c of providing the first external electrode includes the step S22c of forming a first plating layer, the step S23c of heating and melting the first plating layer, and the step S24c of cooling the first plating layer to form the first external electrode.

[0134] 18 , in step S22c of forming the first plating layer, the first via conductor 13A is plated to form the first plating layer 30Ac. This plating may be performed, for example, by a rotary plating method. The first plating layer 30Ac also grows in the planar direction DP during the plating process. Therefore, the first plating layer 30Ac is provided so as to cover the boundary between the dielectric layer 11 (first outer layer portion 111) and the first via conductor 13A.

[0135] In step S23c of heating and melting the first plating layer, the first plating layer 30Ac formed as described above is heated and melted. As a result, the surface tension of the melted first plating layer 30Ac causes the outer surface 301Ac to deform into a curved shape, specifically, a substantially spherical shape, so that the area of ​​the outer surface 301Ac approaches the minimum area of ​​the volume of the first plating layer 30Ac. This deformation increases the height dimension Hpc of the first plating layer 30Ac. Meanwhile, this deformation reduces the width dimension Wpc of the first plating layer 30Ac. Furthermore, the bonding strength between the first plating layer 30Ac and the first outer layer portion 111 is relatively low, while the bonding strength between the first plating layer 30Ac and the first via conductor 13A is relatively high. As a result, outer surface 301Ac of first plating layer 30Ac is deformed so as to extend from edge 13AE of first via conductor 13A on first main surface 101 toward first main surface 101.

[0136] Then, in step S24c of forming the first external electrode by cooling the first plating layer, the melted and deformed first plating layer 30Ac is cooled and solidified, thereby forming the first external electrode 20Ac as shown in Figures 15 and 16. Therefore, the height dimension Hc and width dimension Wc of the first external electrode 20Ac can be controlled by adjusting the height dimension Hpc of the first plating layer 30Ac.

[0137] Therefore, in this embodiment, the width dimension Wc of the first external electrode 20Ac is smaller than the width dimension Wpc of the first plating layer 30Ac before heat melting. The height dimension Hc of the first external electrode 20Ac is greater than the height dimension Hpc of the first plating layer 30Ac before heat melting. The ratio (Wc / Hc) of the first external electrode 20Ac is smaller than the ratio (Wpc / Hpc) of the first plating layer 30A before heat melting.

[0138] 17 , in this embodiment, the step S3c of providing the second external electrode includes the step S32c of forming a second plating layer, the step S33c of heating and melting the second plating layer, and the step S34c of cooling the second plating layer to form the second external electrode. The step S32c of forming the second plating layer is performed simultaneously with the step S22c of forming the first plating layer. The step S33c of heating and melting the second plating layer is performed simultaneously with the step S23c of heating and melting the first plating layer. The step S34c of cooling the second plating layer to form the second surface electrode layer is performed simultaneously with the step S24c of cooling the first plating layer to form the first surface electrode layer.

[0139] The method for forming the second external electrode 20Bc as viewed from the corresponding second via conductor 13B can be the same as the method for forming the first external electrode 20Ac as viewed from the first via conductor 13A. Specifically, in step S32c of forming the second plating layer, the second plating layer can be formed on the second via conductor 13B by the same method as the method for forming the first plating layer 30A on the first via conductor 13A. The heating conditions in step S33c of heating and melting the second plating layer may be the same as the heating conditions in step S23c of heating and melting the first plating layer. This causes the second plating layer to deform in the same way as the first plating layer 30Ac. The conditions for cooling the heated and melted second plating layer in step S34c of cooling the second plating layer to form the second external electrode 20Bc may be the same as the cooling conditions in step S24 of cooling the first plating layer to form the first external electrode 20Ac.

[0140] The multilayer ceramic capacitor 1c according to the fourth preferred embodiment of the present invention is manufactured by the above-described manufacturing method. However, the manufacturing method of the multilayer ceramic capacitor 1c according to the fourth preferred embodiment of the present invention is not limited to the above-described manufacturing method.

[0141] [Manufacturing Method of Mounting Structure of Multilayer Ceramic Capacitor] Fig. 19 is a schematic cross-sectional view showing a state in which the multilayer ceramic capacitor according to the fourth embodiment of the present invention and an electronic component are prepared. Fig. 20 is a schematic cross-sectional view showing a mounting structure of the multilayer ceramic capacitor according to the fourth embodiment of the present invention.

[0142] As shown in FIGS. 19 and 20 , the method for manufacturing the mounting structure of the multilayer ceramic capacitor according to the fourth embodiment of the present invention includes the steps of preparing a multilayer ceramic capacitor 1c manufactured by the above-described method for manufacturing a multilayer ceramic capacitor, and electrically connecting the first external electrodes 20Ac of the multilayer ceramic capacitor 1c to the electronic component 500 by reflow soldering.

[0143] The above-described structure allows the multilayer ceramic capacitor mounting structure 1000c to be manufactured. Furthermore, the above-described structure allows the underfill resin for filling the gap between the capacitor body 10 and the electronic component 500 to be easily provided in the gap.

[0144] The method for manufacturing a mounting structure of a multilayer ceramic capacitor in this embodiment further includes a step of reflow soldering the second external electrodes 20Bc to the electronic component 500, thereby electrically connecting the second external electrodes 20Bc to the electronic component 500. This step can be performed simultaneously with the step of reflow soldering the first external electrodes 20Ac.

[0145] (Additional Note) As described above, the present embodiment includes the following disclosures.

[0146] <1> A capacitor body, a first external electrode, and a second external electrode, wherein the capacitor body includes: a dielectric layer; a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately stacked in a stacking direction with the dielectric layer sandwiched between them; first via conductors electrically connected to the plurality of first internal electrode layers and extending from the inside of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction; and second via conductors electrically connected to the plurality of second internal electrode layers and extending from the inside of the capacitor body to the first main surface, wherein the first external electrode includes: a first base electrode layer provided on the first main surface to cover the first via conductor; and a first surface electrode layer directly covering the first base electrode layer, wherein the second external electrode is provided on the first main surface at a distance from the first external electrode to cover the second via conductor, an outer surface of the first surface electrode layer extends from an edge of the first base electrode layer on the first principal surface so as to be away from the first principal surface;

[0147] <2> The multilayer ceramic capacitor according to <1>, wherein a thickness in the stacking direction of a central portion of the first surface electrode layer in a plane direction parallel to the first main surface is greater than an average thickness of the first surface electrode layer, which is an average thickness from an inner surface, which is a surface of the first surface electrode layer in contact with the first base electrode layer, to the outer surface.

[0148] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the outer surface of the first surface electrode layer includes, in the stacking direction, a first region in contact with the edge and a second region located on the opposite side of the first main surface from the first region, the first region extending such that a cross-sectional area of ​​the first external electrode when viewed from the stacking direction increases with increasing distance from the first main surface, and the second region extending such that a cross-sectional area of ​​the first external electrode when viewed from the stacking direction decreases with increasing distance from the first main surface.

[0149] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the first via conductors and the second via conductors are not exposed from a second main surface of the capacitor body, which is the surface opposite to the first main surface.

[0150] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, further comprising: a third external electrode; and a fourth external electrode; wherein the first via conductor extends from inside the capacitor body to a second main surface that is the opposite side of the first main surface of the capacitor body; the second via conductor extends from inside the capacitor body to the second main surface; the third external electrode includes: a third base electrode layer provided on the second main surface to cover either the first via conductor or the second via conductor; and a third surface electrode layer directly covering the third base electrode layer; the fourth external electrode is provided on the second main surface to cover the other of the first via conductor or the second via conductor, with a gap between it and the third external electrode; and an outer surface of the third surface electrode layer extends from an edge of the third base electrode layer on the second main surface so as to be away from the second main surface.

[0151] <6> The multilayer ceramic capacitor according to <5>, wherein a thickness in the stacking direction of a central portion of the third surface electrode layer in a plane direction parallel to the first principal surface is smaller than a thickness in the stacking direction of a central portion of the first surface electrode layer in a plane direction parallel to the first principal surface.

[0152] <7> A method for manufacturing a multilayer ceramic capacitor, comprising: preparing a capacitor body including a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the dielectric layer sandwiched therebetween, the first via conductor being electrically connected to the plurality of first internal electrode layers and extending from the interior of the capacitor body to a first main surface which is a surface on one side of the capacitor body in the stacking direction, and the second via conductor being electrically connected to the plurality of second internal electrode layers and extending from the interior of the capacitor body to the first main surface; providing a first external electrode including a first base electrode layer provided on the first main surface to cover the first via conductor, and a first surface electrode layer directly covering the first base electrode layer; and providing a second external electrode on the first main surface to cover the second via conductor, with a gap between the first external electrode and the second external electrode, wherein providing the first external electrode comprises: forming a first plating layer on the first base electrode layer by plating; heating and melting the first plating layer; and cooling the heated and melted first plating layer to form the first surface electrode layer.

[0153] <8> A method for manufacturing a mounting structure of a multilayer ceramic capacitor, comprising: preparing a multilayer ceramic capacitor manufactured by the method for manufacturing a multilayer ceramic capacitor according to <7>; and electrically connecting the first surface electrode layer of the multilayer ceramic capacitor to an electronic component by reflow soldering the first surface electrode layer to the electronic component.

[0154] <9> A multilayer ceramic capacitor comprising: a capacitor body; a first external electrode; and a second external electrode, wherein the capacitor body comprises: a dielectric layer; a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked alternately in a stacking direction with the dielectric layer sandwiched between them; first via conductors electrically connected to the plurality of first internal electrode layers and extending from an interior of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction; and second via conductors electrically connected to the plurality of second internal electrode layers and extending from an interior of the capacitor body to the first main surface, wherein the first external electrode is provided on the first main surface to cover the first via conductor; and the second external electrode is provided on the first main surface to be spaced apart from the first external electrode and to cover the second via conductor; and an outer surface of the first external electrode extends from an edge of the first via conductor in the first main surface so as to be away from the first main surface.

[0155] <10> The multilayer ceramic capacitor according to <9>, wherein the outer surface of the first external electrode includes, in the stacking direction, a first region in contact with the edge and a second region located on the opposite side of the first main surface from the first region, the first region extending such that a cross-sectional area of ​​the first external electrode when viewed in the stacking direction increases with increasing distance from the first main surface, and the second region extending such that a cross-sectional area of ​​the first external electrode when viewed in the stacking direction decreases with increasing distance from the first main surface.

[0156] <11> A method for manufacturing a multilayer ceramic capacitor, the method comprising: preparing a capacitor body including a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the dielectric layer sandwiched therebetween, the first via conductor being electrically connected to the plurality of first internal electrode layers and extending from an interior of the capacitor body to a first main surface which is a surface on one side of the capacitor body in the stacking direction, and the second via conductor being electrically connected to the plurality of second internal electrode layers and extending from an interior of the capacitor body to the first main surface; providing a first external electrode on the first main surface to cover the first via conductor; and providing a second external electrode on the first main surface to cover the second via conductor at a distance from the first external electrode, wherein providing the first external electrode includes: forming a first plating layer by plating on the first via conductor in the first main surface; A method for manufacturing a multilayer ceramic capacitor, comprising: heating and melting the first plating layer; and cooling the heated and melted first plating layer to form the first external electrode.

[0157] <12> A method for manufacturing a mounting structure of a multilayer ceramic capacitor, comprising: preparing a multilayer ceramic capacitor manufactured by the method for manufacturing a multilayer ceramic capacitor according to <11>; and reflow soldering the first external electrodes of the multilayer ceramic capacitor to an electronic component, thereby electrically connecting the first external electrodes to the electronic component.

[0158] In the above-described embodiments and examples, configurations that can be combined may be combined with each other.

[0159] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0160] 1, 1a, 1b, 1c, 1m, 1n, 1w, 1x, 1y, 1z Multilayer ceramic capacitor, 10 Capacitor body, 101 First main surface, 102 Second main surface, 103 Peripheral side surface, 11 Dielectric layer, 111 First outer layer portion, 112 Second outer layer portion, 12A, 12Am First internal electrode layer, 12Ah First through hole, 121A, 122A First internal electrode portion, 12B, 12Bm Second internal electrode layer, 12Bh Second through hole, 13A, 13Aa, 13Am, 13An First via conductor, 13B, 13Ba, 13Bm, 13Bn Second via conductor, 20A, 20Ac First external electrode, 20B, 20Bc Second external electrode, 20Ca Third external electrode, 20Da Fourth external electrode, 21A First base electrode layer, 211A Baked electrode layer, 212A First base plating layer, 213A Second base plating layer, 21B Second base electrode layer, 21Ca Third base electrode layer, 21Da Fourth base electrode layer, 22A First surface electrode layer, 22B Second surface electrode layer, 22Ca, 22Cb Third surface electrode layer, 22Da, 22Db Fourth surface electrode layer, 30, 30A, 30Ac First plating layer, 500 Electronic component, 1000, 1000c Mounting structure.

Claims

1. A capacitor body comprising: a first external electrode; and a second external electrode, wherein the capacitor body comprises: a dielectric layer; a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked alternately in a stacking direction with the dielectric layer sandwiched therebetween; a first via conductor electrically connected to the plurality of first internal electrode layers and extending from the inside of the capacitor body to a first main surface which is one side of the capacitor body in the stacking direction; and a second via conductor electrically connected to the plurality of second internal electrode layers and extending from the inside of the capacitor body to the first main surface, wherein the first external electrode comprises: a first base electrode layer provided on the first main surface so as to cover the first via conductor; and a first surface electrode layer directly covering the first base electrode layer, and the second external electrode is provided on the first main surface at a distance from the first external electrode so as to cover the second via conductor, a first surface electrode layer extending from an edge of the first base electrode layer on the first principal surface so as to be away from the first principal surface; 2. The multilayer ceramic capacitor according to claim 1, wherein a thickness in the stacking direction of a central portion of said first surface electrode layer in a plane direction parallel to said first principal surface is greater than an average thickness of said first surface electrode layer, which is an average of a thickness from an inner surface, which is a surface of said first surface electrode layer in contact with said first base electrode layer, to said outer surface.

3. A multilayer ceramic capacitor as claimed in claim 1 or 2, wherein the outer surface of the first surface electrode layer includes, in the stacking direction, a first region in contact with the edge and a second region located on the opposite side of the first main surface as viewed from the first region, the first region extending such that a cross-sectional area of ​​the first external electrode when viewed from the stacking direction increases with increasing distance from the first main surface, and the second region extending such that a cross-sectional area of ​​the first external electrode when viewed from the stacking direction decreases with increasing distance from the first main surface.

4. A multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the first via conductors and the second via conductors are not exposed from a second main surface of the capacitor body, which is the opposite surface to the first main surface.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, further comprising a third external electrode and a fourth external electrode, wherein the first via conductor extends from within the capacitor body to a second main surface which is the opposite side of the first main surface of the capacitor body, the second via conductor extends from within the capacitor body to the second main surface, the third external electrode includes a third base electrode layer provided on the second main surface so as to cover either the first via conductor or the second via conductor, and a third surface electrode layer directly covering the third base electrode layer, the fourth external electrode is provided on the second main surface with a gap between it and the third external electrode and covers the other of the first via conductor or the second via conductor, and the outer surface of the third surface electrode layer extends from an edge of the third base electrode layer on the second main surface so as to be away from the second main surface.

6. The multilayer ceramic capacitor according to claim 5, wherein the thickness in the stacking direction of a central portion of the third surface electrode layer in a plane direction parallel to the first principal surface is smaller than the thickness in the stacking direction of a central portion of the first surface electrode layer in a plane direction parallel to the first principal surface.

7. A method for manufacturing a multilayer ceramic capacitor, comprising: preparing a capacitor body including a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the dielectric layer sandwiched therebetween, the first via conductor being electrically connected to the plurality of first internal electrode layers and extending from the inside of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction, and the second via conductor being electrically connected to the plurality of second internal electrode layers and extending from the inside of the capacitor body to the first main surface; providing a first external electrode including a first base electrode layer provided on the first main surface so as to cover the first via conductor, and a first surface electrode layer directly covering the first base electrode layer; and providing a second external electrode on the first main surface so as to cover the second via conductor, with a gap between the first external electrode and the first external electrode, wherein providing the first external electrode comprises: forming a first plating layer on the first base electrode layer by plating; heating and melting the first plating layer; and cooling the heated and melted first plating layer to form the first surface electrode layer.

8. A method for manufacturing a mounting structure of a multilayer ceramic capacitor, comprising: preparing a multilayer ceramic capacitor manufactured by the method for manufacturing a multilayer ceramic capacitor as defined in claim 7; and electrically connecting the first surface electrode layer of the multilayer ceramic capacitor to an electronic component by reflow soldering the first surface electrode layer to the electronic component.

9. A multilayer ceramic capacitor comprising: a capacitor body, a first external electrode, and a second external electrode, wherein the capacitor body comprises: a dielectric layer; a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked alternately in a stacking direction with the dielectric layer sandwiched between them; a first via conductor electrically connected to the plurality of first internal electrode layers and extending from an interior of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction; and a second via conductor electrically connected to the plurality of second internal electrode layers and extending from an interior of the capacitor body to the first main surface, wherein the first external electrode is provided on the first main surface so as to cover the first via conductor, and the second external electrode is provided on the first main surface at a distance from the first external electrode so as to cover the second via conductor, and an outer surface of the first external electrode extends away from an edge of the first via conductor in the first main surface toward the first main surface.

10. The multilayer ceramic capacitor as described in claim 9, wherein the outer surface of the first external electrode includes, in the stacking direction, a first region in contact with the edge and a second region located on the opposite side of the first main surface as viewed from the first region, the first region extends such that the cross-sectional area of ​​the first external electrode when viewed from the stacking direction increases with increasing distance from the first main surface, and the second region extends such that the cross-sectional area of ​​the first external electrode when viewed from the stacking direction decreases with increasing distance from the first main surface.

11. A method for manufacturing a multilayer ceramic capacitor, comprising: preparing a capacitor body including a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction with the dielectric layer sandwiched therebetween, the first via conductor being electrically connected to the plurality of first internal electrode layers and extending from an interior of the capacitor body to a first main surface which is one surface of the capacitor body in the stacking direction, and the second via conductor being electrically connected to the plurality of second internal electrode layers and extending from an interior of the capacitor body to the first main surface; providing a first external electrode on the first main surface so as to cover the first via conductor; and providing a second external electrode on the first main surface so as to cover the second via conductor at a distance from the first external electrode, wherein providing the first external electrode comprises: forming a first plating layer by plating on the first via conductor in the first main surface; A method for manufacturing a multilayer ceramic capacitor, comprising: heating and melting the first plating layer; and cooling the heated and melted first plating layer to form the first external electrode.

12. A method for manufacturing a mounting structure for a multilayer ceramic capacitor, comprising: preparing a multilayer ceramic capacitor manufactured by the method for manufacturing a multilayer ceramic capacitor as defined in claim 11; and electrically connecting the first external electrode of the multilayer ceramic capacitor to an electronic component by reflow soldering the first external electrode to the electronic component.

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