Memory system, memory controller, external memory, memory control method, and operation method

Abstract

A memory system (100a) comprises: a memory controller (130); and an external memory (140) connected to the memory controller (130). The memory controller (130) transmits, to the external memory (140), a read command or a write command, a data size, an address interval that is an interval between addresses of continuous pieces of data of said data size, and a head address. The external memory (140) performs reading or writing for accessing the data on the basis of the data size, the address interval, and the head address so that the access conforms to the read command or the write command.

Description

Memory system, memory controller, external memory, memory control method, and operation method

[0001] The present disclosure relates to a memory system, a memory controller, an external memory, a memory control method, and an operation method.

[0002] In recent years, memory systems capable of improving access performance have been studied (see, for example, Patent Document 1).

[0003] JP 2024-103198 A

[0004] In some cases, data at discontinuous addresses is accessed in a memory, and in such cases, it is desirable to prevent a decrease in access efficiency.

[0005] Therefore, the present disclosure provides a memory system, a memory controller, an external memory, a memory control method, and an operation method that can suppress deterioration in access efficiency when accessing data at discontinuous addresses.

[0006] A memory system according to one aspect of the present disclosure is a memory system comprising a memory controller and an external memory connected to the memory controller, wherein the memory controller transmits a read command or a write command, a data size, an address interval which is the address interval between consecutive data of the data size, and a starting address to the external memory, and the external memory reads or writes data based on the data size, the address interval, and the starting address so that the access is in accordance with the read command or the write command.

[0007] A memory controller according to one aspect of the present disclosure is a memory controller in the above memory system.

[0008] An external memory according to one aspect of the present disclosure is an external memory in the above memory system.

[0009] A memory control method according to one aspect of the present disclosure is a memory control method executed by a memory controller in the above-described memory system, which transmits a read command or a write command, a data size, an address interval which is the interval between consecutive data of the data size, and a starting address to an external memory.

[0010] An operating method according to one aspect of the present disclosure is an operating method executed by an external memory in the above-described memory system, which obtains a read command or a write command, a data size, an address interval which is the interval between consecutive data of the data size, and a starting address from a memory controller, and reads or writes data based on the data size, the address interval, and the starting address so that the access is in accordance with the read command or the write command.

[0011] According to one aspect of the present disclosure, it is possible to realize a memory system or the like that can suppress a decrease in access efficiency when accessing data at discontinuous addresses.

[0012] FIG. 1 is a diagram illustrating a configuration of an information processing system according to an embodiment. FIG. 2 is a diagram illustrating a configuration of a user device according to an embodiment. FIG. 3 is a diagram illustrating commands output by a memory controller according to an embodiment and data to be read. FIG. 4 is a sequence diagram illustrating the operation of a memory system according to an embodiment. FIG. 5 is a diagram schematically illustrating signals on a transmission path transmitted in a memory system according to an embodiment. FIG. 6A is a diagram illustrating a data reading method for evaluating the effects of the embodiment. FIG. 6B is a diagram illustrating the effects when a compressed image is read according to an embodiment. FIG. 7 is a diagram illustrating the effects when a non-compressed image is read according to an embodiment. FIG. 8A is a sequence diagram illustrating the operation of a memory system according to a first modification of the embodiment. FIG. 8B is a diagram schematically illustrating information transmitted in a memory system according to the first modification of the embodiment. FIG. 9A is a diagram illustrating reading when the address interval is positive according to a second modification of the embodiment. FIG. 9B is a diagram illustrating drawing when the address interval is positive according to the second modification of the embodiment. FIG. 10A is a diagram illustrating reading when the address interval is negative according to the second modification of the embodiment. FIG. 10B is a diagram for explaining drawing when the address interval is negative according to the second modification of the embodiment. FIG. 11 is a diagram for explaining a first example of a command output by a memory controller according to the third modification of the embodiment and data to be read. FIG. 12 is a diagram for explaining a second example of a command output by a memory controller according to the third modification of the embodiment and data to be read. FIG. 13A is a first diagram for explaining processing executed in XR glasses. FIG. 13B is a second diagram for explaining processing executed in XR glasses. FIG. 13C is a third diagram for explaining processing executed in XR glasses. FIG. 14 is a diagram for explaining data communication of a serial interface. FIG. 15 is a diagram for explaining data read by a memory controller in a conventional example. FIG. 16 is a diagram schematically showing a signal transmitted on a transmission path in a memory system in a conventional example.

[0013] (Background to the Invention of the Present Disclosure) Prior to describing embodiments of the present disclosure, the background to the invention of the present disclosure will be described with reference to FIGS. 13A to 16. Hereinafter, as an example of an information processing system, a method for reading two-dimensional image data (2D image data) when the 2D image data is displayed as a three-dimensional image using XR (Cross Reality / Extended Reality) glasses will be described. The XR glasses include an external memory that stores the 2D image data and a memory controller that controls writing and reading of the 2D image data to and from the external memory. The memory controller and the external memory constitute a memory system.

[0014] 13A to 13C are diagrams for explaining the processes executed by the XR glasses.

[0015] 13A is a diagram illustrating how 2D image data is saved (stored) in an external memory in XR glasses. A memory controller acquires the 2D image data from, for example, a host device and saves the acquired 2D image data in the external memory. The 2D image data is stored in the external memory so that the position of each pixel of the 2D image data corresponds to the position of each address in the memory area where the image data is stored.

[0016] 13B is a diagram for explaining how stored 2D image data is read from an external memory. In order to output a 3D image (to project the 2D image into a 3D image), the external memory sequentially reads data in a diagonal direction along a parallelogram region as shown in FIG. 13B in response to a command from a memory controller, for example.

[0017] FIG. 13C is a diagram illustrating the display of a 3D image using the read data. A 3D image is realized by drawing a distorted image of a 2D image represented by 2D image data on a display. For example, a distorted image can be drawn on a display by drawing data read obliquely in a straight line. The arrow in FIG. 13C indicates the scanning direction of drawing. In this way, the XR glasses are configured to distort a 2D image and transform it into a three-dimensional shape before displaying it.

[0018] FIG. 14 is a diagram for explaining data communication of a serial interface.

[0019] The XR glasses include a memory controller 1100 and an external memory 1200. The memory controller 1100 is realized by, for example, a system-on-chip (SoC) based processor. The external memory 1200 is realized by a dynamic random access memory (DRAM) connected to the memory controller 1100. The external memory 1200 may also be realized by, for example, a hyperRAM or the like.

[0020] The memory controller 1100 and external memory 1200 may be connected via a serial interface or a parallel interface. A serial interface connection offers the advantages of fewer transmission paths, reduced implementation area, and compactness, but reduces access efficiency to discontinuous addresses. On the other hand, a parallel interface connection provides the same access efficiency to discontinuous addresses, but requires a larger number of transmission paths, making compactness difficult.

[0021] Therefore, the inventors of the present application have conducted extensive research into memory systems and the like that can suppress deterioration in access efficiency for discontinuous data, for example, memory systems and the like that can improve significantly deteriorating access efficiency while enjoying the benefits of a serial interface, and have devised the memory systems and the like shown below.

[0022] In the following, an example will be shown in which the memory controller 1100 and the external memory 1200 are connected via a serial interface. In a serial interface, commands and addresses from the memory controller 1100 and data from the external memory 1200 (e.g., a serial interface DRAM) are communicated over the same transmission path (signal line). In this specification, "serial" means that commands, addresses, and data are communicated over the same transmission path.

[0023] Here, a decrease in access efficiency when the memory controller 1100 and the external memory 1200 are connected via a serial interface will be described with reference to FIGS.

[0024] Fig. 15 is a diagram for explaining data read by the memory controller 1100 in the conventional example. Fig. 15 schematically shows a memory area in the external memory 1200 that stores 2D image data.

[0025] 15 illustrates a case where data in a parallelogram area as shown in FIG. 13B (data at addresses marked with circles) is read from external memory 1200 using memory controller 1100 in a conventional example. In FIG. 15, for identification purposes, data at start address A0 is indicated by circles with diagonal hatching slanting downward to the right (six consecutive data), data at start address A1 is indicated by circles with diagonal hatching slanting downward to the left (six consecutive data), and data at start address A2 is indicated by circles with linear hatching slanting upward and downward (six consecutive data). Note that consecutive data is a collection of data whose addresses are consecutive in the row direction (horizontal direction on the paper).

[0026] Here, an example will be described in which three rows of data at starting addresses A0, A1, and A2 are read from the external memory 1200. The six consecutive data items (DAT0) at starting address A0, the six data items (DAT1) at starting address A1, and the six data items (DAT2) at starting address A2 are data items on different rows and are discontinuous with each other (discontinuous in the row direction).

[0027] 16 is a diagram schematically illustrating signals transmitted on a transmission line in a conventional memory system, in which a memory controller 1100 (the host shown in FIG. 16) reads data at start addresses A0 to A2 from an external memory 1200 (the DRAM shown in FIG. 16).

[0028] First, the memory controller 1100 transmits a read command to the external memory 1200, including information that the starting address is A0, in order to read consecutive data at the starting address A0, and the external memory 1200 transmits consecutive data DAT0 at the starting address A0 to the memory controller 1100. In this way, in the serial interface transmission protocol, the memory controller 1100 specifies the starting address along with the command to read data. Here, a read latency (the time required for the read process) occurs from the transmission of the command until the transmission of the consecutive data DAT0. The read command is a command for reading data from the external memory 1200.

[0029] Next, the memory controller 1100 transmits a read command including information that the starting address is A1 to the external memory 1200 in order to read the consecutive data at the starting address A1, and the external memory 1200 transmits the consecutive data DAT0 at the starting address A1 to the memory controller 1100. Here, a read latency occurs from the transmission of the command until the transmission of the consecutive data DAT1.

[0030] Thus, in the past, to access discontinuous data, it was necessary to send a read command for each piece of consecutive data, resulting in a read latency equal to the number of read commands sent, as well as a recovery time, which is the waiting time between commands.

[0031] In this way, conventionally, when multiple commands are sent to access discontinuous data, the waiting time (multiple read latencies and multiple recovery times) increases, deteriorating throughput, and thus access efficiency deteriorates.

[0032] These general or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a non-transitory recording medium such as a computer-readable CD-ROM, or as any combination of the system, method, integrated circuit, computer program, or recording medium. The program may be pre-stored in the recording medium, or may be supplied to the recording medium via a wide area communication network including the Internet.

[0033] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0034] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in independent claims are described as optional components.

[0035] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0036] Furthermore, in this specification, terms indicating relationships between elements such as "same," as well as numerical values ​​and numerical ranges, are not expressions that express only the strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about several percent (or about 10%).

[0037] (Embodiment) Hereinafter, an information processing system according to the present embodiment will be described with reference to FIGS.

[0038] 1. Configuration of Information Processing System First, the configuration of an information processing system according to this embodiment will be described with reference to Figures 1 to 3. Figure 1 is a diagram showing the configuration of an information processing system 1 according to this embodiment.

[0039] As shown in Fig. 1, the information processing system 1 includes a user device 10 and an information terminal 20. The information processing system 1 is an image display system in which the user device 10 outputs 2D image data (original image (2D) shown in Fig. 1) received from the information terminal 20 as a 3D image (output image (3D) shown in Fig. 1). Note that the communication method between the user device 10 and the information terminal 20 is not particularly limited, and may be wired communication or wireless communication. Furthermore, the communication standard is also not particularly limited.

[0040] The user device 10 is a display device capable of displaying 3D images from 2D image data. The user device 10 may be, for example, a wearable device or a portable mobile device that can be worn by a user. The wearable device may be, for example, an XR device (e.g., XR glasses) for realizing cross reality. Cross reality is a general term for technologies that enable perception of things that do not exist in reality by merging the real world and the virtual world, and includes technologies such as AR (Augmented Reality), MR (Mixed Reality), and VR (Virtual Reality). In other words, the XR device may be an AR device for realizing an augmented reality space, an MR device for realizing a mixed reality space, or a VR device for realizing a virtual reality space. Examples of such XR devices include, but are not limited to, a head-mounted display (HMD), AR glasses, and MR goggles.

[0041] The user device 10 is not limited to being an XR device, but may be any device that executes a process to read out the 2D image data stored as shown in FIG. 13A along a diagonal direction like a parallelogram region as shown in FIG. 13B, or to write the diagonal data in the 2D image data so that it forms a straight line in the memory (writes a distorted image into the memory).

[0042] The information terminal 20 functions as a host device and transmits 2D image data to the user device 10. In the present embodiment, the information terminal 20 is a portable information terminal such as a smartphone or a tablet terminal, but may also be a stationary information terminal such as a PC (Personal Computer).

[0043] The configuration of the user device 10 will now be described with further reference to Figures 2 and 3. Figure 2 is a diagram showing the configuration of the user device 10 according to this embodiment. Note that Figure 2 shows an exemplary configuration of the user device 10, and the configuration of the user device 10 is not limited to that shown in Figure 2.

[0044] 2, the user device 10 includes a control device 100 and a display device 200. The user device 10 may further include a sensor (e.g., a gyro sensor) for detecting the tilt of the user's face when the user device 10 is attached to the user.

[0045] The control device 100 is an information processing device that controls the 3D images displayed by the display device 200. The control device 100 includes a communication circuit 110, a processor 120, a memory controller 130, and an external memory 140. The memory controller 130 and the external memory 140 constitute a memory system 100a.

[0046] The communication circuitry 110 is a circuit that enables the control device 100 to communicate with the information terminal 20. The communication circuitry 110 acquires 2D image data from the information terminal 20 via communication.

[0047] The processor 120 controls each component of the control device 100. The processor 120 controls various processes for displaying a 3D image on the display device 200 using 2D image data acquired from the information terminal 20. The processor 120 stores the 2D image data acquired via the communication circuit 110 in the external memory 140 by controlling the memory controller 130, and when the display device 200 displays a 3D image, the processor 120 reads data for displaying the 3D image from the external memory 140 by controlling the memory controller 130 and outputs the data to the display device 200.

[0048] When displaying a 3D image, the processor 120 outputs, for example, a read command, a data size, an address interval, a start address, and an end address to the memory controller 130. The read command is a command for reading data from the external memory 140.

[0049] FIG. 3 is a diagram illustrating commands output by the memory controller 130 according to this embodiment and data to be read. FIG. 3 schematically illustrates a memory area storing 2D image data within the storage unit 142 (storage area) of the external memory 140. A block 142a, also referred to as a cell, represents a storage element or a collection of a certain number of cells (or storage elements). The external memory 140 is, for example, a memory in which the blocks 142a are arranged two-dimensionally, but is not limited to this. The arrows in FIG. 3 indicate address intervals S.

[0050] 3 indicates the block 142a in the parallelogram region to be read, but for convenience, the following description will be given of an example in which data of 18 hatched circles is read. The data of the block 142a with six hatched circles from the right down constitutes one continuous data set (DAT0), the data of the block 142a with six hatched circles from the left down constitutes one continuous data set (DAT1), and the data of the block 142a with six hatched circles from the top down constitutes one continuous data set (DAT2). It is assumed that data is read sequentially from left to right in the row direction and from top to bottom in the column direction.

[0051] 3, the data size W is the number of data items to be read (the number of blocks 142a) among the multiple data items arranged consecutively in the row direction on the storage unit 142. In the example of FIG. 3, the data size W is 6.

[0052] The address interval S indicates the distance between addresses of consecutive data of data size W on the storage unit 142. The address interval S is the distance (the number of blocks 142a) between the start address of one consecutive data and the start address of the next consecutive data. In the example of FIG. 3, the address interval between DAT0 and DAT1 and the address interval between DAT1 and DAT2 are both 28, which is the same. In this embodiment, the address interval S is greater than 0.

[0053] The leading address A0 indicates the address of the block 142a that is the leading block when reading data.

[0054] The end address Af indicates the address of the block 142a that is the end when reading data.

[0055] In addition, when the processor 120 displays a 2D image using 2D image data, the processor 120 may read the data using a conventional command (see, for example, FIG. 16).

[0056] Furthermore, when the processor 120 writes an image obtained by distorting an image indicated by the 2D image data to the external memory 140, the processor 120 outputs, for example, a write command, a data size, an address interval, a start address, and an end address to the memory controller 130. The write command is a command for writing data to the external memory 140.

[0057] The processor 120 may also determine the data size, address interval, start address, and end address as appropriate based on the detection result of the tilt of the face of the user wearing the user device 10. In addition, in a user device 10 that displays different images for the left and right eyes, the processor 120 may set different data sizes, address intervals, start addresses, and end addresses for the left and right eyes.

[0058] 2 again, the memory controller 130 is a control circuit that controls writing of data to the external memory 140 and reading of data from the external memory 140. The memory controller 130 controls writing and reading of data under the control of the processor 120, for example.

[0059] The memory controller 130 includes a generating unit 131 , a control unit 132 , and a storage unit 133 .

[0060] The generation unit 131 is a processing unit that generates a read command and a write command based on the command, data size W, address interval S, and starting address A0 acquired from the processor 120. When reading data diagonally, the generation unit 131 generates a command that enables reading of data diagonally in one output, and outputs the command to the external memory 140.

[0061] The data size W and the address interval S are not limited to being determined by the processor 120, but may be determined by the generation unit 131. For example, the generation unit 131 may determine the data size W and the address interval S corresponding to the face inclination using a table in which the face inclination is associated with a set of the data size W and the address interval S.

[0062] The control unit 132 is a processing unit that controls writing of data to the external memory 140 and reading of data from the external memory 140. The control unit 132 controls chip select (chip select signal) based on, for example, the end address Af acquired from the processor 120. The control unit 132 turns on chip select (chip select signal), indicating that reading is permitted, only while data is being read from the start address A0 to the end address Af.

[0063] The storage unit 133 is a storage device that stores various types of information. The storage unit 133 may temporarily store, for example, 2D image data to be stored in the external memory 140 and image data read from the external memory 140. For example, the storage unit 133 may function as a bus buffer for inputting and outputting data. The storage unit 133 may also store the above-mentioned table that is used when the generation unit 131 determines the data size W and the address interval S. The storage unit 133 may be realized by, for example, but is not limited to, a semiconductor memory.

[0064] The external memory 140 is a storage device that stores 2D image data, and performs reading or writing to access data based on a data size W, an address interval S, and a starting address A0, in accordance with a read command or a write command. The external memory 140 is realized by a semiconductor memory, and in this embodiment, by a DRAM. Here, "external" means that the processor 120 does not have a built-in memory. In other words, the external memory 140 is a memory separate from the built-in memory of the processor 120. The external memory 140 includes a decoder 141, a storage unit 142, and a register 143.

[0065] The decoder 141 decodes a command from the memory controller 130 and executes a write or read process according to the command. The decoder 141 is configured to be able to distinguish, for example, between a conventional command and a command according to this embodiment (a proposed command). For example, if the command includes more than a predetermined amount of information (for example, a data size W and an address interval S), or if the command includes information indicating that it is a proposed command, the decoder 141 executes a read process using the proposed command.

[0066] The storage unit 142 is a storage circuit (storage area) that stores data such as image data.

[0067] The register 143 is also called a configuration register and is a storage circuit built into the external memory 140 .

[0068] The display device 200 is a display that displays a 3D image. In the present embodiment, the display device 200 is an eyeglass-type display (so-called smart glasses) such as AR glasses, and is an optically transmissive device that allows a user to view a 3D image displayed on the display and simultaneously view an outside scene directly, but is not limited to this.

[0069] In the memory system 100a, the memory controller 130 and the external memory 140 communicate with each other via a serial interface, and are connected to each other via a transmission line, for example. The memory controller 130 and the external memory 140 are further connected to each other via one transmission line for chip select and two transmission lines (clock lines) for synchronous clocks.

[0070] [2. Operation of Memory System] Next, the operation of the memory system 100a configured as described above will be described with reference to Figures 4 and 5. Figure 4 is a sequence diagram showing the operation (memory control method, operation method (operation method of the external memory 140)) of the memory system 100a according to this embodiment. Figure 4 shows the operation when 2D image data has already been stored in the storage unit 142 and data is read from the storage unit 142 along a parallelogram region to display a 3D image. Figure 5 is a diagram schematically showing signals on a transmission path transmitted in the memory system 100a according to this embodiment.

[0071] As shown in FIG. 4, first, the generator 131 of the memory controller 130 generates a read command including a data size W, an address interval S, and a starting address A0 (S11).

[0072] Next, the generator 131 outputs the generated read command to the external memory 140, and the external memory 140 receives the read command from the memory controller 130 (S12).

[0073] As shown in Fig. 5, the generation unit 131 of the memory controller 130 adds at least one of the data size W and the address interval S (in the example of Fig. 5, both the data size W and the address interval S) and the starting address A0 to a read command and outputs the command to the external memory 140. By generating a command such as that shown in Fig. 5 (a compact instruction format with little overhead), the generation unit 131 can read multiple discontinuous consecutive data by simply outputting the command once. Note that the read command does not include information about the end address Af.

[0074] 4, when the decoder 141 of the external memory 140 receives a read command, it determines whether the read command is a conventional command or a command of the proposed method, and if it determines that the read command is a command of the proposed method, it reads data based on the data size W, address interval S, and starting address A0 included in the command (S13). The decoder 141 can read multiple discontinuous data by simply receiving one read command by sequentially accessing data of data size W starting from the address calculated by the following equation 1 while incrementing n (n is an integer greater than or equal to 0) by 1, starting from 0. n is a variable (increment variable).

[0075] Address An=A0+nS (Equation 1)

[0076] Using FIG. 3 as an example, if the starting address is A0, the data size W is 6, and the address interval S is 28, the decoder 141 first reads out consecutive data DAT0, which is six consecutive pieces of data including the starting address A0, and then sets an address (A0+S) 28 addresses ahead of the starting address A0 as the starting address of the next consecutive data (next starting address) to read out consecutive data DAT1, which is six consecutive pieces of data including that starting address, and then sets an address (A0+2S) 28 addresses ahead of the next starting address as the starting address of the next consecutive data to read out consecutive data DAT2, which is six consecutive pieces of data including that starting address.

[0077] Referring back to FIG. 4, the external memory 140 outputs the read data to the memory controller 130, and the memory controller 130 acquires the data from the external memory 140 (S14).

[0078] 5, the external memory 140 outputs consecutive data DAT0 with a starting address A0, consecutive data DAT1 with a starting address A0+S, and consecutive data DAT2 with a starting address A0+2S to the memory controller 130. The external memory 140 continues to sequentially transmit data at address A0+nS (n=0, 1, 2, ...) up to a data size W. In this embodiment, the consecutive data DAT0, DAT1, and DAT2 all have the same data size W.

[0079] In this way, the memory controller 130 outputs the command only once, and the external memory 140 returns the data (a plurality of discontinuous consecutive data) in one go.

[0080] 4 again, the memory controller 130 outputs the data from the external memory 140 to the processor 120 (S15). This enables the processor 120 to display a 3D image on the display device 200 using the 2D image data stored in the storage unit 142.

[0081] [3. Effects] The effect of improving access efficiency in the memory system 100a configured as described above will be described with reference to Figures 6A to 7. Figure 6A is a diagram for explaining a data reading method when evaluating the effects of this embodiment.

[0082] As shown in FIG. 6A, the effect of reading data at an angle of 90 degrees with respect to the original image (2D image) will be verified.

[0083] Fig. 6B is a diagram for explaining the effect of reading a compressed image according to the present embodiment. The conventional method shown in Fig. 6B is a method of outputting a command for each consecutive data as shown in Fig. 16, while the proposed method is a method of outputting a command only once to read multiple consecutive data as shown in Fig. 5.

[0084] As shown in FIG. 6B, the proposed method can reduce the time other than data exchange. For example, the time required to read one frame of data can be reduced by 51% compared to the conventional method.

[0085] FIG. 7 is a diagram for explaining the effect of reading out an uncompressed image according to this embodiment.

[0086] As shown in Figure 7, the proposed method can reduce the time other than data exchange. For example, the time required to read data per frame can be reduced by 94% compared to the conventional method.

[0087] In conventional methods, commands are output more frequently for uncompressed images than for compressed images, so the proposed method significantly improves access efficiency, especially when reading uncompressed images.

[0088] (Variations of the Embodiments) Variations of the embodiments will be described below with reference to Figures 8A to 12. Note that the following description will focus on differences from the embodiments, and descriptions of content that is the same as or similar to the embodiments will be omitted or simplified. Furthermore, the following description will use the reference numerals of the information processing system 1 of the embodiments.

[0089] (First Modification of the Embodiment) A memory system 100a according to this modification will be described with reference to Fig. 8A and Fig. 8B. Fig. 8A is a sequence diagram showing the operation (memory control method, operating method) of the memory system 100a according to this modification.

[0090] 8A, first, the generation unit 131 of the memory controller 130 generates a write command (register write command) including a data size W and an address interval S (S21). The generation unit 131 generates the register write command based on, for example, information from the processor 120. The register write command here is a command (Reg Write shown in FIG. 8B, which will be described later) for storing the data size W and the address interval S in the register 143.

[0091] In step S21, it is sufficient that a write command including at least one of the data size W and the address interval S is generated.

[0092] Next, the generation unit 131 outputs the generated register write command to the external memory 140, and the external memory 140 receives the register write command from the memory controller 130 (S22).

[0093] Next, the register 143 stores the data size W and address interval S acquired from the memory controller 130 in the external memory 140 (S23). That is, before acquiring a read command for reading out the 2D image data, the data size W and address interval S corresponding to the 2D image data are written in advance to the register 143.

[0094] In this manner, in this modification, a process is executed in which at least one of the data size W and the address interval S is written in advance to the register 143 of the external memory 140 .

[0095] FIG. 8B is a diagram schematically showing information transmitted in the memory system 100a according to this modification.

[0096] 8B , the generation unit 131 of the memory controller 130 adds at least one of the data size W and the address interval S (in the example of FIG. 8B , both the data size W and the address interval S) and the starting address A0 to a write command and outputs the write command to the external memory 140. By generating a command such as that shown in FIG. 8B , the generation unit 131 can store at least one of the data size W and the address interval S in the register 143 before outputting a read command. The following describes the operation when both the data size W and the address interval S are stored in the register 143.

[0097] 8A again, next, the generator 131 of the memory controller 130 generates a read command including the starting address A0 (S24). The generator 131 generates the read command based on information from the processor 120, for example.

[0098] Next, the generator 131 outputs the generated read command to the external memory 140, and the external memory 140 acquires the read command from the memory controller 130 (S25).

[0099] When the decoder 141 of the external memory 140 receives a read command, it determines whether the read command is a conventional command or a command of the proposed method, and if it determines that the read command is a command of the proposed method, it reads data based on the leading address A0 included in the command and the data size W and address interval S pre-stored in the register 143 (S26). The decoder 141 sequentially accesses data of data size W starting from address An=A0+nS while incrementing n (n is an integer equal to or greater than 0) by 1 from 0, thereby reading multiple discontinuous data in response to one read command.

[0100] For example, when the decoder 141 acquires a read command, if at least one of the data size W and the address interval S is stored in the register 143, the decoder 141 may determine that the read command is a command of the proposed method, and if neither the data size W nor the address interval S is stored in the register 143 (for example, if "0" is stored), the decoder 141 may determine that the read command is a command of the conventional method. In this way, the decoder 141 may determine which method the read command is based on the information stored in the register 143 at the time the read command is acquired.

[0101] Steps S27 and S28 are the same processes as steps S14 and S15 shown in FIG. 5, and the description thereof will be omitted.

[0102] This reduces the amount of data in the read command, and also makes it possible to read data using a method that is highly compatible with the existing HyperRAM standard.

[0103] (Second Modification of the Embodiment) A memory system 100a according to this modification will be described with reference to Figures 9A to 10B. In the above embodiment, the case where the address interval S is a positive value (S > 0) was described, but in this modification, the case where the address interval S can take a negative value (S < 0) will be described. The starting address is identified using An = A0 + nS (Equation 1) used in the embodiment.

[0104] 9A and 9B are diagrams for explaining readout and writing operations when the address interval S is positive, respectively, according to this modified example.

[0105] 9A, when memory access is performed to a region of a parallelogram sloping upward to the right, if the address interval S is positive, the read order will be the order of the arrows (order going downward to the left), which is the same as the read order shown in FIG.

[0106] 9B, if the processor 120 were to draw the data read from the external memory 140 by the memory controller 130 in the order of reading without performing an inversion operation, the display would be inverted horizontally. Therefore, an operation to invert the display is required, but this operation imposes a processing load on the processor 120.

[0107] Therefore, a reading method that can omit the inversion operation by making the read order and the writing order the same will be described with reference to FIGS. 10A and 10B.

[0108] 10A and 10B are diagrams for explaining readout and writing operations when the address interval S is negative according to this modification.

[0109] As shown in Figure 10A, when memory access is performed to an area of ​​a parallelogram sloping upward to the right, if the address interval S is negative, the read order will be the order of the arrow (order heading upward to the upper right). This is the reverse order of the read order shown in Figure 3, etc. In this way, the address interval S may take a negative integer.

[0110] As shown in Figure 10B, by making the address interval S negative, the processor 120 can draw the data read from the external memory 140 by the memory controller 130 in the read order without performing any inversion calculations, without the display being reversed left to right.

[0111] In this way, memory access is performed in the same direction as the drawing direction, making it possible to draw without performing inversion calculations.

[0112] (Third Modification of the Embodiment) A memory system 100a according to this modification will be described with reference to Figures 11 and 12. In the above embodiment, an example has been described in which the data size W is a common value for each piece of consecutive data, and the address interval S is a common value for each piece of consecutive data, but at least one of the data size W and the address interval S is not limited to being a common value. Below, a case in which the address interval S is not a common value will be described with reference to Figure 11, and a case in which the data size W is not a common value will be described with reference to Figure 12.

[0113] 11 is a diagram illustrating a first example of commands output by the memory controller 130 according to this modification and data to be read out. In FIG. 11, an arrow indicating that the address interval S is 28 is shown by a solid line, an arrow indicating that the address interval S is 27 is shown by a dashed line, and an arrow indicating that the address interval S is 26 is shown by a dashed line.

[0114] As shown in Fig. 11, the address interval S may be a function of the variable n. Fig. 11 shows data that is read when the data size W is 10 and the address interval S is a value calculated by the following equation 2.

[0115] S(n)=30-n...(Formula 2)

[0116] The parameters of the function S(n) can be set by the memory controller 130. For example, the parameters may be included in the read command and output, or may be stored in the register 143 in advance.

[0117] This allows the address interval S to be different for each row, making it possible to access memory to areas with distortion other than a parallelogram with a single read command. Note that the address interval S is not limited to Equation 2, and may be any function that includes the variable n.

[0118] FIG. 12 is a diagram for explaining a second example of commands output by the memory controller 130 according to this modification and data to be read.

[0119] 12, the data size W may be a function of the variable n. Fig. 12 shows data that is read when the data size W is a value calculated by the following formula 3 and the address interval S is 30.

[0120] W(n)=5×n...(Formula 3)

[0121] The parameters of the function W(n) can be set by the memory controller 130. For example, the parameters may be included in a read command and output, or may be stored in the register 143 in advance.

[0122] This allows the data size W to be different for each row, making it possible to access memory in areas other than parallelograms, such as trapezoids, with a single read command. Note that the data size W is not limited to Equation 3, and may be any function that includes the variable n.

[0123] At least one of the data size W and the address interval S is not limited to being a function of the variable n. At least one of the data size W and the address interval S may be a function including another variable (for example, the position of the row to be accessed (which row number)), or may be a function including another variable.

[0124] (Other Embodiments) As described above, memory systems according to one or more aspects have been described based on the embodiment and variations 1 to 3 of the embodiment (embodiments, etc.), but the present disclosure is not limited to these embodiments, etc. As long as they do not deviate from the spirit of the present disclosure, various modifications that a person skilled in the art can conceive of to the present embodiment and forms constructed by combining components of different embodiments may also be included in the present disclosure.

[0125] For example, in the above-described embodiments, examples have been described in which the command (command format) of the present disclosure is used for the read command output by the memory controller 130. However, the command (command format) of the present disclosure may also be used for the write command. When writing 2D image data to the external memory 140, the memory controller 130 may add a data size W, an address interval S, and a starting address A0 to the write command and output the write command to the external memory 140. The external memory 140 stores the 2D image data in a memory area using the data size W, the address interval S, and the starting address A0. This allows image data representing an image obtained by previously distorting a 2D image to be stored in the external memory 140. In this case, the memory controller 130 can read data for displaying a 3D image using a conventional read command such as that shown in FIG. 16. Furthermore, the memory controller 130 may add multiple sets of the data size W, the address interval S, and the starting address A0 to the write command to accommodate multiple tilts of the user's face.

[0126] In the above embodiments, an example has been described in which data of a data size starting from address An=A0+nS is sequentially accessed while incrementing n by 1 from 0. However, the present invention is not limited to this. n may be incremented by 1 from an integer other than 0, or may be incremented by a numerical value other than 1. Furthermore, for example, variable n may be a fixed value. Furthermore, the external memory 140 may specify a starting address without using variable n. For example, the external memory 140 may use address A0 as one starting address, and an address obtained by adding or subtracting address interval S from address A0 as another starting address.

[0127] In the above-described embodiment, the memory system 100a is built into the user device 10, but the present invention is not limited to this. For example, the memory system 100a may be realized as a standalone device. Furthermore, the memory controller 130 and the external memory 140 that constitute the memory system 100a may each be realized as standalone devices.

[0128] Furthermore, in the above-described embodiment, the data to be written to and read from the external memory 140 is image data, but the data to be written to and read from the external memory 140 may be data other than image data.

[0129] Furthermore, in the above embodiment and the like, an example has been described in which the above commands are used in communication via a serial interface, but the above commands may also be used in communication via a parallel interface, for example.

[0130] In addition, in the second modification of the above embodiment, it has been described that the address interval S may be negative, but this is not limiting, and for example, the variable n may take a negative value. For example, it is sufficient if either the address interval S or the variable n is negative.

[0131] In the above embodiments, each component may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component. Each component may be realized by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0132] The order in which the steps in the flowchart are executed is merely an example for specifically explaining the present disclosure, and other orders may be used. Some of the steps may be executed simultaneously (in parallel) with other steps, or some of the steps may not be executed.

[0133] The division of functional blocks in the block diagram is an example, and multiple functional blocks may be realized as a single functional block, one functional block may be divided into multiple blocks, or some functions may be moved to another functional block.Furthermore, the functions of multiple functional blocks having similar functions may be processed in parallel or in time-sharing by a single piece of hardware or software.

[0134] Furthermore, the memory system 100a according to the above-described embodiments and the like may be realized as a single device or may be realized by multiple devices. When the memory system 100a is realized by multiple devices, the components of at least one of the circuits may be distributed in any manner among the multiple devices. When at least one of the circuits is realized by multiple devices, the communication method between the multiple devices is not particularly limited and may be wireless communication or wired communication. Furthermore, wireless communication and wired communication may be combined between the devices.

[0135] Furthermore, each component described in the above embodiments may be implemented as software or, typically, as an LSI, which is an integrated circuit. These components may be individually integrated into a single chip, or some or all of them may be integrated into a single chip. Here, the term "LSI" is used, but depending on the level of integration, it may also be referred to as an IC, system LSI, super LSI, or ultra LSI. Furthermore, the integrated circuit implementation method is not limited to LSI, and may be implemented using a dedicated circuit (a general-purpose circuit that executes a dedicated program) or a general-purpose processor. After LSI fabrication, a field programmable gate array (FPGA) that can be programmed or a reconfigurable processor that can reconfigure the connections or settings of circuit cells within the LSI may also be used. Furthermore, if an integrated circuit implementation technology that replaces LSI emerges due to advances in semiconductor technology or a derivative technology, that technology may naturally be used to integrate the components.

[0136] A system LSI is an ultra-multifunctional LSI manufactured by integrating multiple processing units on a single chip. Specifically, it is a computer system that includes a microprocessor, ROM (Read Only Memory), RAM (Random Access Memory), etc. Computer programs are stored in the ROM. The system LSI achieves its functions when the microprocessor operates in accordance with the computer program.

[0137] Furthermore, one aspect of the present disclosure may be a computer program that causes a computer to execute each of the characteristic steps included in the memory control method and operation method shown in FIG. 4 or FIG. 8A.

[0138] Furthermore, for example, the program may be a program to be executed by a computer. Another aspect of the present disclosure may be a computer-readable non-transitory recording medium on which such a program is recorded. For example, such a program may be recorded on a recording medium and distributed or circulated. For example, the distributed program may be installed in a device having another processor, and the program may be executed by the processor, thereby causing the device to perform each of the above processes.

[0139] (Additional Note) The above description of the embodiments and the like discloses the following techniques.

[0140] (Technology 1) A memory system comprising a memory controller and an external memory connected to the memory controller, wherein the memory controller transmits a read command or a write command, a data size, an address interval which is the interval between addresses of consecutive data of the data size, and a starting address to the external memory, and the external memory reads or writes data based on the data size, the address interval, and the starting address so that the access is in accordance with the read command or the write command.

[0141] As a result, by using the data size, address interval, and start address, data at discontinuous addresses can be accessed by transmitting a single command. For example, discontinuous data starting from the start address and discontinuous data starting from addresses that are one address interval away from the start address can be accessed by transmitting a single command. In other words, the number of times commands need to be transmitted when accessing data at discontinuous addresses can be reduced. Therefore, it is possible to prevent a decrease in access efficiency when accessing data at discontinuous addresses.

[0142] (Technology 2) When the variable is n (n is an integer equal to or greater than 0), the address interval is S, and the starting address is A0, the external memory is a memory system of Technology 1 that sequentially accesses data of the data size starting from address An=A0+nS while changing n.

[0143] This allows sequential access to data at discontinuous addresses starting from address An=A0+nS by transmitting a single command.

[0144] (Technology 3) This is the memory system of Technology 2, in which changing n includes incrementing n from 0 by 1.

[0145] As a result, by incrementing the variable n by one from 0, data at non-consecutive addresses can be accessed sequentially by transmitting a single command.

[0146] (Technology 4) The memory system according to any one of technologies 1 to 3, wherein the memory controller adds at least one of the data size and the address interval to the read command or the write command and transmits the command to the external memory.

[0147] This allows at least one of the data size and the address interval to be included in the command and transmitted. By accessing discontinuous addresses using at least one of the data size and the address interval included in the command, the number of times the command needs to be transmitted can be reduced.

[0148] (Technology 5) The memory system according to any one of technologies 1 to 4, wherein at least one of the data size and the address interval is written in advance to a configuration register of the external memory.

[0149] This allows access to discontinuous addresses using at least one of the data size and address interval read from the configuration register, thereby reducing the number of times commands are sent.

[0150] (Technology 6) The memory system of any one of technologies 1 to 5, wherein the address interval includes a negative integer.

[0151] This allows the read order and the drawing order to match, so that an uninverted image can be displayed simply by drawing in the read order. In other words, drawing is possible without performing calculations to invert the display. This reduces the processing load of the device in which the memory system is installed.

[0152] (Technology 7) A memory system according to Technology 2 or 3, or any one of Technologies 4 to 6 that are dependent on Technology 2 or 3, in which at least one of the data size and the address interval is expressed as a function of n.

[0153] This makes it possible to accommodate access to areas with shapes other than a parallelogram.

[0154] (Technology 8) The memory system of Technology 7, wherein the memory controller sets parameters of the function.

[0155] This allows the memory controller to set an area of ​​any shape.

[0156] (Technology 9) A memory controller in any of the memory systems of technologies 1 to 8.

[0157] This makes it possible to realize a memory controller that can prevent a decrease in access efficiency when accessing discontinuous addresses.

[0158] (Technology 10) An external memory in the memory system of any one of technologies 1 to 8.

[0159] This makes it possible to realize an external memory that can prevent a decrease in access efficiency when accessing discontinuous addresses.

[0160] (Technology 11) A memory control method executed by a memory controller in a memory system according to any one of technologies 1 to 8, which transmits a read command or a write command, a data size, an address interval which is the interval between successive data of the data size, and a starting address to an external memory.

[0161] This provides the same effect as the memory controller described above.

[0162] (Technology 12) An operating method executed by an external memory in a memory system according to any one of technologies 1 to 8, which obtains a read command or a write command, a data size, an address interval which is the interval between successive data of the data size, and a starting address from a memory controller, and reads or writes data based on the data size, the address interval, and the starting address so that access conforms to the read command or the write command.

[0163] This provides the same effect as the external memory described above.

[0164] The present disclosure is applicable to memory systems.

[0165] REFERENCE SIGNS LIST 1 Information processing system 10 User device 20 Information terminal 100 Control device 100a Memory system 110 Communication circuit 120 Processor 130, 1100 Memory controller 131 Generation unit 132 Control unit 133, 142 Storage unit 140, 1200 External memory 141 Decoder 142a Block 143 Register 200 Display device A0, A1, A2 Start address Af End address DAT0, DAT1, DAT2 Consecutive data S Address interval W Data size

Claims

1. A memory system comprising a memory controller and an external memory connected to the memory controller, wherein the memory controller transmits a read command or a write command, a data size, an address interval which is the address interval between consecutive data of the data size, and a starting address to the external memory, and the external memory reads or writes data based on the data size, the address interval, and the starting address so that access is in accordance with the read command or the write command.

2. The memory system of claim 1, wherein, assuming that a variable is n (n is an integer equal to or greater than 0), the address interval is S, and the starting address is A0, the external memory sequentially accesses data of the data size starting from address An=A0+nS while changing n.

3. The memory system of claim 2, wherein changing n includes incrementing n from 0 by 1.

4. The memory system according to any one of claims 1 to 3, wherein said memory controller adds at least one of said data size and said address interval to said read command or said write command and transmits the command to said external memory.

5. The memory system according to any one of claims 1 to 3, wherein at least one of the data size and the address interval is written in advance to a configuration register of the external memory.

6. The memory system according to any one of claims 1 to 3, wherein the address interval includes a negative integer.

7. The memory system according to claim 2 or 3, wherein at least one of the data size and the address interval is expressed as a function of n.

8. The memory system according to claim 7, wherein the memory controller sets parameters of the function.

9. A memory controller in a memory system according to any one of claims 1 to 3.

10. An external memory in the memory system according to any one of claims 1 to 3.

11. A memory control method executed by a memory controller in a memory system according to any one of claims 1 to 3, comprising the steps of: transmitting a read command or write command, a data size, an address interval which is the interval between successive data of said data size, and a starting address to an external memory.

12. An operating method executed by an external memory in a memory system according to any one of claims 1 to 3, comprising the steps of: acquiring a read command or a write command, a data size, an address interval which is the interval between successive data of said data size, and a starting address from a memory controller; and reading or writing data based on said data size, said address interval, and said starting address so that access conforms to said read command or said write command.

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