Display panel and electronic device comprising same

Abstract

One embodiment of the present invention discloses a display panel, comprising: a substrate in which a transparent region, a dummy region surrounding the transparent region, a display region surrounding the dummy region are defined; a driving circuit disposed in the display region and including a transistor; a voltage line disposed in the display region and electrically connected to the driving circuit; an insulating layer on the voltage line; a first pixel electrode disposed on the insulating layer in the display region; a bank layer that covers an edge of the first pixel electrode and defines a first opening overlapping the first pixel electrode; a light-emitting layer overlapping the first pixel electrode; a counter electrode disposed on the light-emitting layer; and a dummy electrode layer disposed on the insulating layer in the dummy region, wherein the bank layer extends toward the dummy region and defines a plurality of dummy openings overlapping the dummy electrode layer.

Description

Display panel and electronic device including same

[0001] The embodiments relate to a display panel and an electronic device including the same.

[0002] In recent years, display panels have become increasingly versatile. Furthermore, their use is expanding as they become thinner and lighter.

[0003] As the display area within the display panel expands, various functions are being grafted or linked to the display panel. Research is ongoing to utilize a portion of the display area for functions other than image display, as a means of expanding the area and adding diverse functionality.

[0004] Embodiments provide a structure for a display panel including a transparent area and an electronic device including the same.

[0005] Additional aspects will be set forth in part in the following description, and in part will be apparent from the description, or may be learned by reference to the teachings of the present disclosure.

[0006] In one embodiment of the present specification, a display device includes a substrate, in which a transparent area, a dummy area surrounding the transparent area, and a display area surrounding the dummy area are defined, a driving circuit disposed in the display area and including a transistor, a voltage line disposed in the display area and electrically connected to the driving circuit, an insulating layer on the voltage line, a first pixel electrode disposed on the insulating layer in the display area, a bank layer defining a first opening covering an edge of the first pixel electrode and overlapping the first pixel electrode, an emission layer overlapping the first pixel electrode through the first opening of the bank layer, a counter electrode disposed on the emission layer and overlapping the first pixel electrode and the emission layer, and a dummy electrode layer disposed on the insulating layer in the dummy area, wherein the bank layer defines a plurality of dummy openings extending toward the dummy area and overlapping the dummy electrode layer.

[0007] In one embodiment of the present disclosure, an electronic device includes a display panel and a component corresponding to a transparent area of ​​the display panel as described above. The component may include a sensor or a camera.

[0008] In one embodiment, the display panel further includes a dummy transistor disposed under the dummy electrode layer, wherein the dummy electrode layer can be electrically insulated from the dummy transistor.

[0009] In one embodiment, the voltage line extends toward the dummy region and a portion of the voltage line overlaps the dummy electrode layer, and the dummy electrode layer can be electrically connected to the voltage line.

[0010] In one embodiment, the voltage line may have a voltage level that is the same as the voltage level of the counter electrode.

[0011] In one embodiment, the driving circuit further includes an initialization transistor electrically connected to the first pixel electrode and initializing the first pixel electrode, and the voltage line can be electrically connected to the initialization transistor.

[0012] In one embodiment, the plurality of dummy openings of the bank layer may include a first dummy opening, a second dummy opening, and a third dummy opening, each overlapping different portions of the dummy electrode layer.

[0013] In one embodiment, the display panel further includes a second pixel electrode disposed on the insulating layer in the display area, the second pixel electrode being adjacent to the first pixel electrode but separated from each other, and a third pixel electrode disposed on the insulating layer in the display area, the third pixel electrode being adjacent to the first pixel electrode and the second pixel electrode but separated from each other, wherein the bank layer further defines a second opening overlapping the second pixel electrode and a third opening overlapping the third pixel electrode, the first opening and the second opening being defined in the same column, the third opening being defined adjacent to the columns of the first opening and the second opening, the first dummy opening and the second dummy opening being defined in the same column, and the third dummy opening being defined adjacent to the columns of the first dummy opening and the second dummy opening.

[0014] In one embodiment, the size of the first dummy opening and the size of the first opening may be substantially the same, the size of the second dummy opening and the size of the second opening may be substantially the same, and the size of the third dummy opening and the size of the third opening may be substantially the same.

[0015] In one embodiment, the size and shape of the first dummy opening may be different from the size and shape of the first opening.

[0016] In one embodiment, a routing region is further defined on the substrate, which is positioned between the transparent region and the dummy region and surrounds the transparent region, and the dummy electrode layer extends toward the routing region, wherein the bank layer may further define a fourth dummy opening, a fifth dummy opening, and a sixth dummy opening, which overlap different portions of the dummy electrode layer positioned in the routing region, respectively.

[0017] In one embodiment, the size of the first dummy opening, the size of the second dummy opening, and the size of the third dummy opening may be different from each other, the size of the fourth dummy opening and the size of the first dummy opening may be substantially the same, the size of the fifth dummy opening and the size of the second dummy opening may be substantially the same, and the size of the sixth dummy opening and the size of the third dummy opening may be substantially the same.

[0018] In one embodiment, in the routing region, the dummy electrode layer does not overlap with the transistor.

[0019] In one embodiment, the driving circuit further includes a signal line electrically connected to the driving circuit, the signal line detouring along an edge of the transmission area in the routing area, and the dummy electrode layer can overlap a detour portion of the signal line in the routing area.

[0020] In one embodiment, the bank layer may include a light-shielding material.

[0021] According to one embodiment of the present specification, the difference in reflectivity between the display area and the middle area when the display panel is not driven (off) can be reduced, thereby preventing the display area and the middle area from being perceived as distinct by the user when the display panel is not driven (off). These effects are exemplary, and the scope of the present invention is not limited by the aforementioned effects.

[0022] The above-described aspects, features and advantages of the illustrated embodiments of the present specification and other aspects, features and advantages will become more apparent from the description taken in conjunction with the accompanying drawings.

[0023] Figures 1a to 1c are schematic perspective views illustrating one embodiment of an electronic device.

[0024] FIG. 2 is a cross-sectional view of one embodiment of an electronic device taken along line II-II' of FIG. 1c.

[0025] Figure 3 is a plan view illustrating an example of an excerpt of a portion of a display panel.

[0026] FIG. 4 is an equivalent circuit diagram schematically illustrating one embodiment of a light-emitting diode and a driving circuit electrically connected to the aforementioned light-emitting diode.

[0027] Fig. 5 is a cross-sectional view illustrating an embodiment of a part of a display panel.

[0028] FIG. 6 is a plan view showing part III of FIG. 3 and an embodiment of a part of a display panel.

[0029] Fig. 7 is a plan view illustrating an example of an excerpt of part VII illustrated in Fig. 6 as a display panel.

[0030] Fig. 8 is a cross-sectional view taken along lines VIIIa-VIIIa' and VIIIb-VIIIb' of Fig. 7.

[0031] Figure 9 is a plan view showing part III of Figure 3 and an embodiment of a part of a display panel.

[0032] Fig. 10 is a plan view illustrating an example of an extract of the X portion of Fig. 9 as a display panel.

[0033] FIG. 11 is a cross-sectional view of an embodiment of a display panel taken along lines XIa-XIa' and XIb-XIb' of FIG. 10.

[0034] Figure 12 is a plan view schematically illustrating an embodiment of a display panel.

[0035] Fig. 13 is a plan view illustrating a portion of the display panel illustrated in Fig. 12.

[0036] FIGS. 14a and 14b are cross-sectional views illustrating an embodiment of a part of a display panel, taken along line XIV-XIV' of FIG. 13, respectively.

[0037] Fig. 15 is a plan view schematically illustrating an embodiment of a part of a display panel.

[0038] Fig. 16 is a plan view illustrating an excerpt of part XVI of Fig. 15.

[0039] Fig. 17 is a cross-sectional view of part XVI of Fig. 16 along line XVII-XVII' of Fig. 16.

[0040] In one embodiment of the present specification, a display device includes a substrate, which defines a transparent area, a dummy area surrounding the transparent area, and a display area surrounding the dummy area, a driving circuit disposed in the display area and including a transistor, a voltage line disposed in the display area and electrically connected to the driving circuit, an insulating layer on the voltage line, a first pixel electrode disposed on the insulating layer in the display area, a bank layer defining a first opening covering an edge of the first pixel electrode and overlapping the first pixel electrode, an emission layer overlapping the first pixel electrode through the first opening of the bank layer, a counter electrode disposed on the emission layer and overlapping the first pixel electrode and the emission layer, and a dummy electrode layer disposed on the insulating layer in the dummy area, wherein the bank layer defines a plurality of dummy openings extending toward the dummy area and overlapping the dummy electrode layer.

[0041] In one embodiment of the present disclosure, an electronic device includes a display panel and a component corresponding to a transparent area of ​​the display panel as described above. The component may include a sensor or a camera.

[0042] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0043] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0044] In the examples below, terms such as “first”, “second”, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0045] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0046] In the following examples, terms such as “comprise” and / or “comprising” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0047] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0048] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0049] In cases where the exemplary embodiments are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0050] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this specification, the phrase "at least one of a, b, and c" means a, b, c, a and b, a and c together, b and c, a, b, and c, or various variations thereof.

[0051] In the following examples, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0052] The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0053] The term "substantially" as used herein includes the stated value, the measurement in question, and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). The term "substantially" can mean, for example, within one or more standard deviations or within ± 5% of the stated value.

[0054] Figures 1a to 1c are perspective views schematically illustrating one embodiment of an electronic device.

[0055] Referring to FIGS. 1A to 1C, an electronic device (1) is a device that displays a moving image or a still image, and may be a portable electronic device such as a mobile phone, a smart phone, a laptop, a tablet personal computer, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), etc. The electronic device (1) may be a television, a monitor, a billboard, or a display for the Internet of Things (IOT). The electronic device (1) may be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). In addition, the electronic device (1) according to one embodiment can be used as a dashboard of a vehicle, a CID (Center Information Display) placed on the center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, an entertainment device for the rear seat of a vehicle, and a display placed on the back of the front seat. The electronic device described above can be bendable, foldable, or rollable.

[0056] The electronic device (1) may be formed in a quadrangular shape, for example, a rectangular shape, on a plane. The corner where the x-direction side and the y-direction side of the electronic device (1) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the electronic device (1) is not limited to a rectangle, and may be formed in other polygonal, oval, or irregular shapes.

[0057] An electronic device (1) may include a transparent area. In one embodiment, as illustrated in FIG. 1A, the electronic device (1) may include a first transparent area (TA1) and a display area (DA) surrounding the first transparent area (TA1). For example, the electronic device (1) may include an intermediate area (MA) positioned between the first transparent area (TA1) and the display area (DA), and an outer area (PA) surrounding the outside of the display area (DA), for example, the display area (DA). The entire first transparent area (TA1) may be surrounded by the intermediate area (MA), the entire intermediate area (MA) may be surrounded by the display area (DA), and the entire display area (DA) may be surrounded by the outer area (PA).

[0058] Light-emitting diodes are arranged in the display area (DA). The display area (DA) can provide an image by light emitted from the light-emitting diodes. Light-emitting diodes capable of emitting light are not arranged in the first transparent area (TA1), the intermediate area (MA), and the outer area (PA).

[0059] The first transparent area (TA1) may be defined on the inner side of the display area (DA). In one embodiment, the first transparent area (TA1) may be defined on the upper center of the display area (DA) as illustrated in FIG. 1A. In the plan view of the present specification, “left,” “right,” “upper,” and “lower” indicate directions when looking at the electronic device (1) from a vertical direction of the electronic device (1). In one embodiment, for example, “left” indicates the -x direction, “right” indicates the +x direction, “upper” indicates the +y direction, and “lower” indicates the -y direction.

[0060] Although FIG. 1A illustrates that one transparent area is defined, in other embodiments, multiple transparent areas may be provided. As illustrated in FIG. 1B, the electronic device (1) may include two transparent areas. In one embodiment, the entire first transparent area (TA1) and the entire second transparent area (TA2) may be surrounded by the intermediate area (MA), and the entire first transparent area (TA1) and the entire second transparent area (TA2) inside the intermediate area (MA) may be surrounded by the display area (DA). For example, in another embodiment, as illustrated in FIG. 1C, the electronic device (1) may include three transparent areas. In one embodiment, for example, the entirety of the first transparent area (TA1), the second transparent area (TA2), and the third transparent area (TA3) may be surrounded by the intermediate area (MA), and the entirety of the intermediate area (MA) and the first to third transparent areas (TA1, TA2, TA3) inside the intermediate area (MA) may be surrounded by the display area (DA). The size of any one selected from the first to third transparent areas (TA1, TA2, TA3) may be different from the size of the other one.

[0061] FIG. 2 is a cross-sectional view of an embodiment of the electronic device (1) of FIG. 1c taken along line II-II' of FIG. 1c.

[0062] Referring to FIG. 2, the electronic device (1) may include a display panel (10) and components arranged in a transparent area of ​​the display panel (10). The display panel (10), like the electronic device (1), may include a transparent area, an intermediate area (MA), a display area (DA), and an outer area (PA). In one embodiment, FIG. 2 illustrates that the display panel (10) includes three transparent areas, for example, first to third transparent areas (TA1, TA2, TA3), and that the electronic device (1) includes three components corresponding to the first to third transparent areas (TA1, TA2, TA3), for example, a first component (71), a second component (72), and a third component (73). The display panel (10) and the first to third components (71, 72, 73) may be accommodated in a housing (HS).

[0063] The display panel (10) may include a display layer (20), an encapsulation layer (30), an input detection layer (or input sensing layer, 40), an optical function layer (50), and a cover window (60).

[0064] The display layer (20) may include light-emitting elements that emit light to display an image and driving circuits that are electrically connected to the light-emitting elements and include transistors.

[0065] The encapsulating layer (30) can seal the display layer (20). The encapsulating layer (30) can include at least one organic encapsulating layer and at least one inorganic encapsulating layer. In another embodiment, the encapsulating layer (30) can include a glass substrate.

[0066] The input sensing layer (40) can obtain coordinate information according to an external input, for example, a touch event. The input sensing layer (40) can include touch electrodes and signal lines (trace lines) connected to the touch electrodes. The input sensing layer (40) can be placed on the sealing layer (30). The input sensing layer (40) can detect an external input using a mutual capping method or / and a self-capping method.

[0067] The optical functional layer (50) may include an anti-reflection layer. The anti-reflection layer may reduce the reflectance of light (external light) incident from the outside toward the display panel (10) through the cover window (60). The anti-reflection layer may include a retarder and a polarizer.

[0068] In another embodiment, the anti-reflection layer may include a black matrix and color filters. The color filters may be arranged in consideration of the color of light emitted from the display elements (e.g., light emitting diodes) of the display layer (20). In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged in different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, may destructively interfere, thereby reducing the external light reflectance.

[0069] The optical function layer (50) may include a lens layer. The lens layer may improve the light emission efficiency of light emitted from the display layer (20) or reduce color deviation. The lens layer may include a layer having a concave or convex lens shape, or / and may include a plurality of layers having different refractive indices. The optical function layer (50) may include both the anti-reflection layer and the lens layer described above, or may include any one of them.

[0070] An opening (10OP) may be defined in the display panel (10). In this regard, FIG. 2 illustrates that the display panel (10) includes openings (10OP) corresponding to the first transparent area (TA1) and the third transparent area (TA3), respectively. It illustrates that the display layer (20), the encapsulation layer (30), the input sensing layer (40), and the optical function layer (50) define openings (20OP, 30OP, 40OP, 50OP) that overlap each other. The display layer (20), the encapsulation layer (30), the input sensing layer (40), and the optical function layer (50) may not define an opening corresponding to the second transparent area (TA2).

[0071] The cover window (60) may be disposed on the optical function layer (50). The cover window (60) may be bonded to the optical function layer (50) through an adhesive layer (OCA), such as a transparent optical clear adhesive, disposed between the cover window (60) and the optical function layer (50). The cover window (60) may include a glass material or a plastic material. The plastic material may include polyethersulfone, polyacrylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0072] The cover window (60) may include a flexible window. In one embodiment, for example, the cover window (60) may include a polyimide window or an ultra-thin glass window.

[0073] The first to third transparent areas (TA1, TA2, TA3) may be a type of component area (e.g., sensor area, camera area, speaker area, etc.) where the first to third components (71, 72, 73) for adding various functions to the electronic device (1) are located. The first to third components (71, 72, 73) may be arranged on the back surface of the display panel (10) corresponding to the first to third transparent areas (TA1, TA2, TA3), respectively.

[0074] The first to third components (71, 72, 73) may include electronic elements. The first to third components (71, 72, 73) may be electronic elements that utilize light or sound, and the aforementioned light or sound may pass through the first to third transparent areas (TA1, TA2, TA3). For example, the electronic elements may include a camera that receives light to capture an image, a sensor that outputs and detects light or sound to measure a distance, a sensor that recognizes a part of the body such as an iris, a fingerprint, or a face, a relatively small lamp that outputs light, a speaker that outputs sound, and the like. The electronic elements that utilize light may utilize light of various wavelength bands such as visible light, infrared light, and ultraviolet light.

[0075] The first to third components (71, 72, 73) may include different electronic elements. In one embodiment, any one selected from the first to third components (71, 72, 73) may be a camera for taking images such as selfies or for video conferencing. For example, any one of the two selected from the first to third components (71, 72, 73) may be an emitter that emits infrared light and the other may be a receiver that receives the aforementioned infrared light, thereby being capable of recognizing a part of the body. As described above, the first to third components (71, 72, 73) may be electronic elements having different functions.

[0076] In another embodiment, when the electronic device (1) is used as a smartwatch or a vehicle instrument panel, any one of the first to third components (71, 72, 73) may be a member including a clock hand or a needle indicating predetermined information (e.g., vehicle speed, etc.). In this case, unlike the one illustrated in FIG. 2, an opening may be defined in the cover window (60) so that the component, such as the needle, can be exposed to the outside.

[0077] Although FIG. 2 illustrates three transparent regions, the present invention is not limited thereto. In other embodiments, as previously described with reference to FIGS. 1A and 1B, the electronic device (1) and / or the display panel (10) may include one or two transparent regions, or may include four or more transparent regions. When the display panel (10) includes one transparent region, an opening corresponding to one transparent region may be defined in the display panel (10), or no opening may be defined in the display panel (10). When the display panel (10) includes two transparent regions, the display panel (10) may include two openings corresponding to the two transparent regions. In an alternative embodiment, an opening corresponding to a selected one of the two transparent regions may be defined in the display panel (10), and an opening for the remaining transparent region may not be defined in the display panel (10).

[0078] FIG. 3 is a plan view illustrating a portion of a display panel according to one embodiment of the present invention. For convenience of explanation, FIG. 3 illustrates that the display panel (10) includes two transparent areas; however, as previously described with reference to FIGS. 1A to 1C, the number of transparent areas may be varied.

[0079] Referring to FIG. 3, the display panel (10) may include a first transparent area (TA1) and a second transparent area (TA2) that are spaced apart from each other, an intermediate area (MA) surrounding the first transparent area (TA1) and the second transparent area (TA2), and a display area (DA) surrounding the intermediate area (MA).

[0080] The first transparent area (TA1) and the second transparent area (TA2) are areas through which wavelengths such as light can pass, as described above with reference to FIG. 2, and may be a type of non-display area in which no light-emitting diodes for displaying an image are placed.

[0081] The intermediate area (MA) is a kind of non-display area where no light is emitted, and may surround the first transparent area (TA1) and the second transparent area (TA2). The intermediate area (MA) may include a routing area through which a bypass portion of a signal line, for example, a bypass portion of a data line (DL) and a bypass portion of a scan line (SL) pass, and a dummy area (DMA) around the routing area.

[0082] In this regard, FIG. 3 illustrates a first routing area (RA1) surrounding a first transparent area (TA1), and a second routing area (RA2) surrounding a second transparent area (TA2). The first routing area (RA1) and the second routing area (RA2) may have a closed loop shape surrounding the first transparent area (TA1) and the second transparent area (TA2), respectively. The first routing area (RA1) and the second routing area (RA2) may be spaced apart from each other, and a dummy area (DMA) may surround the first routing area (RA1) and the second routing area (RA2).

[0083] Light emitting diodes (LEDs) that emit red, green, and blue light may be arranged in the display area (DA). The red light emitted from the red light emitting diode (LED), the green light emitted from the green light emitting diode (LED), and the blue light emitted from the blue light emitting diode (LED) may correspond to light emitted from a red pixel, light emitted from a green pixel, and light emitted from a blue pixel of the display panel (10), respectively. However, the present invention is not limited thereto, and the light emitting diodes (LEDs) may emit light of various other colors.

[0084] Signal lines, such as scan lines (SL) and data lines (DL), for providing scan signals and data signals to transistors electrically connected to each light emitting diode (LED) arranged in a display area (DA) may pass through the display area (DA) but bypass a transparent area in an intermediate area (MA). In one embodiment, for example, the scan lines (SL) and data lines (DL) may bypass the transparent area by extending along an edge of the transparent area in a routing area (e.g., a first routing area RA1 or a second routing area RA2).

[0085] In one embodiment, for example, a scan line (SL) may extend along the x-direction, bypassing the first transparent area (TA1) above the first transparent area (TA1) and bypassing the second transparent area (TA2) above the second transparent area (TA2). Another scan line (SL) may extend along the x-direction, bypassing the first transparent area (TA1) below the first transparent area (TA1) and bypassing the second transparent area (TA2) below the second transparent area (TA2). One data line (DL) may extend along the y-direction, bypassing the first transparent area (TA1) at the left side of the first transparent area (TA1), and the other data line (DL) may extend along the y-direction, bypassing the first transparent area (TA1) at the right side of the first transparent area (TA1). Another data line (DL) may extend along the y direction but bypass the second transparent area (TA2) on the left side of the second transparent area (TA2), and another data line (DL) may extend along the y direction but bypass the second transparent area (TA2) on the right side of the second transparent area (TA2).

[0086] FIG. 4 is an equivalent circuit diagram schematically illustrating one embodiment of a light-emitting diode and a driving circuit electrically connected to the aforementioned light-emitting diode.

[0087] The driving circuit (PC) may be electrically connected to a first gate line (GWL) for transmitting a first gate signal (GW), a second gate line (GIL) for transmitting a second gate signal (GI), a third gate line (GRL) for transmitting a third gate signal (GR), a fourth gate line (EML) for transmitting a fourth gate signal (EM), a fifth gate line (EMBL) for transmitting a fifth gate signal (EMB), and a data line (DL) for transmitting a data signal (DATA). Since the light emission of the light emitting diode (LED) is controlled by the fourth gate signal (EM) and the fifth gate signal (EMB), the fourth gate signal (EM) and the fifth gate signal (EMB) may also be referred to as light emission control signals, and the fourth gate line (EML) and the fifth gate line (EMBL) may also be referred to as light emission control lines. The driving circuit (PC) can be electrically connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), a reference voltage line (VRL) that transmits a reference voltage (Vref), a first initialization voltage line (VAL) that transmits a first initialization voltage (Vaint), and a second initialization voltage line (VIL) that transmits a second initialization voltage (Vint).

[0088] In one embodiment, a plurality of transistors included in a driving circuit (PC) may be N-type oxide thin film transistors. The oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor in which a semiconductor layer includes an oxide. However, this is merely exemplary, and the transistors of the present invention are not limited thereto. In one embodiment, for example, a semiconductor layer included in an N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polysilicon), an organic semiconductor, or the like.

[0089] The driving circuit (PC) may include first to seventh transistors (T1, T2, T3, T4, T5, T6, and T7), first and second capacitors (C1 and C2), and an auxiliary capacitor (Ca). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal (DATA), and the second to seventh transistors (T2, T3, T4, T5, T6, and T7) may be switching transistors that transmit signals. The first terminal (or first electrode) and the second terminal (or second electrode) of each of the first to seventh transistors (T1, T2, T3, T4, T5, T6, and T7) may be a source (or source electrode) or a drain (or drain electrode) depending on the voltage of the first terminal and the second terminal. In one embodiment, for example, depending on the voltages of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. Hereinafter, the node to which the first-first gate of the first transistor (T1) is connected may be defined as a first node (N1), and the node to which the second terminal of the first transistor (T1) is connected may be defined as a second node (N2).

[0090] A first transistor (T1) may be connected to a driving voltage line (PL) and a light emitting diode (LED). The first transistor (T1) may be connected between a fifth transistor (T5) and a sixth transistor (T6). The first transistor (T1) may include a gate (or gate electrode), a first terminal, and a second terminal connected to a second node (N2). The first transistor (T1) may include a first-first gate connected to the first node (N1). The first transistor (T1) may further include a first-second gate connected to the second terminal of the first transistor (T1). The first-first gate and the first-second gate may be arranged to face each other in different layers. In one embodiment, for example, the first-first gate and the first-second gate of the first transistor (T1) may face each other with a semiconductor layer therebetween. Hereinafter, the gate (or gate electrode) of the first transistor (T1) may refer to the first-first gate involved in turning on and off the first transistor (T1).

[0091] The first-first gate of the first transistor (T1) may be connected to the second terminal of the second transistor (T2), the first terminal of the third transistor (T3), and the first capacitor (C1). The first-second gate of the first transistor (T1) may be connected to the first terminal of the sixth transistor (T6), the first capacitor (C1), and the second capacitor (C2). The first terminal of the first transistor (T1) may be connected to the driving voltage line (PL) via the fifth transistor (T5), and the second terminal of the first transistor (T1) may be connected to the pixel electrode of a light-emitting diode (LED) via the sixth transistor (T6). A first terminal of a first transistor (T1) may be connected to a second terminal of a fifth transistor (T5). A second terminal of the first transistor (T1) may be connected to a first terminal of a sixth transistor (T6), a first capacitor (C1), and a second capacitor (C2). The first transistor (T1) may receive a data signal (DATA) according to a switching operation of the second transistor (T2) and control the amount of driving current flowing to a light emitting diode (LED).

[0092] The second transistor (T2) may be connected to the data line (DL) and the first-first gate of the first transistor (T1). The second transistor (T2) may include a first-first gate connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second terminal of the second transistor (T2) may be connected to the gate of the first transistor (T1), the first terminal of the third transistor (T3), and the first capacitor (C1). The second transistor (T2) may be turned on by the first gate signal (GW) transmitted to the first gate line (GWL) to electrically connect the data line (DL) and the first node (N1), and transmit the data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0093] A third transistor (T3) may be connected to the first-first gate of the first transistor (T1) and the reference voltage line (VRL). The third transistor (T3) may include a gate connected to the third gate line (GRL), a first terminal connected to the first node (N1), and a second terminal connected to the reference voltage line (VRL). The first terminal of the third transistor (T3) may be connected to the first-first gate of the first transistor (T1), the second terminal of the second transistor (T2), and the first capacitor (C1). The third transistor (T3) may be turned on by a third gate signal (GR) transmitted to the third gate line (GRL) and may transmit the reference voltage (Vref) transmitted to the reference voltage line (VRL) to the first node (N1).

[0094] A fourth transistor (also referred to as an initialization transistor, T4) may be connected to a sixth transistor (T6) and a first initialization voltage line (VAL). The fourth transistor (T4) may be connected between a light-emitting diode (LED) and the first initialization voltage line (VAL). The fourth transistor (T4) may include a gate connected to a second gate line (GIL), a first terminal connected to a third node (N3), and a second terminal connected to the first initialization voltage line (VAL). A first terminal of the fourth transistor (T4) may be connected to a second terminal of the sixth transistor (T6) and a pixel electrode of a light-emitting diode (LED). The fourth transistor (T4) is turned on by the second gate signal (GI) transmitted to the second gate line (GIL), and can transmit the first initialization voltage (Vaint) transmitted to the first initialization voltage line (VAL) to the third node (N3), and can initialize the pixel electrode (e.g., anode) of the light-emitting diode (LED).

[0095] The fifth transistor (T5) may be connected to the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate connected to the fourth gate line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to a fourth gate signal (EM) transmitted to the fourth gate line (EML).

[0096] The sixth transistor (T6) may be connected to the first transistor (T1) and a light-emitting diode (LED). The sixth transistor (T6) may be connected between the second node (N2) and the third node (N3). The sixth transistor (T6) may include a gate connected to the fifth gate line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The first terminal of the sixth transistor (T6) may be connected to the second terminal of the first transistor (T1), the first capacitor (C1), and the second capacitor (C2). The second terminal of the sixth transistor (T6) may be connected to the first terminal of the fourth transistor (T4) and a pixel electrode of the light-emitting diode (LED). The sixth transistor (T6) can be turned on or off according to the fifth gate signal (EMB) transmitted to the fifth gate line (EMBL).

[0097] The seventh transistor (T7) may be connected between the first transistor (T1) and the second initialization voltage line (VIL). The seventh transistor (T7) may include a gate connected to the second gate line (GIL), a first terminal connected to the second node (N2), and a second terminal connected to the second initialization voltage line (VIL). The first terminal of the seventh transistor (T7) may be connected to the second terminal of the first transistor (T1), the first terminal of the sixth transistor (T6), the first capacitor (C1), and the second capacitor (C2). The seventh transistor (T7) is turned on by the second gate signal (GI) transmitted to the second gate line (GIL) and can transmit the second initialization voltage (Vint) transmitted to the second initialization voltage line (VIL) to the second node (N2).

[0098] A first capacitor (C1) may be connected between the first-first gate of the first transistor (T1) and the second terminal of the first transistor (T1). A first electrode of the first capacitor (C1) may be connected to a first node (N1), and a second electrode of the first capacitor (C1) may be connected to a second node (N2). A first electrode of the first capacitor (C1) may be connected to the first-first gate of the first transistor (T1), the second terminal of the second transistor (T2), and the first terminal of the third transistor (T3). The second electrode of the first capacitor (C1) can be connected to the second terminal and the first-second gate of the first transistor (T1), the second electrode of the second capacitor (C2), and the first terminal of the sixth transistor (T6). The first capacitor (C1) serves as a storage capacitor and can store a voltage corresponding to the threshold voltage of the first transistor (T1) and a data signal (DATA).

[0099] When the third transistor (T3) and the fifth transistor (T5) are turned on, the first transistor (T1) can be turned on. When the voltage of the second terminal of the first transistor (T1) drops to the difference (Vref-Vth1) between the reference voltage (Vref) and the threshold voltage (Vth1) of the first transistor (T1), the first transistor (T1) is turned off, and a voltage corresponding to the threshold voltage (Vth1) of the first transistor (T1) is stored in the first capacitor (C1), so that the threshold voltage (Vth1) of the first transistor (T1) can be compensated.

[0100] The second capacitor (C2) may be connected between the driving voltage line (PL) and the second node (N2). The first electrode of the second capacitor (C2) may be connected to the driving voltage line (PL). The second electrode of the second capacitor (C2) may be connected to the second terminal and the first-second gate of the first transistor (T1), the second electrode of the first capacitor (C1), and the first terminal of the sixth transistor (T6).

[0101] The capacitance of each of the first capacitor (C1) and the second capacitor (C2) may vary depending on the color of light emitted from the light-emitting diode (LED).

[0102] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the sustain voltage line (VSSL), and the pixel electrode of the light-emitting diode (LED). The auxiliary capacitor (Ca) stores and maintains a voltage corresponding to the voltage difference between the pixel electrode of the light-emitting diode (LED) and the sustain voltage line (VSSL), thereby preventing the problem of black luminance increasing when the sixth transistor (T6) is turned off.

[0103] A light emitting diode (LED) may be connected to the first transistor (T1) via a sixth transistor (T6). The light emitting diode (LED) includes a pixel electrode (anode) connected to a third node (N3) and a counter electrode (cathode) facing the pixel electrode, and the counter electrode may be supplied with a common voltage (ELVSS). In one embodiment, the counter electrode (cathode) may be electrically connected to a sustain voltage line (VSSL) that extends to a display area and provides the common voltage (ELVSS). A driving current output by the first transistor (T1) flows through the light emitting diode (LED) by the turned-on fifth transistor (T5) and the turned-on sixth transistor (T6), and the light emitting diode (LED) may emit light with a brightness corresponding to the magnitude of the driving current.

[0104] Although FIG. 4 illustrates that the driving circuit (PC) includes seven transistors, the present invention is not limited thereto. In other embodiments, the driving circuit (PC) may include six or fewer transistors, eight or more transistors. Furthermore, the driving circuit (PC) may include two or fewer capacitors, or four or more capacitors.

[0105] Fig. 5 is a cross-sectional view illustrating a portion of a display panel (10). For convenience of explanation, Fig. 5 illustrates the display layer (20) and the encapsulation layer (30) of the display panel (10), but as described with reference to Fig. 2, an input sensing layer, an optical function layer, and a cover window may be further included on the encapsulation layer (30).

[0106] Referring to Fig. 5, the display panel (10) includes light emitting diodes (LEDs) arranged in a display area (DA). The light emitting diodes (LEDs) are arranged on a substrate (100), and a driving circuit (PC) may be arranged between the light emitting diodes (LEDs) on the substrate (100). In this regard, Fig. 5 illustrates some components of the driving circuit (PC), including a first transistor (T1), a first capacitor (C1), and a second capacitor (C2).

[0107] The substrate (100) may include a glass material or a polymer resin. As an example, the substrate (100) may have an alternating laminated structure of a base layer including a polymer resin and a barrier layer including an inorganic insulating material such as silicon oxide or silicon nitride. The polymer resin may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate.

[0108] A first conductive layer (CL1) may be disposed on a substrate (100). The first conductive layer (CL1) may include a conductive material such as a metal. In one embodiment, for example, the first conductive layer (CL1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer or multi-layer structure including the aforementioned materials.

[0109] The buffer layer (111) may be disposed on the first conductive layer (CL1). The buffer layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0110] The second conductive layer (CL2) is disposed on the buffer layer (111) and may overlap the first conductive layer (CL1). In one embodiment, the first conductive layer (CL1) may include a first electrode (C21) of the second capacitor (C2), and the second conductive layer (CL2) may include a second electrode (C22) of the second capacitor (C2). The second conductive layer (CL2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer or multi-layer structure including the aforementioned materials.

[0111] The first insulating layer (112) may be disposed on the second conductive layer (CL2). The first insulating layer (112) may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0112] The semiconductor layer (ACT1) may be disposed on the first insulating layer (112). The semiconductor layer (ACT1) may include a channel region (CH1), and a source region (S1) and a drain region (D1) disposed on both sides of the aforementioned channel region (CH1). The semiconductor layer (ACT1) may include an oxide of at least one of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer (ACT1) may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, or the like. A conductive (or conductive) process may be performed on at least a portion of the semiconductor layer (ACT1) by plasma treatment or the like.

[0113] The third conductive layer (CL3) may be disposed on the semiconductor layer (ACT1) with the second insulating layer (113) therebetween. A portion of the third conductive layer (CL3) may include a first-first gate electrode (G11) overlapping the channel region (CH1), and a portion of the second conductive layer (CL2) may include a first-second gate electrode (G12) overlapping the channel region (CH1). The first-first gate electrode (G11) and the first-second gate electrode (G12) may overlap each other with the channel region (CH1) therebetween. The second insulating layer (113) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0114] The third insulating layer (114) may be disposed on the third conductive layer (CL3). The third insulating layer (114) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0115] The third conductive layer (CL3) may include the first electrode (C11) of the first capacitor (C1), and the fourth conductive layer (CL4) on the third insulating layer (114) may include the second electrode (C12) of the first capacitor (C1). The third conductive layer (CL3) and the fourth conductive layer (CL4) may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the aforementioned materials.

[0116] The data line (DL) may be arranged on the third insulating layer (114). The data line (DL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned materials.

[0117] The fourth insulating layer (116) may be placed on the data line (DL). The fourth insulating layer (116) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0118] Although FIG. 5 illustrates that the fourth conductive layer (CL4) and the data line (DL) are arranged on the same layer, the present invention is not limited thereto. In another embodiment, an insulating layer may be further added between the fourth conductive layer (CL4) and the data line (DL), and the data line (DL) may be arranged on top of the added insulating layer, and the fourth conductive layer (CL4) may be arranged below the added insulating layer.

[0119] The driving voltage line (PL) may be arranged on the fourth insulating layer (116) and covered with a fifth insulating layer (117). The driving voltage line (PL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned materials. The fifth insulating layer (117) may include an organic insulating material.

[0120] Although not shown in FIG. 5, other voltage lines, such as the sustain voltage line (VSSL, FIG. 4), the first and second initialization voltage lines (VIL, VAL, FIG. 4), and the reference voltage line (VRL, FIG. 4), may be arranged on the same layer as the driving voltage line (PL), such as the fourth insulating layer (116).

[0121] A light emitting diode (LED) may include a pixel electrode (210), a light emitting layer (222), and a counter electrode (230).

[0122] The pixel electrode (210) may be disposed on the fifth insulating layer (117). The pixel electrode (210) may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a combination thereof. In another embodiment, the pixel electrode (210) may further include a conductive oxide layer on and / or below the aforementioned reflective film. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one embodiment, the pixel electrode (210) may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0123] The bank layer (123) may be disposed on the pixel electrode (210). An opening (123OP) overlapping the pixel electrode (210) may be defined in the bank layer (123), and the bank layer (123) may cover an edge of the pixel electrode (210). The bank layer (123) may include an organic insulator. In one embodiment, for example, the bank layer (123) may include an organic insulator including a light-blocking material. In some embodiments, the bank layer (123) may include a polyimide (PI)-based binder and a red, green, and blue pigment mixture. In an alternative embodiment, the bank layer (123) may include a cardo-based binder resin and a mixture of a lactam black pigment and a blue pigment. In an alternative embodiment, the bank layer (123) may include carbon black. The bank layer (123) can improve the contrast of the display panel (10).

[0124] The spacer (125) may be disposed on the bank layer (123). In one embodiment, the spacer (125) may include a different material from the bank layer (123). For example, the bank layer (123) may include a negative photosensitive material, while the spacer (125) may include a positive photosensitive material, and the spacer (125) may include different materials, and may be formed through separate mask processes. In another embodiment, the spacer (125) may include the same material as the bank layer (123) and may be formed together in the same mask process (e.g., a halftone mask process).

[0125] The light-emitting layer (222) may include a polymer or low-molecular organic material that emits light of a predetermined color. The light-emitting layer (222) may include a material that emits red light, green light, or blue light, depending on the light-emitting diode (LED).

[0126] A functional layer may be further included below and / or above the light-emitting layer (222). In one embodiment, for example, a first functional layer (221) may be further included between the pixel electrode (210) and the light-emitting layer (222), and a second functional layer (223) may be further included between the light-emitting layer (222) and a counter electrode (230) to be described later. The first functional layer (221) may include a hole transport layer and / or a hole injection layer. The second functional layer (223) may include an electron transport layer and / or an electron injection layer.

[0127] The counter electrode (230) may be formed of a conductive material having a low work function. In one embodiment, for example, the counter electrode (230) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0128] Unlike the pixel electrodes (210) that are individually formed to correspond to the light emitting diodes (LEDs), the counter electrodes (230) may be extended to correspond to the pixel electrodes (210). In one embodiment, for example, the pixel electrodes (210) of one light emitting diode (LED) and the pixel electrodes (210) of another light emitting diode (LED) may be separated and spaced from each other, but the counter electrodes (230) that overlap the pixel electrodes (210) may be extended to cover the pixel electrodes (210) described above.

[0129] The encapsulating layer (30) is disposed on the display layer (20) and may include at least one inorganic encapsulating layer and at least one organic encapsulating layer. In one embodiment, FIG. 5 illustrates that the encapsulating layer (30) includes a first inorganic encapsulating layer (310), an organic encapsulating layer (320), and a second inorganic encapsulating layer (330).

[0130] The first inorganic sealing layer (310) and the second inorganic sealing layer (330) may include at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic sealing layer (310) and the second inorganic sealing layer (330) may be a single layer or multiple layers including the aforementioned materials. The organic sealing layer (320) may include a polymer-based material. Examples of the polymer-based material include acrylic resins, epoxy resins, polyimides, and polyethylene. In one embodiment, the organic sealing layer (320) may include acrylate.

[0131] Figure 6 is a plan view showing part III of Figure 3 and an embodiment of a part of the display panel (10).

[0132] Referring to the display area (DA) of FIG. 6, pixels that emit different light, for example, first to third pixels (P1, P2, P3), may be arranged in the display area (DA). In one embodiment, for example, the first pixel (P1) and the second pixel (P2) may be arranged in the same column, and the third pixel (P3) may be arranged in a column adjacent to the column in which the first pixel (P1) and the second pixel (P2) are arranged.

[0133] One of the first to third pixels (P1, P2, P3) may be a red pixel, another may be a green pixel, and the remaining one may be a blue pixel. The first to third pixels (P1, P2, P3) may correspond to light-emitting areas where light is emitted from corresponding light-emitting diodes. In one embodiment, for example, the first pixel (P1) may correspond to a light-emitting area (hereinafter, first light-emitting area, EA1) of the light-emitting diode corresponding to the first pixel (P1), the second pixel (P2) may correspond to a light-emitting area (hereinafter, second light-emitting area, EA2) of the light-emitting diode corresponding to the second pixel (P2), and the third pixel (P3) may correspond to a light-emitting area (hereinafter, third light-emitting area, EA3) of the light-emitting diode corresponding to the third pixel (P3).

[0134] The light-emitting area may be defined as an opening of the bank layer (123, FIG. 5) described above with reference to FIG. 5, for example, an opening (123OP, FIG. 5) overlapping the pixel electrode (210, FIG. 5). Accordingly, the first to third light-emitting areas (EA1, EA2, EA3) illustrated in FIG. 6 may correspond to the first to third openings (1230OP1, 123OP2, 123OP3) of the bank layer (123), respectively.

[0135] Referring to the intermediate area (MA) of FIG. 6, the bank layer (123) may extend toward the intermediate area (MA), and dummy openings arranged in a predetermined pattern may be defined in the bank layer (123) in the intermediate area (MA). In this regard, FIG. 6 illustrates first to third dummy openings (DOP1, DOP2, DOP3) defined in the intermediate area (MA), for example, the dummy area (DMA). In some embodiments, dummy openings may not be defined in a routing area, for example, a second routing area (RA2), as illustrated in FIG. 6.

[0136] The arrangement of the first to third dummy openings (DOP1, DOP2, DOP3) may be substantially the same as the arrangement of the first to third openings (1230OP1, 123OP2, 123OP3). The first dummy opening (DOP1) and the second dummy opening (DOP2) may be defined in the same column, and the third dummy opening (DOP3) may be defined in a column adjacent to the columns of the first dummy opening (DOP1) and the second dummy opening (DOP2). The first dummy opening (DOP1) and the second dummy opening (DOP2), and the first opening (123OP1) and the second opening (123OP2) may be defined in the same column, and the third dummy opening (DOP3) and the third opening (123OP3) may be defined in the same column. The spacing between the first and second dummy openings (DOP1, DOP2) and the spacing between the first and second openings (123OP1, 123OP2) may be substantially equal.

[0137] The size of each of the first to third dummy openings (DOP1, DOP2, DOP3) may be substantially the same as the size of each of the first to third openings (123OP1, 123OP2, 123OP3). In one embodiment, for example, the width of the first dummy opening (DOP1) in the x direction and the length of the first dummy opening (DOP1) in the y direction may be substantially the same as the width of the first opening (123OP1) in the x direction and the length of the first opening (123OP1) in the y direction. The width of the second dummy opening (DOP2) in the x direction and the length of the second dummy opening (DOP2) in the y direction may be substantially the same as the width of the second opening (123OP2) in the x direction and the length of the second opening (123OP2) in the y direction. The width of the third dummy opening (DOP3) in the x direction and the length of the third dummy opening (DOP3) in the y direction may be substantially the same as the width of the third opening (123OP3) in the x direction and the length of the third opening (123OP3) in the y direction.

[0138] Since the bank layer (123) defines dummy openings, for example, first to third dummy openings (DOP1, DOP2, DOP3), the reflectances in the middle area (MA) and the display area (DA) of the display panel (10) can be made similar, respectively. More specifically, since the first to third dummy openings (DOP1, DOP2, DOP3) of the bank layer (123) defined in the middle area (MA) have substantially the same arrangement and / or size as the arrangement and / or size of the first to third openings (123OP1, 123OP2, 123OP3) as described above, the display area (DA) and the middle area (MA) can be effectively prevented from being perceived differently by the user in the off state (non-driven state) of the display panel (10).

[0139] Referring to the transparent area of ​​FIG. 6, for example, the second transparent area (TA2), an opening (hereinafter, referred to as a transparent opening, 123OPT) overlapping the transparent area, for example, the second transparent area (TA2), may be defined in the bank layer (123). The size of the transparent opening (123OPT) may be substantially the same as or larger than the size of the second transparent area (TA2).

[0140] Although FIG. 6 illustrates the intermediate area (MA) and the display area (DA) around the second transparent area (TA2), the present invention is not limited thereto. In other embodiments, the structure around other transparent areas, such as the first transparent area (TA1), may also have the structure illustrated in FIG. 6.

[0141] Fig. 7 is a plan view showing an example of a realization of the VII portion shown in Fig. 6 as a display panel (10), and Fig. 8 is a cross-sectional view taken along lines VIIIa-VIIIa' and VIIIb-VIIIb' of Fig. 7.

[0142] Referring to the display area (DA) of FIG. 7, the first pixel electrode (210-1), the second pixel electrode (210-2), and the third pixel electrode (210-3) may be arranged to be spaced apart from each other in the display area (DA). The first pixel electrode (210-1) and the second pixel electrode (210-2) may be arranged in the same column, and the third pixel electrode (210-3) may be arranged in a column adjacent to the column in which the first pixel electrode (210-1) and the second pixel electrode (210-2) are arranged.

[0143] Referring to the display area (DA) of FIG. 7 and the cross-section along line VIIIa-VIIIa' of FIG. 8, the bank layer (123) covers the edges of each of the first pixel electrode (210-1), the second pixel electrode (210-2), and the third pixel electrode (210-3), and can define a first opening (123OP1) overlapping the first pixel electrode (210-1), a second opening (123OP2) overlapping the second pixel electrode (210-2), and a third opening (123OP3) overlapping the third pixel electrode (210-3).

[0144] The size (or area) of the opening of the bank layer (123) may correspond to the size (or area) of the area where light is emitted and / or the size (or area) of the pixel. In one embodiment, for example, the size (or area) of the first opening (123OP1) of the bank layer (123) may correspond to the size (or area) of the light-emitting area of ​​light emitted by the light-emitting diode including the first pixel electrode (210-1), i.e., the first light-emitting area (EA1, FIG. 6), and / or the size (or area) of the first pixel (P1) of FIG. 6. The size (or area) of the second opening (123OP2) of the bank layer (123) may correspond to the size (or area) of the light-emitting area of ​​light emitted from the light-emitting diode including the second pixel electrode (210-2), i.e., the size (or area) of the second light-emitting area (EA2, FIG. 6) and / or the size (or area) of the second pixel (P2) of FIG. 6. The size (or area) of the third opening (123OP3) of the bank layer (123) may correspond to the size (or area) of the light-emitting area of ​​light emitted from the light-emitting diode including the third pixel electrode (210-3), i.e., the size (or area) of the third light-emitting area (EA3, FIG. 6) and / or the size (or area) of the third pixel (P3) of FIG. 6.

[0145] The first to third pixel electrodes (210-1, 210-2, 210-3) and the first to third openings (123OP1, 123OP2, 123OP3) of the bank layer (123) may overlap with transistors, respectively. In this regard, FIG. 8 illustrates the first and second capacitors (C1, C2), the first transistor (T1), and the sixth transistor (T6) of the driving circuit (PC), and illustrates that the third pixel electrode (210-3) and the third opening (123OP3) of the bank layer (123) overlap with the first transistor (T1) and / or the sixth transistor (T6) of the driving circuit (PC).

[0146] The specific structure of the light emitting diode (LED, FIG. 8) including the third pixel electrode (210-3) is as described above with reference to FIG. 5, and the light emitting diode (LED) can be encapsulated with a sealing layer (30). The only difference is in the material of the light emitting layer overlapping the first to third pixel electrodes (210-1, 210-2, 210-3) through the first to third openings (123OP1, 123OP2, 123OP3), and the specific structure of the light emitting diode including the first and second pixel electrodes (210-1, 210-2) is as described above with reference to FIG. 5.

[0147] Referring to the middle area (MA) of FIG. 7, a dummy electrode layer (DEL) can be defined in the middle area (MA). The dummy electrode layer (DEL) can include a first part having a shape corresponding to the first pixel electrode (210-1), a second part having a shape corresponding to the second pixel electrode (210-2), and a third part having a shape corresponding to the third pixel electrode (210-3), and the first to third parts are integrally connected to each other.

[0148] The bank layer (123) may include first to third dummy openings (DOP1, DOP2, DOP3) overlapping the same dummy electrode layer (DEL). The first dummy opening (DOP1) may overlap a first portion of the dummy electrode layer (DEL), the second dummy opening (DOP2) may overlap a second portion of the dummy electrode layer (DEL), and the third dummy opening (DOP3) may overlap a third portion of the dummy electrode layer (DEL).

[0149] The arrangement of the first to third dummy openings (DOP1, DOP2, DOP3) may be substantially the same as the arrangement of the first to third openings (123OP1, 123OP2, 123OP3). In one embodiment, for example, the first dummy opening (DOP1) and the second dummy opening (DOP2) may be defined in the same column, and the third dummy opening (DOP3) may be defined in a column adjacent to the column in which the first dummy opening (DOP1) and the second dummy opening (DOP2) are defined.

[0150] The first and second dummy openings (DOP1, DOP2) and the first and second openings (123OP1, 123OP2) may be defined in the same column, and the third dummy opening (DOP3) and the third opening (123OP3) may be defined in the same column. The size of each of the first to third dummy openings (DOP1, DOP2, DOP3) may be substantially the same as the size of each of the first to third openings (123OP1, 123OP2, 123OP3). The spacing between the first and second dummy openings (DOP1, DOP2) may be substantially the same as the spacing between the first and second openings (123OP1, 123OP2).

[0151] Referring to the middle area (MA) of FIG. 7 and the cross-section along line VIIIb-VIIIb' of FIG. 8, the dummy electrode layer (DEL) may be disposed on the same layer as the first to third pixel electrodes (210-1, 210-2, 210-3), for example, on the fifth insulating layer (117) as illustrated in FIG. 8. The dummy electrode layer (DEL) may include the same material as the material of the first to third pixel electrodes (210-1, 210-2, 210-3).

[0152] The dummy electrode layer (DEL) can be electrically connected to the voltage line (CVL) through a contact hole (CNT) penetrating an insulating layer, for example, a fifth insulating layer (117), interposed between the dummy electrode layer (DEL) and the voltage line (CVL). The voltage line (CVL) can be the sustain voltage line (VSSL) described with reference to FIG. 4 or the first initialization voltage line (VAL). The voltage line (CVL) can extend from the display area (DA) toward the middle area (MA), and the dummy electrode layer (DEL) can be electrically connected to the voltage line (CVL) disposed thereunder. In one embodiment, the position of the contact hole (CNT) can be located within an imaginary triangle connecting the center of the first dummy opening (DOP1), the center of the second dummy opening (DOP2), and the center of the third dummy opening (DOP3) on a plane, as illustrated in FIG. 7.

[0153] The first to third dummy openings (DOP1, DOP2, DOP3) and the dummy electrode layer (DEL) may overlap with the dummy transistors therebelow, as illustrated in FIG. 8. When the driving circuit (PC) is formed in the display area (DA), a dummy driving circuit (D-PC) may also be formed in the intermediate area (MA), and in this regard, FIG. 8 illustrates that the dummy driving circuit (D-PC) includes a first dummy transistor (D-T1) and a sixth dummy transistor (D-T6). The dummy electrode layer (DEL) and the first to third dummy openings (DOP1, DOP2, DOP3) may overlap with dummy transistors of the dummy driving circuit (D-PC), for example, the first dummy transistor (D-T1) and / or the sixth dummy transistor (D-T6). The dummy driver circuit (D-PC) is not electrically connected to the dummy electrode layer (DEL). In other words, the dummy driver circuit (D-PC) is electrically insulated from the dummy electrode layer (DEL).

[0154] As illustrated in FIG. 8, the first to third dummy light-emitting layers (DML1, DML2, DML3) overlap the first to third portions of the dummy electrode layer (DEL) through the first to third dummy openings (DOP1, DOP2, DOP3) on the dummy electrode layer (DEL), and the counter electrode (230) can extend onto the first to third dummy light-emitting layers (DML1, DML2, DML3). Similarly, the first and second functional layers (221, 223) can also extend onto the first to third dummy light-emitting layers (DML1, DML2, DML3). However, in one embodiment, when the voltage line (CVL) includes a sustain voltage line (VSSL, FIG. 4), since the dummy electrode layer (DEL) has the same voltage level as the counter electrode (230), no light is emitted from the first to third portions of the dummy electrode layer (DEL), the first to third dummy light-emitting layers (DML1, DML2, DML3), and the stacked structure of the counter electrode (230). In another embodiment, when the voltage line (CVL) includes a first initialization voltage line (VAL, FIG. 4), since the dummy electrode layer (DEL) has a voltage level lower than the sum of the common voltage (ELVSS, FIG. 4) and the threshold voltage (Vth) of the light-emitting diode, no light is emitted from the first to third portions of the dummy electrode layer (DEL), the first to third dummy light-emitting layers (DML1, DML2, DML3), and the stacked structure of the counter electrode (230). In other words, the stacked structure of the dummy electrode layer (DEL), the first to third dummy light-emitting layers (DML1, DML2, DML3), and the counter electrode (230) corresponds to a type of dummy light-emitting structure.

[0155] Although FIGS. 7 and 8 illustrate that the dummy electrode layer (DEL) is electrically connected to the voltage line (CVL), the present invention is not limited thereto. In another embodiment, the dummy electrode layer (DEL) may be electrically floating without being electrically connected to the voltage line (CVL). Although FIGS. 6 to 8 illustrate a portion of the intermediate area (MA) around the second transparent area (TA2) corresponding to part III of FIG. 3, the present invention is not limited thereto. The structure of a portion of the intermediate area (MA) around the first transparent area (TA1) illustrated in FIG. 3 is substantially the same as the structure of the embodiment described with reference to FIGS. 6 to 8.

[0156] FIG. 9 is a plan view showing part III of FIG. 3 and an example of a display panel (10).

[0157] The display panel (10) according to the embodiment of FIG. 9 includes the structure previously described with reference to FIG. 6. For example, as illustrated in FIG. 9, the display panel (10) includes pixels that emit different light in the display area (DA), for example, first to third pixels (P1, P2, P3), and dummy openings arranged in the dummy area (DMA), for example, first to third dummy openings (DOP1, DOP2, DOP3), may be defined in the display panel (10). In addition, a transparent opening (123OPT) of a bank layer (123) overlapping a transparent area, for example, a second transparent area (TA2), may be defined in the display panel (10). The first to third pixels (P1, P2, P3) are light-emitting areas of light emitted from light-emitting diodes, and the first to third pixels (P1, P2, P3) correspond to the first to third light-emitting areas (EA1, EA2, EA3), and the first to third light-emitting areas (EA1, EA2, EA3) correspond to the first to third openings (123OP1, 123OP2, 123OP3) of the bank layer (123), as described above.

[0158] The embodiment of FIG. 9 may further include additional dummy openings arranged in a routing area, for example, a second routing area (RA2), within the intermediate area (MA). In this regard, FIG. 9 illustrates the fourth to sixth dummy openings (DOP4, DOP5, DOP6) of the bank layer (123).

[0159] The arrangement of the fourth to sixth dummy openings (DOP4, DOP5, DOP6) may be substantially the same as the arrangement of the first to third dummy openings (DOP1, DOP2, DOP3) and / or the arrangement of the first to third openings (1230OP1, 123OP2, 123OP3). The fourth and fifth dummy openings (DOP4, DOP5) may be defined in the same column, and the sixth dummy opening (DOP6) may be defined in a column adjacent to the column in which the fourth and fifth dummy openings (DOP4, DOP5) are defined. The fourth and fifth dummy openings (DOP4, DOP5), the first and second dummy openings (DOP1, DOP2), and the first and second openings (123OP1, 123OP2) may be defined in the same column, and the sixth dummy opening (DOP6), the third dummy opening (DOP3), and the third opening (123OP3) may be defined in the same column. The spacing between the fourth and fifth dummy openings (DOP4, DOP5), the spacing between the first and second dummy openings (DOP1, DOP2), and the spacing between the first and second openings (123OP1, 123OP2) may be substantially the same.

[0160] The size of each of the fourth to sixth dummy openings (DOP4, DOP5, DOP6) may be substantially the same as the size of each of the first to third dummy openings (DOP1, DOP2, DOP3) and / or the size of each of the first to third openings (123OP1, 123OP2, 123OP3). In one embodiment, for example, the width of the fourth dummy opening (DOP4) in the x direction and the length of the fourth dummy opening (DOP4) in the y direction may be substantially the same as the width of the first dummy opening (DOP1) in the x direction and the length of the first dummy opening (DOP1) in the y direction and / or the width of the first opening (123OP1) in the x direction and the length of the first opening (123OP1) in the y direction. The width of the fifth dummy opening (DOP5) in the x direction and the length of the fifth dummy opening (DOP5) in the y direction may be substantially the same as the width of the second dummy opening (DOP2) in the x direction and the length of the second dummy opening (DOP2) in the y direction and / or the width of the second opening (123OP2) in the x direction and the length of the second opening (123OP2) in the y direction. The width of the sixth dummy opening (DOP6) in the x direction and the length of the sixth dummy opening (DOP6) in the y direction may be substantially the same as the width of the third dummy opening (DOP3) in the x direction and the length of the third dummy opening (DOP3) in the y direction and / or the width of the third opening (123OP3) in the x direction and the length of the third opening (123OP3) in the y direction.

[0161] Since the bank layer (123) defines dummy openings, for example, the first to third dummy openings (DOP1, DOP2, DOP3) and the fourth to sixth dummy openings (DOP4, DOP5, DOP6), the reflectances in the middle area (MA) and the display area (DA) of the display panel (10) can be made similar, respectively. In one embodiment, for example, since the first to third dummy openings (DOP1, DOP2, DOP3) and the fourth to sixth dummy openings (DOP4, DOP5, DOP6) of the bank layer (123) defined in the middle area (MA) have substantially the same arrangement and / or size as the first to third openings (123OP1, 123OP2, 123OP3) as described above, the display area (DA) and the middle area (MA) can be more effectively prevented from being perceived differently by the user in the off state (non-driven state) of the display panel (10).

[0162] Although FIG. 9 illustrates the intermediate area (MA) and the display area (DA) around the second transparent area (TA2), the present invention is not limited thereto. In other embodiments, the structure around other transparent areas, such as the first transparent area (TA1), may also have the structure illustrated in FIG. 9.

[0163] Fig. 10 is a plan view illustrating an example of an X portion of Fig. 9 as a display panel (10), and Fig. 11 is a cross-sectional view taken along lines XIa-XIa' and XIb-XIb' of Fig. 10.

[0164] The structure of the dummy area (DMA) among the display area (DA) and the intermediate area (MA) of FIGS. 10 and 11 is the same as that described with reference to FIGS. 7 and 8, so the description is replaced with that described with reference to FIGS. 7 and 8.

[0165] Referring to the second routing area (RA2) in the middle area (MA) of FIG. 10, the dummy electrode layer (DEL) arranged in the dummy area (DMA) may extend to the second routing area (RA2). In the second routing area (RA2), fourth to sixth dummy openings (DOP4, DOP5, DOP6) arranged in a predetermined pattern and overlapping the dummy electrode layer (DEL) may be defined in the bank layer (123).

[0166] The fourth dummy opening (DOP4) overlaps with the fourth portion of the dummy electrode layer (DEL), the fifth dummy opening (DOP5) overlaps with the fifth portion of the dummy electrode layer (DEL), and the sixth dummy opening (DOP6) can overlap with the sixth portion of the dummy electrode layer (DEL). The first dummy opening (DOP1) overlaps with the first portion of the dummy electrode layer (DEL), the second dummy opening (DOP2) overlaps with the second portion of the dummy electrode layer (DEL), and the third dummy opening (DOP3) can overlap with the third portion of the dummy electrode layer (DEL).

[0167] A portion of the dummy electrode layer (DEL) extending into the routing area, for example, the second routing (RA2), may have substantially the same shape in plan view as a portion of the dummy electrode layer (DEL) disposed in the dummy area (DMA), and may be integrally connected. In one embodiment, for example, the relative arrangement and the size of each portion (e.g., width in the x direction and length in the y direction) between the fourth to sixth portions of the dummy electrode layer (DEL) disposed in the second routing area (RA2) may be the same as the relative arrangement and the size of each portion (e.g., width in the x direction and length in the y direction) between the first to third portions of the dummy electrode layer (DEL) disposed in the dummy area (DMA).

[0168] In the dummy area (DMA), the dummy electrode layer (DEL) may overlap with the dummy transistor of the dummy driver circuit (D-PC) below it, and may be electrically connected to a voltage line (CVL) extending toward the intermediate area (MA). The voltage line (CVL) may be a sustain voltage line (VSSL) described with reference to FIG. 4, or a first initialization voltage line (VAL). In the present specification, “A is disposed below B” may indicate that A and B are arranged and / or overlap each other along a direction perpendicular to the substrate (100, FIG. 11), and other electrodes, components, and / or layers may be interposed between A and B.

[0169] No transistors are placed in the routing area, for example, the second routing area (RA2). Therefore, in the second routing area (RA2), the dummy electrode layer (DEL) does not overlap with transistors, for example, dummy transistors. Similarly, the fourth to sixth dummy openings (DOP4, DOP5, DOP6) do not overlap with transistors.

[0170] In some embodiments, at least one of the dummy electrode layer (DEL) extended to the second routing area (RA2) and / or the fourth to sixth dummy openings (DOP4, DOP5, DOP6) selected may overlap with the bypass portion of the signal line disposed therebelow.

[0171] Referring to the cross-section taken along line XIb-XIb' of Fig. 11, a part of the dummy electrode layer (DEL) extended to the second routing area (RA2) and / or at least one selected from the fourth to sixth dummy openings (DOP4, DOP5, DOP6) may overlap with the bypass portion (DL-C) of the data line and / or the bypass portion (SL-C) of the scan line that bypasses the periphery of the second transmission area (TA2, Fig. 9). The bypass portion (DL-C) of the data line and the bypass portion (SL-C) of the scan line may be arranged on different layers with insulating layers interposed therebetween. The above-described data line bypass portion (DL-C) and / or scan line bypass portion (SL-C) corresponds to a portion of the data line (DL) and scan line (SL) that provide signals for driving the light-emitting diode (LED, FIG. 3) arranged in the display area (DA) as described above with reference to FIG. 3, for example, a portion bypassing the periphery of the transparent area. FIGS. 9 to 11 illustrate a portion of the intermediate area (MA) around the second transparent area (TA2) corresponding to portion III of FIG. 3, but the present invention is not limited thereto. The structure of a portion of the intermediate area (MA) around the first transparent area (TA1) illustrated in FIG. 3 is substantially the same as the structure of the embodiment described with reference to FIGS. 6 to 8.

[0172] Fig. 12 is a plan view schematically illustrating one embodiment of a display panel (10), and Fig. 13 is a plan view illustrating a portion of the display panel illustrated in Fig. 12, for example, part XII.

[0173] The display panel (10) may include a cover window (60) as previously described with reference to FIG. 2. The cover window (60) may include a light-transmitting portion and a light-shielding portion corresponding to the first and second transparent areas (TA1, TA2), the display area (DA), the middle area (MA), and the outer area (PA) of the display panel (10). The light-transmitting portion of the cover window (60) may overlap the first and second transparent areas (RA1, RA2). The light-shielding portion of the cover window (60) may overlap the middle area and the outer area (PA).

[0174] The cover window (60) may include a first light-transmitting portion (61) overlapping the display area (DA), second and third light-transmitting portions (62, 63) overlapping the first and second light-transmitting areas (TA1, TA2), respectively. In addition, the cover window (60) may include a first light-shielding portion (64) overlapping the middle area (MA) and a second light-shielding portion (65) overlapping the outer area (PA).

[0175] The area of ​​the first shading portion (64) of the cover window (60) may not be the same as the area of ​​the intermediate area (MA). In one embodiment, for example, as illustrated in FIG. 13, the first shading portion (64) may have a shape similar to the intermediate area (MA), but the area of ​​the first shading portion (64) may be smaller than the area of ​​the intermediate area (MA).

[0176] The first shading portion (64) may include an outer edge (64OE) defining the shape of the first shading portion (64), and first and second inner edges (64IE1, 64IE2). The first and second inner edges (64IE1, 64IE2) of the first shading portion (64) may have the shape of a closed curve surrounding the first and second transparent areas (TA1, TA2), respectively. The outer edge (64OE) of the first shading portion (64) may have the shape of a closed curve surrounding the first and second inner edges (64IE1, 64IE2) on a plane.

[0177] The boundary between the first shading portion (64) and the first light-transmitting portion (61) can be defined by the outer edge (64OE) of the first shading portion (64). The outer edge (64OE) of the first shading portion (64) can be positioned further from the display area (DA) than the boundary between the intermediate area (MA) and the display area (DA).

[0178] FIG. 14a and FIG. 14b are cross-sectional views illustrating an embodiment of a part of a display panel (10) taken along line XIV-XIV' of FIG. 13.

[0179] Referring to FIGS. 14a and 14b, the first shading portion (64) of the cover window (60) may overlap a portion of the dummy electrode layer (DEL) disposed in the intermediate area (MA), but may not overlap another portion of the dummy electrode layer (DEL). The first shading portion (64) may overlap at least one dummy opening (DOP) among the dummy openings (DOP) of the bank layer (123) defined in the intermediate area (MA), but may not overlap with other dummy openings (DOP). In one embodiment, for example, among the dummy openings (DOP) of the bank layer (123), dummy openings (DOP) defined relatively close to the display area (DA) may not overlap with the first shading portion (64) of the cover window (60), and dummy openings (DOP) defined relatively far from the display area (DA) may overlap with the first shading portion (64) of the cover window (60).

[0180] The first light-emitting portion (61) of the cover window (60) may overlap with the light-emitting diodes (LED) arranged in the display area (DA) and the openings (123OP) of the bank layer (123). The first light-emitting portion (61) may overlap with a portion of the dummy electrode layer (DEL) arranged adjacent to the display area (DA) and a portion of the dummy openings (DOP) of the bank layer (123).

[0181] The first shading portion (64) of the cover window (60) may overlap with the bypass portions of the signal lines passing through the intermediate area (MA). In one embodiment, as illustrated in FIG. 14a, the bypass portion (DL-C) of the data line and the bypass portion (SL-C) of the scan line passing through the second routing area (RA2) may overlap with the first shading portion (64) and the bank layer (123) (e.g., the organic material of the bank layer (123)). In another embodiment, as illustrated in FIG. 14b, the bypass portion (DL-C) of the data line and the bypass portion (SL-C) of the scan line passing through the second routing area (RA2) may overlap with the first shading portion (64) of the cover window (60) while overlapping with the dummy openings (DOP) of the bank layer (123).

[0182] In the embodiment described with reference to FIGS. 13, 14a, and 14b, the first light-shielding portion (64) overlaps with the dummy openings (DOP) underneath in the intermediate area (MA), but the present invention is not limited thereto. FIGS. 14a and 14b illustrate a portion of the intermediate area (MA) and a portion of the display area (DA) around the second transparent area (TA2) of FIG. 13, but the present invention is not limited thereto. The structure of a portion of the intermediate area (MA) and a portion of the display area (DA) around the first transparent area (TA1) is substantially the same as the structure of the embodiment described with reference to FIGS. 14a and 14b.

[0183] Fig. 15 is a plan view schematically illustrating a part of an embodiment of a display panel (10), for example, part XII of Fig. 12, Fig. 16 is a plan view schematically illustrating part XVI of Fig. 15, and Fig. 17 is a cross-sectional view taken along line XVII-XVII' of Fig. 16.

[0184] As illustrated in Fig. 15, the outer edge (64OE) of the first shading portion (64) is located in the middle area (MA), but a dummy opening may not be defined below the first shading portion (64).

[0185] As illustrated in FIGS. 16 and 17, there may be no dummy opening under the first light-shielding portion (64). For example, there may be no dummy opening on a portion of the dummy electrode layer (DEL) disposed under the first light-shielding portion (64). The dummy electrode layer (DEL) may include a cover portion (or non-open portion, NOP) entirely covered by the bank layer (123), as illustrated in FIG. 17.

[0186] Among the cover portions (NOP) of the dummy electrode layer (DEL), some of the cover portions (NOP) may overlap the first light-shielding portion (64), and other cover portions (NOP) may overlap the first light-transmitting portion (61) without overlapping the first light-shielding portion (64).

[0187] As illustrated in FIG. 16, dummy openings overlapping the first light-emitting portion (61) are defined in the bank layer (123), and the shapes of the dummy openings may be different from each other. In one embodiment, for example, one of the first dummy openings (DOP1) may have a different shape and size from the other, and one of the third dummy openings (DOP3) may have a different shape and size from the other.

[0188] As illustrated in FIG. 16, the shape of the dummy opening can define a virtual boundary line (123BE) of the bank layer (123) passing through the intermediate area (MA). The virtual boundary line (123BE) of the bank layer (123) can be defined by edges of the dummy openings. In other words, the shape and size of the dummy opening through which the virtual boundary line (123BE) of the bank layer (123) passes can be different from the shape and size of the dummy opening spaced apart from the virtual boundary line (123BE) of the bank layer (123).

[0189] The shape of the first dummy opening (DOP1) through which the virtual boundary line (123BE) of the bank layer (123) passes may be different from the shape of another first dummy opening (DOP1) spaced apart from the virtual boundary line (123BE) of the bank layer (123) in the intermediate area (MA) and the shape of the first opening (123OP1) defined in the display area (DA). The size of the first dummy opening (DOP1) through which the virtual boundary line (123BE) of the bank layer (123) passes may be smaller than the size of another first dummy opening (DOP1) spaced apart from the virtual boundary line (123BE) of the bank layer (123) in the intermediate area (MA) and smaller than the size of the first opening (123OP1) defined in the display area (DA).

[0190] The shape and size of another first dummy opening (DOP1) spaced apart from the virtual boundary line (123BE) of the bank layer (123) in the intermediate area (MA) may be the same as the shape and size of the first opening (123OP1) defined in the display area (DA). The shape and size of the first dummy opening (DOP1) through which the virtual boundary line (123BE) of the bank layer (123) passes may be different from the shape and size of the first dummy opening (DOP1). In one embodiment, for example, the size of the first dummy opening (DOP1) through which the virtual boundary line (123BE) of the bank layer (123) passes may be smaller than the size of the first dummy opening (DOP1).

[0191] The shape and size of the second dummy opening (DOP2) through which the virtual boundary line (123BE) of the bank layer (123) passes may be different from the shape and size of the second opening (123OP2) defined in the display area (DA). For example, in one embodiment, the size of the second dummy opening (DOP2) through which the virtual boundary line (123BE) of the bank layer (123) passes may be smaller than the size of the second opening (123OP2) defined in the display area (DA). The shape of the second dummy opening (DOP2) through which the virtual boundary line (123BE) of the bank layer (123) passes may be different from the shape of another second dummy opening (not shown) spaced apart from the virtual boundary line (123BE) of the bank layer (123) in the intermediate area (MA).

[0192] The shape and size of the third dummy opening (DOP3) through which the virtual boundary line (123BE) of the bank layer (123) passes may be different from the shape and size of another third dummy opening (DOP3) spaced apart from the virtual boundary line (123BE) of the bank layer (123) in the intermediate area (MA) and the shape and size of the third opening (123OP3) defined in the display area (DA). The size of the third dummy opening (DOP3) through which the virtual boundary line (123BE) of the bank layer (123) passes may be smaller than the size of another third dummy opening (DOP3) spaced apart from the virtual boundary line (123BE) of the bank layer (123) in the intermediate area (MA) and smaller than the size of the third opening (123OP3) defined in the display area (DA). The shape and size of another third dummy opening (DOP3) spaced apart from the virtual boundary line (123BE) of the bank layer (123) in the intermediate area (MA) may be the same as the shape and size of the third opening (123OP3) defined in the display area (DA). FIGS. 16 and 17 illustrate a part of the intermediate area (MA) and a part of the display area (DA) around the second transparent area (TA2) corresponding to part XVI of FIG. 15, but the present invention is not limited thereto. The structure of a part of the intermediate area (MA) around the first transparent area (TA1) of FIG. 15 and a part of the display area (DA) is substantially the same as the structure of the embodiment described with reference to FIGS. 16 and 17.

[0193] While the above description has been made with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A substrate having a transparent area, a dummy area surrounding the transparent area, and a display area surrounding the dummy area defined; A driving circuit disposed in the above display area and including a transistor; A voltage line disposed in the above display area and electrically connected to the driving circuit; Insulating layer on the above voltage line: A first pixel electrode disposed on the insulating layer in the above display area; A bank layer covering an edge of the first pixel electrode and defining a first opening overlapping the first pixel electrode; A light-emitting layer overlapping the first pixel electrode through the first opening of the bank layer; A counter electrode disposed on the light-emitting layer and overlapping the first pixel electrode and the light-emitting layer; and Including a dummy electrode layer arranged on the insulating layer in the above dummy area; A display panel, wherein the above bank layer defines a plurality of dummy openings extending toward the dummy region and overlapping with the dummy electrode layer.

2. In paragraph 1, Further comprising a dummy transistor arranged under the dummy electrode layer, The above dummy electrode layer is electrically insulated from the dummy transistor, the display panel.

3. In paragraph 1, The above voltage line extends toward the dummy area, and a portion of the voltage line overlaps the dummy electrode layer, The above dummy electrode layer is a display panel electrically connected to the voltage line.

4. In paragraph 3, A display panel, wherein the voltage line has the same voltage level as the voltage level of the counter electrode.

5. In paragraph 3, The above driving circuit further includes an initialization transistor electrically connected to the first pixel electrode and initializing the first pixel electrode, The above voltage line is electrically connected to the above initialization transistor, the display panel.

6. In paragraph 1, The above plurality of dummy openings in the above bank layer are, A display panel comprising a first dummy opening, a second dummy opening, and a third dummy opening, each overlapping different portions of the dummy electrode layer.

7. In paragraph 6, A second pixel electrode disposed on the insulating layer in the display area, adjacent to the first pixel electrode but separated from each other; and In the above display area, a third pixel electrode is further included, which is arranged on the insulating layer and is adjacent to the first pixel electrode and the second pixel electrode but is separated from each other; The above bank layer further defines a second opening overlapping the second pixel electrode and a third opening overlapping the third pixel electrode, The first opening and the second opening are defined in the same column, and the third opening is defined adjacent to the columns of the first opening and the second opening. A display panel, wherein the first dummy opening and the second dummy opening are defined in the same column, and the third dummy opening is defined adjacent to the columns of the first dummy opening and the second dummy opening.

8. In paragraph 7, The size of the first dummy opening and the size of the first opening are substantially the same, The size of the second dummy opening and the size of the second opening are substantially the same, A display panel wherein the size of the third dummy opening and the size of the third opening are substantially the same.

9. In paragraph 7, The size and shape of the first dummy opening are different from the size and shape of the first opening in the display panel.

10. In paragraph 6, A routing region is further defined on the substrate, located between the above-mentioned transparent region and the above-mentioned dummy region and surrounding the above-mentioned transparent region, The above dummy electrode layer extends toward the above routing area, A display panel, wherein the above bank layer further defines a fourth dummy opening, a fifth dummy opening, and a sixth dummy opening, each overlapping different portions of the dummy electrode layer located in the above routing area.

11. In paragraph 10, The sizes of the first dummy opening, the second dummy opening, and the third dummy opening are different from each other, The size of the fourth dummy opening and the size of the first dummy opening are substantially the same, The size of the fifth dummy opening and the size of the second dummy opening are substantially the same, A display panel, wherein the size of the sixth dummy opening and the size of the third dummy opening are substantially the same.

12. In paragraph 10, In the above routing area, the dummy electrode layer is a display panel that does not overlap with the transistor.

13. In paragraph 10, Further comprising a signal line electrically connected to the above driving circuit, The above signal line detours along the edge of the transmission area in the above routing area, A display panel in which the dummy electrode layer in the above routing area overlaps with the bypass portion of the signal line.

14. In paragraph 1, A display panel, wherein the above bank layer includes a light-blocking material.

15. A display panel having a transparent area, a dummy area surrounding the transparent area, and a display area surrounding the dummy area defined; and A component positioned to overlap the transparent area of ​​the display panel; including: The above display panel, A driving circuit disposed in the above display area and including a transistor; A voltage line disposed in the above display area and electrically connected to the driving circuit; Insulating layer on the above voltage line: A first pixel electrode disposed on the insulating layer in the above display area; A bank layer covering an edge of the first pixel electrode and defining a first opening overlapping the first pixel electrode; A light-emitting layer overlapping the first pixel electrode through the first opening of the bank layer; A counter electrode disposed on the light-emitting layer and overlapping the first pixel electrode and the light-emitting layer; and Including a dummy electrode layer arranged on the insulating layer in the above dummy area; An electronic device, wherein the bank layer defines a plurality of dummy openings extending toward the dummy region and overlapping the dummy electrode layer.

16. In paragraph 15, The above display panel, Further comprising a dummy transistor arranged under the dummy electrode layer, An electronic device wherein the dummy electrode layer is electrically insulated from the dummy transistor.

17. In paragraph 15, The above voltage line extends toward the dummy area, and a portion of the voltage line overlaps the dummy electrode layer, An electronic device wherein the above dummy electrode layer is electrically connected to the voltage line.

18. In paragraph 17, An electronic device wherein the voltage line has the same voltage level as the voltage level of the counter electrode.

19. In Article 17, The above driving circuit further includes an initialization transistor electrically connected to the first pixel electrode and initializing the first pixel electrode, An electronic device wherein the above voltage line is electrically connected to the above initialization transistor.

20. In paragraph 15, The above plurality of dummy openings in the above bank layer are, An electronic device comprising a first dummy opening, a second dummy opening, and a third dummy opening, each overlapping different parts of the dummy electrode layer.

21. In paragraph 20, The above display panel, A second pixel electrode disposed on the insulating layer in the display area, adjacent to the first pixel electrode but separated from each other; and In the above display area, a third pixel electrode is further included, which is arranged on the insulating layer and is adjacent to the first pixel electrode and the second pixel electrode but is separated from each other; The above bank layer further defines a second opening overlapping the second pixel electrode and a third opening overlapping the third pixel electrode, The first opening and the second opening are defined in the same column, and the third opening is defined adjacent to the columns of the first opening and the second opening. An electronic device, wherein the first dummy opening and the second dummy opening are defined in the same column, and the third dummy opening is defined adjacent to the columns of the first dummy opening and the second dummy opening.

22. In paragraph 21, The size of the first dummy opening and the size of the first opening are substantially the same, The size of the second dummy opening and the size of the second opening are substantially the same, An electronic device wherein the size of the third dummy opening and the size of the third opening are substantially the same.

23. In paragraph 21, An electronic device wherein the size and shape of the first dummy opening are different from the size and shape of the first opening.

24. In paragraph 20, A routing area is further defined on the display panel, located between the above-mentioned transparent area and the above-mentioned dummy area and surrounding the above-mentioned transparent area, The above dummy electrode layer extends toward the above routing area, An electronic device, wherein the above bank layer further defines a fourth dummy opening, a fifth dummy opening, and a sixth dummy opening, each overlapping different portions of the dummy electrode layer located in the above routing area.

25. In paragraph 24, The sizes of the first dummy opening, the second dummy opening, and the third dummy opening are different from each other, The size of the fourth dummy opening and the size of the first dummy opening are substantially the same, The size of the fifth dummy opening and the size of the second dummy opening are substantially the same, An electronic device, wherein the size of the sixth dummy opening and the size of the third dummy opening are substantially the same.

26. In paragraph 24, An electronic device in which, in the above routing area, the dummy electrode layer does not overlap with the transistor.

27. In paragraph 24, Further comprising a signal line electrically connected to the above driving circuit, The above signal line detours along the edge of the transmission area in the above routing area, An electronic device in which the dummy electrode layer in the above routing area overlaps with the bypass portion of the signal line.

28. In paragraph 15, The above display panel, A sealing layer on the counter electrode; and Further comprising a cover window on the above-mentioned bag layer, An electronic device, wherein the cover window includes a light-shielding portion overlapping at least one dummy opening among the dummy openings arranged in the dummy area and a light-transmitting portion overlapping at least another dummy opening among the dummy openings.

29. In paragraph 15, The above component is an electronic device including a sensor or a camera.

30. In paragraph 15, An electronic device, wherein the above-mentioned bank layer includes a light-shielding material.

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