Display device

Abstract

An embodiment of the present invention discloses a display device including: a data line connected to a pixel arranged in a display area and extending in a first direction; a shielding line disposed above the data line in the display area, extending in the first direction, and overlapping the data line in a plan view; and a first voltage line connected to the pixel, extending in a second direction perpendicular to the first direction, disposed below the data line, and overlapping the data line in a plan view.

Description

display device

[0001] The present invention relates to a pixel and a display device including the pixel.

[0002] In recent years, the uses of display devices have become increasingly diverse. Furthermore, as display devices become thinner and lighter, their applications are expanding.

[0003] As display devices are utilized in various ways, there are various methods for designing the form of display devices, and the functions that can be grafted or linked to display devices are increasing.

[0004] Embodiments of the present invention can provide a display device with improved display quality. However, these tasks are exemplary and do not limit the scope of the present invention.

[0005] A display device according to one embodiment of the present invention includes: a data line connected to a pixel arranged in a display area and extending in a first direction; a shield line arranged above the data line in the display area, extending in the first direction, and overlapping the data line in a plane; and a first voltage line connected to the pixel, extending in a second direction perpendicular to the first direction, arranged below the data line, and overlapping the data line in a plane.

[0006] In one embodiment, the pixel includes a first capacitor including a first electrode and a second electrode disposed on the first electrode and overlapping the first electrode in a plane; a first transistor connected to the first voltage line and the second electrode of the first capacitor; and a second transistor connected to the data line and the gate electrode of the first transistor; wherein the data line may be disposed on the same layer as the second electrode of the first capacitor, and a semiconductor layer of the first transistor may be disposed on the same layer as the first electrode of the first capacitor.

[0007] In one embodiment, the voltage supplied to the shielding line and the voltage supplied to the first electrode of the first capacitor may be different.

[0008] In one embodiment, the voltage supplied to the shielding line and the voltage supplied to the first electrode of the first capacitor may be the same.

[0009] In one embodiment, the first capacitor may further include a third electrode disposed below the first electrode, overlapping the first electrode in a plane, and connected to the second electrode.

[0010] In one embodiment, the first voltage line may be disposed on the same layer as the third electrode of the first capacitor and connected to the first electrode of the first capacitor.

[0011] In one embodiment, the device may further include a vertical conductive line disposed on the same layer as the shielding line, overlapping the second electrode of the first capacitor in a plane, and extending in the first direction.

[0012] In one embodiment, the vertical conductive line may be connected to a horizontal conductive line extending in the second direction and supplying a constant voltage to the pixel.

[0013] In one embodiment, the horizontal conductor may include the first voltage line.

[0014] In one embodiment, the pixel further includes a second capacitor connected to the second electrode of the first capacitor and the light-emitting element, wherein the light-emitting element includes a first electrode connected to the first transistor and a second electrode opposite the first electrode, and the second capacitor can be connected to the second electrode of the light-emitting element.

[0015] In one embodiment, the second voltage line may further include a second voltage line extending in a second direction and connected to the first electrode of the first capacitor.

[0016] In one embodiment, the device may further include a vertical conductive line disposed on the same layer as the shielding line, overlapping the first electrode of the first capacitor in a plane, and extending in the first direction.

[0017] In one embodiment, the vertical conductive line may supply a constant voltage to the pixel and be connected to a horizontal conductive line extending in the second direction.

[0018] In one embodiment, the horizontal conductor may include the second voltage line.

[0019] In one embodiment, the device may further include a voltage supply line disposed in a non-display area outside the display area, connected to the shielding line, and supplying a shielding voltage to the shielding line.

[0020] According to one embodiment of the present invention, a display device includes: a first pixel circuit arranged in a first circuit area; and a second pixel circuit arranged in a second circuit area adjacent to the first circuit area in a first direction; wherein each of the first pixel circuit and the second pixel circuit is connected to a light-emitting diode, and each of the first pixel circuit and the second pixel circuit includes: a data line extending in a second direction perpendicular to the first direction; a shield line arranged above the data line, extending in the second direction, and overlapping the first data line in a plane; a first voltage line extending in the first direction, arranged below the data line, and having a portion of the first voltage line overlapping the data line in a plane; a capacitor including a first electrode and a second electrode arranged above the first electrode and overlapping the first electrode in a plane; a first transistor connected to the first voltage line and the second electrode of the capacitor; It includes a second transistor connected to the data line and the gate electrode of the first transistor; a third transistor connected to the second voltage line extending in the first direction and the gate electrode of the first transistor; a fourth transistor connected to the first electrode of the light-emitting diode and the third voltage line extending in the first direction; and a conductive line disposed on the same layer as the shielding line, overlapping the second electrode of the capacitor in a plane, and extending in the second direction. The light emitting diode connected to the first pixel circuit emits light in a first color, the light emitting diode connected to the second pixel circuit emits light in a second color, the conductive line of the first pixel circuit is connected to one of the first voltage line, the second voltage line, the third voltage line, and the fourth voltage line connected to the second electrode of the light emitting diode, and the conductive line of the second pixel circuit is connected to one of the second voltage line, the third voltage line, and the fourth voltage line, excluding the first voltage line.

[0021] In one embodiment, the voltage supplied to the shielding line and the voltage supplied to the first electrode of the capacitor may be different.

[0022] In one embodiment, the voltage supplied to the shielding line and the voltage supplied to the first electrode of the capacitor may be the same.

[0023] In one embodiment, the capacitor may further include a third electrode disposed below the first electrode, planarly overlapping the first electrode, and connected to the second electrode.

[0024] In one embodiment, the first voltage line is disposed on the same layer as the third electrode of the capacitor and can be connected to the first electrode of the capacitor.

[0025] In one embodiment, the second voltage line may be disposed on the same layer as the third electrode of the capacitor and connected to the first electrode of the capacitor.

[0026] According to embodiments of the present invention, a display device with improved display quality can be provided. Of course, the scope of the present invention is not limited by these effects.

[0027] FIG. 1A, FIG. 1B and FIG. 2 are schematic drawings showing a display device according to one embodiment.

[0028] Figure 3 is an equivalent circuit diagram of a pixel according to one embodiment.

[0029] Figures 4a to 4c are schematic drawings showing shielding of a data line according to one embodiment.

[0030] Figures 5a to 5d are schematic drawings showing a shielding line according to one embodiment.

[0031] Fig. 6 is a schematic diagram showing the locations of transistors and capacitors of the pixels illustrated in Fig. 3.

[0032] Figures 7 to 16 are schematic layout diagrams showing the components of the pixels of Figure 3 layer by layer.

[0033] Fig. 17 is a cross-sectional view taken along line I-I' of Fig. 6.

[0034] Fig. 18 is a cross-sectional view taken along line II-II' of Fig. 6.

[0035] Figure 19 is a drawing showing the arrangement of data lines and signal lines according to a comparative example.

[0036] Figure 20 is a schematic diagram illustrating the arrangement of vertical conductive lines according to one embodiment.

[0037] Fig. 21 is an example of a cross-section of a second pixel according to one embodiment.

[0038] Figures 22 to 26 are equivalent circuits of pixels according to embodiments.

[0039] Figures 27 to 32 are equivalent circuit diagrams of pixels according to embodiments.

[0040] Fig. 33 is an equivalent circuit diagram of a pixel according to one embodiment.

[0041] Figure 34 is a schematic diagram showing the locations of transistors and capacitors of the pixels illustrated in Figure 33.

[0042] Figures 35 to 41 are schematic layout diagrams showing the components of the pixels of Figure 33 layer by layer.

[0043] Fig. 42 is a cross-sectional view taken along line III-III' of Fig. 34.

[0044] Figure 43 is a drawing showing the arrangement of data lines and signal lines according to a comparative example.

[0045] Figures 44 to 49 are equivalent circuits of pixels according to one embodiment.

[0046] Figures 50a to 51b are cross-sectional views showing the structure of display elements according to embodiments.

[0047] Fig. 52 is a cross-sectional view showing the structure of a pixel of a display device according to one embodiment.

[0048] A display device according to one embodiment of the present invention includes: a data line connected to a pixel arranged in a display area and extending in a first direction; a shield line arranged above the data line in the display area, extending in the first direction, and overlapping the data line in a plane; and a first voltage line connected to the pixel, extending in a second direction perpendicular to the first direction, arranged below the data line, and overlapping the data line in a plane.

[0049] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0050] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0051] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0052] In the examples below, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0053] In this specification, “A and / or B” refers to the case where it is A, or B, or both A and B. In addition, in this specification, “at least one of A and B” refers to the case where it is A, or B, or both A and B.

[0054] In the following embodiments, when X and Y are said to be connected, this may include cases where X and Y are functionally connected, cases where X and Y are directly connected, or cases where another component is interposed between X and Y and they are indirectly connected. Here, X and Y may be components (e.g., devices, elements, circuits, wiring, electrodes, terminals, films, layers, regions, etc.). For example, cases where X and Y are electrically connected may include cases where X and Y are directly electrically connected, and / or cases where X and Y are indirectly electrically connected with another component interposed between X and Y. Cases where X and Y are indirectly electrically connected may include cases where one or more elements (e.g., switches, transistors, capacitors, inductors, resistors, diodes, etc.) that enable electrical connection between X and Y are connected between X and Y. Therefore, a given connection relationship, for example, a connection relationship shown in the drawings or detailed description, is not limited to this, and may also include connection relationships other than those shown in the drawings or detailed description.

[0055] The case where X and Y are electrically connected may include, for example, a case where one or more elements (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) that enable electrical connection between X and Y are connected between X and Y.

[0056] In the following embodiments, "ON" used in connection with a device state may refer to an activated state of the device, and "OFF" may refer to a deactivated state of the device. "ON" used in connection with a signal received by the device may refer to a signal that activates the device, and "OFF" may refer to a signal that deactivates the device. The device may be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "ON" voltages for P-type transistors and N-type transistors are at opposite (low vs. high) voltage levels.

[0057] In the following examples, the x-direction, y-direction, and z-direction are not limited to directions along the three axes on the orthogonal coordinate system, but can be interpreted in a broad sense that includes them. For example, the x-direction, y-direction, and z-direction may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0058] A display device according to embodiments of the present invention is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), and the like, as well as a television, a laptop, a monitor, a billboard, and an Internet of Things (IOT) device. In addition, a display device according to an embodiment can be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). In addition, the display device according to one embodiment may be used as a dashboard of a vehicle, a CID (Center Information Display) placed on the center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, and a display placed on the back of the front seat as entertainment for the rear seat of a vehicle. In addition, the display device may be a flexible device.

[0059] FIG. 1A, FIG. 1B and FIG. 2 are schematic drawings showing a display device according to one embodiment.

[0060] Referring to FIGS. 1A and 1B, the display device (10) may include a display area (DA) for displaying an image and a peripheral area (PA) outside the display area (DA). The display area (DA) may be entirely surrounded by the peripheral area (PA).

[0061] When the display area (DA) is viewed in a planar shape, the display area (DA) may have a rectangular shape. In another embodiment, the display area (DA) may have a polygonal shape such as a triangle, a pentagon, a hexagon, a circular shape, an oval shape, an irregular shape, etc. The display area (DA) may have a rounded corner at an edge. In one embodiment, the display device (10) may have a display area (DA) of a shape in which the length in the x direction is longer than the length in the y direction, as illustrated in FIG. 1A. In another embodiment, the display device (10) may have a display area (DA) of a shape in which the length in the y direction is longer than the length in the x direction, as illustrated in FIG. 1B.

[0062] Referring to FIG. 2, a display device (10) according to one embodiment may include a pixel area (11), a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0063] The pixel unit (11) may be provided in the display area (DA). The peripheral area (PA) may include various conductive lines for transmitting electrical signals to be applied to the display area (DA), peripheral circuits electrically connected to the pixel circuits, and pads to which a printed circuit board or driver IC chip is attached. For example, the peripheral area (PA) may include a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0064] As illustrated in FIG. 2, a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of pixels (PX) connected thereto may be arranged in a display area (DA). The plurality of pixels (PX) may be arranged in various configurations, such as a stripe arrangement, a pentile arrangement, a diamond arrangement, and a mosaic arrangement, to implement an image. Each pixel (PX) includes an organic light-emitting diode (OLED) as a display element (light-emitting element), and the organic light-emitting diode (OLED) may be connected to a pixel circuit. The pixel (PX) may emit light of, for example, red, green, blue, or white through the organic light-emitting diode (OLED). Each pixel (PX) may be connected to at least one corresponding gate line among the plurality of gate lines (GL) and to a corresponding data line among the plurality of data lines (DL).

[0065] The gate lines (GL) can each extend in the x direction (row direction) and be connected to pixels (PX) located in the same row. The gate lines (GL) can transmit gate signals to pixels (PX) located in the same row. The data lines (DL) can each extend in the y direction (column direction) and be connected to pixels (PX) located in the same column. The data lines (DL) can each transmit data signals (DATA) to pixels (PX) located in the same column in synchronization with the gate signals.

[0066] In one embodiment, the peripheral area (PA) may be a non-display area in which no pixels (PX) are arranged. In another embodiment, a plurality of pixels (PX) may be arranged in a plane overlapping the gate driving circuit (13) at at least one corner of the peripheral area (PA). This can reduce the dead area and expand the display area (DA).

[0067] The gate driving circuit (13) is connected to a plurality of gate lines (GL), and can generate a gate signal in response to a driving control signal (GCS) from a controller (19) and sequentially supply the same to the gate lines (GL). The gate line (GL) can be connected to a gate of a transistor included in a pixel (PX). The gate signal (GS) can be a gate control signal that controls the turn-on and turn-off of a transistor whose gate is connected to the gate line (GL). The gate signal (GS) can be a signal including a gate-on voltage that can turn on the transistor and a gate-off voltage that can turn off the transistor. In one embodiment, the gate-on voltage can be a high-level voltage (first-level voltage) or a low-level voltage (second-level voltage).

[0068] In FIGS. 1a, 1b and 2, the pixel (PX) is illustrated as being connected to one gate line (GL), but this is merely exemplary, and the pixel (PX) may be connected to two or more gate lines, and the gate driving circuit (13) may supply two or more gate signals, at different timings for applying the gate-on voltage, to the corresponding gate lines.

[0069] The data driving circuit (15) is connected to a plurality of data lines (DL) and can supply a data signal (DATA) to the data lines (DL) in response to a driving control signal (DCS) from a controller (19). The data signal (DATA) supplied to the data line (DL) can be supplied to a pixel (PX) supplied with a gate signal (GS). The data driving circuit (15) can convert input image data having a grayscale input from the controller (19) into a data signal (DATA) in the form of a voltage or current.

[0070] The power supply circuit (17) can generate signals (voltage and current) for driving the pixel (PX) in response to a driving control signal (PCS) from the controller (19). The power supply circuit (17) can generate a first driving voltage (ELVDD) and a second driving voltage (ELVSS) and supply them to the pixels (PX). The first driving voltage (ELVDD) can be a high-level voltage provided to a first terminal of a driving transistor connected to a first electrode (pixel electrode or anode) of a display element included in the pixel (PX). The second driving voltage (ELVSS) can be a low-level voltage provided to a second electrode (counter electrode or cathode) of a display element included in the pixel (PX). The power supply circuit (17) can generate a high-level high voltage (VGH) and a low-level low voltage (VGL) and supply them to the gate driving circuit (13).

[0071] The controller (19) can generate drive control signals (GCS, DCS, PCS) based on signals input from the outside and supply them to the gate drive circuit (13), the data drive circuit (15), and the power supply circuit (17). The drive control signal (GCS) output to the gate drive circuit (13) can include a gate start signal and a plurality of clock signals. The drive control signal (DCS) output to the data drive circuit (15) can include a data start signal and a plurality of clock signals.

[0072] The display device (10) includes a display panel, and the display panel may include a substrate. Pixels (PX) may be arranged in a display area (DA) of the substrate. Part or all of the gate driving circuit (13) may be formed directly in a peripheral area (PA) of the substrate during a process of forming transistors constituting a pixel circuit in the display area (DA) of the substrate. The data driving circuit (15), the power supply circuit (17), and the controller (19) may be formed in the form of separate integrated circuit chips or a single integrated circuit chip, respectively, and may be arranged on an FPCB (flexible printed circuit board) electrically connected to pads arranged on one side of the substrate. In another embodiment, the data driving circuit (15), the power supply circuit (17), and the controller (19) may be arranged directly on the substrate in a COG (Chip On Glass) or COP (Chip On Plastic) manner.

[0073] Figure 3 is an equivalent circuit diagram of a pixel according to one embodiment.

[0074] Referring to FIG. 3, a pixel (PX) may include a pixel circuit (PC) and an organic light-emitting diode (OLED) as a display element connected to the pixel circuit (PC).

[0075] A pixel (PX) can be connected to a first gate line (GWL) that transmits a first gate signal (GW), a second gate line (GIL) that transmits a second gate signal (GI), a third gate line (GRL) that transmits a third gate signal (GR), a fourth gate line (EML) that transmits a fourth gate signal (EM), a fifth gate line (EMBL) that transmits a fifth gate signal (EMB), and a data line (DL) that transmits a data signal (DATA). Since the light emission of the pixel (PX) is controlled by the fourth gate signal (EM) and the fifth gate signal (EMB), the fourth gate signal (EM) and the fifth gate signal (EMB) may be referred to as light emission control signals, and the fourth gate line (EML) and the fifth gate line (EMBL) may be referred to as light emission control lines. Additionally, the pixel (PX) can be connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), a reference voltage line (VRL) that transmits a reference voltage (Vref), and an initialization voltage line (VL) that transmits an initialization voltage (Vint).

[0076] In one embodiment, a plurality of transistors included in a pixel circuit (PC) may be N-type oxide thin film transistors. The oxide thin film transistor may include a semiconductor layer formed of an amorphous or crystalline oxide semiconductor. The oxide semiconductor may be a Zn oxide-based material, such as Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In some embodiments, the oxide semiconductor may be an In-Ga-Zn-O (IGZO) semiconductor. In some embodiments, the oxide semiconductor may be an In-Sn-Ga-Zn-O (ITGZO) semiconductor. In one embodiment, the oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. However, this is merely exemplary, and the N-type transistors are not limited thereto. For example, the semiconductor layer included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polysilicon), an organic semiconductor, etc.

[0077] The pixel circuit (PC) may include first to sixth transistors (T1 to T6), and first and second capacitors (C1 and C2). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal (DATA), and the second to sixth transistors (T2 to T6) may be switching transistors that transmit signals. The first terminal (first electrode) and the second terminal (second electrode) of each of the first to sixth transistors (T1 to T6) may be a source or a drain depending on the voltage of the first terminal and the second terminal. For example, depending on the voltage of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. Hereinafter, the node to which the first gate of the first transistor (T1) is connected may be defined as the first node (N1), and the node to which the second terminal of the first transistor (T1) is connected may be defined as the second node (N2).

[0078] A first transistor (T1) may be connected to a driving voltage line (PL) and an organic light-emitting diode (OLED). The first transistor (T1) may be connected between a fifth transistor (T5) and a sixth transistor (T6). The first transistor (T1) may include a gate, a first terminal, and a second terminal connected to a second node (N2). The first transistor (T1) may be a dual-gate transistor. The first transistor (T1) may include a first gate connected to the first node (N1). The first transistor (T1) may further include a second gate connected to its second terminal. The first gate and the second gate of the first transistor (T1) may be arranged to face each other on different layers. For example, the first gate and the second gate of the first transistor (T1) may be positioned facing each other with a semiconductor layer between them. Hereinafter, when referring to the gate (or gate electrode) of the first transistor (T1), it may mean the first gate that receives the data signal (DATA) as a gate signal.

[0079] A first gate of a first transistor (T1) may be connected to a second terminal of a second transistor (T2), a first terminal of a third transistor (T3), and a first capacitor (C1). A second gate of the first transistor (T1) may be connected to a first terminal of a sixth transistor (T6), a first capacitor (C1), and a second capacitor (C2). A first terminal of the first transistor (T1) may be connected to a driving voltage line (PL) via a fifth transistor (T5), and a second terminal of the first transistor (T1) may be connected to a pixel electrode of an organic light-emitting diode (OLED) via a sixth transistor (T6). A first terminal of the first transistor (T1) may be connected to a second terminal of the fifth transistor (T5). The second terminal of the first transistor (T1) can be connected to the first terminal of the sixth transistor (T6), the first capacitor (C1), and the second capacitor (C2). The first transistor (T1) can receive a data signal (DATA) according to the switching operation of the second transistor (T2) and output a driving current corresponding to the data signal (DATA).

[0080] The second transistor (T2) may be connected to the data line (DL) and the first gate of the first transistor (T1). The second transistor (T2) may include a gate connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second terminal of the second transistor (T2) may be connected to the first gate of the first transistor (T1), the first terminal of the third transistor (T3), and the first capacitor (C1). The second transistor (T2) may be turned on by the first gate signal (GW) supplied from the first gate line (GWL) to electrically connect the data line (DL) and the first node (N1), and may transmit a data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0081] A third transistor (T3) may be connected to a first gate of a first transistor (T1) and a reference voltage line (VRL). The third transistor (T3) may include a gate connected to a third gate line (GRL), a first terminal connected to a first node (N1), and a second terminal connected to the reference voltage line (VRL). The first terminal of the third transistor (T3) may be connected to a first gate of the first transistor (T1), a second terminal of a second transistor (T2), and a first capacitor (C1). The third transistor (T3) may be turned on by a third gate signal (GR) supplied from the third gate line (GRL) and may transfer a reference voltage (Vref) transferred to the reference voltage line (VRL) to the first node (N1).

[0082] The fourth transistor (T4) may be connected to the sixth transistor (T6) and the initialization voltage line (VL). The fourth transistor (T4) may be connected between an organic light-emitting diode (OLED) and the initialization voltage line (VL). The fourth transistor (T4) may include a gate connected to a second gate line (GIL), a first terminal connected to a third node (N3), and a second terminal connected to the initialization voltage line (VL). The first terminal of the fourth transistor (T4) may be connected to the second terminal of the sixth transistor (T6) and a pixel electrode of the organic light-emitting diode (OLED). The fourth transistor (T4) is turned on by the second gate signal (GI) supplied from the second gate line (GIL) and can transmit the initialization voltage (Vint) transmitted to the initialization voltage line (VL) to the third node (N3).

[0083] The fifth transistor (T5) may be connected to the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate connected to the fourth gate line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to a fourth gate signal (EM) supplied from the fourth gate line (EML).

[0084] The sixth transistor (T6) may be connected to the first transistor (T1) and the organic light-emitting diode (OLED). The sixth transistor (T6) may be connected between the second node (N2) and the third node (N3). The sixth transistor (T6) may include a gate connected to the fifth gate line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The first terminal of the sixth transistor (T6) may be connected to the second terminal of the first transistor (T1), the first capacitor (C1), and the second capacitor (C2). The second terminal of the sixth transistor (T6) may be connected to the first terminal of the fourth transistor (T4) and the pixel electrode of the organic light-emitting diode (OLED). The sixth transistor (T6) can be turned on or off according to the fifth gate signal (EMB) supplied from the fifth gate line (EMBL).

[0085] A first capacitor (C1) may be connected between a first gate of a first transistor (T1) and a second terminal of the first transistor (T1). A first electrode of the first capacitor (C1) may be connected to a first node (N1), and a second electrode of the first capacitor (C1) may be connected to a second node (N2). A first electrode of the first capacitor (C1) may be connected to a first gate of the first transistor (T1), a second terminal of the second transistor (T2), and a first terminal of a third transistor (T3). A second electrode of the first capacitor (C1) may be connected to a second terminal and a second gate of the first transistor (T1), a second electrode of the second capacitor (C2), and a first terminal of a sixth transistor (T6). The first capacitor (C1) is a storage capacitor and can store a voltage corresponding to the threshold voltage of the first transistor (T1) and a data signal (DATA).

[0086] When the third transistor (T3) and the fifth transistor (T5) are turned on together, the first transistor (T1) can be turned on. When the voltage of the second terminal of the first transistor (T1) becomes the difference (Vref-Vth) between the reference voltage (Vref) and the threshold voltage (Vth) of the first transistor (T1), the first transistor (T1) is turned off, and a voltage corresponding to the threshold voltage (Vth) of the first transistor (T1) is stored in the first capacitor (C1), so that the threshold voltage (Vth) of the first transistor (T1) can be compensated.

[0087] The second capacitor (C2) may be connected between the driving voltage line (PL) and the second node (N2). The first electrode of the second capacitor (C2) may be connected to the driving voltage line (PL). The second electrode of the second capacitor (C2) may be connected to the second terminal and the second gate of the first transistor (T1), the second electrode of the first capacitor (C1), and the first terminal of the sixth transistor (T6). The second capacitor (C2) may allow the voltage stored in the first capacitor (C1) to be maintained.

[0088] The capacitance of each of the first capacitor (C1) and the second capacitor (C2) may vary depending on the color of light emitted by the pixel (PX).

[0089] An organic light-emitting diode (OLED) may be connected to a first transistor (T1) via a sixth transistor (T6). The organic light-emitting diode (OLED) includes a pixel electrode (anode) connected to a third node (N3) and a counter electrode (cathode) facing the pixel electrode, and the counter electrode may be supplied with a common voltage (ELVSS). The counter electrode may be a common electrode common to a plurality of pixels (PX). A driving current output by the first transistor (T1) flows through the organic light-emitting diode (OLED) by the turned-on fifth transistor (T5) and the turned-on sixth transistor (T6), and the organic light-emitting diode (OLED) may emit light with a brightness corresponding to the magnitude of the driving current.

[0090] Figures 4a to 4c are schematic drawings illustrating shielding of a data line according to one embodiment. Figures 5a to 5d are schematic drawings illustrating shielding lines according to one embodiment.

[0091] An embodiment of the present invention may include a shield line (VEL) that overlaps the planar data line (DL) above and / or below the data line (DL). At least one insulating layer (IL) may be disposed between the data line (DL) and the shield line (VEL). Accordingly, the influence of the coupling that occurs between the data line (DL) and at least one signal line due to a change in the data signal (DATA) on the gate-source voltage change of the first transistor (T1), which is a driving transistor, can be minimized.

[0092] In one embodiment, as illustrated in FIG. 4a, a shield line (VEL) may be disposed on top of the data line (DL) and overlapped with the planar data line (DL). In one embodiment, as illustrated in FIG. 4b, a shield line (VEL) may be disposed below the data line (DL) and overlapped with the planar data line (DL). In one embodiment, as illustrated in FIG. 4c, the shield line (VEL) includes a first shield line (VEL1) and a second shield line (VEL2), and the first shield line (VEL1) may be disposed above the data line (DL) and overlapped with the planar data line (DL), and the second shield line (VEL2) may be disposed below the data line (DL) and overlapped with the planar data line (DL).

[0093] As illustrated in FIGS. 5A to 5D , the shield line (VEL) may extend in the y direction in the display area (DA) of the substrate and may have a stripe shape. In one embodiment, the shield line (VEL) may be arranged to overlap the planar data line (DL) in each pixel column of the display area (DA). In one embodiment, the shield line (VEL) may be arranged to overlap the planar data line (DL) in some pixel columns at predetermined intervals among the pixel columns of the display area (DA). The shield line (VEL) may be a conductive line that is not electrically connected to the pixels (PX) in the display area (DA).

[0094] The shield line (VEL) is electrically connected to a shield voltage supply line (PVEL) arranged in the peripheral area (PA) of the substrate, and can receive a positive shield voltage (VES) from the shield voltage supply line (PVEL).

[0095] In one embodiment, as illustrated in FIG. 5A, a shield voltage supply line (PVEL) is arranged to extend in the x direction above the display area (DA) and can be electrically connected to ends of a plurality of shield lines (VEL) extending from the display area (DA).

[0096] In one embodiment, as illustrated in FIG. 5b, a shield voltage supply line (PVEL) is arranged to extend in the x direction below the display area (DA) and can be electrically connected to ends of a plurality of shield lines (VEL) extending from the display area (DA).

[0097] In one embodiment, as illustrated in FIG. 5c, the shield voltage supply line (PVEL) may include a first voltage supply line (PVEL1) extending in the x direction and arranged above the display area (DA) and a second voltage supply line (PVEL2) extending in the x direction and arranged below the display area (DA). One ends of the plurality of shield lines (VEL) may be electrically connected to the first voltage supply line (PVEL1), and the other ends of the plurality of shield lines (VEL) may be electrically connected to the second voltage supply line (PVEL2).

[0098] In one embodiment, the shield voltage (VES) supplied by the shield voltage supply line (PVEL) may be a separate voltage that is different from the plurality of voltages supplied to the pixel (PX) (e.g., the drive voltage (ELVDD), the reference voltage (Vref), and the initialization voltage (Vint)).

[0099] In one embodiment, the shield voltage (VES) supplied by the shield voltage supply line (PVEL) may be one of a plurality of voltages (e.g., a driving voltage (ELVDD), a reference voltage (Vref), and an initialization voltage (Vint)) supplied to the pixels (PX). The shield line (VEL) may not be electrically connected to the driving voltage line (PL), the reference voltage line (VRL), and the initialization voltage line (VL), which are arranged in the display area (DA) and are electrically connected to the pixels (PX). For example, as illustrated in FIG. 5D, the shield voltage supply line (PVEL) may supply the driving voltage (ELVDD) to the shield line (VEL), and the driving voltage supply line (PPL) may supply the driving voltage (ELVDD) to the driving voltage line (PL). The driving voltage line (PL) may be electrically connected to the pixels (PX) arranged in the display area (DA). The shield line (VEL) is placed in the display area (DA), but may not be electrically connected to the pixels (PX) placed in the display area (DA).

[0100] In one embodiment, the shield line (VEL) may be supplied with one of the constant voltages (e.g., high voltage (VGH), low voltage (VGL), ground voltage, etc.) supplied to an external circuit (e.g., gate driver circuit) that supplies electrical signals to the pixel (PX).

[0101] Even if a change in the data signal (DATA) causes a voltage change in the shield line (VEL) due to the coupling of the capacitor formed between the data line (DL) and the shield line (VEL), since the shield line (VEL) is not electrically connected to the pixel (PX), voltage changes at the terminals of other elements of the pixel (PX) can be prevented (minimized).

[0102] FIG. 6 is a schematic layout diagram showing the positions of transistors, capacitors, etc. of the pixel shown in FIG. 3. FIGS. 7 to 16 are schematic layout diagrams showing the components of the pixel of FIG. 3 layer by layer. FIGS. 13 to 15 are schematic diagrams showing the arrangement of vertical conductive lines according to one embodiment. FIG. 17 is a cross-sectional view taken along line II-I' of FIG. 6. FIG. 18 is a cross-sectional view taken along line II-II' of FIG. 6. FIG. 19 is a diagram showing the arrangement of data lines and signal lines according to a comparative example. FIG. 20 is a schematic diagram showing the arrangement of vertical conductive lines according to one embodiment. FIG. 21 is an example of a cross-section of a second pixel according to one embodiment.

[0103] A plurality of pixels (PX) arranged in a display area (DA) may include a first pixel (PX1) emitting light in a first color, a second pixel (PX2) emitting light in a second color, and a third pixel (PX3) emitting light in a third color. For example, the first pixel (PX1) may be a red pixel, the second pixel (PX2) may be a green pixel, and the third pixel (PX3) may be a blue pixel. The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may be repeatedly arranged in a predetermined pattern in the x direction and the y direction. The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may each include an organic light-emitting diode (OLED) as a pixel circuit and a display element electrically connected to the pixel circuit.

[0104] The display area (DA) defined on the substrate (100) is an area where rows (pixel rows) and columns (pixel columns) intersect, and may include a plurality of circuit areas in which pixel circuits are arranged. In one embodiment, a unit circuit area including two or more circuit areas adjacent in the x-direction is defined, and a unit pixel may be defined by pixels arranged in the circuit areas constituting the unit circuit area. For example, a unit circuit area (PCAu) may include three first circuit areas (PCA1), second circuit areas (PCA2), and third circuit areas (PCA3) adjacent in the x-direction, and a unit pixel may include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3). The first circuit area (PCA1) may be an area in which the pixel circuit of the first pixel (PX1) is arranged. The second circuit area (PCA2) may be an area in which the pixel circuit of the second pixel (PX2) is arranged. The third circuit area (PCA3) may be an area where the pixel circuit of the third pixel (PX3) is placed.

[0105] In FIG. 6, the pixel circuits arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) may each correspond to the pixel circuit (PC) of the pixel illustrated in FIG. 3.

[0106] In one embodiment, different initialization voltages (Vint) may be supplied to the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) in consideration of the light-emitting characteristics of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3). For example, the pixel circuit (PC) of the first pixel (PX1) may be connected to the 1-1 initialization voltage line (VL11), the pixel circuit (PC) of the second pixel (PX2) may be connected to the 1-2 initialization voltage line (VL12), and the pixel circuit (PC) of the third pixel (PX3) may be connected to the 1-3 initialization voltage line (VL13). The initialization voltage supplied to the 1-1 initialization voltage line (VL11), the initialization voltage supplied to the 1-2 initialization voltage line (VL12), and the initialization voltage supplied to the 1-3 initialization voltage line (VL13) may be different from each other.

[0107] The same components may be arranged in each layer of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). Hereinafter, for the convenience of illustration and description, identification numbers are assigned to the components of the pixel circuit (PC) arranged in the first circuit area (PCA1), and the description will be centered on the first circuit area (PCA1), and this may be equally applied to the same components of the second circuit area (PCA2) and the third circuit area (PCA3). Hereinafter, description will be made with reference to FIGS. 7 to 18. Hereinafter, the connection electrode may be an electrode that electrically connects conductive lines and electrodes (conductive patterns) arranged in different layers to transmit a signal.

[0108] A first conductive layer may be disposed on a substrate (100). As illustrated in FIG. 7, the first conductive layer may include a conductive line (200), a first electrode (210), a lower first gate line (GWLb), a reference voltage line (VRL), a first-second initialization voltage line (VL12), a first-third initialization voltage line (VL13), and a repair line (RL). In one embodiment, a barrier layer may be further disposed between the substrate (100) and the first conductive layer.

[0109] The first electrode (210) may be arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) in an island type. The first electrode (210) may include the second gate electrode (G12) of the first transistor (T1), the lower second electrode (C12b, FIG. 18) of the first capacitor (C1), and the lower first electrode (C21b, FIG. 18) of the second capacitor (C2).

[0110] The conductive line (200) may extend in the x direction and be arranged to cross the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The conductive line (200) may be a driving voltage line (PL) to which a driving voltage (ELVDD) is applied. Hereinafter, the conductive line (200) and the driving voltage line (PL) may be used interchangeably. The conductive line (200) may include a main line (200m) extending in the x direction in each circuit area and a protrusion (200p) protruding in the +y direction from the main line (200m).

[0111] The lower first gate line (GWLb), the reference voltage line (VRL), the first-second initialization voltage line (VL12), and the first-third initialization voltage line (VL13) extend in the x direction and can be arranged to cross the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0112] The repair line (RL) extends in the x direction and can be arranged across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0113] A first insulating layer (101) is disposed on a substrate (100) to cover a first conductive layer, and a semiconductor layer (ACT) including an oxide semiconductor may be disposed on the first insulating layer (101), as illustrated in FIG. 8. The semiconductor layer (ACT) may include a first semiconductor layer (ACT1), a second semiconductor layer (ACT2), a third semiconductor layer (ACT3), and a fourth semiconductor layer (ACT4). The semiconductor layer (ACT) may include a source region, a drain region, and a channel region between the source region and the drain region of each of the first to sixth transistors (T1 to T6). The source region or the drain region may be interpreted as a source electrode or a drain electrode of the transistor, depending on the case.

[0114] Fig. 11 is a diagram illustrating transistors and capacitors of a first circuit area (PCA1). Referring to Fig. 11, a first semiconductor layer (ACT1) may include a source area (S1) and a drain area (D1) of a first transistor (T1) and a source area (S5) and a drain area (D5) of a fifth transistor (T5). A second semiconductor layer (ACT2) may include a source area (S2) and a drain area (D2) of a second transistor (T2) and a source area (S3) and a drain area (D3) of a third transistor (T3). A third semiconductor layer (ACT3) may include a source area (S4) and a drain area (D4) of a fourth transistor (T4) and a source area (S6) and a drain area (D6) of a sixth transistor (T6). The fourth semiconductor layer (ACT4) may include a second electrode (C22, FIG. 18) of a second capacitor (C2).

[0115] A second insulating layer (102) may be disposed on a first insulating layer (101) to cover a semiconductor layer (ACT), and a second conductive layer may be disposed on the second insulating layer (102). As illustrated in FIG. 9, the second conductive layer may include a second electrode (220), a third electrode (230), an upper first gate line (GWLt), a second gate line (GIL), a third gate line (GRL), a fourth gate line (EML), a fifth gate line (EMBL), and a first-first initialization voltage line (VL11).

[0116] The second electrode (220) and the third electrode (230) may be provided in an island type. The second electrode (220) and the third electrode (230) may be respectively arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). An opening (GOP) that overlaps the first electrode (210) on a plane may be defined in the second electrode (220).

[0117] The upper first gate line (GWLt), second gate line (GIL), third gate line (GRL), fourth gate line (EML), fifth gate line (EMBL), and first-first initialization voltage line (VL11) extend in the x direction and can be arranged to cross the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0118] The upper first gate line (GWLt) may roughly overlap the lower first gate line (GWLtb) in a plan view, and may have a groove (HM) corresponding to a portion of the lower first gate line (GWLb). In one embodiment, a groove (HM) corresponding to a portion of the lower first gate line (GWLb) may be provided on a portion of the upper first gate line (GWLt) passing through the third circuit area (PCA3).

[0119] As illustrated in Fig. 11, the second conductive layer may include gate electrodes (G1 to G6) of the first to sixth transistors (T1 to T6). The planar gate electrodes (G1 to G6) may overlap channel regions of the semiconductor layer (ACT).

[0120] Referring to FIG. 11, the second electrode (220) may include a first gate electrode (G11) of the first transistor (T1) and a first electrode (C11, FIG. 18) of the first capacitor (C1). The first gate electrode (G11) may overlap the first semiconductor layer (ACT1) in a plan view. The third electrode (230) may include a gate electrode (G2) of the second transistor (T2). The gate electrode (G2) of the second transistor (T2) may overlap the second semiconductor layer (ACT2) in a plan view. The gate electrode (G3) of the third transistor (T3) in a plan view may be a part of a third gate line (GRL) that overlaps the second semiconductor layer (ACT2). The gate electrode (G4) of the fourth transistor (T4) on the plane may be a part of the second gate line (GIL) overlapping the third semiconductor layer (ACT3). The gate electrode (G5) of the fifth transistor (T5) on the plane may be a part of the fourth gate line (EML) overlapping the first semiconductor layer (ACT1). The gate electrode (G6) of the sixth transistor (T6) on the plane may be a part of the fifth gate line (EMBL) overlapping the third semiconductor layer (ACT3).

[0121] A third insulating layer (103) may be disposed on a second insulating layer (102) to cover a second conductive layer, and a third conductive layer may be disposed on the third insulating layer (103). As illustrated in Fig. 10, the third conductive layer may include a data line (DL) and connection electrodes (270, 271, 272, 273, 274, 275, 276, 277a, 277b, 277c).

[0122] The data line (DL) can be arranged to extend in the y direction in each circuit area. The data line (DL) can be electrically connected to the drain region (D2) of the second transistor (T2) through a contact hole (43) penetrating the second insulating layer (102) and the third insulating layer (103). The data line (DL) on the plane can overlap the conductive line (200).

[0123] The connecting electrode (270) may include a first region (270a) that overlaps the first electrode (210) and the second electrode (220) on a plane, and a second region (270b) that protrudes in the -y direction from the first region (270a). The connecting electrode (270) may electrically connect the source region (S1) of the first transistor (T1) to the second gate electrode (G12) of the first transistor (T1) and the drain region (D6) of the sixth transistor (T6).

[0124] The first region (270a) of the connecting electrode (270) can be electrically connected to the source region (S1) of the first transistor (T1) through a contact hole (42) penetrating the second insulating layer (102) and the third insulating layer (103). The connecting electrode (270) can include a source electrode electrically connected to the source region (S1) of the first transistor (T1), an upper second electrode (C12t, FIG. 18) of the first capacitor (C1), and an upper first electrode (C21t, FIG. 18) of the second capacitor (C2). The first region (270a) of the connecting electrode (270) can be electrically connected to the first electrode (210) through a contact hole (41) penetrating the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103). The first electrode (210) can be the second gate electrode (G12) of the first transistor (T1). As the connecting electrode (270) is connected to the first electrode (210), the second gate electrode (G12) of the first transistor (T1) can be electrically connected to the source region (S1) of the first transistor (T1).

[0125] The second region (270b) of the connecting electrode (270) can be electrically connected to the drain region (D6) of the sixth transistor (T6) through a contact hole (50) penetrating the second insulating layer (102) and the third insulating layer (103).

[0126] The connection electrode (271) can be electrically connected to the gate electrode (G2) of the second transistor (T2) through a contact hole (45) penetrating the third insulating layer (103). The connection electrode (271) can be electrically connected to the upper first gate line (GWLt) through a contact hole (44) penetrating the third insulating layer (103). The connection electrode (272) arranged in at least one circuit area among the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) can be electrically connected to the lower first gate line (GWLb) through a contact hole (58) penetrating the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103). The contact hole (58) can be positioned corresponding to the groove of the upper first gate line (GWLt).

[0127] The connecting electrode (272) is electrically connected to the drain region (D3) of the third transistor (T3) through a contact hole (46) penetrating the second insulating layer (102) and the third insulating layer (103), and can be electrically connected to the reference voltage line (VRL) through a contact hole (47) penetrating the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103).

[0128] The connecting electrode (273) may be electrically connected to the source region (S2) of the second transistor (T2) and the source region (S3) of the third transistor (T3) through a contact hole (48) penetrating the second insulating layer (102) and the third insulating layer (103). The connecting electrode (273) may be electrically connected to the second electrode (220) through a contact hole (49) penetrating the third insulating layer (103), and may be electrically connected to the first gate electrode (G11) of the first transistor (T1). The connecting electrode (273) may be a node electrode corresponding to the first node (N1) of FIG. 3. The connecting electrode (273) may be a bridge electrode electrically connecting at least two transistors. For example, the connecting electrode (273) may be a bridge electrode connecting the first gate electrode (G11) of the first transistor (T1), the source region (S2) of the second transistor (T2), and the source region (S3) of the third transistor (T3).

[0129] The connecting electrode (274) can be electrically connected to the conductive line (200) through a contact hole (51) penetrating the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103). The connecting electrode (274) can be electrically connected to the drain region (D5) of the fifth transistor (T5) through a contact hole (52) penetrating the second insulating layer (102) and the third insulating layer (103). Accordingly, the drain region (D5) of the fifth transistor (T5) can be electrically connected to the conductive line (200).

[0130] The connecting electrode (275) can be electrically connected to the fourth semiconductor layer (ACT4) through a contact hole (53) penetrating the second insulating layer (102) and the third insulating layer (103). The connecting electrode (275) can be electrically connected to the conductive line (200) through a contact hole (54) penetrating the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103). Accordingly, the driving voltage (ELVDD) can be supplied to the fourth semiconductor layer (ACT4) including the second electrode (C22) of the second capacitor (C2).

[0131] The connection electrode (276) can be electrically connected to the source region (S6) of the sixth transistor (T6) and the drain region (D4) of the fourth transistor (T4) through a contact hole (55) penetrating the second insulating layer (102) and the third insulating layer (103). The planar connection electrode (276) can overlap a portion of the repair line (RL). The connection electrode (276) is insulated from the repair line (RL) and can be electrically connected to the repair line (RL) when a defect occurs in the pixel circuit arranged in the circuit area later.

[0132] In the first circuit area (PCA1), the connecting electrode (277a) can be electrically connected to the source area (S4) of the fourth transistor (T4) through a contact hole (56) penetrating the second insulating layer (102) and the third insulating layer (103). The connecting electrode (277a) can be connected to the first-first initialization voltage line (VL11) through a contact hole (57a) penetrating the third insulating layer (103).

[0133] In the second circuit area (PCA2), the connecting electrode (277b) can be electrically connected to the source area (S4) of the fourth transistor (T4) through a contact hole (56) penetrating the second insulating layer (102) and the third insulating layer (103). The connecting electrode (277b) can be connected to the first-second initialization voltage line (VL12) through a contact hole (57b) penetrating the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103).

[0134] In the third circuit area (PCA3), the connecting electrode (277c) can be electrically connected to the source area (S4) of the fourth transistor (T4) through a contact hole (56) penetrating the second insulating layer (102) and the third insulating layer (103). The connecting electrode (277c) can be connected to the first-third initialization voltage line (VL13) through a contact hole (57c) penetrating the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103).

[0135] A fourth insulating layer (104) may be disposed over a third conductive layer covering a third insulating layer (103), and a fourth conductive layer may be disposed over the fourth insulating layer (104). As illustrated in FIGS. 12 to 15, the fourth conductive layer may include a plurality of vertical conductive lines (VVL) and connection electrodes (281, 283).

[0136] The connection electrode (281) can be electrically connected to the connection electrode (270) through a contact hole (61) penetrating the fourth insulating layer (104). The connection electrode (281) on a planar surface covers the connection electrode (273), which is a node electrode, and can be arranged to overlap the connection electrode (273). The first electrode (210) can be arranged below the connection electrode (273), and the connection electrode (281) can be arranged above the connection electrode (273). The connection electrode (281) can cover the connection electrode (273) approximately entirely, and the first electrode (210) can cover the connection electrode (273) approximately entirely. The connection electrode (281) can function as an upper shielding layer of the connection electrode (273), and the first electrode (210) can function as a lower shielding layer of the connection electrode (273).

[0137] The connecting electrode (283) is electrically connected to the connecting electrode (276) through a contact hole (62) penetrating the fourth insulating layer (104), and can be electrically connected to the source region (S6) of the sixth transistor (T6).

[0138] Referring to FIG. 13, the vertical conductive lines (VVL) may include a shield line (VEL), a first vertical conductive line (VVL1) arranged in a first circuit area (PCA1), a second vertical conductive line (VVL2) arranged in a second circuit area (PCA2), and a third vertical conductive line (VVL3) arranged in a third circuit area (PCA3).

[0139] A planar shield line (VEL) may overlap a data line (DL) in each of a first circuit area (PCA1), a second circuit area (PCA2), and a third circuit area (PCA3). The shield line (VEL) may correspond to the shield line (VEL) illustrated in Fig. 4a. The shield line (VEL) may not be electrically connected to pixels (PX) in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The shield line (VEL) may be electrically connected to a shield voltage supply line (PVEL) arranged in a peripheral area (PA) as illustrated in Figs. 5a to 5d, and may receive a shield voltage (VES), which is a positive voltage, from the shield voltage supply line (PVEL).

[0140] In one embodiment, the shield line (VEL) can receive a separate constant voltage that is different from a plurality of voltages (e.g., a driving voltage (ELVDD), a reference voltage (Vref), and an initialization voltage (Vint)) supplied to the pixel (PX) from the shield voltage supply line (PVEL). In one embodiment, the shield line (VEL) can receive one of a plurality of voltages (e.g., a driving voltage (ELVDD), a reference voltage (Vref), and an initialization voltage (Vint)) supplied to the pixel (PX) from the shield voltage supply line (PVEL). In one embodiment, the shield line (VEL) can receive one of the constant voltages (e.g., a high voltage (VGH), a low voltage (VGL), a ground voltage, etc.) supplied to a gate driving circuit that supplies electrical signals to the pixel (PX) from the shield voltage supply line (PVEL).

[0141] The first vertical conductor (VVL1), the second vertical conductor (VVL2), and the third vertical conductor (VVL3) may be one of the vertical driving voltage line (PLv), the first vertical initialization voltage line (VL11v), the second vertical initialization voltage line (VL12v), the third vertical initialization voltage line (VL13v), the vertical reference voltage line (VRLv), and the vertical common voltage line (EOL). Two of the first vertical conductor (VVL1), the second vertical conductor (VVL2), and the third vertical conductor (VVL3) may be the same vertical conductor (VVL). The vertical driving voltage line (PLv), the first vertical initialization voltage line (VL11v), the second vertical initialization voltage line (VL12v), the third vertical initialization voltage line (VL13v), the vertical reference voltage line (VRLv), and the vertical common voltage line (EOL) can be arranged alternately along the x direction according to a predetermined rule.

[0142] Referring to FIGS. 14 and 15, vertical conductive lines (VVL) may be electrically connected to horizontal conductive lines (VHL) extending in the x direction. The horizontal conductive lines (VHL) may include a driving voltage line (PL) (conductive line (200)), a first-first initialization voltage line (VL11), a first-second initialization voltage line (VL12), a first-third initialization voltage line (VL13), and a reference voltage line (VRL). The driving voltage line (PL) may be electrically connected to the vertical driving voltage line (PLv) to have a mesh structure in the display area (DA). The first-first initialization voltage line (VL11) may be electrically connected to the first vertical initialization voltage line (VL11v) to have a mesh structure in the display area (DA). The first-second initialization voltage line (VL12) may be electrically connected to the second vertical initialization voltage line (VL12v) and may have a mesh structure in the display area (DA). The first-third initialization voltage line (VL13) may be electrically connected to the third vertical initialization voltage line (VL13v) and may have a mesh structure in the display area (DA). The reference voltage line (VRL) may be electrically connected to the vertical reference voltage line (VRLv) and may have a mesh structure in the display area (DA). The shield line (VEL) and the vertical common voltage line (EOL) may not have a mesh structure in the form of stripes extending in the y direction.

[0143] In one embodiment, as illustrated in FIG. 14, in four unit circuit areas (PCAu), the first vertical conductive line (VVL1) is a vertical driving voltage line (PLv), and the second vertical conductive line (VVL2) and the third vertical conductive line (VVL3) may be alternately arranged as a first vertical initialization voltage line (VL11v) / vertical reference voltage line (VRLv), a second vertical initialization voltage line (VL12v) / vertical reference voltage line (VRLv), a vertical reference voltage line (VRLv) / third vertical initialization voltage line (VL13v), and a vertical common voltage line (EOL) / vertical reference voltage line (VRLv).

[0144] In one embodiment, as illustrated in FIG. 15, in four unit circuit areas (PCAu), a first vertical conductive line (VVL1), a second vertical conductive line (VVL2), and a third vertical conductive line (VVL3) may be alternately arranged as a first vertical initialization voltage line (VL11v) / a pair of vertical reference voltage lines (VRLv), a second vertical initialization voltage line (VL12v) / a vertical drive voltage line (PLv) / a vertical reference voltage line (VRLv), a third vertical initialization voltage line (VL13v) / a pair of vertical reference voltage lines (VRLv), and a vertical drive voltage line (PLv) / a vertical common voltage line (EOL) / a vertical reference voltage line (VRLv).

[0145] Figure 12 is an example in which the first vertical conductor (VVL1) is a vertical driving voltage line (PLv), the second vertical conductor (VVL2) is a second vertical initialization voltage line (VL12v), and the third vertical conductor (VVL3) is a vertical reference voltage line (VRLv).

[0146] The vertical driving voltage line (PLv) can be electrically connected to the connection electrode (274) arranged in the first circuit area (PCA1) through a contact hole (63) penetrating the fourth insulating layer (104). Since the connection electrode (274) is electrically connected to the conductive line (200), the vertical driving voltage line (PLv) can be electrically connected to the driving voltage line (PL).

[0147] The second vertical initialization voltage line (VL12v) can be electrically connected to the connection electrode (277b) arranged in the second circuit area (PCA2) through the contact hole (64) penetrating the fourth insulating layer (104). Since the connection electrode (277b) is electrically connected to the first-second initialization voltage line (VL12), the second vertical initialization voltage line (VL12v) can be electrically connected to the first-second initialization voltage line (VL12).

[0148] The vertical reference voltage line (VRLv) can be electrically connected to the connection electrode (272) arranged in the third circuit area (PCA3) through a contact hole (65) penetrating the fourth insulating layer (104). Since the connection electrode (272) is electrically connected to the reference voltage line (VRL), the vertical reference voltage line (VRLv) can be electrically connected to the reference voltage line (VRL).

[0149] Although not shown, voltage supply lines may be further arranged in the peripheral area (PA) electrically connected to the horizontal conductive lines (VHL) and / or the vertical conductive lines (VVL). The voltage supply lines may be arranged on at least one of the upper, lower, left, and right sides of the display area (PA).

[0150] A fourth conductive layer is covered on the fourth insulating layer (104), and a fifth insulating layer (105) is disposed on the fifth insulating layer (105), and an organic light-emitting diode (OLED) as a display element may be disposed on the fifth insulating layer (105). The organic light-emitting diode (OLED) may include a pixel electrode (311), a counter electrode (315), and an intermediate layer between the pixel electrode (311) and the counter electrode (315).

[0151] The pixel electrode (311) can be electrically connected to the first transistor (T1) by being electrically connected to the connection electrode (283), which is a lower conductive pattern, through the contact hole (71) of the fifth insulating layer (105). As illustrated in FIG. 16, the pixel electrode (311a) connected to the pixel circuit of the first pixel (PX1) can be electrically connected to the connection electrode (283) arranged in the first circuit area (PCA1), thereby being electrically connected to the first transistor (T1). The pixel electrode (311b) connected to the pixel circuit of the second pixel (PX2) can be electrically connected to the first transistor (T1) by being electrically connected to the connection electrode (283) arranged in the second circuit area (PCA2). The pixel electrode (311c) connected to the pixel circuit of the third pixel (PX3) may be electrically connected to the connection electrode (283) arranged in the third circuit area (PCA3), thereby being electrically connected to the first transistor (T1). The pixel electrode (311c) may include a first region (311c1) and a second region (311c2) having a rectangular shape, and a third region (311c3) connecting the first region (311c1) and the second region (311c2), and may have a '⊃' shape. An auxiliary electrode (AE) may be further arranged on the same layer as the pixel electrodes (311). The auxiliary electrode (AE) may be arranged between the pixel electrodes (311c) of the third pixel (PX3). The auxiliary electrode (AE) may be in contact with the counter electrode (315) in the display area (DA). In one embodiment, the auxiliary electrode (AE) can be electrically connected to the vertical common voltage line (EOL) in the display area (DA).

[0152] As illustrated in FIGS. 17 and 18, a sixth insulating layer (106), which is a pixel definition layer that covers the edge of the pixel electrode (311), may be disposed on top of the pixel electrode (311). An opening (106OP) that exposes a portion of the pixel electrode (311) and defines a light-emitting area may be defined in the sixth insulating layer (106). The sixth insulating layer (106) may be a single-layer or multi-layer organic insulating layer and / or inorganic insulating layer.

[0153] The intermediate layer may include a light-emitting layer (313) and a first functional layer under the light-emitting layer (313) and / or a second functional layer over the light-emitting layer (313). The first functional layer may be a hole transport layer (HTL). Alternatively, the first functional layer may include a hole injection layer (HIL) and a hole transport layer (HTL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer and the second functional layer may be formed integrally to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area (DA). The first functional layer or the second functional layer may be omitted. FIG. 17 and FIG. 18 illustrate an organic light-emitting diode (OLEDa) electrically connected to a pixel circuit disposed in the first circuit area (PCA1).

[0154] The counter electrode (315) can be formed integrally to correspond to a plurality of organic light-emitting diodes (OLEDs) arranged in the display area (DA).

[0155] Fig. 19 is a drawing showing the arrangement of data lines and signal lines according to a comparative example. In the comparative example, a conductive line (200), which is a planar driving voltage line (PL), is arranged below the data line (DL) to overlap the data line (DL), a planar vertical driving voltage line (PLv) is arranged above the data line (DL) to overlap the data line (DL), and a planar vertical driving voltage line (PLv) is arranged above the connection electrode (270) to overlap the connection electrode (270).

[0156] In a comparative example, a capacitor (C') is formed between a data line (DL) and a driving voltage line (PL) (conductive line (200)) to which a driving voltage (ELVDD) is supplied, and between the data line (DL) and a vertical driving voltage line (PLv) to which the driving voltage (ELVDD) is supplied. When the data signal (DATA) changes, the driving voltage (ELVDD) supplied to the driving voltage line (PL) can change (rise or fall) instantaneously by the coupling of the capacitor (C'). The voltage of the second terminal of the first transistor (T1), i.e., the voltage of the second node (N2), changes by the coupling of the second capacitor (C2) connected to the driving voltage line (PL) due to the change in the driving voltage (ELVDD), which can change the gate-source voltage of the first transistor (T1). As a result, pixels (PX) may emit light at a brightness different from the set brightness, and multi-line horizontal cross talk may occur, which causes staining in the image.

[0157] On the other hand, in the embodiment illustrated in Fig. 18, the shield line (VEL) can be placed above the data line (DL). Since the shield line (VEL) is not electrically connected to the pixel (PX), even if the data signal (DATA) changes, the voltage change of the shield line (VEL) does not affect the voltage change of the second terminal of the first transistor (T1), thereby minimizing the gate-source voltage change of the first transistor (T1).

[0158] In a pixel circuit in which a vertical driving voltage line (PLv) among the vertical conductive lines (VVL) on a plane overlaps a connection electrode (270) including a source region (S1) of a first transistor (T1), a capacitor is formed by the vertical driving voltage line (PLv) and the connection electrode (270), so that the capacitance of the second capacitor (C2) may increase. Due to the increase in the capacitance of the second capacitor (C2), multi-line horizontal crosstalk due to the coupling of the second capacitor (C2) when the data signal (DATA) is changed may increase. In one embodiment, the vertical driving voltage line (PLv) may not be arranged on the connection electrode (270) in at least one circuit region among the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) constituting the unit pixel. In the second circuit area (PCA2) where a pixel with a large luminance contribution in a unit pixel, for example, a green pixel (PX2), is placed, a vertical driving voltage line (PLv) may not be placed.

[0159] In one embodiment, the second vertical conductive line (VVL2) arranged in the second circuit area (PCA2) may be one of the first vertical initialization voltage line (VL11v), the second vertical initialization voltage line (VL12v), the third vertical initialization voltage line (VL13v), the vertical reference voltage line (VRLv), and the vertical common voltage line (EOL), excluding the vertical driving voltage line (PLv). For example, the vertical driving voltage line (PLv) and the vertical reference voltage line (VRLv), which are the second vertical conductive line (VVL2) and the third vertical conductive line (VVL3) of the second unit circuit area (PCAu) illustrated in FIG. 15, may be arranged by being changed to the vertical reference voltage line (VRLv) and the vertical driving voltage line (PLv), as illustrated in FIG. 20. Fig. 21 is a cross-sectional view of an example in which a vertical reference voltage line (VRLv) is arranged as a second vertical conductive line (VVL2) in a second circuit area (PCA2).

[0160] The pixel circuit of the pixel according to the embodiment of the present invention is not limited to the pixel circuit illustrated in FIG. 3. In other embodiments, it can be applied to various pixel circuits including a first capacitor (C1) and a second capacitor (C2) connected to the second terminal (source) of the first transistor (T1).

[0161] Figures 22 to 26 are equivalent circuits of pixels according to one embodiment.

[0162] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 22 differs from the pixel circuit (PC) illustrated in FIG. 3 in that the fourth transistor (T4) is connected to the second node (N2) and the initialization voltage line (VL). The fourth transistor (T4) is turned on by the second gate signal (GI) supplied from the second gate line (GIL) and can transmit the initialization voltage (Vint) supplied from the initialization voltage line (VL) to the second node (N2).

[0163] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 23 differs from the pixel circuit (PC) illustrated in FIG. 22 in that a seventh transistor (T7) connected to the third node (N3) and the second initialization voltage line (VL2) is added. The second initialization voltage line (VL2) is provided separately from the initialization voltage line (VL) and can supply a second initialization voltage (Vaint) different from the initialization voltage (Vint). In one embodiment, the second initialization voltage (Vaint) can have a higher voltage level than the initialization voltage (Vint).

[0164] The seventh transistor (T7) is turned on by the second gate signal (GI) transmitted to the second gate line (GIL) and can transmit the second initialization voltage (Vaint) supplied from the second initialization voltage line (VL2) to the third node (N3). The second node (N2) and the third node (N3) can be initialized to different voltages by the fourth transistor (T4) and the seventh transistor (T7).

[0165] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 24 differs from the pixel circuit (PC) illustrated in FIG. 23 in that the gate of the seventh transistor (T7) is connected to the sixth gate line (GBL) and is supplied with the sixth gate signal (GB). Since the fourth transistor (T4) and the seventh transistor (T7) are connected to different gate lines and controlled by different gate signals, the initialization timing of the second node (N2) and the third node (N3) can be independently controlled.

[0166] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 25 differs from the pixel circuit (PC) illustrated in FIG. 24 in that the seventh transistor (T7) is connected to the second node (N2) and the second initialization voltage line (VL2). Since the fourth transistor (T4) and the seventh transistor (T7) are connected to different gate lines and controlled by different gate signals, the initialization of the second node (N2) can be precisely controlled.

[0167] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 26 differs from the pixel circuit (PC) of the pixel (PX) illustrated in FIG. 25 in that the sixth transistor (T6) is omitted.

[0168] As with the pixel (PX) illustrated in FIG. 3, in the pixels (PX) illustrated in FIGS. 22 to 26, the shielding line may be arranged to overlap the planar data line (DL) on top of the data line (DL) and may not be connected to the pixel (PX). The shielding voltage supplied to the shielding line may be a separate voltage different from the driving voltage (ELVDD), the reference voltage (Vref), the initialization voltage (Vint), and the second initialization voltage (Vaint), and may be one of the driving voltage (ELVDD), the reference voltage (Vref), the initialization voltage (Vint), the second initialization voltage (Vaint), the high voltage (VGH), the low voltage (VGL), and the ground voltage. In addition, the second vertical conductive line (VVL2) arranged in the second circuit area (PCA2) where the pixel circuit of the second pixel (PX2) is arranged may be one of the vertical conductive lines other than the vertical driving voltage line (PLv).

[0169] Figures 27 to 32 are equivalent circuit diagrams of pixels according to embodiments.

[0170] The pixel circuit (PC) of the pixel (PX) illustrated in Fig. 27 differs from the pixel circuit (PC) illustrated in Fig. 3 in that a third capacitor (C3) is added. The third capacitor (C3) can be connected between the second node (N2) and the common voltage line (CEL).

[0171] The pixel circuit (PC) of the pixel (PX) illustrated in Fig. 28 differs from the pixel circuit (PC) illustrated in Fig. 20 in that a third capacitor (C3) is added. The third capacitor (C3) can be connected between the second node (N2) and the common voltage line (CEL).

[0172] The pixel circuit (PC) of the pixel (PX) illustrated in Fig. 29 differs from the pixel circuit (PC) illustrated in Fig. 21 in that a third capacitor (C3) is added. The third capacitor (C3) can be connected between the second node (N2) and the common voltage line (CEL).

[0173] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 30 differs from the pixel circuit (PC) illustrated in FIG. 22 in that a third capacitor (C3) is added. The third capacitor (C3) can be connected between the second node (N2) and the common voltage line (CEL).

[0174] The pixel circuit (PC) of the pixel (PX) illustrated in Fig. 31 differs from the pixel circuit (PC) illustrated in Fig. 23 in that a third capacitor (C3) is added. The third capacitor (C3) can be connected between the second node (N2) and the common voltage line (CEL).

[0175] The pixel circuit (PC) of the pixel (PX) illustrated in Fig. 32 differs from the pixel circuit (PC) illustrated in Fig. 24 in that a third capacitor (C3) is added. The third capacitor (C3) can be connected between the second node (N2) and the common voltage line (CEL).

[0176] In the embodiments illustrated in FIGS. 27 to 32, the common voltage line (CEL) may extend in the x-direction and may be arranged to cross the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The common voltage line (CEL) may be electrically connected to the vertical common voltage line (EOL). In one embodiment, the common voltage line (CEL) may be arranged on the same layer as the first conductive layer.

[0177] The pixels (PX) illustrated in FIGS. 27 to 32 may also overlap the planar data line (DL) and the shielding line may overlap the planar conductive line (200), similar to FIG. 11 in which the embodiment of FIG. 3 is implemented. The pixels (PX) illustrated in FIGS. 27 to 32 may further include a third capacitor (C3) to further minimize the voltage change of the driving voltage line (PL) according to the change of the data signal (DATA). In addition, the second vertical conductive line (VVL2) arranged in the second circuit area (PCA2) where the pixel circuit of the second pixel (PX2) is arranged may be one of the vertical conductive lines other than the vertical driving voltage line (PLv).

[0178] Fig. 33 is an equivalent circuit diagram of a pixel according to one embodiment.

[0179] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 33 differs from the pixel circuit (PC) illustrated in FIG. 3 in that the second capacitor (C2) is connected between the reference voltage line (VRL) and the second node (N2). Since the remaining configuration is the same as the pixel circuit (PC) illustrated in FIG. 3, a detailed description thereof will be omitted.

[0180] Fig. 34 is a layout diagram schematically showing the positions of transistors and capacitors, etc. of the pixel illustrated in Fig. 33. Figs. 35 to 41 are layout diagrams schematically showing the components of the pixel of Fig. 33 by layer. Fig. 39 is a diagram illustrating transistors and capacitors of the first circuit area (PCA1). Fig. 42 is a cross-sectional view taken along line III-III' of Fig. 34. Fig. 43 is a diagram showing the arrangement of data lines and signal lines according to a comparative example. Hereinafter, the same components as those disclosed in Figs. 6 to 18 are given the same identification numbers, and the description of the same components is omitted, focusing on the differences.

[0181] Referring to Fig. 35, a first conductive layer may be arranged on a substrate (100). The first conductive layer may include a conductive line (200) which is a driving voltage line (PL), a first electrode (210), a lower first gate line (GWLb), a reference voltage line (VRL), a first-second initialization voltage line (VL12), a first-third initialization voltage line (VL13), and a repair line (RL).

[0182] Referring to FIG. 36, a first insulating layer (101) is disposed on a substrate (100) to cover a first conductive layer, and a semiconductor layer (ACT) including an oxide semiconductor may be disposed on the first insulating layer (101).

[0183] Referring to Fig. 37, a second insulating layer (102) may be disposed on a first insulating layer (101) to cover a semiconductor layer (ACT), and a second conductive layer may be disposed on the second insulating layer (102). The second conductive layer may include a second electrode (220), a third electrode (230), an upper first gate line (GWLt), a second gate line (GIL), a third gate line (GRL), a fourth gate line (EML), a fifth gate line (EMBL), and a first-first initialization voltage line (VL11).

[0184] Referring to Fig. 38, a third insulating layer (103) may be disposed on a second insulating layer (102) to cover a second conductive layer, and a third conductive layer may be disposed on the third insulating layer (103). The third conductive layer may include a data line (DL) and connection electrodes (270, 271, 272, 273, 274, 275, 276, 277a, 277b, 277c, 278).

[0185] The connecting electrode (272) is electrically connected to the drain region (D3) of the third transistor (T3) through a contact hole (46) penetrating the second insulating layer (102) and the third insulating layer (103), and can be electrically connected to the reference voltage line (VRL) through a contact hole (47) penetrating the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103). The connecting electrode (272) can be electrically connected to the fourth semiconductor layer (ACT4) through a contact hole (59) penetrating the second insulating layer (102) and the third insulating layer (103). Accordingly, the reference voltage (Vref) can be supplied to the fourth semiconductor layer (ACT4).

[0186] The connecting electrode (278) can be electrically connected to the source region (S4) of the fourth transistor (T4) through a contact hole (60) penetrating the second insulating layer (102) and the third insulating layer (103).

[0187] Referring to Fig. 40, a fourth insulating layer (104) may be disposed over a third conductive layer covering a third insulating layer (103), and a fourth conductive layer may be disposed over the fourth insulating layer (104). The fourth conductive layer may include a plurality of vertical conductive lines (VVL) (see Figs. 13 to 15) and connection electrodes (281, 283). Fig. 40 is an example in which a first vertical conductive line (VVL1) is a second vertical initialization voltage line (VL12v), a second vertical conductive line (VVL2) is a vertical reference voltage line (VRLv), and a third vertical conductive line (VVL3) is a vertical driving voltage line (PLv).

[0188] The second vertical initialization voltage line (VL12v) can be electrically connected to the connection electrode (278) arranged in the first circuit area (PCA1) through the contact hole (67) penetrating the fourth insulating layer (104). Since the connection electrode (278) is electrically connected to the source area (S4) of the fourth transistor (T4), and the source area (S4) of the fourth transistor (T4) is electrically connected to the first-second initialization voltage line (VL12), the second vertical initialization voltage line (VL12v) can be electrically connected to the first-second initialization voltage line (VL12).

[0189] The vertical reference voltage line (VRLv) can be electrically connected to the connection electrode (272) arranged in the second circuit area (PCA2) through a contact hole (68) penetrating the fourth insulating layer (104). Since the connection electrode (272) is electrically connected to the reference voltage line (VRL), the vertical reference voltage line (VRLv) can be electrically connected to the reference voltage line (VRL).

[0190] The vertical driving voltage line (PLv) can be electrically connected to the connecting electrode (274) arranged in the third circuit area (PCA3) through a contact hole (69) penetrating the fourth insulating layer (104). Since the connecting electrode (274) is electrically connected to the conductive line (200), the vertical driving voltage line (PLv) can be electrically connected to the driving voltage line (PL).

[0191] Referring to Fig. 41, a fifth insulating layer (105) is disposed over a fourth conductive layer on a fourth insulating layer (104), and an organic light-emitting diode (OLED) as a display element may be disposed over the fifth insulating layer (105). The organic light-emitting diode (OLED) may include a pixel electrode (311), a counter electrode (315), and an intermediate layer between the pixel electrode (311) and the counter electrode (315).

[0192] Figure 43 is a drawing showing the arrangement of data lines and signal lines according to a comparative example. In the comparative example, a conductive line (200), which is a planar driving voltage line (PL), is arranged below the data line (DL) to overlap the data line (DL), a planar shielding line (VEL) is arranged above the data line (DL) to overlap the data line (DL), and a planar vertical driving voltage line (PLv) is arranged above the connection electrode (270) to overlap the connection electrode (270).

[0193] In a comparative example, a capacitor (C') is formed between a data line (DL) and a driving voltage line (PL) (conductive line (200)) to which a driving voltage (ELVDD) is supplied. When the data signal (DATA) changes, the driving voltage (ELVDD) supplied to the driving voltage line (PL) can change (rise or fall) instantaneously by the coupling of the capacitor (C'). The voltage of the second terminal of the first transistor (T1), i.e., the voltage of the second node (N2), changes according to the change in the driving voltage (ELVDD) by the coupling of the capacitor formed between the vertical driving voltage line (PLv) and the connection electrode (270), which can change the gate-source voltage of the first transistor (T1).

[0194] In an embodiment of the present invention, a vertical driving voltage line (PLv) may not be disposed above a connection electrode (270) in a circuit area where at least one of a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3) in a unit pixel is disposed. In one embodiment, by not disposing a vertical driving voltage line (PLv) in a second circuit area (PCA2) where a pixel having a large luminance contribution in a unit pixel, for example, a green pixel, the second pixel (PX2), is disposed, the capacitance of a capacitor formed between the vertical driving voltage line (PLv) and the connection electrode (270) can be minimized.

[0195] The pixel circuit of the pixel according to an embodiment of the present invention is not limited to the pixel circuit illustrated in FIG. 33. In other embodiments, it can be applied to various pixel circuits including a first capacitor (C1) and a second capacitor (C2) connected to a second terminal (source) of a first transistor (T1).

[0196] Figures 44 to 49 are equivalent circuits of pixels according to embodiments.

[0197] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 44 differs from the pixel circuit (PC) illustrated in FIG. 33 in that a fourth transistor (T4) is connected to the second node (N2) and the initialization voltage line (VL), and a seventh transistor (T7) connected to the third node (N3) and the second initialization voltage line (VL2) is added. The fourth transistor (T4) is turned on by a second gate signal (GI) supplied from the second gate line (GIL) and can transmit the initialization voltage (Vint) supplied from the initialization voltage line (VL) to the second node (N2). The second initialization voltage line (VL2) is provided separately from the initialization voltage line (VL) and can supply a second initialization voltage (Vaint) different from the initialization voltage (Vint). In one embodiment, the second initialization voltage (Vaint) may have a higher voltage level than the initialization voltage (Vint). The seventh transistor (T7) may be turned on by the second gate signal (GI) transmitted to the second gate line (GIL) and may transmit the second initialization voltage (Vaint) supplied from the second initialization voltage line (VL2) to the third node (N3). The second node (N2) and the third node (N3) may be initialized with different voltages by the fourth transistor (T4) and the seventh transistor (T7).

[0198] In one embodiment, as illustrated in FIG. 47, a third capacitor (C3) may be added to the pixel circuit (PC) of the pixel (PX) illustrated in FIG. 44. The third capacitor (C3) may be connected between the second node (N2) and the common voltage line (CEL).

[0199] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 45 differs from the pixel circuit (PC) illustrated in FIG. 44 in that the gate of the seventh transistor (T7) is connected to the sixth gate line (GBL) and is supplied with the sixth gate signal (GB). Since the fourth transistor (T4) and the seventh transistor (T7) are connected to different gate lines and controlled by different gate signals, the initialization timing of the second node (N2) and the third node (N3) can be independently controlled.

[0200] In one embodiment, as illustrated in FIG. 48, a third capacitor (C3) may be added to the pixel circuit (PC) of the pixel (PX) illustrated in FIG. 45. The third capacitor (C3) may be connected between the second node (N2) and the common voltage line (CEL).

[0201] The pixel circuit (PC) of the pixel (PX) illustrated in FIG. 46 differs from the pixel circuit (PC) of the pixel (PX) illustrated in FIG. 33 in that the sixth transistor (T6) is omitted.

[0202] In one embodiment, as illustrated in FIG. 49, a third capacitor (C3) may be added to the pixel circuit (PC) of the pixel (PX) illustrated in FIG. 46. The third capacitor (C3) may be connected between the second node (N2) and the common voltage line (CEL).

[0203] Although the above-described embodiments have the pixel circuit (PC) including N-type transistors, the embodiments of the present invention are not limited thereto. For example, various embodiments are possible in which a plurality of transistors of the pixel circuit (PC) may be P-type transistors, or some may be P-type transistors and others may be N-type transistors. In one embodiment, among the plurality of transistors of the pixel circuit (PC), a driving transistor may be an N-type transistor, and at least one of the remaining transistors may be a P-type transistor. The P-type transistor may be a low-temperature poly-silicon (LTPS) thin-film transistor including a semiconductor layer formed of polysilicon.

[0204] Embodiments of the present invention can arrange a shielding line above and / or below a data line (DL) in a pixel in which a capacitor is connected between one electrode (e.g., a source) of a driving transistor and a signal line (e.g., a driving voltage line (PL) or a reference voltage line (VRL)) that supplies a constant voltage to the pixel. Accordingly, by minimizing (e.g., preventing) the formation of a capacitor between the data line (EL) and the signal line, a change in the gate-source voltage of the driving transistor (T1) can be prevented by coupling of the capacitor formed between the data line (DL) and the signal line when the data signal (DATA) changes. Since the shielding line is not electrically connected to the pixel, the shielding voltage supplied to the shielding line can utilize not only a constant voltage not supplied to the pixel but also one of the constant voltages supplied to the pixel.

[0205] In addition, embodiments of the present invention may not place a signal line to which a driving voltage is supplied above one electrode (e.g., a source) of a driving transistor in at least one sub-pixel among sub-pixels (e.g., a red pixel, a green pixel, a blue pixel) within a unit pixel. Accordingly, when a data signal changes, a change in the gate-source voltage of the driving transistor can be prevented by coupling of a capacitor formed between one electrode (e.g., a source) of the driving transistor and the signal line to which the driving voltage is supplied.

[0206] Figures 50a to 51b are cross-sectional views showing the structure of display elements according to embodiments.

[0207] As a display element according to one embodiment, an organic light-emitting diode (OLED) may include a pixel electrode (311), a counter electrode (315), and an intermediate layer (313m) between the pixel electrode (311) (first electrode, anode) and the counter electrode (315) (second electrode, cathode).

[0208] The pixel electrode (311) may include a light-transmitting conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The pixel electrode (311) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. For example, the pixel electrode (311) may have a three-layer structure of ITO / Ag / ITO.

[0209] The counter electrode (315) may be disposed on the intermediate layer (313m). The counter electrode (315) may include a metal, alloy, electrically conductive compound, or any combination thereof having a low work function. For example, the counter electrode (315) may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode (315) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0210] The intermediate layer (313m) may include a polymer or low-molecular organic material that emits light of a predetermined color. In addition to various organic materials, the intermediate layer (313m) may also include metal-containing compounds such as organometallic compounds and inorganic materials such as quantum dots.

[0211] In one embodiment, the intermediate layer (313m) may include a light-emitting layer and a first functional layer and a second functional layer below and above the light-emitting layer, respectively. The first functional layer may include, for example, a hole transport layer (HTL) or a hole transport layer and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer or the second functional layer may be omitted. The first functional layer and the second functional layer may be formed integrally to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area (DA).

[0212] In one embodiment, the intermediate layer (313m) may include two or more emitting units sequentially stacked between the pixel electrode (311) and the counter electrode (315), and a charge generation layer (CGL) disposed between the two emitting units. When the intermediate layer (313m) includes the emitting units and the charge generation layer, the organic light-emitting diode (OLED) may be a tandem light-emitting element. The organic light-emitting diode (OLED) may improve color purity and luminous efficiency by having a stacked structure of a plurality of emitting units.

[0213] One light-emitting unit may include a light-emitting layer and a first functional layer and a second functional layer above and below the light-emitting layer, respectively. The charge generation layer (CGL) may include a negative charge generation layer and a positive charge generation layer. The light-emitting efficiency of an organic light-emitting diode (OLED), which is a tandem light-emitting device having a plurality of light-emitting layers, can be further increased by the negative charge generation layer and the positive charge generation layer.

[0214] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0215] In one embodiment, as illustrated in FIG. 50A, an organic light-emitting diode (OLED) may include a first light-emitting unit (EU1) including a first light-emitting layer (EML1) that is sequentially stacked, and a second light-emitting unit (EU2) including a second light-emitting layer (EML2). A charge generation layer (CGL) may be provided between the first light-emitting unit (EU1) and the second light-emitting unit (EU2). For example, the organic light-emitting diode (OLED) may include a pixel electrode (211), a first light-emitting layer (EML1), a charge generation layer (CGL), a second light-emitting layer (EML2), and a counter electrode (315), which are sequentially stacked. A first functional layer and a second functional layer may be included below and above the first light-emitting layer (EML1), respectively. A first functional layer and a second functional layer may be included below and above the second light-emitting layer (EML2), respectively. The first light-emitting layer (EML1) may be a blue light-emitting layer, and the second light-emitting layer (EML2) may be a yellow light-emitting layer.

[0216] In one embodiment, as illustrated in FIG. 50b, an organic light-emitting diode (OLED) may include a first light-emitting unit (EU1) including a first light-emitting layer (EML1), a third light-emitting unit (EU3), and a second light-emitting unit (EU2) including a second light-emitting layer (EML2). A first charge generation layer (CGL1) may be provided between the first light-emitting unit (EU1) and the second light-emitting unit (EU2), and a second charge generation layer (CGL2) may be provided between the second light-emitting unit (EU2) and the third light-emitting unit (EU3). For example, an organic light-emitting diode (OLED) may include a pixel electrode (311), a first light-emitting layer (EML1), a first charge generation layer (CGL1), a second light-emitting layer (EML2), a second charge generation layer (CGL2), the first light-emitting layer (EML1), and a counter electrode (315) that are sequentially stacked. A first functional layer and a second functional layer may be included below and above the first light-emitting layer (EML1), respectively. A first functional layer and a second functional layer may be included below and above the second light-emitting layer (EML2), respectively. The first light-emitting layer (EML1) may be a blue light-emitting layer, and the second light-emitting layer (EML2) may be a yellow light-emitting layer.

[0217] In one embodiment, the organic light emitting diode (OLED) may further include a third light emitting layer (EML3) and / or a fourth light emitting layer (EML4) that directly contacts, in addition to the second light emitting layer (EML2), the second light emitting unit (EU2) below and / or above the second light emitting layer (EML2). Here, direct contact may mean that no other layer is disposed between the second light emitting layer (EML2) and the third light emitting layer (EML3) and / or between the second light emitting layer (EML2) and the fourth light emitting layer (EML4). The third light emitting layer (EML3) may be a red light emitting layer, and the fourth light emitting layer (EML4) may be a green light emitting layer.

[0218] For example, as illustrated in FIG. 50c, the organic light-emitting diode (OLED) may include a pixel electrode (311), a first light-emitting layer (EML1), a first charge generation layer (CGL1), a third light-emitting layer (EML3), a second light-emitting layer (EML2), a second charge generation layer (CGL2), a first light-emitting layer (EML1), and a counter electrode (315) that are sequentially stacked. Alternatively, as illustrated in FIG. 50d, the organic light-emitting diode (OLED) may include a pixel electrode (311), a first light-emitting layer (EML1), a first charge generation layer (CGL1), a third light-emitting layer (EML3), a second light-emitting layer (EML2), a fourth light-emitting layer (EML4), a second charge generation layer (CGL2), a first light-emitting layer (EML1), and a counter electrode (315) that are sequentially stacked.

[0219] Fig. 51a is a cross-sectional view showing an example of the organic light-emitting diode of Fig. 50c, and Fig. 51b is a cross-sectional view showing an example of the organic light-emitting diode of Fig. 50d.

[0220] Referring to FIG. 51a, an organic light-emitting diode (OLED) may include a first light-emitting unit (EU1), a second light-emitting unit (EU2), and a third light-emitting unit (EU3) that are sequentially stacked. A first charge generation layer (CGL1) may be provided between the first light-emitting unit (EU1) and the second light-emitting unit (EU2), and a second charge generation layer (CGL2) may be provided between the second light-emitting unit (EU2) and the third light-emitting unit (EU3). The first charge generation layer (CGL1) and the second charge generation layer (CGL2) may each include a negative charge generation layer (nCGL) and a positive charge generation layer (pCGL).

[0221] The first light-emitting unit (EU1) may include a blue light-emitting layer (BEML). The first light-emitting unit (EU1) may further include a hole injection layer (HIL) and a hole transport layer (HTL) between the pixel electrode (211) and the blue light-emitting layer (BEML). In one embodiment, a p-doped layer may further be included between the hole injection layer (HIL) and the hole transport layer (HTL). The p-doped layer may be formed by doping the hole injection layer (HIL) with a p-type doping material. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue light-emitting layer (BEML) and the hole transport layer (HTL). The blue light auxiliary layer may increase the light output efficiency of the blue light-emitting layer (BEML). The blue light auxiliary layer may increase the light output efficiency of the blue light-emitting layer (BEML) by controlling a hole charge balance. The electron blocking layer may prevent electron injection into the hole transport layer (HTL). The buffer layer can compensate for the resonance distance according to the wavelength of light emitted from the light-emitting layer.

[0222] The second light-emitting unit (EU2) may include a yellow light-emitting layer (YEML) and a red light-emitting layer (REML) directly in contact with the yellow light-emitting layer (YEML) under the yellow light-emitting layer (YEML). The second light-emitting unit (EU2) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the first charge generation layer (CGL1) and the red light-emitting layer (REML), and may further include an electron transport layer (ETL) between the yellow light-emitting layer (YEML) and the negative charge generation layer (nCGL) of the second charge generation layer (CGL2).

[0223] The third light-emitting unit (EU3) may include a blue light-emitting layer (BEML). The third light-emitting unit (EU3) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the second charge generation layer (CGL2) and the blue light-emitting layer (BEML). The third light-emitting unit (EU3) may further include an electron transport layer (ETL) and an electron injection layer (EIL) between the blue light-emitting layer (BEML) and the counter electrode (215). The electron transport layer (ETL) may be a single layer or a multilayer. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue light-emitting layer (BEML) and the hole transport layer (HTL). At least one of a hole blocking layer and a buffer layer may further be included between the blue light-emitting layer (BEML) and the electron transport layer (ETL). The hole blocking layer may prevent hole injection into the electron transport layer (ETL).

[0224] The organic light emitting diode (OLED) illustrated in FIG. 51b differs from the organic light emitting diode (OLED) illustrated in FIG. 51a in the stacked structure of the second light emitting unit (EU2), but otherwise has the same configuration. Referring to FIG. 51b, the second light emitting unit (EU2) may include a yellow light emitting layer (YEML), a red light emitting layer (REML) located below the yellow light emitting layer (YEML) and in direct contact with the yellow light emitting layer (YEML), and a green light emitting layer (GEML) located above the yellow light emitting layer (YEML) and in direct contact with the yellow light emitting layer (YEML). The second light-emitting unit (EU2) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the first charge generation layer (CGL1) and the red light-emitting layer (REML), and may further include an electron transport layer (ETL) between the green light-emitting layer (GEML) and the negative charge generation layer (nCGL) of the second charge generation layer (CGL2).

[0225] Fig. 52 is a cross-sectional view showing the structure of a pixel of a display device according to one embodiment.

[0226] Referring to FIG. 52, a display device may include a plurality of pixels. The plurality of pixels may include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3). The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may each include a pixel electrode (311), a counter electrode (315), and an intermediate layer (313m). In one embodiment, the first pixel (PX1) may be a red pixel, the second pixel (PX2) may be a green pixel, and the third pixel (PX3) may be a blue pixel. Here, the pixel includes an organic light-emitting diode (OLED) as a display element, and the organic light-emitting diode (OLED) of each pixel may be electrically connected to a pixel circuit.

[0227] The pixel electrode (311) can be independently provided for each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3).

[0228] The intermediate layer (313m) of the organic light-emitting diode (OLED) of each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may include a first light-emitting unit (EU1), a second light-emitting unit (EU2) that are sequentially stacked, and a charge generation layer (CGL) between the first light-emitting unit (EU1) and the second light-emitting unit (EU2). The charge generation layer (CGL) may include a negative charge generation layer (nCGL) and a positive charge generation layer (pCGL). The charge generation layer (CGL) may be a common layer that is formed continuously in the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3).

[0229] The first light-emitting unit (EU1) of the first pixel (PX1) may include a hole injection layer (HIL), a hole transport layer (HTL), a red emission layer (REML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (3111). The first light-emitting unit (EU1) of the second pixel (PX2) may include a hole injection layer (HIL), a hole transport layer (HTL), a green emission layer (GEML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (311). The first light-emitting unit (EU1) of the third pixel (PX3) may include a hole injection layer (HIL), a hole transport layer (HTL), a blue emission layer (BEML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (311). Each of the hole injection layer (HIL), hole transport layer (HTL) and electron transport layer (ETL) of the first light-emitting unit (EU1) may be a common layer formed continuously in the first pixel (PX1), the second pixel (PX2) and the third pixel (PX3).

[0230] The second light-emitting unit (EU2) of the first pixel (PX1) may include a hole transport layer (HTL), an auxiliary layer (AXL), a red light-emitting layer (REML), and an electron transport layer (ETL) sequentially stacked on a charge generation layer (CGL). The second light-emitting unit (EU2) of the second pixel (PX2) may include a hole transport layer (HTL), a green light-emitting layer (GEML), and an electron transport layer (ETL) sequentially stacked on a charge generation layer (CGL). The second light-emitting unit (EU2) of the third pixel (PX3) may include a hole transport layer (HTL), a blue light-emitting layer (BEML), and an electron transport layer (ETL) sequentially stacked on a charge generation layer (CGL). Each of the hole transport layer (HTL) and electron transport layer (ETL) of the second light-emitting units (EU1) may be a common layer formed continuously in the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3). In one embodiment, at least one of a hole blocking layer and a buffer layer may be further included between the light-emitting layer and the electron transport layer (ETL) in the second light-emitting unit (EU2) of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3).

[0231] The thickness (H1) of the red emitting layer (REML), the thickness (H2) of the green emitting layer (GEML), and the thickness (H3) of the blue emitting layer (BEML) can be determined according to the resonance distance. The auxiliary layer (AXL) is a layer added to adjust the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer (AXL) may include the same material as the hole transport layer (HTL).

[0232] In FIG. 52, the auxiliary layer (AXL) is provided only in the first pixel (PX1), but the embodiment of the present invention is not limited thereto. For example, the auxiliary layer (AXL) may be provided in at least one of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) in order to match the resonance distances of each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3).

[0233] The display device may further include a capping layer (317) disposed on the outer side of the counter electrode (315). The capping layer (317) may serve to improve luminous efficiency by the principle of constructive interference. As a result, the light extraction efficiency of the organic light-emitting diode (OLED) may be increased, thereby improving the luminous efficiency of the organic light-emitting diode (OLED).

[0234] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and variations of the embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A data line connected to a pixel placed in a display area and extending in a first direction; A shielding line positioned above the data line in the display area, extending in the first direction, and overlapping the data line in a plane; and A display device, comprising: a first voltage line connected to the pixel, extending in a second direction perpendicular to the first direction, disposed below the data line, and overlapping the data line in a plane; 2. In paragraph 1, The above pixel is, A first capacitor including a first electrode and a second electrode disposed on the first electrode and overlapping the first electrode in a plane; A first transistor connected to the first voltage line and the second electrode of the first capacitor; A second transistor connected to the data line and the gate electrode of the first transistor; The above data line is arranged on the same layer as the second electrode of the first capacitor, A display device, wherein the semiconductor layer of the first transistor is arranged on the same layer as the first electrode of the first capacitor.

3. In paragraph 2, A display device, wherein the voltage supplied to the above shielding line and the voltage supplied to the first electrode of the first capacitor are different.

4. In paragraph 2, A display device in which the voltage supplied to the above shielding line and the voltage supplied to the first electrode of the first capacitor are the same.

5. In paragraph 2, A display device, wherein the first capacitor further includes a third electrode disposed below the first electrode, overlapping the first electrode in a plane, and connected to the second electrode.

6. In paragraph 5, A display device, wherein the first voltage line is arranged on the same layer as the third electrode of the first capacitor and is connected to the first electrode of the first capacitor.

7. In paragraph 6, A display device further comprising a vertical conductive line disposed on the same layer as the shielding line, overlapping the second electrode of the first capacitor in a plane, and extending in the first direction.

8. In paragraph 7, A display device in which the above vertical conductive line supplies a constant voltage to the pixel and is connected to a horizontal conductive line extending in the second direction.

9. In paragraph 8, A display device, wherein the above horizontal conductive line includes the first voltage line.

10. In paragraph 5, The above pixel is, Further comprising a second capacitor connected to the second electrode of the first capacitor and the light-emitting element; The above light-emitting element includes a first electrode connected to the first transistor and a second electrode opposite to the first electrode, A display device, wherein the second capacitor is connected to the second electrode of the light-emitting element.

11. In paragraph 5, A display device further comprising a second voltage line extending in a second direction and connected to the first electrode of the first capacitor.

12. In paragraph 11, A display device further comprising a vertical conductive line disposed on the same layer as the shielding line, overlapping the first electrode of the first capacitor in a plane, and extending in the first direction.

13. In paragraph 12, A display device in which the above vertical conductive line supplies a constant voltage to the pixel and is connected to a horizontal conductive line extending in the second direction.

14. In paragraph 13, A display device, wherein the above horizontal conductive line includes the second voltage line.

15. In paragraph 1, A display device further comprising: a voltage supply line disposed in a non-display area outside the display area, connected to the shielding line, and supplying a shielding voltage to the shielding line.

16. A first pixel circuit arranged in the first circuit area; and A second pixel circuit is disposed in a second circuit area adjacent to the first circuit area in the first direction; Each of the first pixel circuit and the second pixel circuit is connected to a light-emitting diode, Each of the above first pixel circuit and the above second pixel circuit, A data line extending in a second direction perpendicular to the first direction; A shielding line positioned above the data line, extending in the second direction, and overlapping the first data line in a plane; A first voltage line extending in the first direction, positioned below the data line, and having a portion of the line planarly overlapping the data line; A capacitor comprising a first electrode and a second electrode disposed on the first electrode and overlapping the first electrode in a plane; A first transistor connected to the first voltage line and the second electrode of the capacitor; A second transistor connected to the data line and the gate electrode of the first transistor; A third transistor connected to the second voltage line extended in the first direction and the gate electrode of the first transistor; A fourth transistor connected to the first electrode of the light-emitting diode and the third voltage line extending in the first direction; and A conductive line is disposed on the same layer as the shielding line, overlaps the second electrode of the capacitor on a plane, and extends in the second direction; The light-emitting diode connected to the first pixel circuit emits light in the first color, The light emitting diode connected to the second pixel circuit emits light in a second color, The conductive line of the first pixel circuit is connected to one of the first voltage line, the second voltage line, the third voltage line, and the fourth voltage line connected to the second electrode of the light-emitting diode, A display device, wherein the conductive line of the second pixel circuit is connected to one of the second voltage line, the third voltage line, and the fourth voltage line, excluding the first voltage line.

17. In paragraph 16, A display device, wherein the voltage supplied to the shielding line and the voltage supplied to the first electrode of the capacitor are different.

18. In paragraph 16, A display device in which the voltage supplied to the shielding line and the voltage supplied to the first electrode of the capacitor are the same.

19. In Article 16, A display device, wherein the capacitor further includes a third electrode disposed below the first electrode, overlapping the first electrode in a plane, and connected to the second electrode.

20. In paragraph 19, A display device in which the first voltage line is arranged on the same layer as the third electrode of the capacitor and connected to the first electrode of the capacitor.

21. In paragraph 19, A display device in which the second voltage line is arranged on the same layer as the third electrode of the capacitor and connected to the first electrode of the capacitor.

Images