Display driving device and driving method therefor

Abstract

The present invention relates to a display driving device capable of removing flickering by applying interlace scanning. The display driving device according to one embodiment comprises: a first driving circuit for scan-driving scan lines of a first stack connected to light-emitting elements of the first stack in a display panel; and a second driving circuit for scan-driving scan lines of a second stack connected to light-emitting elements of the second stack in the display panel, wherein, when driven in an interlace scan mode, the first driving circuit and the second driving circuit can determine a scan start line of the first driving circuit and a scan start line of the second driving circuit by considering information regarding setting the number of first scan lines of the first driving circuit and information regarding setting the number of second scan line of the second driving circuit.

Description

Display driving device and driving method thereof

[0001] The present invention relates to a display driving device and a driving method thereof.

[0002] Light-emitting diode (LED) display devices have the advantages of high brightness, fast response speed, and excellent energy efficiency, as each pixel uses a self-emitting LED.

[0003] LED display devices utilize inorganic materials, offering superior durability compared to organic light-emitting diode (OLED) displays and allowing them to be applied to a variety of indoor and outdoor display devices. For example, LED display devices can be used in commercial display devices such as video wall displays and signage.

[0004] An LED display device may include a plurality of driver integrated circuits (Driver ICs) that drive the display panel.

[0005] When an LED display device drives a display panel using a progressive scan method, flicker may occur due to a difference in brightness between adjacent lines that is perceived as being sequentially driven.

[0006] The present invention provides a display driving device and a driving method thereof capable of eliminating a flicker phenomenon by applying an interlace scan method.

[0007] The present invention provides a display driving device and a driving method thereof that can apply an interlace scan method without restrictions on the number of scan lines set for each of a plurality of driving circuits.

[0008] A display driving device according to one embodiment of the present invention includes a first driving circuit for scanning-driving scan lines of a first stack connected to light-emitting elements of a first stack in a display panel, and a second driving circuit for scanning-driving scan lines of a second stack connected to light-emitting elements of a second stack in the display panel, wherein the first driving circuit and the second driving circuit can determine a scan start line of the first driving circuit and a scan start line of the second driving circuit by considering first scan line number setting information of the first driving circuit and second scan line number setting information of the second driving circuit when driving in an interlace scan mode.

[0009] A display driving device according to one embodiment of the present invention further includes a third driving circuit for scanning and driving scan lines of a third stack connected to light-emitting elements of a third stack in a display panel, wherein the first driving circuit, the second driving circuit, and the third driving circuit can determine a scan start line of the first driving circuit, a scan start line of the second driving circuit, and a start line of the third driving circuit by considering first scan line number setting information of the first driving circuit, second scan line number setting information of the second driving circuit, and third scan line number setting information of the third driving circuit when driving in an interlace scan mode.

[0010] A driving method of a display driving device according to an embodiment of the present invention comprises the steps of: determining a start line type of a first driving circuit, a start line type of a second driving circuit, and a start line type of a third driving circuit by considering first scan line number setting information of a first driving circuit, second scan line number setting information of a second driving circuit, and third scan line number setting information when driving in an interlace scan mode; sequentially scanning and driving, in the first driving circuit, scan lines of the same type as the start line type of the first driving circuit among a first stack; sequentially scanning and driving, in the second driving circuit, scan lines of the same type as the start line type of the second driving circuit among a second stack; sequentially scanning and driving, in the third driving circuit, scan lines of the same type as the start line type of the third driving circuit among a third stack; sequentially scanning and driving, in the first driving circuit, scan lines of the opposite type to the start line type of the first driving circuit among the first stack; and sequentially scanning and driving, in the second driving circuit, scan lines of the opposite type to the start line type of the second driving circuit among the second stack. A step of sequentially driving scan lines of a type, and a step of sequentially driving scan lines of a type opposite to the start line type of a third driving circuit among the third stacks in a third driving circuit.

[0011] A display driving device and a driving method thereof according to one embodiment of the present invention can improve image quality by eliminating flicker phenomenon by driving a display panel in an interlaced scan manner to prevent perception of brightness deviation between adjacent lines.

[0012] A display driving device and a driving method thereof according to one embodiment of the present invention can apply an interlace scan method without restrictions on the scan line number setting of each driving circuit by determining the scan start type of each driving circuit according to the scan line number setting of each of a plurality of driving circuits.

[0013] Figure 1 is an exemplary diagram showing the configuration of a display device according to one embodiment of the present invention.

[0014] FIG. 2 is a block diagram illustrating a display driving device according to one embodiment of the present invention.

[0015] FIG. 3 and FIG. 4 are waveform diagrams illustrating scan output of a display driving device according to one embodiment of the present invention.

[0016] FIGS. 5A to 5D are exemplary diagrams for explaining an interlace scan operation according to the number of scan lines of each driving circuit in a display driving device according to one embodiment of the present invention.

[0017] FIG. 6 is a block diagram illustrating a display driving device according to one embodiment of the present invention.

[0018] FIGS. 7A to 7C are diagrams illustrating a start line determination process of each driving circuit in a display driving device according to one embodiment of the present invention.

[0019] FIG. 8A and FIG. 8B are diagrams illustrating look-up tables stored in each driving circuit in display driving according to one embodiment of the present invention.

[0020] FIGS. 9a and 9b are exemplary diagrams for explaining an interlace scan operation according to the number of scan lines of each driving circuit in a display driving device according to one embodiment of the present invention.

[0021] Fig. 10 is an exemplary diagram schematically showing the internal configuration of a first driving circuit according to one embodiment of the present invention.

[0022] Fig. 11 is a flowchart illustrating a driving method of a display driving device according to one embodiment of the present invention.

[0023] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0024] Throughout the specification, identical reference numerals designate identical components. Furthermore, in describing the present invention, detailed descriptions of related known technologies are omitted if they are deemed to unnecessarily obscure the gist of the present invention.

[0025] In this specification, when the terms "includes," "has," and "consists of," are used, other parts may be added, unless "only" is used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0026] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description of the error range.

[0027] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on," "above," "below," "next to," or "adjacent to," there may be one or more other parts located between the two parts, unless, for example, "directly," "directly," or "nearby" is used.

[0028] When describing a temporal relationship, for example, when the temporal continuity is described as 'after', 'following', 'next to', 'before', etc., it can also include cases where it is not continuous, as long as 'right away' or 'directly' is not used.

[0029] While terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0030] The term "at least one" should be understood to include all possible combinations of one or more associated items. For example, "at least one of the first, second, and third items" can mean any combination of items that can be represented by two or more of the first, second, and third items, as well as each of the first, second, and third items.

[0031] The features of each of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical connections and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0032] Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. The scale of the components illustrated in the drawings is different from the actual scale for convenience of explanation, and is therefore not limited to the scale illustrated in the drawings.

[0033] FIG. 1 is an exemplary diagram showing the configuration of a display device according to one embodiment of the present invention, and FIG. 2 is a block diagram showing a display driving device according to one embodiment of the present invention.

[0034] Referring to FIG. 1, a display device according to one embodiment may include a display panel (100) and a display driving device (200).

[0035] The display panel (100) can display information, images, and the like using a pixel matrix in which a plurality of light-emitting elements (LEDs) are arranged in a matrix form. The pixel matrix of the display panel (100) can include a plurality of pixels (PX). Each pixel (PX) can include a plurality of light-emitting elements (LEDs) that can implement various colors by combining light-emitting colors. For example, each pixel (PX) can include a red light-emitting element (RLED) that emits red light, a green light-emitting element (GLED) that emits green light, and a blue light-emitting element (BLED) that emits blue light, but is not limited thereto.

[0036] The display panel (100) may include a plurality of scan lines (SL1 to SLx+y, where x and y are integers of 2 or greater) and a plurality of drive lines (DL1 to DLm+n, where m and n are integers of 2 or greater) connected to a display driver (200). Each of the plurality of light-emitting elements (LEDs) may be respectively arranged at the intersections of the plurality of scan lines (SL1 to SLx+y) and the plurality of drive lines (DL1 to DLm+n). Each of the plurality of scan lines (SL1 to SLx+y) may be commonly connected to a plurality of light-emitting elements (LEDs) arranged in a row direction (a first direction, a horizontal direction, an X-axis direction). Each of the plurality of drive lines (DL1 to DLm+n) may be commonly connected to a plurality of light-emitting elements (LEDs) arranged in a column direction (a second direction, a vertical direction, a Y-axis direction). A first electrode terminal (anode terminal) of a light-emitting element (LED) can be connected to a driving line (DL), and a second electrode terminal (cathode terminal) can be connected to a scan line (SL).

[0037] The display driving device (200) can output scan signals (SCAN1 to SCANx, (SCAN1 to SCANy)) to a plurality of scan lines (SL1 to SLx, SLx+1 to SLx+y) in a progressive scan manner or an interlaced scan manner. Each scan signal (SCAN) can have a scan-on voltage during the scan period of the corresponding scan line and a scan-off voltage during the scan periods of other scan lines.

[0038] The display driving device (200) can output a driving signal (light-emitting signal) controlled by a pulse width modulation (PWM) method through a plurality of output channels (CH1 to CHm, CH1 to CHn) respectively connected to a plurality of driving lines (DL1 to DLm, DLm+1 to DLm+n). Each driving signal can have a light-emitting on voltage and a light-emitting off voltage. The display driving device (200) can convert grayscale data corresponding to each light-emitting element (LED) into a PWM signal. The display driving device (200) can control the brightness by controlling the pulse width of the driving signal (light-emitting on voltage) using the PWM signal and thereby controlling the light-emitting period of each light-emitting element (LED).

[0039] The display driving device (200) may include a plurality of driving circuits (Driver ICs; D-ICs) that separately drive the display panel (100). For example, the display driving device (200) may include a first driving circuit (D-IC1) and a second driving circuit (D-IC2) that separately drive the display panel (100), but is not limited thereto, and the number of driving circuits (D-ICs) may increase depending on the resolution of the display panel (100).

[0040] The first driving circuit (D-IC1) and the second driving circuit (D-IC2) can divide and drive a plurality of driving lines (DL1 to DLm+n) into m driving lines (DL1 to DLm, first group) and n driving lines (DLm+1 to DLm+n, second group). The number (m) of driving lines (DL1 to DLm) connected to the first driving circuit (D-IC1) and the number (n) of driving lines (DLm+1 to DLm+n) driven by the second driving circuit (D-IC2) may be the same or different.

[0041] The first driving circuit (D-IC1) and the second driving circuit (D-IC2) can divide and drive a plurality of scan lines (SL1 to SLx+y) into x scan lines (SL1 to SLx) of the first stack (stack1) and y scan lines (SLx+1 to SLx+y) of the second stack (stack2). The number (x) of the scan lines (SL1 to SLx) connected to the first driving circuit (D-IC1) and the number (y) of the scan lines (SLx+1 to SLx+y) connected to the second driving circuit (D-IC2) may be the same or different.

[0042] The first driving circuit (D-IC1) and the second driving circuit (D-IC2) can share the scan of the first stack (stack1) scan lines (SL1 to SLx) driven by the first driving circuit (D-IC1) and can share the scan of the second stack (stack2) scan lines (SLx+1 to SLx+y) driven by the second driving circuit (D-IC2). Accordingly, the number of driving circuits (D-ICs) required for driving the display panel (100) can be reduced.

[0043] For example, the first driving circuit (D-IC1) can output scan signals (SCAN1 to SCANx) to the scan lines (SL1 to SLx) of the first stack (stack1) for each scan period. For each scan period of the scan lines (SL1 to SLx) of the first stack (stack1), the first and second driving circuits (D-IC1, D-IC2) can output driving signals to the driving lines (DL1 to DLm, DLm+1 to DLm+n) to control the brightness of each light-emitting element (LED) scanned in the first stack (Stack1) according to the driving signals.

[0044] The second driving circuit (D-IC2) can output scan signals (SCAN1 to SCANy) to the scan lines (SLx+1 to SLx+y) of the second stack (stack2) in each scan period. In each scan period of the scan lines (SLx+1 to SLx+y) of the second stack (stack2), the first and second driving circuits (D-IC1, D-IC2) output driving signals to the driving lines (DL1 to DLm, DLm+1 to DLm+n) so that the brightness of each light-emitting element (LED) scanned in the second stack (Stack2) can be adjusted according to the driving signals.

[0045] Referring to FIG. 2, the first driving circuit (D-IC1) and the second driving circuit (D-IC2) can be connected to the host (HOST) (1000) in a daisy chain manner.

[0046] The host (1000) can transmit setting information and data for driving the display panel (100) to the first driving circuit (D-IC1), and the first driving circuit (D-IC1) can transmit setting information and data received from the host (1000) to the second driving circuit (D-IC2). The first driving circuit (D-IC1) and the second driving circuit (D-IC2) can store and use the setting information received in a daisy chain manner in an internal register, and can store and use image data in a memory.

[0047] Based on the setting information received from the host (1000), the first driving circuit (D-IC1) can output scan signals (SCAN1 to SCANx) to the scan lines (SL1 to SLx) of the first stack (stack1), and the second driving circuit (D-IC2) can output scan signals (SCAN1 to SCANy) to the scan lines (SLx+1 to SLx+y) of the second stack (stack2).

[0048] In each scan period in which scan signals (SCAN1 to SCANx) are output to the first stack (stack1) by the first driving circuit (D-IC1), the first and second driving circuits (D-IC1, D-IC2) can output driving signals through channels (CH1 to CHm, CH1 to CHn) to drive the light-emitting elements (LEDs) of the first stack (stack1), and the brightness of each light-emitting element (LED) can be controlled according to the pulse width of the driving signal.

[0049] At each scan period in which scan signals (SCAN1 to SCANy) are output to the second stack (stack2) by the second driving circuit (D-IC2), the first and second driving circuits (D-IC1, D-IC2) can output driving signals through channels (CH1 to CHm, CH1 to CHn) to drive the light-emitting elements (LEDs) of the second stack (stack2), and the brightness of each light-emitting element (LED) can be controlled according to the pulse width of the driving signal.

[0050] When an interlace enable signal is received from the host (1000), the driving circuit (D-IC1, D-IC2) can drive the display panel (100) in an interlace scan mode. When an interlace disable signal is received from the host (1000), the driving circuit (D-IC1, D-IC2) can drive the display panel (100) in a progressive scan mode (normal scan mode).

[0051] When in interlace scan mode, the driving circuits (D-IC1, D-IC2) can determine the scan start line type of each driving circuit (D-IC1, D-IC2) based on the scan line number (x, y) information of each driving circuit (D-IC1, D-IC2) received from the host (1000).

[0052] When the number of scan lines (x, y) of each of the driving circuits (D-IC1, D-IC2) is an EVEN_EVEN combination in which both are even numbers, or an EVEN_ODD combination in which x is even and y is odd, both the driving circuits (D-IC1, D-IC2) can determine the scan start line type as an odd type or an even type.

[0053] On the other hand, if the number of scan lines (x, y) of each of the driving circuits (D-IC1, D-IC2) is an odd_odd (ODD_ODD) combination in which both numbers are odd, or an odd_even (ODD_EVEN) combination in which x is odd and y is even, the first driving circuit (D-IC1) and the second driving circuit (D-IC2) can determine the scan start line types to be opposite types.

[0054] FIG. 3 and FIG. 4 are waveform diagrams illustrating scan output of a display driving device according to one embodiment of the present invention.

[0055] Referring to FIGS. 3 and 4, each frame period can be determined by an internal vertical synchronization signal (i_VSYNC), and each frame period can include a plurality of sub-frame periods (SF1, SF2, 쪋). A plurality of driving circuits (D-IC1, D-IC2) can scan scan lines in an interlaced scan mode for each sub-frame period (SF1, SF2, 쪋).

[0056] Referring to FIG. 3, when the number of scan lines (x=4) of the first driving circuit (D-IC1) and the number of scan lines (y=4) of the second driving circuit (D-IC2) are both set to an even number (EVEN), in the interlace scan mode, the first and second driving circuits (D-IC1, D-IC2) can equally determine the scan start as an odd start type or an even start type.

[0057] For example, the first and second driving circuits (D-IC1, D-IC2) can equally determine the scan start as an odd start type. In the first period of half of each sub-frame period (SF1, SF2, 쪋), the first driving circuit (D-IC1) and the second driving circuit (D-IC2) can sequentially output odd-numbered scan signals (SCAN1, SCAN3, SCAN1, SCAN3) to sequentially drive odd-numbered scan lines of the first stack and the second stack. Subsequently, in the second period of the remaining half of each sub-frame period (SF1, SF2, 쪋), the first driving circuit (D-IC1) and the second driving circuit (D-IC2) can sequentially output even-numbered scan signals (SCAN2, SCAN4, SCAN2, SCAN4) to sequentially drive even-numbered scan lines of the first stack and the second stack.

[0058] Referring to FIG. 4, when the number of scan lines (x=3) of the first driving circuit (D-IC1) is set to an odd number (ODD) and the number of scan lines (y=4) of the second driving circuit (D-IC2) is set to an even number (EVEN), in the interlace scan mode, the first driving circuit (D-IC1) and the second driving circuit (D-IC2) can determine scan starts in opposite types.

[0059] For example, the first driving circuit (D-IC1) may determine the scan start as an odd start type, and the second driving circuit (D-IC2) may determine the scan start as an even start type. In the first period of each sub-frame period (SF1, SF2, 쪋), the first driving circuit (D-IC1) may sequentially output odd scan signals (SCAN1, SCAN3) to sequentially drive odd scan lines of the first stack, and then the second driving circuit (D-IC2) may sequentially output even scan signals (SCAN2, SCAN4) to sequentially drive even scan lines of the second stack. Next, in the second period among each sub-frame period (SF1, SF2, 쪋), the first driving circuit (D-IC1) sequentially outputs even-numbered scan signals (SCAN2) to sequentially drive even-numbered scan lines of the first stack, and then the second driving circuit (D-IC2) sequentially outputs odd-numbered scan signals (SCAN1, SCAN3) to sequentially drive odd-numbered scan lines of the second stack.

[0060] FIGS. 5A to 5D are exemplary diagrams for explaining an interlace scan operation according to the number of scan lines of each driving circuit in a display driving device according to one embodiment of the present invention.

[0061] Referring to FIGS. 5A to 5D, the first and second driving circuits (D-IC1, D-IC2) can continuously perform a line count operation for a scan operation and output a scan signal (SCAN) based on the line count value (i_line_count). For example, the first and second driving circuits (D-IC1, D-IC2) can scan 16 scan lines in a progressive scan mode (normal scan mode) or in an interlace scan mode based on the line count value (i_line_count).

[0062] In the interlaced scan mode, the scan start of the first and second driving circuits (D-IC1, D-IC2) in each sub-frame period can be determined according to a combination (ODD_EVEN, ODD_ODD, EVEN_EVEN, EVEN_ODD) of the scan line number (x, y) information of the first and second driving circuits (D-IC1, D-IC2).

[0063] Referring to FIGS. 5A and 5B, the number of scan lines (x=7) of the first driving circuit (D-IC1) is set to an odd number (ODD), and the number of scan lines (y=8, y=7) of the second driving circuit (D-IC2) can be set to an even number (EVEN) or an odd number (ODD). In this case, in the interlace scan mode, the scan start of the first driving circuit (D-IC1) and the scan start of the second driving circuit (D-IC2) can be determined to be opposite types.

[0064] Referring to FIG. 5a, when the number of scan lines (x=7, y=8) of the first and second driving circuits (D-IC1, D-IC2) is set to an odd-even combination, the first driving circuit (D-IC1) can determine the scan start as an odd type, and the second driving circuit (D-IC2) can determine the scan start as an even type.

[0065] The first half of each subframe (1 st In the Half) period, the first driving circuit (D-IC1) sequentially outputs odd scan signals (SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan odd scan lines of the first stack, and then the second driving circuit (D-IC2) sequentially outputs even scan signals (SCAN2, SCAN4, SCAN6, SCAN8) to sequentially scan even scan lines of the second stack.

[0066] The second half of each subframe (2nd1) st In the first half (1) period stIn contrast to the Half period, the first driving circuit (D-IC1) sequentially outputs even scan signals (SCAN2, SCAN4, SCAN6) to sequentially scan the even scan lines of the first stack, and then the second driving circuit (D-IC2) sequentially outputs odd scan signals (SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan the odd scan lines of the second stack.

[0067] Referring to FIG. 5b, when the number of scan lines (x=7, y=7) of the first and second driving circuits (D-IC1, D-IC2) is set to an odd-odd combination (ODD-ODD), the first driving circuit (D-IC1) can determine the scan start as an odd type, and the second driving circuit (D-IC2) in which the number of scan lines (y=7) is set to an odd number can determine the scan start as an even type.

[0068] The first half of each subframe (1 st In the Half) period, the first driving circuit (D-IC1) sequentially outputs odd-numbered scan signals (SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan the odd-numbered scan lines of the first stack, and then the second driving circuit (D-IC2) sequentially outputs even-numbered scan signals (SCAN2, SCAN4, SCAN6) to sequentially scan the even-numbered scan lines of the second stack.

[0069] The second half of each subframe (2nd1) st In the first half (1) period st In contrast to the Half) period, the first driving circuit (D-IC1) sequentially outputs even-numbered scan signals (SCAN2, SCAN4, SCAN6) to sequentially scan the even-numbered scan lines of the first stack, and then the second driving circuit (D-IC2) sequentially outputs odd-numbered scan signals (SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan the odd-numbered scan lines of the second stack.

[0070] Referring to FIGS. 5c and 5d, the number of scan lines (x=8) of the first driving circuit (D-IC1) is set to an even number (EVEN), and the number of scan lines (y=8, y=7) of the second driving circuit (D-IC2) can be set to an even number (EVEN) or an odd number (ODD). In this case, in the interlace scan mode, the scan starts of the first driving circuit (D-IC1) and the second driving circuit (D-IC2) can be determined to be of the same type.

[0071] Referring to FIG. 5c, when the number of scan lines (x=8, y=8) of the first and second driving circuits (D-IC1, D-IC2) is set to an EVEN-EVEN combination, the first driving circuit (D-IC1) and the second driving circuit (D-IC2) can determine the scan start to be the same odd type.

[0072] The first half of each subframe (1 st In the half period, the first driving circuit (D-IC1) and the second driving circuit (D-IC2) sequentially output odd-numbered scan signals (SCAN1, SCAN3, SCAN5, SCAN7, SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan odd-numbered scan lines of the first stack and the second stack.

[0073] The second half of each subframe (2nd1) st In the first half (1) period st In contrast to the Half period, the first driving circuit (D-IC1) and the second driving circuit (D-IC2) sequentially output even-numbered scan signals (SCAN2, SCAN4, SCAN6, SCAN8, SCAN2, SCAN4, SCAN6, SCAN8) to sequentially scan the even-numbered scan lines of the first stack and the second stack.

[0074] Referring to FIG. 5d, when the number of scan lines (x=8, y=7) of the first and second driving circuits (D-IC1, D-IC2) is set to an even-odd combination, the first driving circuit (D-IC1) and the second driving circuit (D-IC2) can determine the scan start to be the same odd type.

[0075] The first half of each subframe (1 st In the half period, the first driving circuit (D-IC1) and the second driving circuit (D-IC2) sequentially output odd-numbered scan signals (SCAN1, SCAN3, SCAN5, SCAN7, SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan odd-numbered scan lines of the first stack and the second stack.

[0076] The second half of each subframe (2nd1) st In the first half (1) period st In contrast to the Half period, the first driving circuit (D-IC1) and the second driving circuit (D-IC2) can sequentially output even-numbered scan signals (SCAN2, SCAN4, SCAN6, SCAN8, SCAN2, SCAN4, SCAN6) to sequentially scan the even scan lines of the first stack and the second stack.

[0077] FIG. 6 is a block diagram illustrating a display driving device according to one embodiment of the present invention.

[0078] Referring to FIG. 6, a display driving device according to one embodiment may include first to third driving circuits (D-IC1, D-IC2, D-IC3) connected to a host (HOST) (1000) in a daisy chain manner. A pixel matrix of a display panel according to one embodiment may include first to third stacks.

[0079] The host (1000) can transmit setting information and data for driving the display panel (100) to the first driving circuit (D-IC1), the first driving circuit (D-IC1) can transmit the setting information and data received from the host (1000) to the second driving circuit (D-IC2), and the second driving circuit (D-IC3) can transmit the setting information and data received from the first driving circuit (D-IC2) to the third driving circuit (D-IC3). The first to third driving circuits (D-IC1, D-IC2, D-IC3) can store and use the setting information received from the host (1000) in a daisy chain manner in an internal register, and can store and use image data in a memory.

[0080] Based on the setting information received from the host (1000), the first driving circuit (D-IC1) can output a plurality of scan signals (SCAN1 to SCANx) to the scan lines of the first stack, respectively, the second driving circuit (D-IC2) can output a plurality of scan signals (SCAN1 to SCANy) to the scan lines of the second stack, respectively, and the third driving circuit (D-IC2) can output a plurality of scan signals (SCAN1 to SCANz) to the scan lines of the third stack. The number of scan lines (x) of the first driving circuit (D-IC1), the number of scan lines (y) of the second driving circuit (D-IC2), and the number of scan lines (z) of the third driving circuit (D-IC2) may be the same as or different from each other.

[0081] In each scan period in which scan signals (SCAN1 to SCANx) are output to the scan lines of the first stack by the first driving circuit (D-IC1), the first to third driving circuits (D-IC1, D-IC2, D-IC3) can output driving signals through channels (CH1 to CHm, CH1 to CHn, CH1 to CHk) to drive the light-emitting elements (LEDs) of the first stack, and the brightness of each light-emitting element (LED) can be controlled according to the pulse width of the driving signal.

[0082] In each scan period in which scan signals (SCAN1 to SCANy) are output to the scan lines of the second stack by the second driving circuit (D-IC2), the first to third driving circuits (D-IC1, D-IC2, D-IC3) can output driving signals through the channels (CH1 to CHm, CH1 to CHn, CH1 to CHk) to drive the light-emitting elements (LEDs) of the second stack, and the brightness of each light-emitting element (LED) can be controlled according to the pulse width of the driving signal.

[0083] In each scan period in which scan signals (SCAN1 to SCANz) are output to the scan lines of the third stack by the third driving circuit (D-IC3), the first to third driving circuits (D-IC1, D-IC2, D-IC3) can output driving signals through channels (CH1 to CHm, CH1 to CHn, CH1 to CHk) to drive the light-emitting elements (LEDs) of the third stack, and the brightness of each light-emitting element (LED) can be controlled according to the pulse width of the driving signal.

[0084] When an interlace enable signal is received from the host (1000), the driving circuits (D-IC1, D-IC2, D-IC3) can drive the display panel in interlace scan mode. When an interlace disable signal is received from the host (1000), the driving circuits (D-IC1, D-IC2, D-IC3) can drive the display panel in progressive scan mode (normal scan mode).

[0085] When in interlaced scan mode, the driving circuits (D-IC1, D-IC2, D-IC3) can determine the scan start line type of each driving circuit (D-IC1, D-IC2, D-IC3) based on the scan line number (x, y, z) information of each driving circuit (D-IC1, D-IC2, D-IC3) received from the host (1000).

[0086] FIGS. 7A to 7C are diagrams illustrating a process of determining a start line of each driving circuit in a display driving device according to an embodiment of the present invention, and FIGS. 8A and 8B are diagrams illustrating a look-up table stored in each driving circuit in a display driving device according to an embodiment of the present invention. FIGS. 9A and 9B are diagrams illustrating an interlace scan operation according to the number of scan lines of each driving circuit in a display driving device according to an embodiment of the present invention.

[0087] Referring to FIGS. 7A to 7C, a plurality of driving circuits (D-IC1, D-IC2, D-IC3) can receive initial setting information in a daisy chain manner from the host (1000). The initial setting information can include an interlace enable signal (Interlace_en), a shared mode signal (Share mode), and the number of scan lines (x, y, z) of the first to third driving circuits (D-IC1, D-IC2, D-IC3).

[0088] The first to third driving circuits (D-IC1, D-IC2, D-IC3) can sequentially determine the scan start line type of each of the first to third driving circuits (D-IC1, D-IC2, D-IC3) operating in an interlace scan mode using initial setting information transmitted in a daisy chain manner from the host (1000).

[0089] Each of the first to third driving circuits (D-IC1, D-IC2, D-IC3) can determine a scan start line type using the scan line number (x, y, z) setting information of the first to third driving circuits (D-IC1, D-IC2, D-IC3) and a look-up table (LUT) stored in a register. The number of combinations of the scan line number (x, y, z) setting information of the first to third driving circuits (D-IC1, D-IC2, D-IC3) can be defined as eight types, as shown in the LUTs of FIGS. 8a and 8b.

[0090] Referring to FIG. 8a, when the interlace type (r_interlace_type) is 0, the scan start of the first driving circuit (D-IC1) can be set to an odd line (ODD line) type, like the first LUT set, and the scan start of each of the remaining driving circuits (D-IC2, D-IC3) can be set according to a combination of scan line number (x, y, z) setting information of the first to third driving circuits (D-IC1, D-IC2, D-IC3).

[0091] Referring to FIG. 8b, when the interlace type (r_interlace_type) is 1, the scan start of the first driving circuit (D-IC1) can be set to an even line type like the second LUT set, and the scan start of each of the remaining driving circuits (D-IC2, D-IC3) can be set according to a combination of scan line number (x, y, z) setting information of the first to third driving circuits (D-IC1, D-IC2, D-IC3).

[0092] Referring to FIGS. 8A and 8B, when the combination of scan line number (x, y, z) setting information of the first to third driving circuits (D-IC1, D-IC2, D-IC3) has a first combination of EVEN-EVEN-EVEN or a second combination of EVEN-EVEN-ODD, each of the first to third driving circuits (D-IC1, D-IC2, D-IC3) can determine the scan start as the same odd line type (ODD line) or the same even type (EVEN line).

[0093] When the combination of the scan line number (x, y, z) setting information of the first to third driving circuits (D-IC1, D-IC2, D-IC3) has a third combination of EVEN-ODD-EVEN or a fourth combination of EVEN-ODD-ODD, each of the first and second driving circuits (D-IC1, D-IC2) can determine the scan start as the same odd line type (ODD line) or the same even type (EVEN line), and the third driving circuit (D-IC3) can determine the scan start as the opposite line type to the start line type of the first and second driving circuits (D-IC1, D-IC2).

[0094] When the combination of the scan line number (x, y, z) setting information of the first to third driving circuits (D-IC1, D-IC2, D-IC3) has a fifth combination of odd-even-even (ODD-EVEN-EVEN) or a sixth combination of odd-even-odd (ODD-ENEN-ODD), each of the second and third driving circuits (D-IC2, D-IC3) can determine the scan start as the same odd line type (ODD line) or the same even type (EVEN line), and the first driving circuit (D-IC1) can determine the scan start as the opposite line type to the start line type of the second and third driving circuits (D-IC2, D-IC3).

[0095] When the combination of the scan line number (x, y, z) setting information of the first to third driving circuits (D-IC1, D-IC2, D-IC3) has a seventh combination of odd-odd-even (ODD-ODD-EVEN) or an eighth combination of odd-odd-odd (ODD-ODD-ODD), each of the first and third driving circuits (D-IC1, D-IC3) can determine the scan start as the same odd line type (ODD line) or the same even type (EVEN line), and the second driving circuit (D-IC2) can determine the scan start as the opposite line type to the start line type of the first and third driving circuits (D-IC1, D-IC3).

[0096] Referring to FIGS. 9A and 9B, the first to third driving circuits (D-IC1, D-IC2, D-IC3) can continuously perform a line count operation for a scan operation and output a scan signal (SCAN) based on the line count value (i_line_count). For example, the first to third driving circuits (D-IC1, D-IC2, D-IC3) can scan 19 scan lines in a progressive scan mode (normal scan mode) or in an interlace scan mode based on the line count value (i_line_count).

[0097] Referring to Fig. 9a, the number of scan lines (x=7, y=8, z=4) of the first to third driving circuits (D-IC1, D-IC2, D-IC3) can be set to the fifth combination of odd-even-even (ODD-EVEN-EVEN). In the interlace scan mode, the first driving circuit (D-IC1) can determine the odd type as the scan start, and each of the second and third driving circuits (D-IC2, D-IC3) can determine the even type as the scan start.

[0098] The first half of each subframe (1 stIn the half) period, the first driving circuit (D-IC1) sequentially outputs odd-numbered scan signals (SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan odd-numbered scan lines of the first stack, then the second driving circuit (D-IC2) sequentially outputs even-numbered scan signals (SCAN2, SCAN4, SCAN6, SCAN8) to sequentially scan even-numbered scan lines of the second stack, and then the third driving circuit (D-IC3) sequentially outputs even-numbered scan signals (SCAN2, SCAN4) to sequentially scan even-numbered scan lines of the third stack.

[0099] The second half of each subframe (2nd1) st In the first half (1) period st In contrast to the Half period, the first driving circuit (D-IC1) sequentially outputs even scan signals (SCAN2, SCAN4, SCAN6) to sequentially scan the even scan lines of the first stack, then the second driving circuit (D-IC2) sequentially outputs odd scan signals (SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan the odd scan lines of the second stack, and then the third driving circuit (D-IC3) sequentially outputs odd scan signals (SCAN1, SCAN3) to sequentially scan the odd scan lines of the third stack.

[0100] Referring to Fig. 9b, the number of scan lines (x=7, y=7, z=4) of the first to third driving circuits (D-IC1, D-IC2, D-IC3) can be set to the seventh combination of odd-odd-even (ODD-ODD-EVEN). In the interlace scan mode, each of the first and third driving circuits (D-IC1, D-IC3) can determine an odd type as a scan start, and the second driving circuit (D-IC2) can determine an even type as a scan start.

[0101] The first half of each subframe (1st In the Half) period, the first driving circuit (D-IC1) sequentially outputs odd scan signals (SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan the odd scan lines of the first stack, then the second driving circuit (D-IC2) sequentially outputs even scan signals (SCAN2, SCAN4, SCAN6) to sequentially scan the even scan lines of the second stack, and then the third driving circuit (D-IC3) sequentially outputs odd scan signals (SCAN1, SCAN3) to sequentially scan the odd scan lines of the third stack.

[0102] The second half of each subframe (2nd1) st In the first half (1) period st In contrast to the Half period, the first driving circuit (D-IC1) sequentially outputs even scan signals (SCAN2, SCAN4, SCAN6) to sequentially scan the even scan lines of the first stack, then the second driving circuit (D-IC2) sequentially outputs odd scan signals (SCAN1, SCAN3, SCAN5, SCAN7) to sequentially scan the odd scan lines of the second stack, and then the third driving circuit (D-IC3) sequentially outputs even scan signals (SCAN2, SCAN4) to sequentially scan the even scan lines of the third stack.

[0103] Fig. 10 is an exemplary diagram schematically showing the internal configuration of a first driving circuit according to one embodiment of the present invention.

[0104] Referring to FIG. 10, another first driving circuit (D-IC1) according to one embodiment may include a SPI (Serial Peripheral Interface) communication unit (310), a register (320), a timing controller (330), a scan controller (340), a memory (350), a memory controller (360), and a PWM controller (370).

[0105] The SPI communication unit (310) of the first driving circuit (D-IC1) can receive initial setting information of the first to third driving circuits (D-IC1, D-IC2, D-IC3) from the host (1000) in an SPI manner, transmit the information to the second driving circuit (D-IC2), and store the information in the register (320). The initial setting information can include an interlace enable signal (Interlace_en), a shared mode signal (Share mode), and the number of scan lines (x, y, z) of the first to third driving circuits (D-IC1, D-IC2, D-IC3).

[0106] The register (320) can output the stored initial setting information to the timing controller (330) and can output the interlace enable signal (Interlace_en) among the initial setting information to the memory controller (360).

[0107] The memory (350) can store image data corresponding to the first driving circuit (D-IC1) in line units. The memory (350) can receive and store image data corresponding to the first driving circuit (D-IC1) from the host (1000) via the SPI communication unit (310) and the memory controller (360). The memory (350) may be a volatile memory such as a DRAM (dynamic RAM), an SRAM (static RAM), or an SDRAM (synchronous dynamic RAM), but is not limited thereto and may be various types of memory.

[0108] When the interlace enable signal (Interlace_en) is enabled, the timing controller (300) operates in interlace scan mode and can control the scan controller (340) and the memory controller (360) to operate in interlace scan mode. When the interlace enable signal (Interlace_en) is disabled, the timing controller (300) operates in progressive scan mode (normal scan mode) and can control the scan controller (340) and the memory controller (360) to operate in progressive scan mode (normal scan mode).

[0109] The timing controller (300) can control the driving timing of the PWM controller (370) using a timing signal such as an internal vertical synchronization signal.

[0110] When the timing controller (300) operates in an interlaced scan mode, the timing controller (300) can determine the scan start line of each of the first to third driving circuits (D-IC1, D-IC2, D-IC3) using the scan line number (x, y, z) information of the first to third driving circuits (D-IC1, D-IC2, D-IC3) received from the register (330) and the LUT set.

[0111] The scan controller (340) can operate in a progressive scan mode or an interlaced scan mode under the control of the timing controller (300) to output scan signals (SCAN1 to SCANx) to the scan lines of the first stack. When the scan controller (340) operates in the interlaced scan mode, the scan controller (340) can sequentially drive the odd scan lines of the first stack or sequentially drive the even lines according to a line count value that increases by two lines from the start line determined by the timing controller (300).

[0112] The memory controller (360) can read image data from the memory (350) in a progressive scan mode or an interlace scan mode under the control of the timing controller (330) and output the data to the PWM controller (370). When the memory controller (360) operates in the interlace scan mode, the memory controller (360) can sequentially read data of odd lines or even lines corresponding to the first driving circuit (D-IC1) according to address information that increases by two lines from the start line determined by the timing controller (300) and output the data to the PWM controller (370).

[0113] The PWM controller (370) converts image data output from the memory controller (360) into a PWM signal, and can control the pulse width of the driving signal according to the PWM signal and output it through the channels (CH1 to CHm).

[0114] FIG. 11 is a flowchart illustrating an interlace scan method of a display driving device according to one embodiment of the present invention, and will be described with reference to the display driving device illustrated in FIG. 6.

[0115] Referring to FIG. 6 and FIG. 11, the display driving device starts driving by powering on, and the host (1000) can sequentially transmit initial setting information to the first to third driving circuits (D-IC1, D-IC2, D-IC3) in a daisy chain manner (S102).

[0116] The first to third driving circuits (D-IC1, D-IC2, D-IC3) can receive initial setting information from the host (1000) in a daisy chain manner and operate in an interlace scan mode, and can determine a scan start line of each of the first to third driving circuits (D-IC1, D-IC2, D-IC3) (S104). The first to third driving circuits (D-IC1, D-IC2, D-IC3) can determine a scan start line of each of the first to third driving circuits (D-IC1, D-IC2, D-IC3) using the scan line number (x, y, z) information of the first to third driving circuits (D-IC1, D-IC2, D-IC3) and a LUT set.

[0117] The first to third driving circuits (D-IC1, D-IC2, D-IC3) receive a vertical synchronization signal (Vsync) from the host (1000) and can start each frame period in synchronization with the vertical synchronization signal (Vsync) (S106).

[0118] The first driving circuit (D-IC1) can sequentially output scan signals to scan lines of the same type (odd type or even type) as the start determined in the first stack, increasing by two lines from the determined start line (S108, S110).

[0119] When the first driving circuit (D-IC1) completes the scan output to the scan lines (1 / 2 scan lines) of the same type in the first stack (S112, Yes), then the second driving circuit (D-IC2) increases by 2 lines from the determined start line and can sequentially output scan signals to the scan lines of the same type (odd type or even type) as the determined start in the second stack (S114, S116).

[0120] When the second driving circuit (D-IC2) completes scan output to the same type of scan lines (1 / 2 scan lines) in the second stack (S118, Yes), then the third driving circuit (D-IC3) increases by 2 lines from the determined start line and can sequentially output scan signals to the scan lines of the same type (odd type or even type) as the determined start line in the third stack (S120, S122).

[0121] When the third driving circuit (D-IC3) completes the scan output to the same type of scan lines (1 / 2 scan lines) in the third stack (S124, Yes), the first driving circuit (D-IC1) can sequentially output scan signals by increasing by 2 lines to the scan lines of the opposite type to the determined start (S126, S128).

[0122] When the first driving circuit (D-IC1) completes outputting the scan lines of the first stack (S130, Yes), the second driving circuit (D-IC2) can sequentially output scan signals by increasing by two lines for scan lines of the opposite type to the determined start (S132, S134).

[0123] When the second driving circuit (D-IC2) completes outputting the scan lines of the second stack (S136, Yes), the third driving circuit (D-IC3) can sequentially output scan signals by increasing by two lines for scan lines of the opposite type to the determined start (S138, S140).

[0124] When the third driving circuit (D-IC3) completes outputting the scan lines of the third stack (S142, Yes), the first to third driving circuits (D-IC1, D-IC2, D-IC3) can operate in an interlace scan mode by proceeding to the input stage (S106) of a vertical synchronization signal (Vsync) and repeatedly performing the steps (S108 to S142) described above.

[0125] The first to third driving circuits (D-IC1, D-IC2, D-IC) share the scan operation of the first driving circuit (D-IC1) when scanning the scan lines of the first stack (S108, S110, S126, S128) in the first driving circuit (D-IC1) and can output a plurality of driving signals to a plurality of driving lines connected to the light-emitting elements of the first stack, respectively.

[0126] The first to third driving circuits (D-IC1, D-IC2, D-IC) share the scan operation of the second driving circuit (D-IC2) when scanning the scan lines of the second stack (S114, S116, S132, S134) in the second driving circuit (D-IC2), and can output a plurality of driving signals to a plurality of driving lines connected to the light-emitting elements of the second stack, respectively.

[0127] The first to third driving circuits (D-IC1, D-IC2, D-IC) share the scan operation of the third driving circuit (D-IC3) when scanning the scan lines of the third stack (S120, S122, S138, S140) in the third driving circuit (D-IC3), and can output a plurality of driving signals to a plurality of driving lines connected to the light-emitting elements of the third stack, respectively.

[0128] The display driving device can terminate operation when a power off occurs (S144, Yes).

[0129] As described above, the display driving device and driving method according to one embodiment of the present invention can improve image quality by eliminating the flicker phenomenon by driving the display panel in an interlaced scan manner to prevent the perception of luminance deviation between adjacent lines.

[0130] A display driving device and a driving method thereof according to one embodiment of the present invention can apply an interlace scan method without restrictions on the scan line number setting of each driving circuit by determining the scan start type of each driving circuit according to the scan line number setting of each of a plurality of driving circuits.

[0131] The display driving device according to one embodiment of the present invention can be applied to a video wall display, a signage display, etc. that use a self-luminous element, but is not limited thereto and can be applied to various indoor and outdoor display devices. The display driving device according to one embodiment of the present invention can be applied to a foldable display, a rollable display, a bendable display, a flexible display, a curved display, a sliding display, a variable display, etc.

[0132] Those skilled in the art will appreciate that the present invention described above can be implemented in other specific forms without changing the technical idea or essential features thereof.

[0133] Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included within the scope of the present invention.

Claims

1. A first driving circuit for scanning and driving scan lines of a first stack connected to light-emitting elements of a first stack in a display panel; and In the display panel, a second driving circuit is included for driving scan lines of a second stack connected to light-emitting elements of a second stack, The above first driving circuit and the above second driving circuit, A driving device of a display device that determines a scan start line of the first driving circuit and a scan start line of the second driving circuit by considering the first scan line number setting information of the first driving circuit and the second scan line number setting information of the second driving circuit when driving in an interlace scan mode.

2. In claim 1, The above first driving circuit and the above second driving circuit, A display driving device in which the first driving circuit shares an operation of scanning and driving scan lines of the first stack, and outputs a plurality of driving signals to a plurality of driving lines connected to light-emitting elements of the first stack, respectively.

3. In claim 1, The above first driving circuit and the above second driving circuit, A display driving device in which the second driving circuit shares an operation of scanning and driving scan lines of the second stack, and outputs a plurality of driving signals to a plurality of driving lines connected to light-emitting elements of the second stack, respectively.

4. In claim 1, The above first driving circuit and the above second driving circuit, If the first scan line number setting information is an odd number and the second scan line number setting information is an even or odd number, A display driving device that determines the scan start line of the first driving circuit and the scan start line of the second driving circuit as opposite types among the odd type and the even type.

5. In claim 1, The above first driving circuit and the above second driving circuit, If the first scan line number setting information is an even number and the second scan line number setting information is an even or odd number, A display driving device that determines the scan start line of the first driving circuit and the scan start line of the second driving circuit as the same type among the odd type and the even type.

6. In claim 1, In addition, the display panel further includes a third driving circuit for scanning and driving scan lines of the third stack connected to the light-emitting elements of the third stack, The first driving circuit, the second driving circuit and the third driving circuit, A driving device of a display device that determines a scan start line of the first driving circuit, a scan start line of the second driving circuit, and a start line of the third driving circuit by considering the first scan line number setting information of the first driving circuit, the second scan line number setting information of the second driving circuit, and the third scan line number setting information of the third driving circuit when driving in the interlace scan mode.

7. In claim 6, The first to third driving circuits are, The first driving circuit shares the operation of scanning and driving the scan lines of the first stack, and outputs a plurality of driving signals to a plurality of driving lines connected to the light-emitting elements of the first stack, respectively. The second driving circuit shares the operation of scanning and driving the scan lines of the second stack, and outputs a plurality of driving signals to the plurality of driving lines connected to the light-emitting elements of the second stack, respectively. A display driving device in which the third driving circuit shares an operation of scanning and driving scan lines of the third stack, and outputs a plurality of driving signals to the plurality of driving lines connected to the light-emitting elements of the third stack, respectively.

8. In claim 7, The first to third driving circuits are, daisy chained to the host, A display driving device that receives all of the first scan line number setting information of the first driving circuit, the second scan line number setting information of the second driving circuit, and the third scan line number setting information of the third driving circuit.

9. In claim 6, The first to third driving circuits are, If the first scan line number setting information of the first driving circuit is an even number, the second scan line number setting information of the second driving circuit is an even number, and the third scan line number setting information of the third driving circuit is an even number or an odd number, A display driving device that determines the scan start line of the first driving circuit, the scan start line of the second driving circuit, and the scan start line of the third driving circuit as the same type among the odd type and the even type.

10. In claim 6, The first to third driving circuits are, If the first scan line number setting information of the first driving circuit is an even number, the second scan line number setting information of the second driving circuit is an odd number, and the third scan line number setting information of the third driving circuit is an even number or an odd number, A display driving device that determines the scan start line of the first driving circuit and the scan start line of the second driving circuit as the same type among an odd type and an even type, and determines the scan start line of the third driving circuit as the opposite type to the determined type.

11. In claim 6, The first to third driving circuits are, If the first scan line number setting information of the first driving circuit is an odd number, the second scan line number setting information of the second driving circuit is an even number, and the third scan line number setting information of the third driving circuit is an even number or an odd number, A display driving device that determines the scan start line of the second driving circuit and the scan start line of the third driving circuit as the same type among an odd type and an even type, and determines the scan start line of the first driving circuit as the opposite type to the determined type.

12. In claim 6, The first to third driving circuits are, If the first scan line number setting information of the first driving circuit is an odd number, the second scan line number setting information of the second driving circuit is an odd number, and the third scan line number setting information of the third driving circuit is an even number or an odd number, A display driving device that determines the scan start line of the first driving circuit and the scan start line of the third driving circuit as the same type among an odd type and an even type, and determines the scan start line of the second driving circuit as the opposite type to the determined type.

13. When driving in interlace scan mode, a step of determining a start line type of the first driving circuit, a start line type of the second driving circuit, and a start line type of the third driving circuit by considering the first scan line number setting information of the first driving circuit, the second scan line number setting information of the second driving circuit, and the third scan line number setting information of the second driving circuit; In the first driving circuit, a step of sequentially scanning and driving scan lines of the same type as the start line type of the first driving circuit among the first stacks; In the second driving circuit, a step of sequentially scanning and driving scan lines of the same type as the start line type of the second driving circuit among the second stacks; In the third driving circuit, a step of sequentially scanning and driving scan lines of the same type as the start line type of the third driving circuit among the third stacks; In the first driving circuit, a step of sequentially scanning and driving scan lines of a type opposite to the start line type of the first driving circuit among the first stack; In the second driving circuit, a step of sequentially scanning and driving scan lines of the opposite type to the start line type of the second driving circuit among the second stacks; and A driving method of a display driving device, comprising a step of sequentially scanning and driving scan lines of a type opposite to the start line type of the third driving circuit among the third stacks in the third driving circuit.

14. In claim 13, The step of determining the start line type of the first driving circuit, the start line type of the second driving circuit, and the start line type of the third driving circuit is: If the first scan line number setting information of the first driving circuit is an even number, the second scan line number setting information of the second driving circuit is an even number, and the third scan line number setting information of the third driving circuit is an even number or an odd number, A driving method of a display driving device, wherein the scan start line of the first driving circuit, the scan start line of the second driving circuit, and the scan start line of the third driving circuit are determined to be the same type among an odd type and an even type.

15. In claim 13, The step of determining the start line type of the first driving circuit, the start line type of the second driving circuit, and the start line type of the third driving circuit is: If the first scan line number setting information of the first driving circuit is an even number, the second scan line number setting information of the second driving circuit is an odd number, and the third scan line number setting information of the third driving circuit is an even number or an odd number, A driving method of a display driving device, wherein the scan start line of the first driving circuit and the scan start line of the second driving circuit are determined to be the same type among an odd type and an even type, and the scan start line of the third driving circuit is determined to be the opposite type to the determined type.

16. In claim 13, The step of determining the start line type of the first driving circuit, the start line type of the second driving circuit, and the start line type of the third driving circuit is: If the first scan line number setting information of the first driving circuit is an odd number, the second scan line number setting information of the second driving circuit is an even number, and the third scan line number setting information of the third driving circuit is an even number or an odd number, A driving method of a display driving device, wherein the scan start line of the second driving circuit and the scan start line of the third driving circuit are determined to be the same type among an odd type and an even type, and the scan start line of the first driving circuit is determined to be the opposite type to the determined type.

17. In claim 13, The step of determining the start line type of the first driving circuit, the start line type of the second driving circuit, and the start line type of the third driving circuit is: If the first scan line number setting information of the first driving circuit is an odd number, the second scan line number setting information of the second driving circuit is an odd number, and the third scan line number setting information of the third driving circuit is an even number or an odd number, A driving method of a display driving device, wherein the scan start line of the first driving circuit and the scan start line of the third driving circuit are determined to be the same type among an odd type and an even type, and the scan start line of the second driving circuit is determined to be the opposite type to the determined type.

18. In claim 13, The first to third driving circuits are, When scanning the scan lines of the first stack in the first driving circuit, the scan operation of the first driving circuit is shared, and a plurality of driving signals are output to each of the plurality of driving lines connected to the light-emitting elements of the first stack, When scanning the scan lines of the second stack in the second driving circuit, the scan operation of the second driving circuit is shared, and a plurality of driving signals are output to each of the plurality of driving lines connected to the light-emitting elements of the second stack, A driving method of a display driving device that shares the scan operation of the third driving circuit when scanning the scan lines of the third stack in the third driving circuit and outputs a plurality of driving signals to the plurality of driving lines connected to the light-emitting elements of the third stack.

Images