I2c slave device-based i2c interface system, and data read-write method

Abstract

The present invention provides an I2C slave device-based I2C interface system. The I2C interface system comprises an I2C master controller, an I2C slave device, a first functional module, and a second functional module. The I2C master controller is connected to the I2C slave device by means of an I2C clock line and an I2C data line. The I2C slave device is connected to the first functional module, and is connected to the second functional module. The present invention uses only one I2C slave device to support both command packet transmission and operation data byte transmission for I2C data, reducing interface signals, and solving the problem of insufficient chip pins in small-package integrated circuits.

Description

An I2C interface system based on I2C slave device and data reading and writing method Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an I2C interface system based on an I2C slave device and a data reading and writing method. Background Art

[0002] The I2C bus is a simple, bidirectional serial bus developed by Philips. Devices interconnected via the I2C bus are called I2C devices, and the interface connecting an I2C device to the I2C bus is called an I2C interface. The I2C bus has become a de facto international standard. The design specifications for the I2C bus and its protocol (referred to as the Standard I2C Specification) are generally based on the description in the document "THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000."

[0003] The I2C interface includes an I2C clock line (usually named SCL) and an I2C data line (usually named SDA). The I2C master controller connects to one or more I2C slave devices through the I2C clock line and the I2C data line. The I2C master controller drives the I2C clock line, initiates I2C write or read operations, and determines whether the data is sent successfully through the acknowledge bit. Bit errors on the bus due to signal interference and other reasons cannot be recognized by the I2C slave device.

[0004] The electrical characteristics of the I2C interface require that devices participating in I2C communication share a common ground; otherwise, data transmission will fail. Therefore, I2C communication is not suitable for applications with long transmission distances or high signal interference. To address this issue, devices used to forward I2C data are usually added to the I2C bus. However, the introduction of forwarding devices presents new problems:

[0005] The I2C communication mechanism requires that each time the I2C master controller sends a byte, the I2C slave device must reply with an acknowledge bit. When the acknowledge bit level is low, it is I2C ACK, and when the acknowledge bit level is high, it is I2C CNAK.

[0006] The existing I2C communication mechanism has two modes: one transmits I2C data as command packets, and the other transmits I2C data as operation data bytes. Specifically, each byte sent by the I2C master controller is passed to the module that ultimately receives the data (referred to as a functional module in this disclosure). The functional module then generates an acknowledgement bit and transmits it back to the I2C master controller. Transmitting I2C data as command packets has the advantage of high speed, especially over long distances. Transmitting I2C data as operation data bytes has the advantage of good compatibility with all current I2C master controllers without requiring any modifications. However, the disadvantage is slow speed.

[0007] In the prior art, supporting two I2C data transmission modes requires two I2C interfaces (two I2C slave devices), one supporting command packet transmission mode and the other supporting operation data byte transmission mode. Using two I2C interface signals results in wasted interface signals and a shortage of chip pins in small package integrated circuits.

[0008] Summary of the Invention

[0009] In order to solve the problems of waste of interface signals and insufficient chip pins in small package integrated circuits caused by using two I2C interfaces to support command packet transmission mode and operation data byte transmission mode respectively in the prior art, an object of the present invention is to provide an I2C interface system based on an I2C slave device, the I2C interface system comprising an I2C master controller, an I2C slave device, a first functional module, and a second functional module;

[0010] The I2C master controller is connected to the I2C slave device via an I2C clock line and an I2C data line; the I2C slave device is connected to the first functional module, and the I2C slave device is connected to the second functional module.

[0011] Another object of the present invention is to provide a data reading and writing method based on an I2C slave device, characterized in that the method uses the I2C interface system based on the I2C slave device provided by the present invention to read and write data, comprising:

[0012] The I2C master controller initiates a first I2C write operation and a second I2C write operation, wherein the first I2C write operation includes a first write address byte and first write operation data, and the first write operation data includes a command packet; the second I2C write operation includes a second write address byte and a second write operation data; and the first write address byte and the second write address byte both include an I2C write address and a write operation indication bit;

[0013] When the I2C write address received by the I2C slave device meets a first preset condition, the I2C slave device receives the command packet sent by the first I2C write operation, and after receiving the command packet, the I2C slave device sends the command packet to the first functional module;

[0014] The first functional module receives the command packet and executes the command. When the first functional module completes the command, the first functional module returns a feedback packet to the I2C slave device; the I2C slave device returns the information contained in the feedback packet to the I2C master controller;

[0015] When the I2C write address received by the I2C slave device meets a second preset condition, the I2C slave device receives a second I2C write operation, and after the I2C slave device receives each byte of the second write operation, sends each received byte of the second write operation to the second functional module;

[0016] After receiving each byte of the second write operation, the second functional module returns a second write status packet to the I2C slave device;

[0017] When the I2C slave device receives the second write status packet and the status information of the second write status packet is success, the I2C slave device returns an I2C ACK to the I2C master controller;

[0018] When the I2C slave device receives the second write status packet and the status information of the second write status packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller.

[0019] Preferably, the command packet received by the I2C slave device is a write command packet. After receiving the write command packet, the I2C slave device pulls down the I2C clock line level and sends the write command packet to the first functional module.

[0020] The first functional module receives the write command packet and executes the write command. When the first functional module completes the write command, the feedback packet returned to the I2C slave device is a first write status packet; the information contained in the feedback packet is the status information of the first write status packet, and the I2C slave device returns the status information of the first write status packet to the I2C master controller.

[0021] Preferably, the I2C slave device returns the status information of the first write status packet to the I2C master controller, including:

[0022] When the I2C slave device receives the first write status packet and the status information of the first write status packet is success, the I2C slave device stops pulling down the I2C clock line level and returns an I2C ACK to the I2C master controller;

[0023] When the I2C slave device receives the first write status packet and the status information of the first write status packet is failure, the I2C slave device stops pulling down the I2C clock line level and returns an I2C NAK to the I2C master controller.

[0024] Preferably, the command packet received by the I2C slave device is a write command packet, and after receiving the write command packet, the I2C slave device sends the write command packet to the first functional module;

[0025] The first functional module receives the write command packet and executes the write command. When the first functional module completes the write command, a feedback packet returned to the I2C slave device is a first write status packet. Information contained in the feedback packet is status information of the first write status packet. The I2C slave device returns the status information of the first write status packet to the I2C master controller, including:

[0026] After the I2C slave device receives the write command packet,

[0027] If the subsequent I2C operation initiated by the I2C master controller is a first I2C write operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device, and the status information of the first write status packet is success, then the I2C slave device receives the subsequent first I2C write operation initiated by the I2C master controller;

[0028] If the subsequent I2C operation initiated by the I2C master controller is a first I2C write operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device, and the status information of the first write status packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller;

[0029] If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device, the I2C slave device returns status information of the first write status packet to the I2C master controller.

[0030] Preferably, the command packet received by the I2C slave device is a read command packet. After receiving the read command packet, the I2C slave device pulls down the I2C clock line level and sends the read command packet to the first functional module.

[0031] The first functional module receives the read command packet and executes the read command. When the first functional module completes the read command, the feedback packet returned to the I2C slave device is the first read data packet, and the information contained in the feedback packet is the read data in the first read data packet; the I2C slave device returns the read data in the first read data packet to the I2C master controller.

[0032] Preferably, the I2C slave device returns the read data in the first read data packet to the I2C master controller, comprising:

[0033] When the I2C slave device receives the first read data packet, the I2C slave device stops pulling down the I2C clock line level;

[0034] If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, the I2C slave device returns the read data in the first read data packet to the I2C master controller.

[0035] Preferably, the command packet received by the I2C slave device is a read command packet, and after receiving the read command packet, the I2C slave device sends the read command packet to the first functional module;

[0036] The first functional module receives the read command packet and executes the read command. When the first functional module completes the read command, a feedback packet returned to the I2C slave device is a first read data packet, and information contained in the feedback packet is the read data in the first read data packet; the I2C slave device returns the read data in the first read data packet to the I2C master controller, including:

[0037] After the I2C slave device receives the read command packet,

[0038] If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, and the I2C slave device receives a first read data packet returned by the first functional module to the I2C slave device, the I2C slave device returns the read data in the first read data packet to the I2C master controller.

[0039] Preferably, the second functional module is further connected to a remote I2C slave device, and when the I2C slave device receives the second write address byte, the received second write address byte is sent to the second functional module;

[0040] After receiving the second write address byte, the second functional module sends an I2C START signal and the second write address byte to the remote I2C slave device, and receives an I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module;

[0041] If the remote I2C slave device returns an I2C ACK to the second functional module, the status information of the second write status packet returned by the second functional module to the I2C slave device is success;

[0042] If the remote I2C slave device returns an I2C NAK to the second functional module, the status information of the second write status packet returned by the second functional module to the I2C slave device is failure.

[0043] Preferably, the second functional module is further connected to a remote I2C slave device, and after receiving each second write operation data byte, the second functional module sends each received second write operation data byte to the remote I2C slave device, and after sending each second write operation data byte, receives an I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module;

[0044] If the remote I2C slave device returns an I2C ACK to the second functional module, the status information of the second write status packet returned by the second functional module to the I2C slave device is success;

[0045] If the remote I2C slave device returns an I2C NAK to the second functional module, the status information of the second write status packet returned by the second functional module to the I2C slave device is failure.

[0046] Preferably, the second functional module is also connected to a remote I2C slave device, and the I2C master controller can also send an I2C STOP signal to the I2C slave device.

[0047] After receiving the I2C STOP signal, the I2C slave device sends the I2C STOP signal to the remote I2C slave device through the second functional module.

[0048] Another object of the present invention is to provide a data reading and writing method based on an I2C slave device, using the I2C interface system based on the I2C slave device of the present invention to read and write data, comprising:

[0049] The I2C master controller initiates a first I2C read operation and a second I2C read operation, wherein the first I2C read operation includes a first read address byte and first read operation data; the second I2C read operation includes a second read address byte and second read operation data; the first read address byte and the second read address byte both include an I2C read address and a read operation indication bit;

[0050] When the I2C read address received by the I2C slave device meets a third preset condition, the I2C slave device receives a first I2C read operation, and the I2C slave device returns the first read operation data to the I2C master controller;

[0051] When the I2C read address received by the I2C slave device meets a fourth preset condition, the I2C slave device receives a second I2C read operation, and after the I2C slave device receives the second read address byte, sends the received second read address byte to the second functional module;

[0052] After receiving the second read address byte, the second functional module returns a second read data packet to the I2C slave device; wherein the second read data packet includes status information and / or one byte of second read operation data;

[0053] When the I2C slave device receives the second read data packet and the information status of the second read data packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller;

[0054] When the I2C slave device receives the second read data packet including one byte of second read operation data, the I2C slave device returns an I2C ACK and one byte of second read operation data to the I2C master controller;

[0055] After the I2C master controller receives one byte of the second read operation data, it sends an I2C ACK or an I2C NAK to the I2C slave device;

[0056] The I2C slave device sends the received I2C ACK or I2C NAK sent by the I2C master controller to the second functional module;

[0057] When the second functional module receives the I2C ACK, it returns a second read data packet containing one byte of second read operation data to the I2C slave device; after the I2C slave device receives the second read data packet containing one byte of second read operation data, it returns one byte of second read operation data to the I2C master controller.

[0058] Preferably, the second functional module is further connected to a remote I2C slave device, and when the I2C read address received by the I2C slave device meets a fourth preset condition, the I2C slave device receives a second I2C read operation, and after receiving the second read address byte, the I2C slave device sends the received second read address byte to the second functional module;

[0059] After receiving the second read address byte, the second functional module sends an I2C START signal and the second read address byte to the remote I2C slave device, and receives an I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module;

[0060] If the remote I2C slave device returns an I2C NAK to the second functional module, the information status of the second read data packet returned by the second functional module to the I2C slave device is failure;

[0061] If the remote I2C slave device returns an I2C ACK to the second functional module, the second functional module reads one byte of second read operation data from the remote I2C slave device and returns a second read data packet containing one byte of second read operation data to the I2C slave device.

[0062] Preferably, the I2C slave device sends the received I2C ACK or I2C NAK sent by the I2C master controller to the second functional module;

[0063] After receiving the I2C ACK, the second functional module sends an I2C ACK to the remote I2C slave device, reads one byte of second read operation data from the remote I2C slave device, and returns a second read data packet containing one byte of second read operation data to the I2C slave device.

[0064] Preferably, the I2C slave device sends the received I2C ACK or I2C NAK sent by the I2C master controller to the second functional module;

[0065] When the second functional module receives the I2C NAK, it sends an I2C NAK to the remote I2C slave device.

[0066] Preferably, when the I2C read address received by the I2C slave device meets a fourth preset condition, the I2C slave device receives a second I2C read operation, and after the I2C slave device receives the second read address byte, the received second read address byte is sent to the second functional module;

[0067] After receiving the second read address byte, the second functional module returns a second read data packet with failure status information to the I2C slave device, or after receiving the second read address byte, the second functional module returns a second read data packet with success status information and a second read data packet including one byte of second read operation data to the I2C slave device.

[0068] Preferably, the second functional module is further connected to a remote I2C slave device, and when the I2C read address received by the I2C slave device meets a fourth preset condition, the I2C slave device receives a second I2C read operation, and after receiving the second read address byte, the I2C slave device sends the received second read address byte to the second functional module;

[0069] After receiving the second read address byte, the second functional module sends an I2C START signal and the second read address byte to the remote I2C slave device, and receives an I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module;

[0070] If the remote I2C slave device returns an I2C NAK to the second functional module, the second functional module returns a second read data packet with an information status of failure to the I2C slave device;

[0071] If the remote I2C slave device returns an I2C ACK to the second functional module, the second functional module returns a second read data packet with status information indicating success to the I2C slave device.

[0072] And the second functional module reads a byte of second read operation data from the remote I2C slave device,

[0073] And the second functional module returns a second read data packet containing one byte of second read operation data to the I2C slave device.

[0074] Preferably, the functions of the second functional module and the functions of the first functional module can be integrated and implemented in the same module.

[0075] The present invention provides an I2C interface system and data reading and writing method based on an I2C slave device, which realizes supporting two modes of I2C data command packet transmission and operation data byte transmission using only one I2C slave device, saves interface signals, and solves the problem of insufficient chip pins in small package integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0077] FIG1 schematically shows a schematic diagram of an I2C interface system based on an I2C slave device according to the present invention.

[0078] FIG2 shows a timing diagram of an I2C write operation according to the present invention.

[0079] FIG3 shows a timing diagram of an I2C read operation according to the present invention.

[0080] FIG4 shows a timing diagram of the I2C continuous read and write operations of the present invention.

[0081] FIG5 shows a timing diagram of an I2C master controller initiating an I2C write operation according to the present invention.

[0082] FIG6 shows a timing diagram of the first mode of the present invention in which the I2C master controller initiates the first I2C write operation, sends a write command packet, and the status information of the first write status packet is success.

[0083] FIG7 shows a timing diagram of the first mode of the present invention in which the I2C master controller initiates the first I2C write operation, sends a write command packet, and the status information of the first write status packet is failure.

[0084] FIG8 shows a timing diagram of the second mode of the present invention in which the I2C master controller initiates the first I2C write operation, sends a write command packet, and the status information of the write status packet is success.

[0085] FIG9 shows a timing diagram of the second mode of the present invention in which the I2C master controller initiates the first I2C write operation, sends a write command packet, and the status information of the write status packet is failure.

[0086] FIG10 shows a timing diagram of the second mode of the present invention in which the I2C master controller initiates a first I2C write operation, sends a write command packet, and receives an I2C read operation.

[0087] FIG11 shows a timing diagram of the third mode of the present invention in which the I2C master controller initiates a first I2C write operation to send a read command packet, and the subsequent I2C operation is a first I2C read operation.

[0088] FIG12 shows a timing diagram of the fourth mode of the present invention in which the I2C master controller initiates a first I2C write operation to send a read command packet, and the subsequent I2C operation is a first I2C read operation.

[0089] FIG13 shows a timing diagram of the I2C master controller initiating a second I2C write operation and the I2C slave device receiving the second write operation according to the present invention.

[0090] 14 shows a timing diagram of the present invention in which the I2C master controller initiates a second I2C read operation, and the second functional module receives the second read address byte and returns a second read data packet containing one byte of second read operation data to the I2C slave device.

[0091] 15 shows a timing diagram of the present invention in which the I2C master controller initiates a second I2C read operation, and the second functional module receives the second read address byte and returns the status information of the second read data packet to the I2C slave device as failure.

[0092] 16 shows a timing diagram of the present invention in which the I2C master controller initiates a second I2C read operation, and after receiving the second read address byte, the second functional module returns a second read data packet with success status information and a second read data packet containing one byte of second read operation data to the I2C slave device.

[0093] The meanings of the text symbols in the above drawings are as follows:

[0094] 100: I2C master controller; 200: I2C slave device; 300: first functional module; 400: second functional module; 500: remote I2C slave device; 600: I2C data line (SDA); 700: I2C clock line (SCL);

[0095] S: Indicates the I2C START signal. The corresponding I2C bus state is that when SCL is high, SDA jumps from high to low.

[0096] P: Indicates the I2C STOP signal. The corresponding I2C bus state is that when SCL is high, SDA jumps from low to high.

[0097] Sr: The corresponding I2C bus state is the same as S;

[0098] Sr / P: The corresponding I2C bus state is Sr or P;

[0099] ADDR: I2C address (I2C write address or I2C read address);

[0100] R / W: indicates the read / write operation indication bit. When the bit is R, it indicates that the current operation is an I2C read operation. When the bit is W, it indicates that the current operation is an I2C write operation.

[0101] R: indicates the read operation indicator bit. The corresponding I2C bus state is that SDA is high while SCL is high.

[0102] W: indicates the write operation indicator bit. The corresponding I2C bus state is that SCL is high and SDA is low.

[0103] BYTE: write operation data or read operation data, usually a multi-byte sequence. The content in the brackets after it indicates the sequence number of the byte in the sequence. Write operation data is used to send write command packets or read command packets, and read operation data or status information is read through read operation data. The smaller sequence number is sent first;

[0104] A: Indicates I2C ACK. The corresponding I2C bus state is that SDA is always low while SCL is high.

[0105] N: Indicates I2C NAK. The corresponding I2C bus state is that SDA is always high while SCL is high.

[0106] DATA: Contains the bytes of read data and a sequence of I2C ACK / I2C NAK between bytes;

[0107] STATUS: Bytes containing status information and a sequence of I2C ACK / I2C NAK between bytes;

[0108] A / N: The corresponding I2C bus state is that SDA is always high or always low during the period when SCL is high.

[0109] HOLD: SCL is continuously low level;

[0110] IDLE: The corresponding I2C bus status includes the following two possibilities:

[0111] (1) Both SCL and SDA are high;

[0112] (2) SCL and SDA may have other level states, but no legal I2C operation occurs in the combination of these level states. When IDLE is about to end, SCL and SDA are both high. DETAILED DESCRIPTION

[0113] In order to make the above and other features and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explaining to those skilled in the art and are only exemplary and not restrictive.

[0114] The clock line (SCL) and the I2C data line (SDA) are collectively called the I2C bus. The I2C bus has become a de facto international standard. The design specifications of the I2C bus and its protocol (called the standard I2C specification) are usually based on the description in the document "THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000".

[0115] As shown in FIG1 , according to an embodiment of the present invention, an I2C interface system based on an I2C slave device is provided, including an I2C master controller 100 , an I2C slave device 200 , a first functional module 300 , and a second functional module 400 .

[0116] The I2C master controller 100 is connected to the I2C slave device 200 via an I2C clock line (SCL) 700 and an I2C data line (SDA) 600 . The I2C slave device 200 is connected to the first functional module 300 , and the I2C slave device 200 is connected to the second functional module 400 .

[0117] The first functional module 300 and the second functional module 400 of the present invention may be modules with different functions (thus, physically being two modules), or modules with the same function (in which case, they may be physically two modules or one module). The first functional module 300 and the second functional module 400 are merely for ease of description and may be two modules with different functions, two modules with the same function, or one module with the same function.

[0118] The embodiment shown in FIG. 1 further includes a remote I2C slave device 500 ; the second functional module 400 is connected to the remote I2C slave device 500 .

[0119] In other embodiments of the present invention, the remote I2C slave device 500 may not be included, and the second functional module 400 is not connected to the remote I2C slave device 500 .

[0120] The embodiment shown in Figure 1 includes a first functional module 300 and a second functional module 400. In other embodiments of the present invention, there may be multiple first functional modules 300 and second functional modules 400. In the following embodiments, one first functional module 300 and one second functional module 400 are used as an example for description.

[0121] An I2C master controller 100 can connect to one or more I2C slave devices 200 via the same I2C bus (clock line 500 and I2C data line 400), and transmit byte sequences carrying information through I2C read operations or I2C write operations. This embodiment uses an example of an I2C master controller 100 connecting to an I2C slave device 200 via the same I2C bus (I2C clock line (SCL) 700 and I2C data line (SDA) 600).

[0122] As shown in Figure 2, the I2C write operation includes a write address byte and one or more write operation data bytes (BYTE (1), ..., BYTE (N), shaded). The write address byte is the first byte sent. The write address byte includes the I2C write address (ADDR) and the write operation indicator bit (W). According to the standard I2C specification, the write operation indicator bit (W) is low.

[0123] In this embodiment, the write address byte and the write operation data byte are both 8 bits, wherein the write address byte includes a 7-bit I2C write address (ADDR) and a 1-bit write operation indicator bit (W). The present invention does not limit the number of bits of the write address byte and the write operation data byte. In other embodiments, the write address byte and the write operation data byte can have other bit numbers.

[0124] When the I2C master controller 100 initiates an I2C write operation, it first drives the I2C clock line (SCL) 700 and the I2C data line (SDA) 600 according to the standard I2C specification, generating an I2C START signal (S). It then sends a write address byte. After receiving the write address byte, the I2C slave device 200 drives the I2C data line (SDA) 600, generating an acknowledge bit. According to the standard I2C specification, the acknowledge bit can be either an I2C ACK (I2C data line (SDA) 600 is low) or an I2C NAK (I2C data line (SDA) 600 is high).

[0125] When the response bit of the write address byte is I2C ACK, the I2C master controller 100 can send one or more write operation data bytes. After receiving each write operation data byte, the I2C slave device 200 drives the I2C data line (SDA) 600 to generate an response bit. The response bit of the write operation data byte can be I2C ACK (the level of the I2C data line (SDA) 600 is low) or I2C NAK (the level of the I2C data line (SDA) 600 is high).

[0126] According to the standard I2C specification, when sending a write address byte and one or more write operation data bytes, the I2C master controller 100 drives the I2C data line (SDA) 600 to send the number of bits contained in the write address byte and the write operation data byte, and for each bit contained in the write address byte and the write operation data byte, the I2C master controller 100 drives the I2C clock line (SCL) 700 to generate a clock pulse.

[0127] According to the standard I2C specification, the I2C master controller 100 also drives the I2C clock line (SCL) 700 to generate a clock pulse corresponding to the acknowledge bit of the write address byte and the acknowledge bit of the write operation data byte. The I2C master controller 100 ends the current write operation by sending the I2C STOP signal (P) or the I2C START signal (S) as defined in the standard I2C specification.

[0128] As shown in FIG3 , an I2C read operation includes a read address byte and one or more read operation data bytes (BYTE(1), …, BYTE(N), unshaded). The read address byte is the first byte sent by the I2C master controller 100, and one or more read operation data bytes are sent by the I2C slave device 200. The read address byte includes an I2C read address (ADDR) and a read operation indicator bit (R). According to the standard I2C specification, the read operation indicator bit (R) is a high level.

[0129] In this embodiment, the read address byte and the read operation data byte are both 8 bits, wherein the read address byte includes a 7-bit I2C read address (ADDR) and a 1-bit read operation indicator bit (R). The present invention is not limited to the number of bits in the read address byte and the read operation data byte. In other embodiments, the read address byte and the read operation data byte can have other bit numbers.

[0130] When the I2C master controller 100 initiates an I2C read operation, the I2C master controller 100 first drives the I2C clock line (SCL) 700 and the I2C data line (SDA) 600 according to the standard I2C specification to generate an I2C START signal (S), and then sends a read address byte. After receiving the read address byte, the I2C slave device 200 drives the I2C data line (SDA) 600 to generate an acknowledge bit. According to the standard I2C specification, the acknowledge bit can be I2C ACK (the level of the I2C data line (SDA) 600 is low) or I2C NAK (the level of the I2C data line (SDA) 600 is high).

[0131] When the response bit of the read address byte is I2C ACK, the I2C slave device 200 can return one or more read operation data bytes by driving the I2C data line (SDA) 600. The I2C master controller 100 drives the I2C data line (SDA) 600 to generate an response bit after receiving each read operation data byte. The response bit of the read operation data byte can be I2C ACK (the level of the I2C data line (SDA) 600 is low) or I2C NAK (the level of the I2C data line (SDA) 600 is high).

[0132] According to the standard I2C specification, when the I2C master controller 100 sends a read address byte and the I2C slave device 20 returns one or more read operation data bytes, the I2C master controller 100 drives the I2C data line (SDA) 600 to send the number of bits contained in the read address byte, and the I2C slave device 200 returns the bits contained in the read operation data byte by driving the I2C data line (SDA) 600. In addition, for each bit contained in the read address byte and the read operation data byte, the I2C master controller 100 drives the I2C clock line (SCL) 700 to generate a clock pulse.

[0133] According to the standard I2C specification, the I2C master controller 100 also drives the I2C clock line (SCL) 700 to generate a clock pulse corresponding to the acknowledge bit of the read address byte and the acknowledge bit of the read operation data byte. The I2C master controller 100 ends the current read operation by sending the I2C STOP signal (P) or the I2C START signal (S) as defined in the standard I2C specification.

[0134] An I2C write or read cycle is initiated by the I2C START signal (S) but can be terminated in two ways. The first is with the I2C STOP signal (P). The timing sequences are shown in Figures 2 and 3, respectively.

[0135] The second method generates a new I2C START signal (S), which initiates the next I2C write or read operation. The timing sequence is shown in Figure 4. The dashed line between the acknowledge bit (A / N) and the I2C START signal (Sr) in Figure 4 (similar lines appear in other figures) is because the timing diagram is too long to be described on a single line, so it is split across multiple lines to indicate the connection between the two timing diagrams.

[0136] The use of any of the above-mentioned ending methods will not affect the data writing method and the data reading method of the present invention. For the convenience of description, the end of an I2C operation (I2C write operation or I2C read operation) is described in this embodiment in a manner with an I2C STOP signal (P).

[0137] 5 , the I2C master controller 100 initiates an I2C write operation, writing 0xA0, 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61 to the I2C slave device 200 in sequence. The 0xA0 byte corresponds to the write address byte, its upper 7 bits correspond to the I2C write address (ADDR) 0x50, and the lower 1 bit is the write operation indicator bit (W). A value of 0 for the write operation indicator bit (W) indicates that the current operation is a write operation. The value of this byte is the binary number 10100000, or the hexadecimal number 0xA0. A total of 7 bytes (0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61) correspond to the write operation data.

[0138] According to an embodiment of the present invention, a data reading and writing method based on an I2C slave device is provided, which uses an I2C interface system based on the I2C slave device to read and write data, including:

[0139] The I2C master controller 100 initiates a first I2C write operation and a second I2C write operation. The first I2C write operation includes a first write address byte and first write operation data, and the first write operation data includes a command packet.

[0140] The second I2C write operation includes a second write address byte and second write operation data. The first write address byte and the second write address byte both include an I2C write address (ADDR) and a write operation indicator bit (W).

[0141] The I2C master controller 100 initiates a first I2C write operation and a second I2C write operation, and the I2C slave device 200 receives the first I2C write operation and the second I2C write operation.

[0142] When the I2C write address (ADDR) received by the I2C slave device 200 meets the first preset condition, the I2C write operation received by the I2C slave device 200 is a first I2C write operation, and the I2C slave device 200 receives the command packet sent by the first I2C write operation. After receiving the command packet, the I2C slave device 200 sends the command packet to the first functional module 300.

[0143] When the I2C write address (ADDR) received by the I2C slave device 200 meets the second preset condition, the I2C write operation received by the I2C slave device 200 is a second I2C write operation.

[0144] The present invention does not specify or limit the first preset condition or the second preset condition. In one embodiment, the I2C write address (ADDR) received by the I2C slave device 200 satisfies the first preset condition, which may be that the I2C write address (ADDR) received by the I2C slave device 200 is in the first preset address range. The I2C write address (ADDR) received by the I2C slave device 200 satisfies the second preset condition, which may be that the I2C write address (ADDR) received by the I2C slave device 200 is in the second preset address range.

[0145] In the present invention, the first preset condition or the second preset condition may or may not have an intersection. If the first preset condition or the second preset condition has an intersection, it is necessary to further specify how to determine whether the I2C write operation received by the I2C slave device 200 is the first I2C write operation or the second I2C write operation when the I2C write address (ADDR) satisfies both the first preset condition and the second preset condition. The present invention does not impose any limitation on this provision.

[0146] 5, an example is given to illustrate the first preset condition. If the first preset condition is that the I2C write address (ADDR) received by the I2C slave device 200 is in the first preset address range, and the first preset address range includes the I2C address 0x50, when the value of the I2C write address (ADDR) byte received by the I2C slave device 200 is equal to the hexadecimal number 0xA0, the high 7 bits of the I2C write address (ADDR) byte correspond to the I2C write address (ADDR) 0x50, the I2C write address (ADDR) received by the I2C slave device 200 is equal to the hexadecimal number 0xA0, and the high 7 bits of the I2C write address (ADDR) byte correspond to the I2C write address (ADDR) 0x50. DDR) is in the first preset address range, thereby satisfying the first preset condition, then what the I2C slave device 200 receives is the first I2C write operation, 0xA0 corresponds to the first write address byte, 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61, a total of 7 bytes, correspond to the first write operation data, and the first write operation data includes a command packet. The I2C slave device 200 receives the command packet sent by the first I2C write operation, and after receiving the command packet, the I2C slave device 200 sends the command packet to the first functional module 300.

[0147] The command packet includes a write command packet and a read command packet. The write command packet of the present invention is sent through the write operation data bytes (BYTE (1), ..., BYTE (N)). The read command packet of the present invention is also sent through the write operation data bytes (BYTE (1), ..., BYTE (N)).

[0148] For example, when the I2C master controller 100 sends a write command packet, the I2C master controller 100 initiates a first I2C write operation to send a first write address byte and one or more first write operation data bytes (BYTE(1),…, BYTE(N)) containing the write command packet to the I2C slave device 200.

[0149] When the I2C master controller 100 sends a read command packet, the I2C master controller 100 initiates a first I2C write operation to send a first write address byte and one or more first write operation data bytes (BYTE(1), . . . , BYTE(N)) containing the read command packet to the I2C slave device 200 .

[0150] As shown in Figure 5, the I2C slave device 200 receives the last bit of the 0x61 byte, that is, the I2C slave device 200 receives the command packet, the I2C slave device 200 pulls down the I2C clock line 500 level, the I2C bus is in the HOLD state (continuous low level state), and the I2C slave device 200 sends the command packet to the first functional module 300.

[0151] The first functional module 300 receives the command packet and executes the command. After completing the command, the first functional module 300 returns a feedback packet to the I2C slave device 200. The I2C slave device 200 returns the information in the feedback packet to the I2C master controller 100.

[0152] The feedback packet of the present invention can be the first write status packet or the first read data packet. When the I2C master controller 100 sends a write command packet, the feedback packet is the first write status packet, and the information contained in the feedback packet is the status information of the first write status packet. When the I2C master controller 100 sends a read command packet, the feedback packet is the first read data packet, and the information contained in the feedback packet is the read data in the first read data packet.

[0153] In the present invention, when the I2C slave device 200 sends a command packet to the first functional module 300, the content in the command packet may be modified, added or deleted, and the present invention does not impose any limitation or stipulation on this.

[0154] The first write operation data in the present invention includes a command packet. In some embodiments of the present invention, the I2C slave device 200 receives the command packet when the I2C slave device 200 receives the last first write operation data byte BYTE (N). In other embodiments of the present invention, if the command packet is only included in part of the first write operation data, the command packet can be considered to be received after all the first write operation data bytes containing the command packet are received.

[0155] In FIG. 5 and the following description of the present invention, the I2C slave device 200 receiving the command packet means that the I2C slave device 200 receives the last first write operation data byte BYTE (N).

[0156] According to an embodiment of the present invention, when the command packet received by the I2C slave device 200 is a write command packet, the I2C slave device 200 pulls down the level of the I2C clock line (SCL) 700 after receiving the write command packet and sends the write command packet to the first functional module 300 .

[0157] The first functional module 300 receives the write command packet and executes the write command. After completing the write command, the first functional module 300 returns a first write status packet to the I2C slave device 200. The I2C slave device 200 returns the status information of the first write status packet to the I2C master controller 100.

[0158] According to an embodiment of the present invention, the I2C slave device 200 returns the status information of the first write status packet to the I2C master controller 100, including:

[0159] When the I2C slave device 200 receives the first write status packet and the status information of the first write status packet is success, the I2C slave device 200 stops pulling down the I2C clock line (SCL) 700 level and returns an I2C ACK to the I2C master controller 100 .

[0160] When the I2C slave device 200 receives the first write status packet and the status information of the first write status packet is failure, the I2C slave device 200 stops pulling down the level of the I2C clock line (SCL) 700 and returns an I2C NAK to the I2C master controller 100 .

[0161] For example, as shown in FIG6 , the I2C master controller 100 initiates an I2C operation (the first I2C write operation) with a sequence number of m (m is a natural number).

[0162] As shown in FIG6 , the I2C master controller 100 sends a write command packet through the first I2C write operation with sequence number m. After receiving the write command packet (after receiving BYTE(N)), the I2C slave device 200 pulls down the I2C clock line (SCL) 700 level, and the I2C bus is in the HOLD state (continuous low level state).

[0163] At time ①, the I2C slave device 200 receives the first write status packet and the status information of the first write status packet is success. The I2C slave device 200 stops pulling down the I2C clock line (SCL) 700 level, terminating the HOLD state (terminating the continuous low level state).

[0164] At time ②, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation with sequence number m (the first I2C write operation).

[0165] As shown in FIG7 , the I2C master controller 100 sends a write command packet through the first I2C write operation with sequence number m. After receiving the write command packet (after receiving BYTE(N)), the I2C slave device 200 pulls down the I2C clock line (SCL) 700 level, and the I2C bus is in the HOLD state (continuous low level state).

[0166] At time ①, the I2C slave device 200 receives the first write status packet and the status information of the first write status packet is failure. The I2C slave device 200 stops pulling down the I2C clock line (SCL) 700 level, terminating the HOLD state (terminating the continuous low level state).

[0167] At time ②, the I2C slave device 200 returns an I2C NAK to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation with sequence number m (the first I2C write operation).

[0168] In one embodiment, when the command packet received by the I2C slave device 200 is a write command packet, the I2C slave device 200 sends the write command packet to the first functional module 300 after receiving the write command packet.

[0169] The first functional module 300 receives the write command packet and executes the write command. After the first functional module 300 completes the write command, it returns a first write status packet to the I2C slave device 200. The I2C slave device 200 returns the first write status packet to the I2C master controller 100, including:

[0170] After the I2C slave device 200 receives the write command packet, if the subsequent I2C operation initiated by the I2C master controller 100 is the first I2C write operation, and the I2C slave device 200 receives the first write status packet returned by the first functional module 300 to the I2C slave device 200 and the status information of the first write status packet is success, then the I2C slave device 200 receives the subsequent first I2C write operation initiated by the I2C master controller 100.

[0171] If the subsequent I2C operation initiated by the I2C master controller 100 is the first I2C write operation, and the I2C slave device 200 receives the first write status packet returned by the first functional module 300 to the I2C slave device 200 and the status information of the first write status packet is failure, the I2C slave device 200 returns an I2C NAK to the I2C master controller 100.

[0172] If the subsequent I2C operation initiated by the I2C master controller 100 is a first I2C read operation, and the I2C slave device 200 receives the first write status packet returned by the first functional module 300 to the I2C slave device 200, the I2C slave device 200 returns status information of the first write status packet to the I2C master controller 100.

[0173] When the I2C master controller 100 initiates an I2C read operation and the I2C read address (ADDR) received by the I2C slave device 200 meets the third preset condition, the I2C read operation received by the I2C slave device 200 is a first I2C read operation. When the I2C read address (ADDR) received by the I2C slave device 200 meets the fourth preset condition, the I2C read operation received by the I2C slave device 200 is a second I2C read operation.

[0174] The present invention does not specify or limit the third preset condition or the fourth preset condition. In one embodiment, the I2C read address (ADDR) received by the I2C slave device 200 satisfies the third preset condition, which may be that the I2C read address (ADDR) received by the I2C slave device 200 is in the third preset address range. The I2C read address (ADDR) received by the I2C slave device 200 satisfies the fourth preset condition, which may be that the I2C read address (ADDR) received by the I2C slave device 200 is in the fourth preset address range.

[0175] In the present invention, the third preset condition or the fourth preset condition may or may not have an intersection. If the third preset condition or the fourth preset condition has an intersection, it is necessary to further specify how to determine whether the I2C read operation received by the I2C slave device 200 is the first I2C read operation or the second I2C read operation when the I2C read address (ADDR) satisfies both the third preset condition and the fourth preset condition. The present invention does not impose any limitation on this provision.

[0176] The first I2C read operation includes a first read address byte and first read operation data. In the present invention, the I2C slave device 200 can return status information of the first write status packet to the I2C master controller 100 through the first read operation data. The I2C slave device 200 can also return read data in the first read data packet (described below in the present invention) to the I2C master controller 100 through the first read operation data. The I2C slave device 200 can also return other status information generated by itself due to errors related to the write command packet and the read command packet to the I2C master controller 100 through the first read operation data.

[0177] As shown in Figures 8, 9 and 10, the I2C operation with sequence number m initiated by the I2C master controller 100 is the first I2C write operation, and the write command packet is sent to the I2C slave device 200. For the first N-1 first write operation data bytes (BYTE(1), ..., BYTE(N-1)), after each first write operation data byte is sent, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100.

[0178] After the I2C slave device 200 receives the Nth first write operation data byte (BYTE(N)) (i.e., after the I2C slave device 200 receives the complete write command packet), the I2C slave device 200 may return an I2C ACK or an I2C NAK to the I2C master controller 100. The specific selection is made by the agreement between the I2C master controller 100 and the I2C slave device 200. The I2C master controller 100 and the I2C slave device 200 may agree that after the Nth first write operation data byte (BYTE(N)), whether I2C ACK or I2C NAK indicates the successful reception of the Nth first write operation data byte (i.e., the complete write command packet). It can also be agreed that the I2C NAK indicates that the Nth first write operation data byte (BYTE(N)) was not successfully received (i.e., the complete write command packet was not successfully received). In the following description of the present invention, whether the I2C slave device 200 returns an I2C ACK or an I2C NAK to the I2C master controller 100 after the Nth first write operation data byte (BYTE(N)), it indicates that the Nth first write operation data byte (i.e., the complete write command packet) was successfully received.

[0179] After the I2C master controller 100 completes sending the Nth first write operation data byte (BYTE(N)), regardless of whether the I2C slave device 200 returns an I2C ACK or an I2C NAK to the I2C master controller 100, the I2C master controller 100 terminates the I2C operation with sequence number m (the first I2C write operation) and may choose to initiate an I2C operation with sequence number m+1 (a subsequent I2C operation).

[0180] When the I2C operation with sequence number m+1 (the subsequent I2C operation) is the first I2C write operation, if the I2C slave device 200 receives the first write status packet (the first write status packet corresponding to the I2C operation with sequence number m) returned by the first functional module 300 to the I2C slave device 200 and the status information of the first write status packet is success, then after the I2C master controller 100 sends the first write address byte, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100, and the I2C slave device 200 receives the first write operation data byte sent by the I2C operation with sequence number m+1 (the subsequent I2C operation / the first I2C write operation) initiated by the I2C master controller 100, as shown in Figure 8.

[0181] When the I2C operation with sequence number m+1 (subsequent I2C operation) is the first I2C write operation, if the I2C slave device 200 receives the first write status packet (the first write status packet corresponding to the I2C operation process with sequence number m) returned by the first functional module 300 to the I2C slave device 200 and the status information of the first write status packet is failure, then after the I2C master controller 100 sends the first write address byte, the I2C slave device 200 returns an I2C NAK to the I2C master controller 100, and the master controller 100 terminates initiation of the I2C operation m+1 (subsequent I2C operation / first I2C write operation), as shown in Figure 9.

[0182] As shown in Figure 10, when the I2C operation with sequence number m+1 initiated by the I2C master controller 100 is the first I2C read operation, if the I2C slave device 200 receives the first write status packet returned by the first functional module 300 to the I2C slave device 200 (the first write status packet corresponding to the I2C operation process with sequence number m), the I2C slave device 200 returns an I2C ACK to the I2C master controller 100 and returns status information (STATUS) of the first write status packet to the I2C master controller 100.

[0183] In one embodiment, when the command packet received by the I2C slave device 200 is a read command packet, the I2C slave device 200 pulls down the level of the I2C clock line (SCL) 700 after receiving the read command packet and sends the read command packet to the first functional module 300 .

[0184] The first functional module 300 receives the read command packet and executes the read command. After completing the read command, the first functional module 300 returns a first read data packet including the read data to the I2C slave device 200. The I2C slave device 200 returns the read data in the first read data packet to the I2C master controller 100.

[0185] According to an embodiment of the present invention, the I2C slave device 200 returns the read data of the first read data packet to the I2C master controller 100, including:

[0186] When the I2C slave device 200 receives the first read data packet, the I2C slave device 200 stops pulling down the level of the I2C clock line (SCL) 700 .

[0187] If the subsequent I2C operation initiated by the I2C master controller 100 is a first I2C read operation, the I2C slave device 200 returns the read data in the first read data packet to the I2C master controller 100 .

[0188] For example, as shown in Figure 11, the I2C master controller 100 initiates a first I2C write operation with a sequence number of m to send a read command packet to the I2C slave device 200. After receiving the read command packet (after receiving BYTE (N)), the I2C slave device 200 pulls down the I2C clock line (SCL) 700 level, and the I2C bus is in the HOLD state (continuous low level state).

[0189] At time ①, the I2C slave device 200 receives the first read data packet, and the I2C slave device 200 stops pulling down the level of the I2C clock line (SCL) 700, terminating the HOLD state (terminating the continuous low level state).

[0190] At time ②, the I2C slave device 200 returns an I2C ACK or I2C NAK to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation with sequence number m (the first I2C write operation).

[0191] In the present invention, the first read data packet includes the data (read data) read by the first functional module 300, or the status information generated by the first functional module 300 executing the read command, or both the data (read data) read by the first functional module 300 and the status information generated by the first functional module 300 executing the read command.

[0192] The present invention does not limit or stipulate that after the I2C slave device 200 receives the first read data packet and stops pulling down the I2C clock line level, it returns an I2C ACK or an I2C NAK to the I2C master controller 100. As an embodiment, the I2C slave device 200 can choose to stop pulling down the I2C clock line 500 level and return an I2C ACK to the I2C master controller 100 when the I2C slave device 200 receives the read data packet and the status information (read data) of the read data packet is success. When the I2C slave device 200 receives the read data packet and the status information of the read data packet is failure, the I2C slave device 200 stops pulling down the I2C clock line 500 level and returns an I2C NAK to the I2C master controller 100.

[0193] If the I2C operation (subsequent I2C operation) with sequence number m+1 initiated by the I2C master controller 100 is the first I2C read operation, then after the I2C slave device 200 receives the first read address byte, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100 and continues to return the read data (DATA) in the first read data packet, thereby allowing the I2C master controller 100 to continue to execute the I2C operation (subsequent I2C operation / I2C read operation) with sequence number m+1.

[0194] The I2C master controller 100 continues to execute the I2C operation with sequence number m+1 (subsequent I2C operation / I2C read operation) and reads the read data (DATA).

[0195] In one embodiment, when the command packet received by the I2C slave device 200 is a read command packet, the I2C slave device 200 sends the read command packet to the first functional module 300 after receiving the read command packet.

[0196] The first functional module 300 receives a read command packet and executes the read command. After completing the read command, the first functional module 300 returns a first read data packet to the I2C slave device 200. The first read data packet includes read data. The I2C slave device 200 returns the read data in the first read data packet to the I2C master controller 100, including:

[0197] After the I2C slave device 200 receives the read command packet, if the subsequent I2C operation initiated by the I2C master controller 100 is the first I2C read operation, and the I2C slave device 200 receives the first read data packet returned by the first functional module 300 to the I2C slave device 200, the I2C slave device 200 returns the read data in the first read data packet to the I2C master controller 100.

[0198] For example, as shown in Figure 12, the I2C operation with sequence number m initiated by the I2C master controller 100 is the first I2C write operation, and the read command packet is sent to the I2C slave device 200. For the first N-1 first write operation data bytes (BYTE(1), ..., BYTE(N-1)), after each first write operation data byte is sent, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100.

[0199] After the I2C slave device 200 receives the Nth first write operation data byte (BYTE(N)) (i.e., after the I2C slave device 200 receives the complete read command packet), the I2C slave device 200 may return an I2C ACK or an I2C NAK to the I2C master controller 100. The specific selection is made by the agreement between the I2C master controller 100 and the I2C slave device 200. The I2C master controller 100 and the I2C slave device 200 may agree that after the Nth first write operation data byte (BYTE(N)), whether I2C ACK or I2C NAK indicates the successful reception of the Nth first write operation data byte (i.e., the complete read command packet). It can also be agreed that the I2C NAK indicates that the Nth first write operation data byte (BYTE(N)) was not successfully received (i.e., the complete read command packet was not successfully received). In the following description of the present invention, whether the I2C slave device 200 returns an I2C ACK or an I2C NAK to the I2C master controller 100 after the Nth first write operation data byte (BYTE(N)), it indicates that the Nth first write operation data byte (i.e., the complete read command packet) was successfully received.

[0200] If the I2C operation (subsequent I2C operation) with sequence number m+1 initiated by the I2C master controller 100 is the first I2C read operation, and the I2C slave device 200 receives the first read data packet returned by the first functional module 300 to the I2C slave device 200 (the first read data packet corresponding to the I2C operation process with sequence number m), after receiving the first read address byte, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100 and returns the read data (DATA) in the first read data packet to the I2C master controller 100.

[0201] According to an embodiment of the present invention, the I2C master controller 100 is connected to the I2C slave device 200 via the I2C clock line (SCL) 700 and the I2C data line (SDA) 600. The I2C slave device 200 is connected to the first functional module 300 and the second functional module 400.

[0202] The I2C master controller 100 initiates a first I2C write operation and a second I2C write operation. The first I2C write operation includes a first write address byte and first write operation data, and the first write operation data includes a command packet.

[0203] The second I2C write operation includes a second write address byte and second write operation data. The first write address byte and the second write address byte both include an I2C write address (ADDR) and a write operation indicator bit (W).

[0204] The I2C master controller 100 initiates a first I2C write operation and a second I2C write operation, and the I2C slave device 200 receives the first I2C write operation and the second I2C write operation.

[0205] When the I2C write address received by the I2C slave device 200 meets the second preset condition, the I2C slave device 200 receives the second I2C write operation, and after the I2C slave device 200 receives each byte of the second write operation (including the second write address byte and each second write operation data byte), it sends each received byte of the second write operation to the second functional module 400.

[0206] 13 , for example, according to an embodiment of the present invention, the I2C master controller 100 sends a second write operation. After the I2C slave device 200 receives each byte of the second write operation (including the second write address byte and the second write operation data bytes BYTE(1),…, BYTE(N)), it sends each received byte of the second write operation to the second functional module 400. After the second functional module 400 receives each byte of the second write operation, it returns a second write status packet to the I2C slave device 200.

[0207] When the I2C slave device 200 receives the second write status packet and the status information of the second write status packet is success, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100 .

[0208] When the I2C slave device 200 receives the second write status packet and the status information of the second write status packet is failure, the I2C slave device 200 returns an I2C NAK to the I2C master controller 100 .

[0209] In the embodiment shown in FIG13 , the second write status packet returned by the second functional module 400 after receiving the second write address byte and the second write operation data bytes BYTE(1), ..., BYTE(N-1) indicates success. The second write status packet returned by the second functional module 400 after receiving the second write operation data byte BYTE(N) indicates success or failure. According to an embodiment of the present invention, the I2C master controller 100 is connected to the I2C slave device 200 via the I2C clock line (SCL) 700 and the I2C data line (SDA) 600. The I2C slave device 200 is connected to the first functional module 300, which is in turn connected to the second functional module 400. The second functional module 400 is also connected to the remote I2C slave device 500.

[0210] Further, when the I2C write address received by the I2C slave device 200 meets the second preset condition, the I2C slave device 200 receives the second write operation, and after receiving the second write address byte, the I2C slave device 200 sends the received second write address byte to the second functional module 400.

[0211] After receiving the second write address byte, the second functional module 400 sends an I2C START signal and the second write address byte to the remote I2C slave device 500 , and receives an I2C ACK or I2C NAK returned by the remote I2C slave device 500 to the second functional module 400 .

[0212] If the remote I2C slave device 500 returns an I2C ACK to the second functional module 400 , the status information of the second write status packet returned by the second functional module 400 to the I2C slave device 200 is success, and the I2C slave device 200 returns an I2C ACK to the I2C master controller 100 .

[0213] If the remote I2C slave device 500 returns an I2C NAK to the second functional module 400 , the status information of the second write status packet returned by the second functional module 400 to the I2C slave device 200 is failure, and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100 .

[0214] In the embodiment shown in FIG13 , the remote I2C slave device 500 returns an I2C ACK after receiving the second write address byte.

[0215] Furthermore, after the I2C slave device 200 receives each second write operation data byte (BYTE(1), ..., BYTE(N)), it sends the received second write operation data byte to the second functional module 400. After the second functional module 400 receives each second write operation data byte (BYTE(1), ..., BYTE(N)), it sends each received second write operation data byte (BYTE(1), ..., BYTE(N)) to the remote I2C slave device 500, and receives an I2C ACK or I2C NAK returned by the remote I2C slave device 500 to the second functional module 400.

[0216] If the remote I2C slave device 500 returns an I2C ACK to the second functional module 400 , the status information of the second write status packet returned by the second functional module 400 to the I2C slave device 200 is success, and the I2C slave device returns an I2C ACK to the I2C master controller 100 .

[0217] If the remote I2C slave device 500 returns an I2C NAK to the second functional module 400 , the status information of the second write status packet returned by the second functional module 400 to the I2C slave device 200 is failure, and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100 .

[0218] In the embodiment shown in FIG13 , the remote I2C slave device 500 returns an I2C ACK after receiving the second write operation data bytes BYTE(1), ..., BYTE(N-1). The remote I2C slave device 500 returns an I2C ACK or I2C NAK after receiving the second write operation data byte BYTE(N). Furthermore, as shown in FIG13 , the I2C master controller 100 can also send an I2C STOP signal to the I2C slave device 200. After receiving the I2C STOP signal, the I2C slave device 200 sends the I2C STOP signal to the remote I2C slave device 500 via the second functional module 400.

[0219] According to an embodiment of the present invention, a data reading and writing method based on an I2C slave device is provided, which uses an I2C interface system based on the I2C slave device to read and write data, including:

[0220] The I2C master controller 100 initiates a first I2C read operation and a second I2C read operation. The first I2C read operation includes a first read address byte and first read operation data.

[0221] In the present invention, the I2C slave device 200 returns the status information of the first write status packet to the I2C master controller 100 through the first read operation data. The I2C slave device 200 can also return the read data in the first read data packet to the I2C master controller 100 through the first read operation data. The I2C slave device 200 can also return other status information generated by itself due to errors related to the write command packet and the read command packet to the I2C master controller 100 through the first read operation data.

[0222] The second I2C read operation includes a second read address byte and a second read operation data. The first read address byte and the second read address byte both include an I2C read address (ADDR) and a read operation indicator bit (R).

[0223] When the I2C read address received by the I2C slave device 200 meets the third preset condition, the I2C slave device 200 receives the first I2C read operation, and the I2C slave device 200 returns the first read operation data to the I2C master controller 100 .

[0224] When the I2C read address received by the I2C slave device 200 meets the fourth preset condition, the I2C slave device receives a second I2C read operation, and after receiving the second read address byte, the I2C slave device 200 sends the received second read address byte to the second functional module 400 .

[0225] After receiving the second read address byte, the second functional module 400 returns a second read data packet to the I2C slave device 200. The second read data packet includes status information and / or one byte of second read operation data.

[0226] When the I2C slave device 200 receives the second read data packet and the information status of the second read data packet is failure, the I2C slave device 200 returns an I2C NAK to the I2C master controller 100 .

[0227] When the I2C slave device 200 receives the second read data packet including one byte of second read operation data, the I2C slave device 200 returns an I2C ACK and one byte of second read operation data to the I2C master controller 100 .

[0228] In the embodiment shown in FIG. 14 , after receiving the second read address byte, the second functional module 400 returns a second read data packet including one byte of second read operation data to the I2C slave device 200 .

[0229] In the embodiment shown in FIG. 15 , after receiving the second read address byte, the second functional module 400 returns a second read data packet with an information status of failure to the I2C slave device 200 .

[0230] 14 , according to an embodiment of the present invention, after receiving one byte of the second read operation data, the I2C master controller 100 sends an I2C ACK or I2C NAK to the I2C slave device 200. After receiving the I2C ACK or I2C NAK sent by the I2C master controller 100, the I2C slave device 200 sends the received I2C ACK or I2C NAK to the second functional module 400.

[0231] After receiving the I2C ACK, the second functional module 400 returns a second read data packet containing one byte of second read operation data to the I2C slave device 200. After receiving the second read data packet containing one byte of second read operation data, the I2C slave device 200 returns one byte of second read operation data to the I2C master controller 100.

[0232] According to an embodiment of the present invention, the I2C master controller 100 is connected to the I2C slave device 200 via the I2C clock line (SCL) 700 and the I2C data line (SDA) 600. The I2C slave device 200 is connected to the first functional module 300, which is in turn connected to the second functional module 400. The second functional module 400 is also connected to the remote I2C slave device 500.

[0233] When the I2C read address received by the I2C slave device 200 meets the fourth preset condition, the I2C slave device 200 receives the second I2C read operation, and after receiving the second read address byte, the I2C slave device 200 sends the received second read address byte to the second functional module 400 .

[0234] After receiving the second read address byte, the second functional module 400 sends an I2C START signal and the second read address byte to the remote I2C slave device 500, and receives an I2C ACK or I2C NAK returned by the remote I2C slave device 500 to the second functional module 400.

[0235] If the remote I2C slave device 500 returns an I2C NAK to the second functional module 400 , the information status of the second read data packet returned by the second functional module 400 to the I2C slave device 200 is failure, and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100 .

[0236] If the remote I2C slave device 500 returns an I2C ACK to the second functional module 400, the second functional module 400 reads one byte of second read operation data from the remote I2C slave device 500 and returns a second read data packet including the one byte of second read operation data to the I2C slave device 200. The I2C slave device 200 returns an I2C ACK and one byte of second read operation data to the I2C master controller 100.

[0237] In the embodiment shown in FIG14 , after the remote I2C slave device 500 receives the second read address byte, it returns an I2C ACK to the second functional module 400. The second functional module 400 then reads one byte of second read operation data from the remote I2C slave device 500 and returns a second read data packet containing one byte of second read operation data to the I2C slave device 200. The I2C slave device 200 then returns an I2C ACK and one byte of second read operation data to the I2C master controller 100.

[0238] In the embodiment shown in FIG15 , after the remote I2C slave device 500 receives the second read address byte, it returns an I2C NAK to the second functional module 400 . Then, the information status of the second read data packet returned by the second functional module 400 to the I2C slave device 200 is failure, and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100 .

[0239] 14 , according to an embodiment of the present invention, after receiving one byte of the second read operation data, the I2C master controller 100 sends an I2C ACK or I2C NAK to the I2C slave device 200. After receiving the I2C ACK or I2C NAK sent by the I2C master controller 100, the I2C slave device 200 sends the received I2C ACK or I2C NAK to the second functional module 400.

[0240] After receiving the I2C ACK, the second functional module 400 sends an I2C ACK to the remote I2C slave device 500, reads one byte of second read operation data from the remote I2C slave device 500, and returns a second read data packet containing the one byte of second read operation data to the I2C slave device 200. After receiving the second read data packet containing the one byte of second read operation data, the I2C slave device 200 returns the one byte of second read operation data to the I2C master controller 100.

[0241] After receiving the I2C NAK, the second functional module 400 sends an I2C NAK to the remote I2C slave device 500 .

[0242] In one embodiment, when the I2C read address received by the I2C slave device 200 meets the fourth preset condition, the I2C slave device 200 receives the second I2C read operation, and after the I2C slave device 200 receives the second read address byte, it sends the received second read address byte to the second functional module 400.

[0243] After receiving the second read address byte, the second functional module 400 returns a second read data packet with failure status information to the I2C slave device 200 (as shown in FIG15 ), or after receiving the second read address byte, the second functional module 400 returns a second read data packet with success status information and a second read data packet containing one byte of second read operation data to the I2C slave device 200. After receiving the second read data packet containing the one byte of second read operation data, the I2C slave device 200 returns an I2C ACK and one byte of second read operation data to the I2C master controller 100 (as shown in FIG16 ).

[0244] As shown in FIG16 , after the I2C master controller 100 receives one byte of the second read operation data, the processing is the same as that shown in FIG14 , which will not be described again here.

[0245] According to an embodiment of the present invention, the I2C master controller 100 is connected to the I2C slave device 200 via the I2C clock line (SCL) 700 and the I2C data line (SDA) 600. The I2C slave device 200 is connected to the first functional module 300, which is in turn connected to the second functional module 400. The second functional module 400 is also connected to the remote I2C slave device 500.

[0246] When the I2C read address received by the I2C slave device 200 meets the fourth preset condition, the I2C slave device 200 receives the second I2C read operation, and after receiving the second read address byte, the I2C slave device 200 sends the received second read address byte to the second functional module 400 .

[0247] After receiving the second read address byte, the second functional module 400 sends an I2C START signal and the second read address byte to the remote I2C slave device 500 , and receives an I2C ACK or I2C NAK returned by the remote I2C slave device 500 to the second functional module 400 .

[0248] If the remote I2C slave device 500 returns an I2C NAK to the second functional module 400 , the second functional module 400 returns a second read data packet with a failed information status to the I2C slave device 200 , and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100 , as shown in FIG15 .

[0249] If the remote I2C slave device 500 returns an I2C ACK to the second functional module 400, the second functional module 400 returns a second read data packet with success status information to the I2C slave device 200, and the second functional module 400 reads one byte of second read operation data from the remote I2C slave device 500, and the second functional module 400 returns a second read data packet including one byte of second read operation data to the I2C slave device 200.

[0250] After receiving the second read data packet including one byte of second read operation data, the I2C slave device 200 returns an I2C ACK and one byte of second read operation data to the I2C master controller 100 , as shown in FIG16 .

[0251] As shown in FIG16 , after the I2C master controller 100 receives one byte of the second read operation data, the processing is the same as that shown in FIG14 , which will not be described again here.

[0252] In the present invention, the I2C slave device 200 can suspend the I2C bus (the I2C bus is in the HOLD state) by pulling down the level of the I2C clock line (SCL) 700. In addition to the situation explicitly described above where the I2C slave device 200 pulls down the level of the I2C clock line (SCL) 700 to put the I2C bus in the HOLD state, the I2C slave device 200 can also suspend the I2C bus by pulling down the level of the I2C clock line (SCL) 700 in other situations (for example, when the I2C slave device 200 is internally busy) in accordance with the standard I2C specification, which will not be repeated herein.

[0253] In the above description of the present invention, a first functional module 300 and a second functional module 400 are used as examples. The present invention does not specify or limit the number or functions of the first functional module 300 and the second functional module 400. The number of the first functional module 300 and the second functional module 400 can be one or more. The functions of the second functional module 400 and the functions of the first functional module 300 can also be integrated and implemented in the same module. The I2C slave device 200 is connected to this module. When the embodiment of the present invention also includes a remote I2C slave device 500, the remote I2C slave device 500 is also connected to this module. Simple permutations, combinations, or divisions of the functions of the second functional module 400 and the functions of the first functional module 300 fall within the scope of protection of the present invention.

[0254] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. Any changes, modifications, substitutions and variations of the above embodiments made by a person skilled in the art within the scope of the present invention shall fall within the scope of protection of the present invention.

Claims

1. An I2C interface system based on an I2C slave device, characterized in that: The I2C interface system includes an I2C master controller, an I2C slave device, a first functional module, and a second functional module; The I2C master controller is connected to the I2C slave device via an I2C clock line and an I2C data line; the I2C slave device is connected to the first functional module, and the I2C slave device is connected to the second functional module.

2. A data reading and writing method based on an I2C slave device, characterized in that: Using the I2C interface system of claim 1 to read and write data includes: The I2C master controller initiates a first I2C write operation and a second I2C write operation, wherein the first I2C write operation includes a first write address byte and first write operation data, and the first write operation data includes a command packet; the second I2C write operation includes a second write address byte and a second write operation data; the first write address byte and the second write address byte both include an I2C write address and a write operation indication bit; When the I2C write address received by the I2C slave device meets the first preset condition, the I2C slave device receives the command packet sent by the first I2C write operation, and after the I2C slave device receives the command packet, sends the command packet to the first functional module; The first functional module receives the command packet and executes the command, and when the first functional module completes the command, returns a feedback packet to the I2C slave device; the I2C slave device returns the information contained in the feedback packet to the I2C master controller; When the I2C write address received by the I2C slave device meets the second preset condition, the I2C slave device receives a second I2C write operation, and after the I2C slave device receives each byte of the second write operation, sends each received byte of the second write operation to the second functional module; After receiving each byte of the second write operation, the second functional module returns a second write status packet to the I2C slave device; When the I2C slave device receives the second write status packet and the status of the second write status packet When the status information is successful, the I2C slave device returns an I2C ACK to the I2C master controller; When the I2C slave device receives the second write status packet and the status information of the second write status packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller.

3. The data reading and writing method according to claim 2, characterized in that: The command packet received by the I2C slave device is a write command packet. After receiving the write command packet, the I2C slave device pulls down the I2C clock line level and sends the write command packet to the first functional module; The first functional module receives the write command packet and executes the write command. When the first functional module completes the write command, the feedback packet returned to the I2C slave device is a first write status packet; the information contained in the feedback packet is the status information of the first write status packet, and the I2C slave device returns the status information of the first write status packet to the I2C master controller.

4. The data reading and writing method according to claim 3, characterized in that: The I2C slave device returns the status information of the first write status packet to the I2C master controller, including: When the I2C slave device receives the first write status packet and the status information of the first write status packet is success, the I2C slave device stops pulling down the I2C clock line level and returns an I2C ACK to the I2C master controller; When the I2C slave device receives the first write status packet and the status information of the first write status packet is failure, the I2C slave device stops pulling down the I2C clock line level and returns an I2C NAK to the I2C master controller.

5. The data reading and writing method according to claim 2, characterized in that: The command packet received by the I2C slave device is a write command packet. After receiving the write command packet, the I2C slave device sends the write command packet to the first functional module; The first functional module receives the write command packet and executes the write command, and when the first functional module completes the write command, the feedback packet returned to the I2C slave device is a first write status packet; The information contained in the feedback packet is the status information of the first write status packet, and the I2C slave device returns the status information of the first write status packet to the I2C master controller, including: After the I2C slave device receives the write command packet, If the subsequent I2C operation initiated by the I2C master controller is a first I2C write operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device and the status information of the first write status packet is success, then the I2C slave device receives the subsequent first I2C write operation initiated by the I2C master controller; If the subsequent I2C operation initiated by the I2C master controller is a first I2C write operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device and the status information of the first write status packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller; If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device, the I2C slave device returns status information of the first write status packet to the I2C master controller.

6. The data reading and writing method according to claim 2, characterized in that: The command packet received by the I2C slave device is a read command packet. After receiving the read command packet, the I2C slave device pulls down the I2C clock line level and sends the read command packet to the first functional module; The first functional module receives the read command packet and executes the read command. When the first functional module completes the read command, a feedback packet returned to the I2C slave device is a first read data packet, and information included in the feedback packet is the read data in the first read data packet; The I2C slave device returns the read data in the first read data packet to the I2C master controller.

7. The data reading and writing method according to claim 6, characterized in that: The I2C slave device returns the read data in the first read data packet to the I2C master controller, including: When the I2C slave device receives the first read data packet, the I2C slave device stops pulling down the I2C clock line level; If the subsequent I2C operation initiated by the I2C master controller is the first I2C read operation, the The I2C slave device returns the read data in the first read data packet to the I2C master controller.

8. The data reading and writing method according to claim 2, characterized in that: The command packet received by the I2C slave device is a read command packet. After receiving the read command packet, the I2C slave device sends the read command packet to the first functional module; The first functional module receives the read command packet and executes the read command. When the first functional module completes the read command, a feedback packet returned to the I2C slave device is a first read data packet, and information included in the feedback packet is the read data in the first read data packet; The I2C slave device returns the read data in the first read data packet to the I2C master controller, including: After the I2C slave device receives the read command packet, If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, and the I2C slave device receives a first read data packet returned by the first functional module to the I2C slave device, the I2C slave device returns the read data in the first read data packet to the I2C master controller.

9. The data reading and writing method according to claim 2, characterized in that: The second functional module is also connected to a remote I2C slave device, and when the I2C slave device receives a second write address byte, the received second write address byte is sent to the second functional module; After receiving the second write address byte, the second functional module sends an I2C START signal and the second write address byte to the remote I2C slave device, and receives an I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module; If the remote I2C slave device returns an I2C ACK to the second functional module, the status information of the second write status packet returned by the second functional module to the I2C slave device is success; If the remote I2C slave device returns an I2C NAK to the second functional module, the status information of the second write status packet returned by the second functional module to the I2C slave device is failure.

10. The data reading and writing method according to claim 2, characterized in that: The second functional module is also connected to a remote I2C slave device. After receiving each second write operation data byte, the second functional module sends each received second write operation data byte to the remote I2C slave device, and after sending each second write operation data byte, receives an I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module. If the remote I2C slave device returns an I2C ACK to the second functional module, the status information of the second write status packet returned by the second functional module to the I2C slave device is success; If the remote I2C slave device returns an I2C NAK to the second functional module, the status information of the second write status packet returned by the second functional module to the I2C slave device is failure.

11. The data reading and writing method according to claim 2, characterized in that: The second functional module is also connected to a remote I2C slave device, and the I2C master controller can also send an I2C STOP signal to the I2C slave device. After receiving the I2C STOP signal, the I2C slave device sends the I2C STOP signal to the remote I2C slave device through the second functional module.

12. A data reading and writing method based on an I2C slave device, characterized in that: Using the I2C interface system of claim 1 to read and write data includes: The I2C master controller initiates a first I2C read operation and a second I2C read operation, wherein the first I2C read operation includes a first read address byte and a first read operation data; the second I2C read operation includes a second read address byte and a second read operation data; the first read address byte and the second read address byte both include an I2C read address and a read operation indication bit; When the I2C read address received by the I2C slave device meets a third preset condition, the I2C slave device receives a first I2C read operation, and the I2C slave device returns the first read operation data to the I2C master controller; When the I2C read address received by the I2C slave device meets a fourth preset condition, the I2C slave device receives a second I2C read operation, and after the I2C slave device receives the second read address byte, the received second read address byte is sent to the second functional module; After receiving the second read address byte, the second functional module returns a second read data packet to the I2C slave device; wherein the second read data packet includes status information and / or a second read operation of one byte. data; When the I2C slave device receives the second read data packet and the information status of the second read data packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller; When the I2C slave device receives the second read data packet including one byte of second read operation data, the I2C slave device returns an I2C ACK and one byte of second read operation data to the I2C master controller; When the I2C master controller receives one byte of second read operation data, it sends an I2C ACK or an I2C NAK to the I2C slave device; The I2C slave device sends the received I2C ACK or I2C NAK sent by the I2C master controller to the second functional module; When the second functional module receives the I2C ACK, it returns a second read data packet containing one byte of second read operation data to the I2C slave device; after the I2C slave device receives the second read data packet containing one byte of second read operation data, it returns one byte of second read operation data to the I2C master controller.

13. The data reading and writing method according to claim 12, characterized in that: The second functional module is also connected to a remote I2C slave device. When the I2C read address received by the I2C slave device meets a fourth preset condition, the I2C slave device receives a second I2C read operation, and after the I2C slave device receives the second read address byte, the received second read address byte is sent to the second functional module. After receiving the second read address byte, the second functional module sends an I2C START signal and the second read address byte to the remote I2C slave device, and receives an I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module; If the remote I2C slave device returns an I2C NAK to the second functional module, the information status of the second read data packet returned by the second functional module to the I2C slave device is failure; If the remote I2C slave device returns an I2C ACK to the second functional module, the first The second functional module reads one byte of second read operation data from the remote I2C slave device, and returns a second read data packet containing one byte of second read operation data to the I2C slave device.

14. The data reading and writing method according to claim 13, characterized in that: The I2C slave device sends the received I2C ACK or I2C NAK sent by the I2C master controller to the second functional module; After receiving the I2C ACK, the second functional module sends an I2C ACK to the remote I2C slave device, reads one byte of second read operation data from the remote I2C slave device, and returns a second read data packet containing one byte of second read operation data to the I2C slave device.

15. The data reading and writing method according to claim 13, characterized in that: The I2C slave device sends the received I2C ACK or I2C NAK sent by the I2C master controller to the second functional module; When the second functional module receives the I2C NAK, it sends the I2C NAK to the remote I2C slave device.

16. The data reading and writing method according to claim 12, characterized in that: When the I2C read address received by the I2C slave device meets a fourth preset condition, the I2C slave device receives a second I2C read operation, and after the I2C slave device receives the second read address byte, the received second read address byte is sent to the second functional module; After receiving the second read address byte, the second functional module returns a second read data packet with failure status information to the I2C slave device, or after receiving the second read address byte, the second functional module returns a second read data packet with success status information and a second read data packet containing one byte of second read operation data to the I2C slave device.

17. The data reading and writing method according to claim 16, characterized in that: The second functional module is also connected to a remote I2C slave device. When the I2C read address received by the I2C slave device meets a fourth preset condition, the I2C slave device receives a second I2C read operation, and after the I2C slave device receives the second read address byte, the received second read address byte is sent to the second functional module. After receiving the second read address byte, the second functional module sends an I2C START signal and the second read address byte to the remote I2C slave device, and receives an I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module; If the remote I2C slave device returns an I2C NAK to the second functional module, the second functional module returns a second read data packet with an information status of failure to the I2C slave device; If the remote I2C slave device returns an I2C ACK to the second functional module, the second functional module returns a second read data packet with status information of success to the I2C slave device. And the second functional module reads a byte of second read operation data from the remote I2C slave device, And the second functional module returns a second read data packet including one byte of second read operation data to the I2C slave device.

18. The I2C interface system according to claim 1, characterized in that: The functions of the second functional module and the functions of the first functional module can be integrated and implemented in the same module.

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