Data processing method, switching board, data processing system and data processing apparatus

Abstract

The embodiments of the present application provide a data processing method, a switching board, a data processing system and a data processing apparatus. The method comprises: receiving a first fault instruction sent by a controller; on the basis of the first fault instruction, acquiring first target data; and transmitting the first target data to a second host system, so as to instruct the second host system to control a second processor to continue to process first data according to the first target data, wherein the second host system is a host system in a normal operating state among a plurality of host systems connected to a CXL switching device, and the second processor is a processor allocated to the second host system by the CXL switching device. By means of the present application, the problem of it not being possible to ensure the continuity of data processing in the related art is solved, and thus the effect of ensuring the continuity of data processing is achieved.

Description

Data processing method, switch board, data processing system, and data processing device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on September 6, 2023, with application number 202311144706.0, and application name “Data processing method and switching board, data processing system, data processing device”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of computers, and in particular, to a data processing method and a switch board, a data processing system, and a data processing device. Background Art

[0004] As more and more businesses are conducted online, there are more and more application scenarios with high concurrency and high computing power requirements, such as artificial intelligence (AI), high-performance computing (HPC), and cloud services. At this time, there is a huge demand for the number of memory pools in data centers. In addition, there are a large number of PCI-Express (Peripheral Component Interconnect Express, PCIe) computing accelerators, which require massive cache data exchange. At this time, the amount of memory and memory segmentation will cause huge waste of computing power and performance degradation. Therefore, cluster servers are gradually shifting from computing centers to data centers. Therefore, increasing memory capacity and improving cache consistency are extremely important.

[0005] In addition, the more data there is, the greater the risk. Data of all sizes are constantly interacting and calculated every day. There are many reasons that can cause equipment to crash and lose the current computing data. After the device is restarted, all calculations need to be restarted. This cannot meet the needs of scenarios such as AI, HPC, and cloud services that use massive computing models. Therefore, ensuring the continuity of computing services and ensuring that the system does not shut down has become an urgent problem that needs to be solved.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a data processing method and a switch board, a data processing system, and a data processing device to at least solve the problem in the related art that the continuity of data processing cannot be guaranteed.

[0008] According to a first aspect of an embodiment of the present application, a data processing method is provided, applied to a CXL switching device, comprising: receiving a first fault instruction sent by a controller, wherein the first fault instruction is used to indicate a fault in a first host system, the first host system being configured to control a first processor to process first data, the first processor being an accelerator assigned to the first host system by the CXL switching device, the CXL switching device being a device supporting the open interconnection standard CXL protocol; obtaining first target data based on the first fault instruction, wherein the first target data includes processing logic data for the first processor processing the first data and first result data of the first processor processing the first data; and transmitting the first target data to a second host system to instruct the second host system to control the second processor to continue processing the first data according to the first target data, wherein the second host system is a host system in a normal operating state among multiple host systems connected to the CXL switching device, and the second processor is a processor assigned to the second host system by the CXL switching device.

[0009] According to a second aspect of an embodiment of the present application, a switch board is provided, comprising: a CXL switch device and multiple device interfaces, wherein the multiple device interfaces are configured to allow a controller, multiple host systems, extended memory, and multiple processors to access the CXL switch device under the control of the CXL switch device. The CXL switch device is configured to execute a data processing method.

[0010] According to a third aspect of an embodiment of the present application, a data processing system is provided, comprising: a switch board, a controller, multiple host systems, extended memory, and multiple processors. A CXL switch device and multiple device interfaces are deployed on the switch board, and the multiple device interfaces are configured to allow the controller, multiple host systems, extended memory, and multiple processors to access the CXL switch device under the control of the CXL switch device. The CXL switch device is configured to execute a data processing method. The controller is configured to send a first fault instruction to the switch device, wherein the first fault instruction is used to indicate that a first host system among the multiple host systems has failed. The first host system is configured to control a first processor to process first data. The first processor is an accelerator that the CXL switch device allocates to the first host system from the multiple processors.

[0011] In an exemplary embodiment, the controller includes a target processor and a baseboard management controller, wherein the baseboard management controller is connected to multiple host systems and is configured to monitor the working status of the multiple host systems, and when a faulty host system is included in the multiple host systems, the baseboard management controller sends the faulty working status of the faulty host system to the target processor; the target processor is configured to generate a fault instruction based on the faulty working status, and the fault instruction includes system information of the corresponding faulty host system.

[0012] In an exemplary embodiment, the baseboard management controller is further configured to monitor the first host system through multiple signals, and when multiple signals indicate that the first host system has failed, the fault working status of the first host system is sent to the target processor; the target processor is configured to generate a first fault instruction based on the fault working status of the first host system.

[0013] In an exemplary embodiment, the baseboard management controller is also configured to restart the first host system and, when the first host system is restarted, send a fault recovery instruction to the target processor, wherein the fault recovery instruction is used to indicate that the fault of the first host system has been repaired and is currently in normal working condition.

[0014] In an exemplary embodiment, the controller further includes a programmable logic device, wherein the programmable logic device is connected to the target processor and configured to receive a fault recovery instruction sent by the target processor and send the fault recovery instruction to the CXL switch device to instruct the CXL switch device to switch the second host system to the first host system to continue processing the first data.

[0015] In an exemplary embodiment, the CXL switch device is further configured to allocate memory and processors to multiple host systems, wherein the allocated memory is idle memory in the extended memory, and the allocated processor is an idle processor among the multiple processors.

[0016] In an exemplary embodiment, expanded memory, multiple processors, and multiple host systems are all enabled to interface with multiple devices via CXL links under the control of a CXL switch device.

[0017] In an exemplary embodiment, expanded memory, multiple processors, and multiple host systems are all enabled to interface with multiple devices via CXL links under the control of a CXL switch device.

[0018] According to a fourth aspect of an embodiment of the present application, a data processing device is further provided, comprising: a first receiving module configured to receive a first fault instruction sent by a controller, wherein the first fault instruction is used to indicate that a fault has occurred in a first host system, the first host system being configured to control a first processor to process first data, the first processor being an accelerator assigned to the first host system by a CXL switch device, the CXL switch being a device supporting the open interconnection standard CXL protocol; a first acquiring module configured to acquire first target data based on the first fault instruction, wherein the first target data includes processing logic data for processing the first data by the first processor and first result data of the processing of the first data by the first processor; and a first transmitting module configured to transmit the first target data to a second host system to instruct the second host system to control the second processor to continue processing the first data according to the first target data, wherein the second host system is a host system in a normal operating state among multiple host systems connected to the CXL switch device, and the second processor is a processor assigned to the second host system by the CXL switch device.

[0019] In an exemplary embodiment, a first receiving module includes: a first receiving unit, configured to receive a first fault instruction sent by a target processor in a controller; wherein the target processor is connected to a baseboard management controller, the baseboard management controller is connected to multiple host systems, and is configured to monitor the working status of multiple host systems, and when a faulty host system is included in the multiple host systems, the faulty working status of the faulty host system is sent to the target processor, and the target processor is configured to generate a fault instruction based on the faulty working status, and the fault instruction includes system information of the corresponding faulty host system.

[0020] In an exemplary embodiment, a first acquisition module includes: a first response unit configured to, in response to a first fault instruction, acquire processing logic data from a first memory corresponding to a first host system, and acquire first result data from a first cache corresponding to a first processor, wherein the first memory is idle memory in an extended memory allocated by a CXL switch device to the first host system, and the extended memory is connected to the CXL switch device via a CXL link.

[0021] In an exemplary embodiment, a first transmission module includes: a first storage unit configured to store processing logic data in a second memory corresponding to a second host system, and to store first result data in a second cache corresponding to a second processor, so as to instruct the second host system to control the second processor to continue processing first remaining data according to the processing logic data, wherein the first remaining data is data remaining after the first processor processes the first data, and the second memory is idle memory in an extended memory allocated by a CXL switch device to the second host system, and the extended memory is connected to the CXL switch device via a CXL link.

[0022] In an exemplary embodiment, the device also includes: a first cache module, which is configured to store the first target data in a second memory corresponding to the second host system, so as to instruct the second host system to control the second processor to continue processing the first remaining data according to the processing logic data and the first result data, and then cache the current processing result of the second processor on the first remaining data and the first result data into the second cache.

[0023] In an exemplary embodiment, the apparatus further includes: a first allocation module, configured to allocate the first memory to other host systems after obtaining the first target data based on the first fault instruction, wherein the other host systems are host systems in normal operating state other than the first host system among multiple host systems connected to the CXL switch device, and the other host systems include a second host system; and a second allocation module, configured to allocate the first processor to the other host systems.

[0024] In an exemplary embodiment, the apparatus further includes: a second receiving module configured to receive a fault recovery instruction sent by a programmable logic device in a controller after obtaining the first target data based on the first fault instruction, wherein the fault recovery instruction is configured to indicate that the fault of the first host system has been repaired and is currently in a normal working state; a first responding module configured to allocate other processors to the first host system in response to the fault recovery instruction, wherein the other processors are idle processors among a plurality of processors connected to the CXL switch device, and the other processors correspond to other caches; and a third allocating module configured to allocate other memory to the first host system, wherein the other memory is idle memory among extended memory connected to the CXL switch device.

[0025] In an exemplary embodiment, the device also includes: a second acquisition module, which is configured to acquire second target data from the second host system after allocating other memory to the first host system, when the second host system is currently in a state of processing the first data, wherein the second target data includes processing logic data, second result data of the second processor continuing to process the first data, and the first result data; a second transmission module, which is configured to transmit the second target data to the first host system to instruct the first host system to control other processors to continue processing the first data according to the second target data.

[0026] In an exemplary embodiment, the second transmission module includes: a second storage unit, which is configured to store the logical data in other memories, and store the second result data and the first result data in other caches, so as to instruct the first host system to control other processors to continue processing the second remaining data according to the processing logical data, wherein the second remaining data is the data remaining after the second processor continues to process the first data.

[0027] According to a fifth aspect of the embodiments of the present application, a computer non-volatile readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0028] According to the sixth aspect of the embodiments of the present application, an electronic device is also provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

[0029] With this application, when a failure occurs in the first host system, the controller sends a first fault command to the CXL switch. The CXL switch then transfers the first data processed by the first host system to the second host system, which then continues to process the first data. This means that the first data is not interrupted by the failure of the first host system, but is instead processed by the second host system through the CXL switch. This ensures the continuity of data processing. This solves the problem of data processing continuity in related technologies, ensuring the continuity of data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a hardware structure block diagram of a mobile terminal according to a data processing method according to an embodiment of the present application;

[0031] FIG2 is a flow chart of a data processing method according to an embodiment of the present application;

[0032] FIG3 is a schematic diagram of implementing memory capacity expansion in a cluster server according to an embodiment of the present application;

[0033] FIG4 is a schematic diagram showing the connections of various devices according to an embodiment of the present application;

[0034] FIG5 is a flow chart illustrating a breakpoint-resume calculation function according to an embodiment of the present application;

[0035] FIG6 is a structural block diagram of a data processing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0038] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, FIG1 is a hardware structure block diagram of a mobile terminal of a data processing method in an embodiment of the present application. As shown in FIG1 , the mobile terminal may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU (Microcontroller Unit) or a programmable logic device FPGA (Field Programmable Gate Array)) and a memory 104 configured to store data, wherein the mobile terminal also includes a transmission device 106 and an input / output device 108 configured to have a communication function. It will be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0039] The memory 104 is configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the data processing method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 includes a memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0040] The transmission device 106 is configured to receive or transmit data via a network. Examples of such networks may include wireless networks provided by the mobile terminal's communications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module configured to communicate with the Internet wirelessly.

[0041] In this embodiment, a data processing method is provided, which is applied to a CXL (Compute Express Link) switch device. FIG2 is a flow chart of the data processing method according to the embodiment of the present application. As shown in FIG2 , the flow chart includes the following steps:

[0042] Step S202: receiving a first fault instruction sent by the controller, wherein the first fault instruction is used to indicate that a first host system has a fault, the first host system is configured to control a first processor to process first data, the first processor is an accelerator assigned to the first host system by a CXL switch device, and the CXL switch device is a device that supports the open interconnection standard CXL protocol;

[0043] Step S204: acquiring first target data based on the first fault instruction, wherein the first target data includes processing logic data of the first processor processing the first data and first result data of the first processor processing the first data;

[0044] Step S206 : The first target data is transmitted to the second host system, instructing the second host system to control the second processor to continue processing the first data according to the first target data. The second host system is a host system in a normal operating state among the multiple host systems connected to the CXL switch device, and the second processor is a processor assigned to the second host system by the CXL switch device.

[0045] Through the above steps, when a failure occurs in the first host system, the controller sends a first fault command to the CXL switch. The CXL switch then transfers the first data processed by the first host system to the second host system, which then continues to process the first data. This means that the first data is not interrupted by the failure of the first host system, but is instead processed by the second host system through the CXL switch. This ensures the continuity of data processing. This solves the problem of data processing continuity in related technologies, ensuring the continuity of data processing.

[0046] Optionally, the CXL switching device includes, but is not limited to, a device having interface switching and resource allocation functions, such as a CXL switch. The first memory and the second memory are both memories in an extended memory connected to the CXL switch. The first processor and the second processor are also processors mounted in the CXL switch.

[0047] Optionally, the first fault instruction includes system information of the first host system, such as the name and identifier of the first host system. The processor and memory corresponding to the first host system can be allocated by the CXL switch device, and are not limited by its own memory, allowing for efficient memory expansion.

[0048] Optionally, the processing logic data for the first data includes steps for processing the first data, for example, performing processing on the first data in the order of steps S1, S2, S3, etc. The first processing result includes a partial result of processing the first data, for example, the processing results of steps S1 and S2. By transferring the processing logic data for the first data to the second host system, the second processor corresponding to the second host system can determine which step to continue processing the first data. Transferring the first result data to the second host system facilitates the second host system to obtain the complete processing result.

[0049] Optionally, multiple host systems are connected to the CXL switching device, all of which are connected through CXL links. Required resources (e.g., memory and processors) are allocated to each host system. This allows for memory expansion and allocation of processing resources for cluster servers. For example, as shown in FIG3 , this is a schematic diagram of implementing memory capacity expansion in a cluster server. The CPU itself retains memory, and capacity expansion is achieved through a persistent device. This ensures that when a host system goes down, the computing cache data of the host system can be fully preserved, and that computing services are not lost, and computing services can continue after the node is restored. It should be noted that the CXL switching device prioritizes allocating idle resources to the host system. Fixed resources can also be allocated, for example, allocating the first memory, the second memory, and the first processor to the first host system, and the third memory, the fourth memory, and the second processor to the second host system. The first processor and the second processor include, but are not limited to, accelerators.

[0050] In an exemplary embodiment, receiving a first fault instruction sent by a controller includes: receiving a first fault instruction sent by a target processor in the controller; wherein the target processor is connected to a baseboard management controller, the baseboard management controller is connected to multiple host systems, and is configured to monitor the working status of the multiple host systems, and when a faulty host system is included in the multiple host systems, the faulty working status of the faulty host system is sent to the target processor, and the target processor is configured to generate a fault instruction based on the faulty working status, and the fault instruction includes system information of the corresponding faulty host system.

[0051] Alternatively, the target processor may be a device having a data processing function, such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an m (Mobile) CPU, etc. The baseboard management controller may be a device having a device monitoring function, such as a BMC (Baseboard Management Controller). The BMC may use two management signals (mCpu_heartError, SMI_GPIO) to simultaneously monitor the operating status of multiple host systems. The BMC communicates with the mCPU via an LPC (Low Pin Count Bus) / IIC (Inter-Integrated Circuit) to transmit a first fault instruction. The BMC monitors the operating status of multiple host systems. To prevent a single link from being interfered with and causing a misjudgment, the BMC waits for the two-way monitoring feedback signal of the first host system. Only when all three monitoring feedback signals (mCpu_heartError, SMI_GPIO) sound an alarm will the BMC determine that the host system is in a fault state.

[0052] This embodiment monitors the host system through the baseboard management controller, and can promptly determine whether the host system has a fault, so that data processing can be switched in a timely manner, thereby ensuring uninterrupted data processing.

[0053] In an exemplary embodiment, obtaining first target data based on a first fault instruction includes: in response to the first fault instruction, obtaining processing logic data from a first memory corresponding to the first host system, and obtaining first result data from a first cache corresponding to the first processor, wherein the first memory is idle memory in an extended memory allocated to the first host system by a CXL switch device, and the extended memory is connected to the CXL switch device via a CXL link.

[0054] Optionally, after receiving the first fault instruction, the CXL switch first extracts fault information to determine that the fault occurred in the first host system. It then reads processing logic data from the first memory corresponding to the first host system and first result data from the first cache. Both data are then transferred to the idle second host system for further processing. The first memory and first processor are allocated by the CXL switch based on the resource requirements of the first host system. By transferring data in a timely manner, this embodiment ensures that cached data is fully preserved, ensures that computing operations are not lost, and allows for continued data processing in a timely manner.

[0055] In an exemplary embodiment, first target data is transmitted to a second host system to instruct the second host system to control the second processor to continue processing the first data according to the first target data, including: storing processing logic data in a second memory corresponding to the second host system, and storing first result data in a second cache corresponding to the second processor, to instruct the second host system to control the second processor to continue processing the first remaining data according to the processing logic data, wherein the first remaining data is data remaining after the first processor processes the first data, and the second memory is an idle memory in the extended memory allocated by the CXL switch device to the second host system, and the extended memory is connected to the CXL switch device via a CXL link.

[0056] Optionally, in this embodiment, the secondary memory and second processor are allocated by the CXL switch device based on the resource requirements of the second host system. These allocations can be made before the first target data is transferred, or they can be temporarily allocated when the data transfer is determined. The second host system can be a system with the same functionality as the first host system, or it can be a backup host system for the first host system. By promptly transferring data to the second host system for continued processing, this embodiment ensures that computing services are not lost and that data can continue to be processed in a timely manner.

[0057] In an exemplary embodiment, after storing the first target data in a second memory corresponding to the second host system to instruct the second host system to control the second processor to continue processing the first remaining data according to the processing logic data and the first result data, the above method also includes: caching the current processing result of the second processor on the first remaining data and the first result data into the second cache.

[0058] Optionally, in this embodiment, the second processor needs to cache the processed data promptly and merge it with the first result data to ensure the integrity of the processed results. After the first data is processed, the cached, complete data can be stored in the second memory for long-term preservation. Alternatively, the data can be transferred to the second host system's own memory for storage, or the CXL switch can reallocate memory for storage.

[0059] In an exemplary embodiment, after obtaining the first target data based on the first fault instruction, the method further includes: allocating the first memory to another host system, wherein the other host system is a host system in a normal operating state other than the first host system among multiple host systems connected to the CXL switch device, and the other host system includes a second host system; and allocating the first processor to the other host system.

[0060] Optionally, in this embodiment, after a failure in the first host system and after the data processing logic and first result data are transferred, the first memory and the first processor are both idle. The CXL switch device then releases its association with the first host system. The first memory and the first processor are then allocated to another host system requiring resources, such as a second or third host system. This not only fully utilizes resources but also alleviates data processing pressure on other host systems.

[0061] In an exemplary embodiment, after obtaining the first target data based on the first fault instruction, the method further includes: receiving a fault recovery instruction sent by a programmable logic device in the controller, wherein the fault recovery instruction is used to indicate that the fault of the first host system has been repaired and the system is currently in a normal working state; in response to the fault recovery instruction, allocating other processors to the first host system, wherein the other processors are idle processors among multiple processors connected to the CXL switch device, and the other processors correspond to other caches; and allocating other memory to the first host system, wherein the other memory is idle memory among extended memory connected to the CXL switch device.

[0062] Optionally, programmable logic devices include, but are not limited to, devices with a reset function, such as a CPLD (Complex Programmable Logic Device). The BMC communicates with the mCPU and CPLD via LPC / IIC to transmit a first fault instruction. The mCPU and CPLD perform status assignment and reset actions on the CXL switching device via UART. Furthermore, after completing control of the first target data cache, the BMC and CPLD restart the faulty first host system. When the faulty first host system successfully restarts, the upper-layer user device is notified through the BMC to complete the restart. During the restart of this first host system, all devices are mounted on the second host system and operate normally, without affecting the progress of computing services.

[0063] Optionally, after receiving the fault recovery instruction, the CXL switch device recovers resources for the first host system and, if the first processor and the first memory are idle, mounts the first processor and the first memory to the first host system. If the first processor and the first memory are already mounted to another host system, remounts the other processor and memory to the first host system.

[0064] Optionally, after allocating the additional memory to the first host system, the method further includes: when the second host system is currently processing the first data, obtaining second target data from the second host system, wherein the second target data includes processing logic data, second result data resulting from the second processor's continued processing of the first data, and the first result data; and transmitting the second target data to the first host system to instruct the first host system to control the other processors to continue processing the first data according to the second target data. In this embodiment, if the second host system is currently processing the first data, this indicates that processing of the first data is not complete, and processing can be switched to the first host system. The switching process is the same as the process for switching to the second host system and will not be further described here. It should be noted that if the second host system is a backup system for the first host system, the first host system serves as the primary processing system and primarily assumes data processing functions after the fault is rectified. After the first host system recovers and the second host system has completed processing the first data, the CXL switch device also needs to transfer the complete processing results to the first host system so that the first host system can analyze the processing results.

[0065] Optionally, transmitting the second target data to the first host system to instruct the first host system to control other processors to continue processing the first data according to the second target data includes: storing the logical data in another memory, and storing the second result data and the first result data in another cache, to instruct the first host system to control other processors to continue processing the second remaining data according to the processing logic data, wherein the second remaining data is the data remaining after the second processor continues to process the first data. In this embodiment, while the first host system continues to process the second remaining data, the CXL switch device can release resources of the second host system and promptly transfer the data to ensure timely storage of the data.

[0066] In an optional embodiment, where the CXL switching device is a CXL Switch, the first host system is Host0, the second host system is Host1, and the controller includes a BMC, an mCPU, and a CPLD, the CXL Switch and CXL Expander implement memory expansion and management via the CXL protocol. The BMC also monitors the operating status of each host. When a host fails, the BMC sends switching information to the mCPU and CPLD, which then issue a computing port switching instruction to the CXL Switch, simultaneously saving and writing the current data cache. After switching to a healthy host, computing services continue based on the cached data in memory. When the failed host recovers, the current computing services are switched, thus implementing service breakpoint resumption.

[0067] Optionally, under normal operating conditions, the host is interconnected with the CXL Switch and CXL Expander via CXL links. The accelerator, responsible for data processing and high-performance computing, is also connected to the CXL Switch via CXL links. Each host has one heartbeat monitoring channel (mCpu_heartError) and one abnormal interrupt alarm SMI_GPIO connected to the BMC. The BMC monitors the operating status of each host in real time via the heartbeat monitoring link and the interrupt alarm link. If the BMC detects a heartbeat anomaly on a host, it communicates with the mCPU and CPLD via the SPI (Serial Peripheral Interface) / IIC link, saves the current computing data through the CXL Switch, and then configures the CXL Switch to mount the memory to the normally operating host to continue computing. The failed host is restarted via the control link. Once the failed host successfully restarts and resumes normal operation, the mCPU and CPLD restore the CXL Switch to its initial configuration and return computing services to the original host. This not only expands the cluster server's memory capacity but also enables breakpoint-resume computing through cache coherence. This ensures that if a node in the system fails, the node's computing cache data is fully preserved, ensuring computing services are not lost and can resume after the node recovers.

[0068] Optionally, as shown in FIG4 , this embodiment includes the following steps:

[0069] In S1, the host interconnects with the CXL switch, CXL expander, and accelerator via CXL signals. The CXL expander expands memory capacity via the CXL link, and the accelerator is attached to the host via the CXL link to perform accelerated computing. The monitoring and management switching solution is centered around the BMC, mCPU, and CPLD. The BMC uses two management signals (mCpu_heartError and SMI_GPIO) to simultaneously monitor the operating status of each host. The BMC communicates with the mCPU and CPLD via LPC / IIC to transmit switching instructions. The mCPU and CPLD assign status and reset actions to the CXL switch via UART.

[0070] In step S2, the BMC monitors the working status of each host. To prevent misjudgment due to interference on a single link, the BMC waits for two monitoring feedback signals from the host. Only when all three monitoring feedback signals (mCpu_heartError and SMI_GPIO) generate alarms does the BMC determine that the host is in a faulty state.

[0071] S3, the extended memory (DDR) 0, DDR1, DDR2, and DDR3) is mounted to the CXL Switch via the CXL Expander. The CXL Switch allocates address space to the extended memory and mounts it to Host0 and Host1, respectively. The accelerator communicates with Host0 via the CXL Switch, performs related computing tasks, and caches the computed data in DDR4 and DDR5. When the BMC notifies the mCPU of a fault status via LPC / IIC signals, the mCPU communicates with the CXL Switch via the UART. Assuming Host0 fails, breakpoint-resume computing is performed according to the steps shown in Figure 5. The CXL Switch first accesses and saves the data in DDR0 and DDR1 mounted on Host0. It then verifies and saves the data in the accelerator, which interacts with Host0 and performs computing tasks, to ensure that the data in DDR4 and DDR5 is up to date. This latest data is named Date_old.

[0072] S4: All old data (Date_old) is cached in Host1's memory space through the CXL Switch. Simultaneously, the mCPU notifies the CXL Switch to change its internal register configuration and reset the Accelerator.

[0073] In step S5, the Accelerator caches the old data in Host 1 into its own memory and continues to execute the computing business from the last breakpoint. The new data generated by the continued computing business is defined as Date_new.

[0074] In step S6, the BMC and CPLD restart Host0 after caching the old data. Once Host0 successfully restarts, the BMC notifies the upper-layer user device of the restart completion. During this Host0 restart, all devices are mounted on Host1 and function normally, without affecting computing services.

[0075] In step S7, after Host0 successfully restarts, steps S3 through S5 are repeated, caching the latest calculation results in DDR0, DDR1, DDR4, and DDR5. The accelerator then continues the calculation process based on the latest results. Throughout this process, while Host0 was down, the calculation data at the breakpoint was saved on Host1, and calculations continued. After Host0 restarts, the new calculation data is written back to Host1, and calculations resume from the new breakpoint, thus implementing breakpoint-resume calculations.

[0076] The embodiment of the present application can expand the memory capacity of the cluster server and complete the breakpoint resumption function by realizing cache consistency. It ensures that when a node in the system goes down, the calculation cache data of the node can be completely saved, and the calculation business is not lost, and the calculation business continues after the node is restored. It can effectively solve the problem that the memory capacity of the cluster server cannot be effectively expanded and there is cache consistency. When a node in the system goes down, the calculation data of the node cannot be completely saved and the breakpoint resumption function cannot be realized, which will bring heavy economic losses.

[0077] This embodiment provides a switch board, a CXL switch device, and multiple device interfaces. The multiple device interfaces are configured to allow a controller, multiple host systems, expansion memory, and multiple processors to access the CXL switch device under the control of the CXL switch device. The CXL switch device is configured to execute the aforementioned data processing method.

[0078] Optionally, the CXL switching device includes, but is not limited to, a device having interface switching and resource allocation functions, such as a CXL switch. The extended memory is mounted on the CXL switch and includes multiple memories, such as a first memory and a second memory. Multiple processors are also mounted on the CXL switch, such as a first processor and a second processor.

[0079] Optionally, as shown in FIG4 , the multiple device interfaces include S0 - S9 , which can be connected to different devices, for example, connected to the mCPU via S0 .

[0080] With this switch board, when a fault occurs in the first host system, the controller sends a first fault command to the CXL switch. The CXL switch then transfers the first data processed by the first host system to the second host system, which then continues to process the first data. This means that the first data is not interrupted by the first host system's fault. Instead, it is processed by the second host system through the CXL switch, ensuring the continuity of data processing. This solves the problem of data processing continuity in related technologies, ensuring data processing continuity.

[0081] This embodiment provides a data processing system, including: a switch board, a controller, multiple host systems, extended memory, and multiple processors. A CXL switch device and multiple device interfaces are deployed on the switch board. The multiple device interfaces are configured to allow the controller, multiple host systems, extended memory, and multiple processors to access the CXL switch device under the control of the CXL switch device. The CXL switch device is configured to execute a data processing method. The controller is configured to send a first fault instruction to the switch device, wherein the first fault instruction is used to indicate that a first host system among the multiple host systems has failed. The first host system is configured to control a first processor to process first data. The first processor is an accelerator assigned by the CXL switch device to the first host system from among the multiple processors.

[0082] With the above data processing system, when a failure occurs in the first host system, the controller sends a first fault command to the CXL switch. The CXL switch then transfers the first data processed by the first host system to the second host system, which then continues to process the first data. This means that the first data is not interrupted by the failure of the first host system, but is instead processed by the second host system through the CXL switch. This ensures the continuity of data processing. This solves the problem of data processing continuity in related technologies, ensuring the continuity of data processing.

[0083] Optionally, the CXL switching device includes, but is not limited to, a device having interface switching and resource allocation functions, such as a CXL switch. The first memory and the second memory are both memories in an extended memory connected to the CXL switch. The first processor and the second processor are also processors mounted in the CXL switch.

[0084] Optionally, the first fault instruction includes system information of the first host system, such as the name and identifier of the first host system. The processor and memory corresponding to the first host system can be allocated by the CXL switch device, and are not limited by its own memory, allowing for effective memory expansion.

[0085] Optionally, the processing logic data for the first data includes steps for processing the first data, for example, performing processing on the first data in the order of steps S1, S2, S3, etc. The first processing result includes a partial result of processing the first data, for example, the processing results of steps S1 and S2. By transferring the processing logic data for the first data to the second host system, the second processor corresponding to the second host system can determine which step to continue processing the first data. Transferring the first result data to the second host system facilitates the second host system to obtain the complete processing result.

[0086] Optionally, multiple host systems are connected to the CXL switching device, all of which are connected through CXL links. Required resources (e.g., memory and processors) are allocated to each host system. This allows for memory expansion and allocation of processing resources for cluster servers. For example, as shown in FIG3 , this is a schematic diagram of implementing memory capacity expansion in a cluster server. The CPU itself retains memory, and capacity expansion is achieved through a persistent device. This ensures that when a host system goes down, the computing cache data of the host system can be fully preserved, and that computing services are not lost, and computing services can continue after the node is restored. It should be noted that the CXL switching device prioritizes allocating idle resources to the host system. Fixed resources can also be allocated, for example, allocating the first memory, the second memory, and the first processor to the first host system, and the third memory, the fourth memory, and the second processor to the second host system. The first processor and the second processor include, but are not limited to, accelerators.

[0087] In an exemplary embodiment, the controller includes a target processor and a baseboard management controller, wherein the baseboard management controller is connected to multiple host systems and is configured to monitor the working status of the multiple host systems, and when a faulty host system is included in the multiple host systems, the baseboard management controller sends the faulty working status of the faulty host system to the target processor; the target processor is configured to generate a fault instruction based on the faulty working status, and the fault instruction includes system information of the corresponding faulty host system.

[0088] Optionally, the target processor may be a device with data processing capabilities, such as a CPU, GPU, mCPU, etc. The baseboard management controller may be a device with device monitoring capabilities, such as a BMC. The BMC can use two management signals (mCpu_heartError, SMI_GPIO) to simultaneously monitor the working status of multiple host systems. The BMC communicates with the mCPU via LPC / IIC and transmits a first fault instruction. The BMC monitors the working status of multiple host systems. To prevent misjudgment caused by interference with a single link, the BMC will wait for the two-way monitoring feedback signal of the first host system. Only when all three monitoring feedback signals (mCpu_heartError, SMI_GPIO) sound an alarm will the BMC determine that the host system is in a fault state.

[0089] This embodiment monitors the host system through the baseboard management controller, and can promptly determine whether the host system has a fault, so that data processing can be switched in a timely manner to ensure uninterrupted data processing.

[0090] In an exemplary embodiment, the baseboard management controller is further configured to monitor the first host system through multiple signals, and when multiple signals indicate that the first host system has failed, the fault working status of the first host system is sent to the target processor; the target processor is configured to generate a first fault instruction based on the fault working status of the first host system.

[0091] In an exemplary embodiment, the baseboard management controller is also configured to restart the first host system and, when the first host system is restarted, send a fault recovery instruction to the target processor, wherein the fault recovery instruction is used to indicate that the fault of the first host system has been repaired and is currently in normal working condition.

[0092] In an exemplary embodiment, the controller further includes a programmable logic device, wherein the programmable logic device is connected to the target processor and configured to receive a fault recovery instruction sent by the target processor and send the fault recovery instruction to the CXL switch device to instruct the CXL switch device to switch the second host system to the first host system to continue processing the first data.

[0093] Optionally, the programmable logic device includes but is not limited to a device with a reset function, such as a CPLD. The BMC communicates with the mCPU and CPLD through LPC / IIC to transmit the first fault instruction. The mCPU and CPLD perform status assignment and reset actions on the CXL switching device through UART (Universal Synchronous / Asynchronous Receiver / Tran). In addition, after completing the control of the first target data cache, the BMC and CPLD restart the faulty first host system. When the faulty first host system is successfully restarted, the upper-layer user device will be notified through the BMC to complete the restart. During the restart of this first host system, all devices are mounted on the second host system and operate normally, and will not affect the progress of computing services.

[0094] In an exemplary embodiment, the CXL switch device is further configured to allocate memory and processors to multiple host systems, wherein the allocated memory is idle memory in the extended memory, and the allocated processor is an idle processor among the multiple processors.

[0095] In an exemplary embodiment, expanded memory, multiple processors, and multiple host systems are all enabled to interface with multiple devices via CXL links under the control of a CXL switch device.

[0096] In an exemplary embodiment, expanded memory, multiple processors, and multiple host systems are all enabled to interface with multiple devices via CXL links under the control of a CXL switch device.

[0097] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a non-volatile readable storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0098] In this embodiment, a data processing method and data device is also provided. The device is configured to implement the above-mentioned embodiments and optional implementations. Details already described are not repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0099] FIG6 is a structural block diagram of a data processing device according to an embodiment of the present application. As shown in FIG6 , the device includes:

[0100] a first receiving module 62 configured to receive a first fault instruction sent by the controller, wherein the first fault instruction is used to indicate that a fault has occurred in a first host system, the first host system being configured to control a first processor to process first data, the first processor being an accelerator assigned to the first host system by the CXL switch device, the CXL switch device being a device supporting the open interconnection standard CXL protocol;

[0101] A first acquisition module 64 is configured to acquire first target data based on the first fault instruction, wherein the first target data includes processing logic data of the first processor processing the first data and first result data of the first processor processing the first data;

[0102] The first transmission module 66 is configured to transmit the first target data to a second host system, so as to instruct the second host system to control the second processor to continue processing the first data according to the first target data. The second host system is a host system in a normal operating state among the multiple host systems connected to the CXL switch device, and the second processor is a processor assigned to the second host system by the CXL switch device.

[0103] In an exemplary embodiment, the above-mentioned first receiving module includes: a first receiving unit, which is configured to receive the above-mentioned first fault instruction sent by the target processor in the above-mentioned controller; wherein the above-mentioned target processor is connected to the baseboard management controller, and the above-mentioned baseboard management controller is connected to the multiple above-mentioned host systems, and is configured to monitor the working status of the multiple above-mentioned host systems, and when a faulty host system is included in the multiple above-mentioned host systems, the faulty working status of the faulty host system is sent to the above-mentioned target processor, and the above-mentioned target processor is configured to generate a fault instruction based on the above-mentioned faulty working status, and the above-mentioned fault instruction includes system information of the corresponding faulty host system.

[0104] In an exemplary embodiment, the first acquisition module includes a first response unit configured to, in response to the first fault instruction, acquire the processing logic data from a first memory corresponding to the first host system, and acquire the first result data from a first cache corresponding to the first processor, wherein the first memory is idle memory in an extended memory allocated by the CXL switch device to the first host system, and the extended memory is connected to the CXL switch device via a CXL link.

[0105] In an exemplary embodiment, the first transmission module includes a first storage unit configured to store the processing logic data in a second memory corresponding to the second host system, and to store the first result data in a second cache corresponding to the second processor, so as to instruct the second host system to control the second processor to continue processing the first remaining data according to the processing logic data, wherein the first remaining data is data remaining after the first processor processes the first data, and the second memory is an idle memory in the extended memory allocated by the CXL switch device to the second host system, and the extended memory is connected to the CXL switch device via a CXL link.

[0106] In an exemplary embodiment, the above-mentioned device also includes: a first cache module, which is configured to store the above-mentioned first target data in the second memory corresponding to the above-mentioned second host system, so as to instruct the above-mentioned second host system to control the above-mentioned second processor to continue processing the first remaining data according to the above-mentioned processing logic data and the above-mentioned first result data, and then cache the current processing result of the above-mentioned second processor on the above-mentioned first remaining data and the above-mentioned first result data into the above-mentioned second cache.

[0107] In an exemplary embodiment, the apparatus further includes: a first allocation module, configured to allocate the first memory to other host systems after acquiring the first target data based on the first fault instruction, wherein the other host systems are host systems in normal operating state other than the first host system among multiple host systems connected to the CXL switch device, and the other host systems include the second host system; and a second allocation module, configured to allocate the first processor to the other host systems.

[0108] In an exemplary embodiment, the apparatus further includes: a second receiving module configured to receive a fault recovery instruction sent by a programmable logic device in the controller after obtaining the first target data based on the first fault instruction, wherein the fault recovery instruction is used to indicate that the fault of the first host system has been repaired and the system is currently in a normal working state; a first responding module configured to allocate other processors to the first host system in response to the fault recovery instruction, wherein the other processors are idle processors among the multiple processors connected to the CXL switch device, and the other processors correspond to other caches; and a third allocating module configured to allocate other memory to the first host system, wherein the other memory is idle memory among the extended memory connected to the CXL switch device.

[0109] In an exemplary embodiment, the above-mentioned device also includes: a second acquisition module, which is configured to allocate other memory to the above-mentioned first host system, and when the above-mentioned second host system is currently in a state of processing the above-mentioned first data, obtain second target data from the above-mentioned second host system, wherein the above-mentioned second target data includes the above-mentioned processing logic data, second result data of the above-mentioned second processor continuing to process the above-mentioned first data, and the above-mentioned first result data; a second transmission module, which is configured to transmit the above-mentioned second target data to the above-mentioned first host system to instruct the above-mentioned first host system to control the above-mentioned other processors to continue to process the above-mentioned first data according to the above-mentioned second target data.

[0110] In an exemplary embodiment, the second transmission module includes: a second storage unit, which is configured to store the above-mentioned logical data in the above-mentioned other memory, and store the above-mentioned second result data and the above-mentioned first result data in the above-mentioned other cache, so as to instruct the above-mentioned first host system to control the above-mentioned other processor to continue processing the second remaining data according to the above-mentioned processing logic data, wherein the above-mentioned second remaining data is the data remaining after the above-mentioned second processor continues to process the above-mentioned first data.

[0111] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0112] An embodiment of the present application further provides a computer non-volatile readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0113] In an exemplary embodiment, the above-mentioned computer non-volatile readable storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0114] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0115] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0116] For optional examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementations, and this embodiment will not be described in detail here.

[0117] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0118] The above are merely optional embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may be subject to various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A data processing method, applied to a CXL switching device, characterized in that: include: receiving a first fault instruction sent by a controller, wherein the first fault instruction is used to indicate that a first host system fails, the first host system is configured to control a first processor to process first data, the first processor is an accelerator assigned to the first host system by the CXL switch device, and the CXL switch device is a device supporting an open interconnection standard CXL protocol; Acquire first target data based on the first fault instruction, wherein the first target data includes processing logic data of the first processor processing the first data and first result data of the first processor processing the first data; The first target data is transmitted to a second host system to instruct the second host system to control a second processor to continue processing the first data according to the first target data, wherein the second host system is a host system in a normal operating state among a plurality of host systems connected to the CXL switch device, and the second processor is a processor allocated to the second host system by the CXL switch device.

2. The method according to claim 1, characterized in that Receiving a first fault instruction sent by the controller includes: receiving the first fault instruction sent by the target processor in the controller; Wherein, the target processor is connected to a baseboard management controller, and the baseboard management controller is connected to a plurality of the host systems and is configured to monitor the working status of the plurality of the host systems, and when a faulty host system is included in the plurality of the host systems, the faulty working status of the faulty host system is sent to the target processor, and the target processor is configured to generate a fault instruction based on the faulty working status, and the fault instruction includes system information of the corresponding faulty host system.

3. The method according to claim 1, characterized in that Acquiring first target data based on the first fault instruction includes: In response to the first fault instruction, the processing logic data is obtained from a first memory corresponding to the first host system, and the first result data is obtained from a first cache corresponding to the first processor, wherein the first memory is an idle memory in an extended memory allocated by the CXL switch device to the first host system, and the extended memory is connected to the CXL switch device via a CXL link.

4. The method according to claim 1, characterized in that: Transmitting the first target data to a second host system to instruct the second host system to control the second processor to continue processing the first data according to the first target data, comprising: The processing logic data is stored in a second memory corresponding to the second host system, and the first result data is stored in a second cache corresponding to the second processor, so as to instruct the second host system to control the second processor to continue processing the first remaining data according to the processing logic data, wherein the first remaining data is data remaining after the first processor processes the first data, and the second memory is an idle memory in the extended memory allocated by the CXL switch device to the second host system, and the extended memory is connected to the CXL switch device via a CXL link.

5. The method according to claim 4, characterized in that After storing the first target data in a second memory corresponding to the second host system to instruct the second host system to control the second processor to continue processing the first remaining data according to the processing logic data and the first result data, the method further includes: The current processing result of the second processor processing the first remaining data and the first result data are both cached in the second cache.

6. The method according to claim 1, characterized in that After acquiring the first target data based on the first fault instruction, the method further includes: Allocate the first memory corresponding to the first host system to other host systems, wherein the other host systems are host systems in a normal operating state other than the first host system among multiple host systems connected to the CXL switch device, and the other host systems include the second host system; The first processor is assigned to the other host system.

7. The method according to claim 1, characterized in that After acquiring the first target data based on the first fault instruction, the method further includes: receiving a fault recovery instruction sent by the programmable logic device in the controller, wherein the fault recovery instruction is used to indicate that the fault of the first host system has been repaired and is currently in a normal working state; In response to the fault recovery instruction, allocating other processors to the first host system, wherein the other processors are processors in an idle state among a plurality of processors connected to the CXL switch device, and the other processors correspond to other caches; Allocate other memory to the first host system, wherein the other memory is an idle memory in the extended memory connected to the CXL switch device.

8. The method according to claim 7, characterized in that After allocating other memory to the first host system, the method further includes: When the second host system is currently in a state of processing the first data, obtaining second target data from the second host system, wherein the second target data includes the processing logic data, second result data of the second processor continuing to process the first data, and the first result data; The second target data is transmitted to the first host system to instruct the first host system to control the other processors to continue processing the first data according to the second target data.

9. The method according to claim 8, characterized in that The method of transmitting the second target data to the first host system to instruct the first host system to control the other processors to continue processing the first data according to the second target data includes: The logic data is stored in the other memory, and the second result data and the first result data are stored in the other cache, so as to instruct the first host system to control the other processor to continue processing the second remaining data according to the processing logic data, wherein the second remaining data is the data remaining after the second processor continues to process the first data.

10. A switching board, characterized in that: include: CXL switching equipment and multiple equipment interfaces, among which, A plurality of the device interfaces are configured to allow a controller, a plurality of host systems, an extended memory, and a plurality of processors to access the CXL switch device under the control of the CXL switch device; The CXL switching device is configured to execute the data processing method according to any one of claims 1 to 9.

11. A data processing system, characterized in that: include: Switch board, controller, multiple host systems, extended memory, multiple processors, among which, A CXL switching device and a plurality of device interfaces are deployed on the switching board, wherein the plurality of device interfaces are configured to allow the controller, the plurality of host systems, the extended memory, and the plurality of processors to access the CXL switching device under the control of the CXL switching device, and the CXL switching device is configured to execute the data processing method according to any one of claims 1 to 9; The controller is configured to send a first fault instruction to the switching device, wherein the first fault instruction is used to indicate that a first host system among the plurality of host systems fails, the first host system is configured to control a first processor to process first data, and the first processor is an accelerator allocated by the CXL switching device to the first host system from the plurality of processors.

12. The system according to claim 11, characterized in that The controller includes a target processor and a baseboard management controller, wherein: The baseboard management controller is connected to the plurality of host systems, and is configured to monitor the working status of the plurality of host systems, and when a faulty host system is included in the plurality of host systems, send the faulty working status of the faulty host system to the target processor; The target processor is configured to generate a fault instruction based on the fault working state, wherein the fault instruction includes system information of a corresponding host system where the fault occurs.

13. The system according to claim 12, characterized in that The baseboard management controller is further configured to monitor the first host system through multiple signals, and send a faulty working state of the first host system to the target processor when multiple signals indicate that the first host system fails; The target processor is configured to generate the first fault instruction based on the faulty working state of the first host system.

14. The system according to claim 13, characterized in that The baseboard management controller is also configured to restart the first host system, and send a fault recovery instruction to the target processor when the first host system is restarted, wherein the fault recovery instruction is used to indicate that the fault of the first host system has been repaired and is currently in normal working state.

15. The system according to claim 14, characterized in that The controller also includes a programmable logic device, wherein: The programmable logic device is connected to the target processor and is configured to receive the fault recovery instruction sent by the target processor and send the fault recovery instruction to the CXL switch device to instruct the CXL switch device to switch the second host system to the first host system to continue processing the first data.

16. The system according to claim 11, characterized in that The CXL switch device is further configured to allocate memory and processors to the plurality of host systems, wherein the allocated memory is memory in an idle state in the extended memory, and the allocated processor is a processor in an idle state among the plurality of processors.

17. The system according to claim 11, characterized in that The extended memory, the plurality of processors, and the plurality of host systems are all allowed to be connected to the plurality of device interfaces via CXL links under the control of the CXL switch device.

18. The system according to claim 11, characterized in that The extended memory, the plurality of processors, and the plurality of host systems are all allowed to be connected to the plurality of device interfaces via CXL links under the control of the CXL switch device.

19. A data processing device, characterized in that: include: A first receiving module is configured to receive a first fault instruction sent by a controller, wherein the first fault instruction is used to indicate that a first host system fails, the first host system is configured to control a first processor to process first data, the first processor is an accelerator assigned to the first host system by a CXL switching device, and the CXL switching device is a device supporting an open interconnection standard CXL protocol; a first acquisition module, configured to acquire first target data based on the first fault instruction, wherein the first target data includes processing logic data of the first processor processing the first data and first result data of the first processor processing the first data; The first transmission module is configured to transmit the first target data to a second host system to instruct the second host system to control the second processor to continue processing the first data according to the first target data, wherein the second host system is a host system in a normal operating state among multiple host systems connected to the CXL switch device, and the second processor is a processor assigned to the second host system by the CXL switch device.

20. A computer non-volatile readable storage medium, characterized in that: The computer non-volatile readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 9 when executed by a processor.

21. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 9 are implemented.

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