Display panel and manufacturing method therefor, and display apparatus

Abstract

A display panel and a manufacturing method therefor, and a display apparatus, wherein the display panel comprises an array substrate and a cathode layer. The display panel has a display area, and the display panel comprises an array substrate and a cathode layer, the cathode layer being arranged on the array substrate; and the cathode layer comprising a first sub-portion and a second sub-portion, which surrounds the first sub-portion, wherein the first sub-portion and the second sub-portion are both located in the display area, and the resistance per unit length of the first sub-portion is less than the resistance per unit length of the second sub-portion.

Description

Display panel, manufacturing method, and display device

[0001] This application claims priority to Chinese patent application No. 202311142466.0, filed on September 5, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) have been widely used in the display field due to their advantages such as self-luminescence, low driving voltage, high luminous efficiency, fast response speed and flexible display.

[0004] Summary of the Invention

[0005] An object of the embodiments of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device, for improving the brightness uniformity of the display panel.

[0006] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0007] In one aspect, a display panel is provided. The display panel includes an array substrate and a cathode layer. The display panel has a display area, and includes the array substrate and the cathode layer. The cathode layer is disposed on the array substrate. The cathode layer includes a first subsection and a second subsection surrounding the first subsection, wherein both the first subsection and the second subsection are located in the display area; wherein the resistance per unit length of the first subsection is lower than the resistance per unit length of the second subsection.

[0008] The resistance per unit length of the first sub-section is smaller than that of the second sub-section, which can reduce the voltage difference between the first sub-section and the second sub-section, thereby improving the brightness uniformity of the display panel.

[0009] In some embodiments, the thickness of the first subsection is greater than the thickness of the second subsection.

[0010] In some embodiments, the cathode layer includes a first conductive layer and a second conductive layer. The first conductive layer is provided on the array substrate, located in the display area. The first conductive layer includes the third sub-portion and a second sub-portion surrounding the third sub-portion. The second conductive layer is provided on a side of the first conductive layer away from the array substrate. The orthographic projection of the second conductive layer on the array substrate coincides with the orthographic projection of the third sub-portion on the array substrate. The second conductive layer and the third sub-portion form the first sub-portion.

[0011] In some embodiments, the display panel further includes a plurality of light-emitting devices. The plurality of light-emitting devices are disposed on the array substrate. In a direction perpendicular to and away from the array substrate, the light-emitting devices include a stacked light-emitting functional layer and a cathode, the cathode being located on the cathode layer, and an orthographic projection of the second conductive layer on the array substrate partially overlapping with the orthographic projections of the plurality of light-emitting functional layers on the array substrate.

[0012] In some embodiments, the thickness of the cathode layer gradually decreases from the center of the display area to the boundary of the display area.

[0013] In some embodiments, the material of the first subsection includes at least one of aluminum, iron, tin, magnesium, copper, silver, and gold, and / or the material of the second subsection includes at least one of aluminum, iron, tin, magnesium, copper, silver, and gold.

[0014] In some embodiments, the electrical conductivity of the first subsection is greater than the electrical conductivity of the second subsection.

[0015] In some embodiments, the material of the first subsection includes at least one of copper, silver, and gold, and the material of the second subsection includes at least one of aluminum, iron, tin, and magnesium.

[0016] In some embodiments, the conductivity of the cathode layer gradually decreases from the center of the display area to the boundary of the display area.

[0017] In some embodiments, the cathode layer comprises a host material and a dopant material. The host material has a greater electrical conductivity than the dopant material, and the ratio of the host material to the dopant material decreases from the center of the display area to the boundary of the display area. Alternatively, the host material has a lesser electrical conductivity than the dopant material, and the ratio of the host material to the dopant material increases from the center of the display area to the boundary of the display area.

[0018] In some embodiments, the thickness of the first subsection is greater than or equal to the thickness of the second subsection.

[0019] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments.

[0020] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here.

[0021] In yet another aspect, a method for manufacturing a display panel is provided. The display panel has a display area. The method includes providing an array substrate; the array substrate includes a first region and a second region surrounding the first region, wherein both the first region and the second region are located in the display area; forming a first subsection in the first region and a second subsection in the second region; the second subsection is connected to the first subsection to form a cathode layer; wherein the resistance per unit length of the first subsection is less than the resistance per unit length of the second subsection.

[0022] The method for preparing the display panel has the same structure and beneficial technical effects as the display panels provided in some of the above embodiments, and will not be described in detail here.

[0023] In some embodiments, forming the first sub-section in the first area and forming the second sub-section in the second area includes: forming a first conductive layer on the array substrate; the first conductive layer includes the third sub-section located in the first area, and the second sub-section located in the second area; forming a second conductive layer on the side of the first conductive layer away from the array substrate; the orthographic projection of the second conductive layer on the array substrate coincides with the orthographic projection of the third sub-section on the array substrate, and the second conductive layer and the third sub-section form the first sub-section.

[0024] In some embodiments, forming the first conductive layer on the array substrate includes: placing a first mask plate on one side of the array substrate; the first opening of the first mask plate is projected onto the array substrate, covering the first area and the second area; and forming the first conductive layer through the first opening.

[0025] In some embodiments, forming the second conductive layer on the side of the first conductive layer away from the array substrate includes: blocking the edge area of ​​the first opening of the first mask plate; placing the first mask plate that blocks the edge area on the side of the first conductive layer away from the array substrate; the orthographic projection of the first opening on the array substrate covers the first area and the second area, and the orthographic projection of the edge area on the array substrate covers the second area and exposes the first area; and forming the second conductive layer through the first opening.

[0026] In some embodiments, forming a second conductive layer on a side of the first conductive layer away from the array substrate includes: forming a first metal suppression layer on a side of the first conductive layer away from the array substrate; the orthographic projection of the first metal suppression layer on the array substrate covers the second area and exposes the first area; placing the first mask plate on a side of the first conductive layer away from the array substrate; the orthographic projection of the first opening on the array substrate covers the first area and the second area; forming a second conductive layer through the first opening and the first metal suppression layer; and removing the first metal suppression layer.

[0027] In some embodiments, forming a second conductive layer on a side of the first conductive layer away from the array substrate includes: forming a metal promotion layer on the first conductive layer; the orthographic projection of the metal promotion layer on the array substrate covers the first area and exposes the second area; placing the first mask plate on a side of the first conductive layer and the metal promotion layer away from the array substrate; the orthographic projection of the first opening on the array substrate covers the first area and the second area; forming a second conductive layer through the first opening and the metal promotion layer; the metal promotion layer is configured so that the orthographic projection of the second conductive layer on the array substrate is located in the first area and exposes the second area.

[0028] In some embodiments, forming a second conductive layer on a side of the first conductive layer away from the array substrate includes: placing a second mask plate on a side of the first conductive layer away from the array substrate; a second opening of the second mask plate is projected onto the array substrate, covering the first area and exposing the second area; and forming the second conductive layer through the second opening.

[0029] In some embodiments, forming the first sub-section in the first area includes: placing a third mask plate on one side of the array substrate; the third mask plate has a third opening area, and the orthographic projection of the third opening area on the array substrate covers the first area and exposes the second area; forming the first sub-section through the third opening area.

[0030] In some embodiments, forming the first sub-section in the first area includes: forming a second metal suppression layer on the array substrate; the orthographic projection of the second metal suppression layer on the array substrate covers the second area and exposes the first area; forming the first sub-section through the second metal suppression layer; and removing the second metal suppression layer.

[0031] In some embodiments, forming the second sub-section in the second area includes: placing a fourth mask plate on one side of the array substrate; the fourth mask plate has a fourth opening area, and the orthographic projection of the fourth opening area on the array substrate covers the second area and exposes the first area; forming the second sub-section through the fourth opening area; wherein the thickness of the first sub-section is greater than the thickness of the second sub-section, and / or the conductivity of the first sub-section is greater than the conductivity of the first sub-section.

[0032] In some embodiments, forming a second sub-section in the second area includes: forming a third metal suppression layer on the array substrate; the orthographic projection of the third metal suppression layer on the array substrate covers the first area and exposes the second area; forming a second sub-section through the third metal suppression layer; wherein the thickness of the first sub-section is greater than the thickness of the second sub-section, and / or the conductivity of the first sub-section is greater than the conductivity of the first sub-section; and removing the third metal suppression layer.

[0033] In some embodiments, forming a first sub-section in the first area and forming a second sub-section in the second area includes: placing a fifth mask plate on one side of the array substrate; the fifth mask plate has a fifth opening area, and the fifth opening area is located in the display area; gradually increasing the area of ​​the fifth opening area, and evaporating a cathode material onto the array substrate through the fifth opening area to form a cathode layer; wherein, the thickness of the cathode layer gradually decreases from the center of the display area to the boundary of the display area.

[0034] In some embodiments, while increasing the area of ​​the fifth opening region, the preparation method further includes: gradually reducing the conductivity of the evaporated cathode material; wherein the cathode material includes a main material and a doping material, and when the conductivity of the main material is greater than the conductivity of the doping material, gradually reducing the ratio of the main material to the doping material; when the conductivity of the main material is less than the conductivity of the doping material, gradually increasing the ratio of the main material to the doping material. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0036] FIG1 is a structural diagram of a display panel according to some embodiments;

[0037] FIG2 is a cross-sectional view along section line AA in FIG1 ;

[0038] FIG3 is a structural diagram of a light-emitting functional layer of a display panel according to some embodiments;

[0039] FIG4 is an energy transfer diagram of a light emitting device according to some embodiments;

[0040] FIG5 is a structural diagram of a cathode layer including a first sub-portion and a second sub-portion according to some embodiments;

[0041] FIG6 is a cross-sectional view along section line BB in FIG5;

[0042] FIG7 is a current model diagram of the resistance of the first sub-section and the resistance of the second sub-section;

[0043] FIG8 is a structural diagram showing a cathode layer with gradually decreasing thickness according to some embodiments;

[0044] FIG9 is a cross-sectional view taken along section line CC in FIG8 ;

[0045] FIG10 is another cross-sectional view along section line BB in FIG5;

[0046] FIG11 is another cross-sectional view along section line BB in FIG5 ;

[0047] FIG12 is a structural diagram showing a cathode layer having a gradually decreasing ratio of a main material to a dopant material according to some embodiments;

[0048] FIG13 is a cross-sectional view along section line DD in FIG12;

[0049] FIG14 is a structural diagram showing a cathode layer having a gradually increasing ratio of a main material to a dopant material according to some embodiments;

[0050] FIG15 is a cross-sectional view taken along section line EE in FIG14;

[0051] FIG16 is a structural diagram of a light emitting device of a display panel according to some embodiments;

[0052] 17 to 29 are diagrams illustrating steps of a method for manufacturing a display panel according to some embodiments. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0054] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0056] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium.

[0057] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0058] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0059] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0060] As used herein, “approximately” includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0061] As used herein, "perpendicular" and "equal" include the conditions described and conditions similar to the conditions described, where the range of the similar conditions is within an acceptable deviation range, where the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equalities is less than or equal to 5% of either.

[0062] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0063] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0064] Some embodiments of the present disclosure provide a display device 1000, as shown in FIG1 . The display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. For example, the display device 1000 can be a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or any other product or component with a display function.

[0065] The display device 1000 may be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QLED) display device, or an active-matrix organic light-emitting diode (AMOLED) display device. The embodiments of the present disclosure are described using an OLED display device as an example.

[0066] The following takes the above-mentioned display device 1000 as an organic light emitting diode display device 1000 as an example to schematically illustrate some embodiments of the present disclosure, but the implementation of the present disclosure is not limited to this, and any other display device 1000 can also be considered as long as the same technical concept is applied.

[0067] As shown in Figure 1 , the display device 1000 includes a display panel 100 having a display area AA and a peripheral area BB disposed on at least one side of the display area AA. Figure 1 illustrates an example in which the peripheral area BB surrounds the display area AA.

[0068] As shown in FIG1 , the display area AA is an area for displaying images, and the peripheral area BB is an area for not displaying images. The peripheral area BB is configured to set a driving circuit, for example, a gate driving circuit and a source driving circuit.

[0069] As shown in FIG. 2 , the display panel 100 includes an array substrate 10 , and a plurality of light emitting devices 20 and an encapsulation layer 30 disposed on the array substrate 10 .

[0070] As shown in FIG2 , the encapsulation layer 30 is located on a side of the plurality of light-emitting devices 20 away from the array substrate 10. The encapsulation layer 30 may be an encapsulation film. In some embodiments, the encapsulation layer 30 may include a single layer of encapsulation film, or may include two or more layers of encapsulation films stacked one on top of the other. For example, the encapsulation layer 30 includes three layers of encapsulation films stacked one on top of the other.

[0071] When encapsulation layer 30 includes three layers of encapsulation films stacked sequentially, the encapsulation film in the middle layer is made of an organic material, while the encapsulation films on both sides are made of an inorganic material. The organic material may be, for example, polymethyl methacrylate (PMMA) or polyimide (PI).

[0072] As shown in FIG. 2 , the array substrate 10 includes a substrate 11 and a pixel circuit 12 disposed on the substrate 11 .

[0073] Exemplarily, the substrate 11 is a flexible substrate 11. For example, the flexible substrate 11 may be a polyethylene terephthalate (PET) substrate 11, a polyethylene naphthalate (PEN) substrate 11, or a polyimide substrate 11.

[0074] Exemplarily, the substrate 11 may be a rigid substrate 11. For example, the rigid substrate 11 may be a glass substrate 11 or a polymethyl methacrylate substrate 11.

[0075] It should be noted that the substrate 11 may have a single-layer structure or a multi-layer structure. For example, in the case of a multi-layer structure, as shown in FIG2 , the substrate 11 may include a base 111 and a buffer layer 112 disposed on the base 111. The material of the buffer layer 112 may include silicon oxide or silicon nitride. The embodiments of the present disclosure do not specifically limit the material and structure of the substrate 11.

[0076] As shown in FIG. 2 , the pixel circuit 12 includes a plurality of thin film transistors 121 and a storage capacitor 122 .

[0077] In some embodiments, the thin film transistor 121 is, for example, an oxide thin film transistor. The oxide thin film transistor has a high carrier mobility, which can improve the response speed of the thin film transistor 121. Exemplarily, the pixel circuit 12 can be a 2T1C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C or 9T2C structure, and the embodiments of the present disclosure are not listed one by one. For example, the pixel circuit 12 is a 7T1C structure. Among them, the pixel circuit 12 is aTbC, which means that the pixel circuit 12 includes a thin film transistor 121 and b storage capacitors 122.

[0078] The thin film transistor 121 includes an active layer 1211, a source electrode 1212, a drain electrode 1213, and a gate electrode 1214. The source electrode 1212 and the drain electrode 1213 are respectively in contact with the active layer 1211. The storage capacitor 122 includes a first electrode plate 1221 and a second electrode plate 1222 that are opposite to each other.

[0079] It should be noted that the source 1212 and the drain 1213 can be interchanged, that is, 1212 in FIG. 2 represents the drain, and 1213 represents the source.

[0080] As shown in FIG1 , a plurality of light-emitting devices 20 are located in the display area AA. The plurality of light-emitting devices 20 may be arranged, for example, in multiple rows and columns. A row of light-emitting devices 20 includes a plurality of light-emitting devices 20 arranged along a first direction X, and a column of light-emitting devices 20 includes a plurality of light-emitting devices 20 arranged along a second direction Y. The first direction X is substantially perpendicular to the second direction Y.

[0081] The plurality of light-emitting devices 20 may include light-emitting devices 20 emitting a first color, light-emitting devices 20 emitting a second color, and light-emitting devices 20 emitting a third color. The first, second, and third colors are three primary colors. For example, the first color is red, the second color is blue, and the third color is green. This is not specifically limited in the present embodiment.

[0082] 2 , the light emitting device 20 includes a cathode 21, a light emitting functional layer 22, and an anode 23. The anode 23 may be electrically connected to a source of a thin film transistor 121 serving as a driving transistor among the plurality of thin film transistors 121, for example.

[0083] As shown in FIG3 , the light-emitting functional layer 22 may include only a light-emitting layer 221, or, in addition to the light-emitting layer 221, may further include at least one of an electron transporting layer (ETL) 222, an electron injection layer (EIL) 223, a hole blocking layer (HBL) 224, a hole transporting layer (HTL) 225, a hole injection layer (HIL) 226, and an electron blocking layer (EBL) 227.

[0084] In some embodiments, as shown in FIG. 2 , the light-emitting functional layer 22 includes a plurality of red light-emitting functional layers, a plurality of green light-emitting functional layers, and a plurality of blue light-emitting functional layers.

[0085] The red light-emitting functional layer includes a host material and a red fluorescent material, so that the red light-emitting functional layer can emit red light. Exemplarily, the doping ratio of the red fluorescent material is 2% to 4%. For example, the doping ratio of the red fluorescent material is 2%, 2.2%, 2.5%, 2.6%, 2.7%, 2.9%, 3.1%, 3.2%, 3.5%, 3.8% or 4%, and the embodiments of the present disclosure are not listed one by one.

[0086] The green light-emitting functional layer includes a host material and a green fluorescent material, so that the green light-emitting functional layer can emit green light. Exemplarily, the doping ratio of the green fluorescent material is 8% to 10%. For example, the doping ratio of the green fluorescent material is 8%, 8.1%, 8.3%, 8.4%, 8.6%, 8.8%, 9%, 9.2%, 9.5%, 9.6%, 9.8% or 10%, and the embodiments of the present disclosure are not listed one by one.

[0087] The blue light-emitting functional layer includes a host material and a blue fluorescent material, so that the blue light-emitting functional layer can emit blue light. Exemplarily, the doping ratio of the blue fluorescent material is 1% to 5%. For example, the doping ratio of the blue fluorescent material is 1%, 1.1%, 1.3%, 1.4%, 1.6%, 1.8%, 2%, 2.5%, 2.8%, 3%, 3.2%, 3.5%, 3.8%, 4%, 4.2%, 4.6% or 5%, and the embodiments of the present disclosure are not listed one by one.

[0088] The cooperation of multiple red light-emitting functional layers, multiple green light-emitting functional layers, and multiple blue light-emitting functional layers can realize full-color display of the display panel. For example, the cooperation of multiple red light-emitting functional layers, multiple blue light-emitting functional layers, and multiple green light-emitting functional layers can make the display panel 100 display a white image.

[0089] In some embodiments, the thickness of the light emitting layer 221 is 20 nm to 40 nm. For example, the thickness of the light emitting layer 221 is 20 nm, 22 nm, 25 nm, 26 nm, 28 nm, 29 nm, 31 nm, 34 nm, 35 nm, 38 nm, or 40 nm. The embodiments of the present disclosure are not listed one by one.

[0090] The material of the light-emitting layer 221 includes one or more organic compounds. The structural formula of the organic compound is as follows:

[0091] The thickness of the electron transport layer 222 is 20 nm to 35 nm. For example, the thickness of the electron transport layer 222 is 20 nm, 22 nm, 25 nm, 26 nm, 28 nm, 29 nm, 31 nm, 34 nm, or 35 nm. The embodiments of the present disclosure are not listed one by one.

[0092] The material of the electron transport layer 222 includes one or more organic compounds. The organic compound includes lithium fluoride or a compound with the following structural formula:

[0093] The thickness of the electron injection layer 223 is 0.5 nm to 3 nm. For example, the thickness of the electron injection layer 223 is 0.5 nm, 0.6 nm, 0.8 nm, 0.9 nm, 1 nm, 1.5 nm, 2 nm, 2.2 nm, 2.5 nm or 3 nm. The embodiments of the present disclosure are not listed one by one.

[0094] The material of the electron injection layer 223 includes one or more organic compounds. The organic compound includes lithium fluoride, ytterbium or a compound with the following structural formula:

[0095] The thickness of the electron blocking layer 227 is 10 nm to 80 nm. For example, the thickness of the electron transport layer 222 is 10 nm, 14 nm, 20 nm, 28 nm, 32 nm, 40 nm, 50 nm, 65 nm, 70 nm, or 80 nm. The embodiments of the present disclosure are not listed one by one.

[0096] The material of the electron blocking layer 227 includes one or more organic compounds. The structural formula of the organic compound is shown below:

[0097] The thickness of the hole transport layer 225 is 100 nm to 130 nm. For example, the thickness of the hole transport layer 225 is 100 nm, 102 nm, 105 nm, 108 nm, 110 nm, 113 nm, 117 nm, 120 nm, 121 nm, 124 nm, 126 nm, or 130 nm. The embodiments of the present disclosure are not listed one by one.

[0098] The material of the hole transport layer 225 includes one or more organic compounds. The structural formula of the organic compound is shown below:

[0099] The thickness of the hole injection layer 226 is 5 nm to 30 nm. For example, the thickness of the hole injection layer 226 is 5 nm, 6 nm, 8 nm, 10 nm, 11 nm, 14 nm, 15 nm, 16 nm, 19 nm, 22 nm, 25 nm, 28 nm, or 30 nm. The embodiments of the present disclosure are not listed one by one.

[0100] The material of the hole injection layer 226 includes one or more organic compounds. The structural formula of the organic compound is shown below:

[0101] The thickness of the hole blocking layer 224 is 5 nm to 10 nm. For example, the thickness of the hole injection layer 226 is 5 nm, 5.6 nm, 5.8 nm, 6 nm, 6.1 nm, 6.4 nm, 7 nm, 7.2 nm, 7.5 nm, 7.9 nm, 8 nm, 8.5 nm, 9 nm, or 10 nm. The embodiments of the present disclosure are not listed one by one.

[0102] The material of the hole blocking layer 224 includes one or more organic compounds. The structural formula of the organic compound is shown below:

[0103] The following is an illustrative example of the light-emitting principle of the light-emitting device 20. As shown in Figure 4, the light-emitting functional layer 22 includes a host material and a fluorescent material. The anode 23 provides holes to the light-emitting functional layer 22, which are injected into the high-occupied molecular orbital (HOMO) of the host material and migrate therein. The cathode 21 provides electrons to the light-emitting functional layer 22, which are injected into the lower unoccupied molecular orbital (LUMO) and migrate therein.

[0104] As shown in Figure 4, the combination of holes and electrons can cause the organic molecules in the host material (the host material does not emit light; its function is to transfer energy to the fluorescent material, exciting the organic molecules in the fluorescent material to transition from the ground state to the excited state) to transition from the ground state S0 to the excited state, forming excitons. Excitons are divided into two types: singlet excitons S1 and triplet excitons T1. According to the statistical rules of electron spin, the ratio of singlet excitons S1 to triplet excitons T1 is 1:3. According to the principles of quantum mechanics, the electron-hole pair in the singlet exciton S1 has opposite spin directions and can transition to the ground state S0. The electron-hole pair in the triplet exciton T1 has the same spin direction and cannot transition to the ground state S0. The large energy difference between the triplet T1 and singlet S1 states in the host material makes it difficult for triplet T1 excitons to transition to the singlet exciton S1 through reverse intersystem crossing (RISC). The singlet exciton S1 in the host material can cause the organic molecules in the fluorescent material to accept energy and transition from the ground state S0 to an excited state through Foster Resonance Energy Transfer (FRET), forming singlet exciton S1. The triplet exciton T1 in the host material can also cause the organic molecules in the fluorescent material to accept energy and transition from the ground state S0 to an excited state through Dexter Excitation Transfer (Dexter), forming triplet exciton T1. The singlet exciton S1 in the fluorescent material is unstable and easily returns from the excited state to the ground state S0. When the singlet exciton S1 in the fluorescent material returns from the excited state to the ground state S0, the fluorescent material simultaneously emits light.

[0105] In some embodiments, as shown in FIG2 , the cathodes 21 of multiple light-emitting devices 20 are connected together to form a cathode layer 201. That is, the cathodes 21 are located in the cathode layer 201. In this way, the area of ​​the cathode layer 201 is relatively large. When a mask is used to evaporate the material of the cathode 21 to form the cathode layer 201, the mask opening corresponding to the cathode layer 201 is relatively large, thereby reducing the difficulty of mask preparation.

[0106] In the related art, when current flows from the anode to the cathode, a voltage difference occurs on the cathode layer, which leads to poor brightness uniformity of the display panel.

[0107] To solve the above problems, as shown in FIG5 and FIG6 , the cathode layer 201 provided in the embodiment of the present disclosure includes a first sub-portion 2011 and a second sub-portion 2012 surrounding the first sub-portion 2011 , and both the first sub-portion 2011 and the second sub-portion 2012 are located in the display area AA.

[0108] Figure 7 shows a current model of the resistance of the first subsection 2011 and the resistance of the second subsection 2012. As shown in Figure 7, the resistance of the first subsection 2011 is R1, and the light-emitting device 20 corresponding to the first subsection 2011 is the first light-emitting device L1. The resistance of the second subsection 2012 is R2, and the light-emitting device 20 corresponding to the second subsection 2012 is the second light-emitting device L2. The current passing through the first light-emitting device L1 is I1, and the current passing through the second light-emitting device L2 is I2. The anode voltage of the first light-emitting device L1 is U A , the anode voltage of the second light emitting device L2 is U B .

[0109] In the embodiment of the present disclosure, the first light emitting device L1 and the second light emitting device L2 included in the display panel 100 are at the same gray scale, that is, the anode voltage U of the first light emitting device L1 is A , and the anode voltage U of the second light emitting device L2 B Let’s take equality as an example to illustrate.

[0110] As shown in FIG6 , the unit resistance of the first subsection 2011 is smaller than the unit resistance of the second subsection 2012, so that the resistance R1 of the first subsection 2011 can be smaller, thereby reducing the total resistance of the first subsection 2011, the second subsection 2012, the first light-emitting device L1, and the second light-emitting device L2. The total current I1+I2 passing through the resistor R2 of the second subsection 2012 increases, and the voltage drop U on the second subsection 2012 is reduced. DE Increase, that is, the voltage drop U on the second light emitting device L2 BD Decrease, the voltage U at point D D increases, I2 passing through the second light emitting device L2 decreases, I1 passing through the first light emitting device L1 increases, and the voltage drop U on the first light emitting device L1 AC Increase, the voltage U at point C C Reduce (it should be noted that the voltage U C Always greater than the voltage U at point D D ).

[0111] The voltage U at point D D Increase, the voltage U at point C C The voltage difference between point D and point C can be reduced, that is, the voltage difference between the first sub-portion 2011 and the second sub-portion 2012 can be reduced, thereby improving the brightness uniformity of the display panel 100.

[0112] In some embodiments, as shown in FIG6 , the thickness of the first subsection 2011 is greater than the thickness of the second subsection 2012, so that the cross-sectional area of ​​the first subsection 2011 is greater than the cross-sectional area of ​​the second subsection 2012. As a result, the unit resistance of the first subsection 2011 is smaller than the unit resistance of the second subsection 2012, which can reduce the voltage difference between the first subsection 2011 and the second subsection 2012, thereby improving the brightness uniformity of the display panel 100.

[0113] In some examples, as shown in FIG6 , cathode layer 201 includes a first conductive layer 2013 and a second conductive layer 2014. First conductive layer 2013 is disposed on array substrate 10. First conductive layer 2013 is located in display area AA and includes a third sub-portion 2015 and a second sub-portion 2012 surrounding third sub-portion 2015. Second conductive layer 2014 is disposed on a side of first conductive layer 2013 away from array substrate 10. The orthographic projection of second conductive layer 2014 on array substrate 10 overlaps with the orthographic projection of third sub-portion 2015 on array substrate 10. Second conductive layer 2014 and third sub-portion 2015 form first sub-portion 2011.

[0114] Exemplarily, as shown in FIG. 6 , the orthographic projection of the second conductive layer 2014 on the array substrate 10 partially overlaps with the orthographic projections of the plurality of light-emitting functional layers 22 on the array substrate 10 .

[0115] In some embodiments, as shown in Figures 8 and 9, the thickness of the cathode layer 201 gradually decreases from the center of the display area AA to the boundary of the display area AA, that is, from the center of the cathode layer 201 to the boundary of the display area AA, so that the cross-sectional area of ​​the cathode layer 201 can be gradually reduced, thereby causing the unit resistance of the cathode layer 201 to gradually increase, and further reducing the voltage difference in the first sub-section 2011, the voltage difference in the second sub-section 2012, and the voltage difference between the first sub-section 2011 and the second sub-section 2012, thereby improving the brightness uniformity of the display panel 100.

[0116] In some examples, the thickness of the cathode layer 201 decreases gradually from the center of the display area AA to the boundary of the display area AA. For example, the reduction ratio is 5% to 15%. For example, the reduction ratio of the thickness of the cathode layer 201 is 5%, 7%, 8%, 10%, 12%, or 15%, which are not listed in the embodiments of the present disclosure.

[0117] In other examples, the thickness of the cathode layer 201 decreases linearly or curvilinearly from the center of the display area AA to the boundary of the display area AA. In other words, the orthographic projection of the surface of the cathode layer 201 away from the array substrate 10 onto a reference plane is a straight line or a curve. The reference plane is perpendicular to the array substrate 10 and passes through the center of the display area AA.

[0118] In some embodiments, the material of the first sub-section 2011 includes at least one of aluminum (Al), iron (Fe), tin (Sn), magnesium (Mg), copper (Cu), silver (Ag), and gold (Au). And / or the material of the second sub-section 2012 includes at least one of aluminum, iron, tin, Mg, copper, silver, and gold.

[0119] For example, the material of the first sub-section 2011 is the same as the material of the second sub-section 2012. For example, the material of the first sub-section 2011 and the material of the second sub-section 2012 are both copper. This can improve the material uniformity of the cathode layer 201 and reduce the manufacturing cost of the cathode layer 201.

[0120] When the material of the first sub-section 2011 and the material of the second sub-section 2012 are copper, copper has a low light transmittance (light transmittance less than or equal to 15%). In order to allow the light emitted by the light-emitting functional layer 22 to be emitted from the display panel, the material of the anode 23 needs to be a material with high light transmittance (light transmittance greater than or equal to 85%). For example, the material of the anode 23 includes indium tin oxide (ITO). In this case, the light-emitting device 20 is a bottom-emitting light-emitting device 20.

[0121] In other embodiments, the light-emitting device 20 may be a top-emitting light-emitting device 20. In this case, the cathode 21 includes a semi-transmissive and semi-reflective electrode, which is configured to reflect a portion of light incident on the cathode 21 and transmit a portion of light incident on the cathode 21. The semi-transmissive and semi-reflective electrode refers to an electrode having a reflectivity of 50% to 60%.

[0122] Anode 23 includes a reflective electrode for reflecting light incident on anode 23. Anode 23 may have a single-layer structure or a laminated structure. For example, if anode 23 has a laminated structure, anode 23 may include indium tin oxide, silver, and indium tin oxide. A reflective electrode is an electrode having a reflectivity greater than 90%.

[0123] The cathode 21 and anode 23 form a resonant cavity. The light-emitting functional layer 22 is located between the cathode 21 and anode 23, that is, within the resonant cavity. This increases the intensity of light of a certain wavelength emitted by the light-emitting functional layer 22, narrowing the spectrum of that wavelength. This resonant cavity allows most of the light emitted by the light-emitting functional layer 22 to exit the display panel 100, thereby improving the luminous efficiency of the light-emitting device 20.

[0124] In some embodiments, as shown in FIG10 , the conductivity of the first sub-section 2011 is greater than the conductivity of the second sub-section 2012. This allows the resistivity of the first sub-section 2011 to be lower than the resistivity of the second sub-section 2012, thereby making the unit resistance of the first sub-section 2011 lower than the unit resistance of the second sub-section 2012, reducing the voltage difference between the second sub-section 2012 and the first sub-section, and improving the brightness uniformity of the display panel 100.

[0125] In some embodiments, the material of the first subsection 2011 includes at least one of copper, silver, and gold. The material of the second subsection 2012 includes at least one of aluminum, iron, tin, and magnesium. Copper, silver, and gold have greater electrical conductivity than aluminum, iron, tin, and magnesium. This allows the electrical conductivity of the first subsection 2011 to be greater than that of the second subsection 2012, thereby reducing the voltage difference between the second subsection 2012 and the first subsection 2011 and improving the brightness uniformity of the display panel 100.

[0126] Exemplarily, the material of the first sub-section 2011 includes copper, and the material of the second sub-section 2012 includes aluminum. Alternatively, exemplary, the material of the first sub-section 2011 includes copper, and the material of the second sub-section 2012 includes tin. Alternatively, exemplary, the material of the first sub-section 2011 includes silver, and the material of the second sub-section 2012 includes aluminum. The embodiments of the present disclosure are not enumerated one by one.

[0127] In some embodiments, on the basis that the electrical conductivity of the first sub-portion 2011 is greater than the electrical conductivity of the second sub-portion 2012 , the thickness of the first sub-portion 2011 is greater than or equal to the thickness of the second sub-portion 2012 .

[0128] In some examples, as shown in FIG10 , the thickness of the first sub-portion 2011 is equal to the thickness of the second sub-portion 2012, which can make the thickness of the cathode layer 201 relatively uniform. When a user applies force to the display panel 100, the force applied to the cathode layer 201 is relatively uniform, which in turn makes the force applied to the light-emitting device 20 relatively uniform, thereby improving the uniformity of the force applied to the light-emitting device 20 and extending the service life of the dimming display panel 100.

[0129] In other examples, as shown in Figure 11, the thickness of the first sub-section 2011 is greater than the thickness of the second sub-section 2012, which can make the cross-sectional area of ​​the first sub-section 2011 larger than the cross-sectional area of ​​the second sub-section 2012, and the unit resistance of the first sub-section 2011 is smaller than the unit resistance of the second sub-section 2012, thereby reducing the voltage difference between the first sub-section 2011 and the second sub-section 2012, thereby improving the brightness uniformity of the display panel 100.

[0130] In some embodiments, the conductivity of the cathode layer 201 gradually decreases from the center of the display area AA to the boundary of the display area AA, which can gradually increase the resistivity of the cathode layer 201, thereby gradually increasing the unit resistance of the cathode layer 201, and further reduce the voltage difference in the first sub-section 2011, the voltage difference in the second sub-section 2012, and the voltage difference between the first sub-section 2011 and the second sub-section 2012, thereby improving the brightness uniformity of the display panel 100.

[0131] In some examples, the conductivity gradient of the cathode layer 201 decreases from the center of the display area AA to the boundary of the display area AA, for example, by a reduction ratio of 5% to 15%. For example, the conductivity of the cathode layer 201 decreases by a ratio of 5%, 7%, 8%, 10%, 12%, or 15%, which are not listed in the embodiments of the present disclosure.

[0132] In other examples, the conductivity of the cathode layer 201 decreases linearly or curvedly from the center of the display area AA to the boundary of the display area AA.

[0133] In some embodiments, the material of the cathode layer 201 includes a host material and a dopant material, and the electrical conductivity of the host material is greater than or less than the electrical conductivity of the dopant material.

[0134] In some examples, the electrical conductivity of the host material is greater than the electrical conductivity of the dopant material, for example, the host material is magnesium and silver, and the dopant material is titanium (Ti).

[0135] As shown in Figures 12 and 13 (the darker parts in Figures 12 and 13 indicate a larger ratio of the main material to the doping material. The whiter parts indicate a smaller ratio of the main material to the doping material), the ratio of the main material to the doping material decreases from the center of the display area AA to the outer boundary of the display area AA, which can gradually reduce the conductivity of the cathode layer 201, gradually increase the resistivity of the cathode layer 201, and gradually reduce the unit resistance of the cathode layer 201, thereby improving the brightness uniformity of the display panel 100.

[0136] For example, the ratio of the main material to the dopant material decreases gradually from the center of the display area AA to the outer boundary of the display area AA, for example, the reduction ratio is 5% to 15%. For example, the ratio of the main material to the dopant material decreases by 5%, 7%, 8%, 10%, 12%, or 15%, which are not listed in the embodiments of the present disclosure. Alternatively, for example, the ratio of the main material to the dopant material decreases in a straight line or curve from the center of the display area AA to the outer boundary of the display area AA.

[0137] In other examples, the conductivity of the host material is less than the conductivity of the dopant material, for example, the host material is magnesium and silver, and the dopant material is copper.

[0138] As shown in Figures 14 and 15 (the darker parts in Figures 14 and 15 indicate a larger ratio of the main material to the doping material. The whiter parts indicate a smaller ratio of the main material to the doping material), the ratio of the main material to the doping material increases from the center of the display area AA to the outer boundary of the display area AA, which can gradually reduce the conductivity of the cathode layer 201, increase the resistivity of the cathode layer 201, and gradually increase the unit resistance of the cathode layer 201, thereby improving the brightness uniformity of the display panel.

[0139] For example, the ratio of the main material to the dopant material increases gradually from the center of the display area AA to the outer boundary of the display area AA, for example, the increase ratio is 5% to 15%. For example, the ratio of the main material to the dopant material increases by 5%, 7%, 8%, 10%, 12%, or 15%, and the embodiments of the present disclosure are not listed one by one. Alternatively, for example, the straight line or curve of the main material to the dopant material increases from the center of the display area AA to the outer boundary of the display area AA.

[0140] In some embodiments, as shown in FIG16 , at least two light-emitting layers 221 are provided between the cathode 21 and the anode 23 that are arranged opposite to each other, and the at least two light-emitting layers 221 are stacked in a direction perpendicular to the cathode layer 201. The display panel 100 further includes a charge generation layer 40 (CGL for short), which is located between two adjacent light-emitting layers 221 and is used to provide carriers (holes or electrons) to the two adjacent light-emitting layers 221. In this way, the excitons in the light-emitting functional layer 22 in the embodiment of the present disclosure are dispersed in at least two light-emitting layers 221, which can improve the problem of exciton quenching caused by a high exciton density in one light-emitting layer 221, and reduce the risk of reduced luminous efficiency of the light-emitting layer 221 due to exciton quenching.

[0141] For example, as shown in FIG16 , the charge generation layer 40 includes a hole charge generation layer 41 and an electron charge generation layer 42, wherein the hole charge generation layer 41 is closer to the cathode 21 than the electron charge generation layer 42. The hole charge generation layer 41 generates holes under the action of the cathode 21 and the anode 23, and then provides holes to the light-emitting layer 221 near the anode 23. The electron charge generation layer 42 generates electrons under the action of the cathode 21 and the anode 23, and then provides electrons to the light-emitting layer 221 near the cathode 21.

[0142] In some embodiments, as shown in Figure 16, the light-emitting device 20 includes an anode 23, a hole injection layer 226, a first hole transport layer 2251, a first electron blocking layer 2271, a first light-emitting layer 2211, a first hole blocking layer 2241, an electron charge generating layer 42, a hole charge generating layer 41, a second hole transport layer 2252, a second electron blocking layer 2272, a second light-emitting layer 2212, a second hole blocking layer 2242, an electron transport layer 222, an electron injection layer 223 and a cathode 21, which are stacked in a direction perpendicular to the array substrate 10 and away from the array substrate 10.

[0143] The thickness of the hole injection layer 226 is 5 nm to 30 nm. For example, the thickness of the hole injection layer 226 is 5 nm, 6 nm, 8 nm, 10 nm, 11 nm, 14 nm, 15 nm, 16 nm, 19 nm, 22 nm, 25 nm, 28 nm, or 30 nm. The embodiments of the present disclosure are not listed one by one.

[0144] The thickness of the first hole transport layer 2251 is 100 nm to 130 nm. For example, the thickness of the first hole transport layer 2251 is 100 nm, 102 nm, 105 nm, 108 nm, 110 nm, 113 nm, 117 nm, 120 nm, 121 nm, 124 nm, 126 nm, or 130 nm. The embodiments of the present disclosure are not listed one by one.

[0145] The thickness of the second hole transport layer 2252 is 100 nm to 130 nm. For example, the thickness of the second hole transport layer 2252 is 100 nm, 103 nm, 105 nm, 108 nm, 112 nm, 113 nm, 117 nm, 121 nm, 121 nm, 124 nm, 128 nm, or 130 nm. The embodiments of the present disclosure are not listed one by one.

[0146] For example, the thickness of the first hole transport layer 2251 may be the same as the thickness of the second hole transport layer 2252. For example, the thickness of the first hole transport layer 2251 and the second hole transport layer 2252 are both 100 nm, 105 nm, 108 nm, 113 nm, 121 nm, 126 nm, or 130 nm, which are not listed in detail in the embodiments of the present disclosure.

[0147] Alternatively, illustratively, the thickness of the first hole transport layer 2251 may be different from the thickness of the second hole transport layer 2252. For example, the thickness of the first hole transport layer 2251 is 100 nm, the thickness of the second hole transport layer 2252 is 105 nm, the thickness of the first hole transport layer 2251 is 102 nm, the thickness of the second hole transport layer 2252 is 105 nm, the thickness of the first hole transport layer 2251 is 100 nm, the thickness of the second hole transport layer 2252 is 121 nm, the thickness of the first hole transport layer 2251 is 110 nm, and the thickness of the second hole transport layer 2252 is 130 nm. The embodiments of the present disclosure are not listed one by one.

[0148] The thickness of the first electron blocking layer 2271 is 10 nm to 80 nm. For example, the thickness of the first electron blocking layer 2271 is 10 nm, 14 nm, 20 nm, 28 nm, 32 nm, 40 nm, 50 nm, 65 nm, 70 nm, or 80 nm. The embodiments of the present disclosure are not listed one by one.

[0149] The thickness of the second electron blocking layer 227 is 10 nm to 80 nm. For example, the thickness of the second electron blocking layer 227 is 10 nm, 14 nm, 22 nm, 28 nm, 32 nm, 42 nm, 50 nm, 65 nm, 72 nm, or 80 nm. The embodiments of the present disclosure are not listed one by one.

[0150] For example, the thickness of the first electron blocking layer 2271 can be the same as the thickness of the second electron blocking layer 227. For example, the thickness of the first electron blocking layer 2271 and the second electron blocking layer 2272 can both be 10 nm, 14 nm, 20 nm, 28 nm, 32 nm, 40 nm, 50 nm, 65 nm, 70 nm, or 80 nm. The embodiments of the present disclosure are not listed one by one.

[0151] Alternatively, illustratively, the thickness of the first electron blocking layer 2271 may be different from the thickness of the second electron blocking layer 2272. For example, the thickness of the first electron blocking layer 2271 is 10 nm, the thickness of the second electron blocking layer 2272 is 14 nm, the thickness of the first electron blocking layer 2271 is 10 nm, the thickness of the second electron blocking layer 2272 is 20 nm, the thickness of the first electron blocking layer 2271 is 65 nm, the thickness of the second electron blocking layer 2272 is 50 nm, the thickness of the first electron blocking layer 2271 is 70 nm, and the thickness of the second electron blocking layer 2272 is 80 nm. The embodiments of the present disclosure are not listed one by one.

[0152] The thickness of the first light-emitting layer 2211 is 20 nm to 40 nm. For example, the thickness of the first light-emitting layer 2211 is 20 nm, 22 nm, 25 nm, 26 nm, 28 nm, 29 nm, 31 nm, 34 nm, 35 nm, 38 nm, or 40 nm. The embodiments of the present disclosure are not listed one by one.

[0153] The thickness of the second light-emitting layer 2212 is 20 nm to 40 nm. For example, the thickness of the first light-emitting layer 2211 is 20 nm, 22 nm, 25 nm, 27 nm, 28 nm, 29 nm, 32 nm, 34 nm, 35 nm, 39 nm, or 40 nm. The embodiments of the present disclosure are not listed one by one.

[0154] For example, the thickness of the first light-emitting layer 2211 can be the same as the thickness of the second light-emitting layer 2212. For example, the thickness of the first light-emitting layer 2211 and the second light-emitting layer 2212 can both be 20 nm, 22 nm, 25 nm, 26 nm, 28 nm, 29 nm, 31 nm, 34 nm, 35 nm, 38 nm, or 40 nm. The embodiments of the present disclosure are not listed one by one.

[0155] Alternatively, for example, the thickness of the first light-emitting layer 2211 may be different from the thickness of the second light-emitting layer 2212. For example, the thickness of the first light-emitting layer 2211 is 20 nm, the thickness of the second light-emitting layer 2212 is 25 nm, the thickness of the first light-emitting layer 2211 is 25 nm, the thickness of the second light-emitting layer 2212 is 31 nm, the thickness of the first light-emitting layer 2211 is 35 nm, the thickness of the second light-emitting layer 2212 is 34 nm, the thickness of the first light-emitting layer 2211 is 38 nm, and the thickness of the second light-emitting layer 2212 is 40 nm. The embodiments of the present disclosure are not listed one by one.

[0156] The thickness of the first hole blocking layer 2241 is 5 nm to 10 nm. For example, the thickness of the first hole blocking layer is 5 nm, 5.6 nm, 5.8 nm, 6 nm, 6.1 nm, 6.4 nm, 7 nm, 7.2 nm, 7.5 nm, 7.9 nm, 8 nm, 8.5 nm, 9 nm, or 10 nm. The embodiments of the present disclosure are not listed one by one.

[0157] The thickness of the second hole blocking layer 2242 is 5 nm to 10 nm. For example, the thickness of the second hole blocking layer is 5 nm, 5.6 nm, 5.8 nm, 6 nm, 6.2 nm, 6.4 nm, 7 nm, 7.2 nm, 7.6 nm, 7.9 nm, 8 nm, 8.5 nm, 9.1 nm, or 10 nm. The embodiments of the present disclosure are not listed one by one.

[0158] For example, the thickness of the first hole blocking layer 2241 may be the same as the thickness of the second hole blocking layer 2242. For example, the thickness of the first hole blocking layer 2241 and the second hole blocking layer 2242 may both be 5 nm, 5.6 nm, 5.8 nm, 6 nm, 6.1 nm, 6.4 nm, 7 nm, 7.2 nm, 7.5 nm, 7.9 nm, 8 nm, 8.5 nm, 9 nm, or 10 nm. The embodiments of the present disclosure are not listed one by one.

[0159] Alternatively, for example, the thickness of the first hole blocking layer 2241 may be different from the thickness of the second hole blocking layer 2242. For example, the thickness of the first hole blocking layer 2241 is 5 nm, the thickness of the second hole blocking layer 2242 is 6 nm, the thickness of the first hole blocking layer 2241 is 5 nm, the thickness of the second hole blocking layer 2242 is 7.2 nm, the thickness of the first hole blocking layer 2241 is 8 nm, the thickness of the second hole blocking layer 2242 is 10 nm, the thickness of the first hole blocking layer 2241 is 9 nm, and the thickness of the second hole blocking layer 2242 is 8 nm. The embodiments of the present disclosure are not listed one by one.

[0160] The thickness of the electron charge generation layer 42 is 17 nm to 19 nm. Exemplarily, the thickness of the electron charge generation layer 42 is 17 nm, 17.2 nm, 17.6 nm, 17.9 nm, 18.1 nm, 18.5 nm, 18.8 nm or 19 nm, which are not listed one by one in the embodiments of the present disclosure.

[0161] The thickness of the hole charge generation layer 41 is 8 nm to 10 nm. Exemplarily, the thickness of the hole charge generation layer 41 is 8 nm, 8.2 nm, 8.6 nm, 8.9 nm, 9 nm, 9.1 nm, 9.5 nm, 9.8 nm or 10 nm, which are not listed one by one in the embodiments of the present disclosure.

[0162] The thickness of the electron transport layer 222 is 20 nm to 35 nm. For example, the thickness of the electron transport layer 222 is 20 nm, 22 nm, 25 nm, 26 nm, 28 nm, 29 nm, 31 nm, 34 nm, or 35 nm. The embodiments of the present disclosure are not listed one by one.

[0163] The thickness of the electron injection layer 223 is 0.5 nm to 3 nm. For example, the thickness of the electron injection layer 223 is 0.5 nm, 0.6 nm, 0.8 nm, 0.9 nm, 1 nm, 1.5 nm, 2 nm, 2.2 nm, 2.5 nm, or 3 nm. The embodiments disclosed herein are not listed one by one. In this way, the color of light emitted by a light-emitting device 20 varies within the same color system.

[0164] Some embodiments of the present disclosure further provide a method for manufacturing a display panel 100 . The display panel 100 has a display area AA. As shown in FIG. 17 , the method includes steps S100 to S200 .

[0165] S100 , providing an array substrate 10 .

[0166] The array substrate 10 includes a first area 101 and a second area 102 surrounding the first area 101 . Both the first area 101 and the second area 102 are located in the display area AA.

[0167] Exemplarily, the array substrate 10 includes a substrate 11 and a pixel circuit 12 provided on the substrate 11 .

[0168] S200, forming a first sub-section 2011 in the first region 101, and forming a second sub-section 2012 in the second region 102;

[0169] The second subsection 2012 is connected to the first subsection 2011 to form the cathode layer 201. The resistance per unit length of the first subsection 2011 is smaller than the resistance per unit length of the second subsection 2012. This reduces the voltage difference between the first subsection 2011 and the second subsection 2012, thereby improving the brightness uniformity of the display panel 100.

[0170] In some embodiments, as shown in FIG. 18 , S200 (forming a first sub-portion 2011 in the first region 101 and forming a second sub-portion 2012 in the second region 102 ) includes: S10 to S20 .

[0171] As shown in FIG. 18 , S10 , a first conductive layer 2013 is formed on the array substrate 10 .

[0172] The first conductive layer 2013 includes a third sub-portion 2015 located in the first region 101 and a second sub-portion 2012 located in the second region 102. For example, the first conductive layer 2013 may be a whole layer structure covering the array substrate 10.

[0173] For example, the first conductive layer 2013 may be formed by a thin film deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0174] Exemplarily, the material of the first conductive layer 2013 includes at least one of aluminum, iron, tin, magnesium, copper, silver, and gold. For example, the material of the first conductive layer 2013 includes copper.

[0175] In some examples, as shown in FIG. 19 , S10 (forming a first conductive layer 2013 on the array substrate 10 ) includes: S11 to S12 .

[0176] S11 , placing the first mask plate 1001 on one side of the array substrate 10 .

[0177] The orthographic projection of the first opening 1011 of the first mask 1001 on the array substrate 10 covers the first area 101 and the second area 102 .

[0178] S12 , forming a first conductive layer 2013 through the first opening 1011 .

[0179] For example, a first rate is used (for example, the first rate is ) The cathode 21 material is evaporated onto the array substrate 10 until the thickness of the cathode 21 material reaches a first preset thickness (for example, the first preset thickness can be a designed thickness).

[0180] As shown in FIG. 18 , S20 , a second conductive layer 2014 is formed on a side of the first conductive layer 2013 away from the array substrate 10 .

[0181] The orthographic projection of the second conductive layer 2014 on the array substrate 10 coincides with the orthographic projection of the third sub-portion 2015 on the array substrate 10 . The second conductive layer 2014 and the third sub-portion 2015 form the first sub-portion 2011 .

[0182] Exemplarily, the material of the second conductive layer 2014 includes at least one of aluminum, iron, tin, magnesium, copper, silver, and gold. For example, the material of the second conductive layer 2014 includes copper.

[0183] For example, the material of the second conductive layer 2014 may be the same as that of the first conductive layer 2013 , which can improve the identity of the display panel materials and reduce the manufacturing cost of the display panel.

[0184] In some examples, S20 (forming the second conductive layer 2014 on a side of the first conductive layer 2013 away from the array substrate 10 ) includes S21 .

[0185] Exemplarily, as shown in FIG20 , S21 includes S211 to S213 .

[0186] S211 , shielding the edge region 2001 of the first opening 1011 of the first mask plate 1001 .

[0187] S212 , placing the first mask plate 1001 that blocks the edge area 2001 on a side of the first conductive layer 2013 away from the array substrate 10 .

[0188] The orthographic projection of the first opening 1011 of the first mask 1001 on the array substrate 10 covers the first region 101 and the second region 102 , and the orthographic projection of the edge region 2001 on the array substrate 10 covers the second region 102 and exposes the first region 101 .

[0189] S213 , forming a second conductive layer 2014 through the first opening 1011 .

[0190] Exemplarily, the cathode 21 material is evaporated at a second rate until the cathode 21 material reaches a second preset thickness (for example, the second preset thickness may be a designed thickness).

[0191] For example, the second rate can be equal to the first rate, for example, the first rate and the second rate are both

[0192] In some other examples, S20 (preparing the second conductive layer 2014 on the first conductive layer 2013 ) includes S22 .

[0193] Exemplarily, as shown in FIG. 21 , S22 includes S221 to S224 .

[0194] S221 , forming a first metal suppression layer 301 on a side of the first conductive layer 2013 away from the array substrate 10 ;

[0195] The orthographic projection of the first metal inhibition layer 301 on the array substrate 10 covers the second region 102 and exposes the first region 101 .

[0196] Exemplarily, the material of the first metal suppression layer 301 may include a conductor patterning material (CPM), which is a material that is selectively deposited only on the cathode 21 material. That is, in areas with the conductor patterning material, the cathode 21 material will be difficult to adhere to, and in areas without the conductor patterning material, the cathode 21 material can adhere.

[0197] Exemplarily, S221 (forming the first metal inhibition layer 301 on the side of the first conductive layer 2013 away from the array substrate 10 ) includes: S2211 ˜ S2211 .

[0198] S2211 , blocking the central area of ​​the first opening of the first mask plate.

[0199] S2212 , placing a first mask plate for shielding the central area on a side of the first conductive layer away from the array substrate 10 .

[0200] The orthographic projection of the first opening of the first mask on the array substrate 10 covers the first area and the second area, and the orthographic projection of the central area on the array substrate 10 covers the first area and exposes the second area.

[0201] S2213 , forming a first metal inhibition layer through the first opening.

[0202] Alternatively, illustratively, S221 (forming the first metal inhibition layer 301 on the side of the first conductive layer 2013 away from the array substrate 10 ) includes: S2214 to S2215 .

[0203] S2214 , placing a sixth mask plate on a side of the first conductive layer away from the array substrate; an orthographic projection of the sixth opening of the sixth mask plate on the array substrate 10 covers the second area and exposes the first area.

[0204] S2215 , forming a first metal inhibition layer through the sixth opening.

[0205] As shown in FIG. 21 , S222 , placing the first mask plate 1001 on a side of the first conductive layer 2013 away from the array substrate 10 .

[0206] The orthographic projection of the first opening 1011 on the array substrate 10 covers the first area 101 and the second area 102 .

[0207] As shown in FIG. 21 , at S223 , a second conductive layer 2014 is formed through the first opening 1011 and the first metal inhibition layer 301 .

[0208] The orthographic projection of the first metal inhibition layer 301 on the array substrate 10 covers the second area 102 and exposes the first area 101, so that the cathode 21 material is deposited less or even not at all in the second area 102. In other words, the cathode 21 material does not form a continuous layered structure on the first metal inhibition layer 301, and the cathode 21 material forms a continuous layered structure in the area without the first metal inhibition layer 301.

[0209] As shown in FIG. 21 , S224 , the first metal inhibition layer 301 is removed.

[0210] The cathode layer 201 can also be patterned using a conductive pattern material. For example, the orthographic projection of the cathode layer 201 on the array substrate 10 partially overlaps with the orthographic projection of the light-emitting layer 221 on the array substrate 10. That is, a portion of the light-emitting layer 221 is free of the cathode layer 201, and light emitted from the light-emitting layer 221 can be emitted from the light-emitting device 20 from this portion, thereby improving the light transmittance of the cathode layer 201.

[0211] When the patterned cathode layer 201 is applied to the field of under-screen technology, the patterned cathode layer 201 has a high light transmittance, and most of the external light can be incident on the functional devices in the field of under-screen technology (such as front camera components, under-screen fingerprint components, 3D face recognition components, iris recognition components, proximity sensors, etc. that can realize specific functions), thereby improving the sensitivity of the functional devices.

[0212] In some other embodiments, as shown in FIG. 22 , S20 (preparing the second conductive layer 2014 on the first conductive layer 2013 ) includes S23 .

[0213] As shown in FIG. 22 , illustratively, S23 includes: S231 to S233 .

[0214] S231, forming a metal promotion layer 401 on the first conductive layer 2013;

[0215] The orthographic projection of the metal promotion layer 401 on the array substrate 10 covers the first area 101 and exposes the second area 102 .

[0216] Exemplarily, the thickness of the metal promotion layer 401 is less than that of the first conductive layer 2013 , that is, the metal promotion layer 401 is thinner, which can reduce the thickness of the light-emitting device 20 , thereby reducing the thickness of the display panel 100 , which is conducive to making the display device 1000 lighter and thinner.

[0217] Illustratively, S231 (forming the metal promotion layer 401 on the first conductive layer 2013) includes: S2311 to S2313.

[0218] S2311, covering an edge area of ​​a first opening of a first mask plate;

[0219] S2312: Place a first mask plate for shielding the edge area on a side of the first conductive layer away from the array substrate.

[0220] The orthographic projection of the first opening of the first mask plate on the array substrate covers the first area and the second area, and the orthographic projection of the edge area on the array substrate covers the second area and exposes the first area;

[0221] S2313, forming a metal promotion layer through the first opening.

[0222] Alternatively, illustratively, S231 (forming the metal promotion layer 401 on the first conductive layer 2013) includes: S2314 to S2315.

[0223] S2314, placing a second mask plate on a side of the first conductive layer 2013 away from the array substrate 10;

[0224] The orthographic projection of the second opening of the second mask plate on the array substrate covers the first area and exposes the second area.

[0225] S2315 , forming a metal promotion layer 401 through the second opening.

[0226] As shown in FIG. 22 , S232 , placing the first mask plate 1001 on a side of the first conductive layer 2013 and the metal promotion layer 401 away from the array substrate 10 .

[0227] The orthographic projection of the first opening 1011 of the first mask 1001 on the array substrate 10 covers the second area 102 and the second area.

[0228] As shown in FIG. 22 , in step S233 , a second conductive layer 2014 is formed through the first opening 1011 and the metal promotion layer 401 .

[0229] The metal promotion layer 401 is configured such that the orthographic projection of the second conductive layer 2014 on the array substrate 10 is located in the first region 101 and the second region 102 is exposed.

[0230] In some other examples, S20 (forming the second conductive layer 2014 on a side of the first conductive layer 2013 away from the array substrate 10 ) includes S24 .

[0231] Exemplarily, as shown in FIG. 23 , S24 includes S241 to S242 .

[0232] S241, placing the second mask plate 1002 on a side of the first conductive layer 2013 away from the array substrate 10;

[0233] The orthographic projection of the second opening 1012 of the second mask 1002 on the array substrate 10 covers the first region 101 and exposes the second region 102 .

[0234] S242 , preparing a second conductive layer 2014 using a second mask plate 1002 .

[0235] Exemplarily, the cathode 21 material is evaporated at a second rate until the cathode 21 material reaches a second preset thickness (for example, the second preset thickness may be a designed thickness).

[0236] In some other embodiments, S200 (forming the first sub-portion 2011 in the first region 101 and forming the second sub-portion 2012 in the second region 102 ) includes: S30 to S40 .

[0237] As shown in FIG. 24 , S30 , a first sub-portion 2011 is formed in the first region 101 .

[0238] In some examples, as shown in FIG. 25 , S30 (forming the first sub-portion 2011 in the first region 101 ) includes: S31 to S32 .

[0239] S31 , placing the third mask plate 1003 on one side of the array substrate 10 .

[0240] The third mask 1003 has a third opening area 1013 . The orthographic projection of the third opening area 1013 on the array substrate 10 covers the first area 101 and exposes the second area 102 .

[0241] Exemplarily, the edge region 2001 of the first opening 1011 of the first mask 1001 is blocked, and the blocked first mask 1001 serves as the third mask 1003 , and the unblocked region of the first opening 1011 forms the third opening region 1013 .

[0242] Alternatively, illustratively, the second mask plate 1002 directly serves as the third mask plate 1003 , and the second opening 1012 of the second mask plate 1002 forms a third opening region 1013 .

[0243] S32 , forming a first sub-portion 2011 through the third opening area 1013 .

[0244] For example, a third rate is used (for example, the third rate is ) The cathode 21 material is evaporated onto the array substrate 10 until the thickness of the cathode 21 material reaches a third preset thickness (for example, the third preset thickness can be a designed thickness).

[0245] In some other examples, as shown in FIG. 26 , S30 (the first region 101 forms the first sub-portion 2011 ) includes: S33 to S35 .

[0246] As shown in FIG. 26 , S33 , forming a second metal suppression layer 302 on the array substrate 10 ;

[0247] The orthographic projection of the second metal inhibition layer 302 on the array substrate 10 covers the second region 102 and exposes the first region 101. The material of the second metal inhibition layer 302 may include a conductor pattern material.

[0248] Illustratively, S33 (forming the second metal inhibition layer 302 on the array substrate 10 ) includes: S331 to S333 .

[0249] S331 , blocking the central area of ​​the first opening of the first mask plate.

[0250] S332 , placing a first mask plate for shielding the central area on a side of the first conductive layer away from the array substrate.

[0251] The orthographic projection of the first opening of the first mask on the array substrate covers the first area and the second area, and the orthographic projection of the central area on the array substrate covers the first area and exposes the second area.

[0252] S333 , forming a second metal inhibition layer through the first opening.

[0253] Alternatively, illustratively, S33 (forming the second metal inhibition layer 302 on the array substrate 10 ) includes: S334 to S335 .

[0254] S334 , placing a sixth mask plate on a side of the first conductive layer away from the array substrate.

[0255] An orthographic projection of the sixth opening of the sixth mask plate on the array substrate covers the second area and exposes the first area.

[0256] S335 , forming a second metal inhibition layer through the sixth opening.

[0257] As shown in FIG. 26 , at S34 , a first sub-portion 2011 is formed through the second metal inhibition layer 302 .

[0258] The orthographic projection of the second metal inhibition layer 302 on the array substrate 10 covers the second area 102 and exposes the first area 101, so that the cathode 21 material is deposited less or even not at all in the second area 102. In other words, the cathode 21 material does not form a continuous layered structure on the first metal inhibition layer 301, and the cathode 21 material forms a continuous layered structure only in the area without the first metal inhibition layer 301.

[0259] As shown in FIG. 26 , S35 , the second metal inhibition layer 302 is removed.

[0260] As shown in FIG. 27 , S40 , the second region 102 forms a second sub-portion 2012 .

[0261] For example, the conductivity of the first sub-section 2011 is greater than that of the second sub-section 2012, which can make the resistivity of the first sub-section 2011 smaller than that of the second sub-section 2012, thereby making the unit resistance of the first sub-section 2011 smaller than that of the second sub-section 2012, reducing the voltage difference between the second sub-section 2012 and the first sub-section, and improving the brightness uniformity of the display panel.

[0262] When the electrical conductivity of the first sub-portion 2011 is greater than that of the second sub-portion 2012, the thickness of the first sub-portion 2011 is equal to the thickness of the second sub-portion 2012, which enables a relatively uniform thickness of the cathode layer 201. When a user applies force to the cathode layer 201, the force applied to the cathode layer 201 is relatively uniform, which in turn enables a relatively uniform force applied to the light-emitting device 20. This improves the uniformity of the force applied to the light-emitting device 20, thereby extending the service life of the dimming display panel.

[0263] For example, the thickness of the first subsection 2011 is greater than the thickness of the second subsection 2012, so that the cross-sectional area of ​​the first subsection 2011 is greater than the cross-sectional area of ​​the second subsection 2012. As a result, the unit resistance of the first subsection 2011 is smaller than the unit resistance of the second subsection 2012, which can reduce the voltage difference between the first subsection 2011 and the second subsection 2012 and improve the brightness uniformity of the display panel.

[0264] In some examples, as shown in FIG. 28 , S40 (forming the second sub-portion 2012 in the second region 102 ) includes: S41 to S42 .

[0265] S41 , placing the fourth mask plate 1004 on one side of the array substrate 10 .

[0266] The fourth mask 1004 has a fourth opening area 1014 . The orthographic projection of the fourth opening area 1014 on the array substrate 10 covers the second area 102 and exposes the first area 101 .

[0267] Illustratively, the central area 2002 of the first opening 1011 of the first mask 1001 is blocked, and the blocked first mask 1001 serves as the fourth mask 1004 , and the unblocked area of ​​the first opening 1011 forms the fourth opening area 1014 .

[0268] Alternatively, illustratively, the sixth mask plate directly serves as the fourth mask plate 1004 , and the sixth opening of the sixth mask plate forms the fourth opening region 1014 .

[0269] S42 , forming a second sub-portion 2012 through the fourth opening area 1014 .

[0270] For example, the fourth rate is used (for example, the fourth rate is ) The cathode 21 material is evaporated onto the array substrate 10 until the thickness of the cathode 21 material reaches a fourth preset thickness (for example, the fourth preset thickness can be a designed thickness).

[0271] In the case where the thickness of the first sub-section 2011 is greater than the thickness of the second sub-section 2012, the third rate may be greater than the fourth rate, for example, the third rate is The fourth rate is

[0272] In some other examples, as shown in FIG. 29 , S40 (forming the second sub-portion 2012 in the second region 102 ) includes: S43 to S45 .

[0273] As shown in FIG. 29 , S43 , forming a third metal suppression layer 303 on the array substrate 10 ;

[0274] The orthographic projection of the third metal inhibition layer 303 on the array substrate 10 covers the first region 101 and exposes the second region 102. The material of the third metal inhibition layer 303 may include a conductor pattern material.

[0275] Illustratively, S43 (forming the third metal inhibition layer 303 on the array substrate 10 ) includes: S431 to S433 .

[0276] S431 , shielding an edge area of ​​a first opening of a first mask plate.

[0277] S432 , placing a first mask plate for shielding the edge area on a side of the first conductive layer away from the array substrate.

[0278] The orthographic projection of the first opening of the first mask on the array substrate 10 covers the first area and the second area, and the orthographic projection of the edge area on the array substrate covers the second area and exposes the first area.

[0279] S433 , forming a third metal inhibition layer through the first opening.

[0280] Alternatively, illustratively, S43 (forming the third metal inhibition layer 303 on the array substrate 10 ) includes: S434 to S435 .

[0281] S434 , placing a second mask plate on a side of the first conductive layer away from the array substrate.

[0282] The orthographic projection of the second opening of the second mask plate on the array substrate covers the first area and exposes the second area.

[0283] S435 , forming a third metal inhibition layer through the second opening.

[0284] As shown in FIG. 29 , at S44 , a second sub-portion 2012 is formed through the third metal inhibition layer 303 .

[0285] The orthographic projection of the third metal inhibition layer 303 on the array substrate 10 covers the first area 101 and exposes the second area 102, so that the cathode 21 material is deposited less or even not at all in the first area 101. In other words, the cathode 21 material does not form a continuous layered structure on the third metal inhibition layer 303, and the cathode 21 material only forms a continuous layered structure in the area without the third metal inhibition layer 303.

[0286] S45 , removing the third metal inhibition layer 303 .

[0287] It is understandable that the order of step S30 and step S40 can be interchanged, that is, S30 and S40 can be performed sequentially; or S40 can be performed first and then S30.

[0288] In some other embodiments, S200 (forming the first sub-portion 2011 in the first region 101 and forming the second sub-portion 2012 in the second region 102 ) includes S50 to S60 .

[0289] S50 , placing a fifth mask plate on one side of the array substrate 10 .

[0290] The fifth mask plate has a fifth opening area, and the fifth opening area is located in the display area.

[0291] Exemplarily, the edge region 2001 of the first opening 1011 of the first mask plate 1001 is blocked, and the blocked first mask plate 1001 serves as the fifth mask plate, and the unblocked region of the first opening 1011 forms the fifth opening region.

[0292] Alternatively, illustratively, the second mask plate 1002 directly serves as the fifth mask plate, and the second opening 1012 of the second mask plate 1002 forms a fifth opening region.

[0293] S60 , gradually increasing the area of ​​the fifth opening region, and evaporating cathode 21 material onto the array substrate 10 through the fifth opening region to form a cathode layer 201 .

[0294] For example, the area of ​​the fifth opening region increases gradually, for example, the increase ratio is 5% to 15%. For example, the increase ratio of the area of ​​the fifth opening region is 5%, 7%, 8%, 10%, 12% or 15%, which are not listed one by one in the embodiments of the present disclosure.

[0295] For example, when the shielded first mask 1001 is used as the fifth mask, the area of ​​the shielding region in the first opening 1011 needs to be reduced so as to increase the area of ​​the fifth opening region.

[0296] Alternatively, illustratively, when the second mask plate 1002 is directly used as the fifth mask plate, the mask plate needs to be replaced, and the opening area of ​​the replaced mask plate is increased.

[0297] For example, after the area of ​​the fifth opening region increases, the rate of evaporating the cathode 21 material onto the array substrate 10 can be reduced. For example, the rate of evaporating the cathode 21 material onto the array substrate 10 for the first time is Next, the area of ​​the fifth opening region is increased, and the rate of evaporating the cathode 21 material is reduced. For example, the rate of evaporating the material onto the array substrate 10 for the second time is Then, the area of ​​the fifth opening region is increased, and the rate of evaporating the cathode 21 material is reduced. For example, the rate of evaporating onto the array substrate 10 for the third time is:

[0298] In some embodiments, while S60 (gradually increasing the area of ​​the fifth opening region), the preparation method further includes S601.

[0299] S601 , gradually reducing the conductivity of the evaporated cathode 21 material.

[0300] For example, the conductivity gradient of the cathode layer 201 decreases, for example, by a ratio of 5% to 15%. For example, the conductivity of the cathode layer 201 decreases by a ratio of 5%, 7%, 8%, 10%, 12%, or 15%, which are not listed in the embodiments of the present disclosure.

[0301] In some examples, the cathode 21 material includes a host material and a dopant material. The electrical conductivity of the host material is greater than or less than that of the dopant material.

[0302] Exemplarily, the electrical conductivity of the host material is greater than that of the dopant material, and the ratio of the host material to the dopant material is gradually reduced.

[0303] Alternatively, illustratively, the electrical conductivity of the host material is lower than that of the doping material, and the ratio of the host material to the doping material is gradually increased.

[0304] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0305] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel having a display area, the display panel comprising: An array substrate; A cathode layer is arranged on the array substrate; the cathode layer includes a first sub-section and a second sub-section surrounding the first sub-section, and the first sub-section and the second sub-section are both located in the display area; wherein the unit length resistance of the first sub-section is less than the unit length resistance of the second sub-section.

2. The display panel according to claim 1, wherein: The thickness of the first sub-portion is greater than the thickness of the second sub-portion.

3. The display panel according to claim 2, wherein: The cathode layer comprises: A first conductive layer is provided on the array substrate; the first conductive layer is located in the display area; the first conductive layer includes a third sub-portion and a second sub-portion surrounding the third sub-portion; The second conductive layer is arranged on a side of the first conductive layer away from the array substrate; the orthographic projection of the second conductive layer on the array substrate coincides with the orthographic projection of the third sub-section on the array substrate; wherein the second conductive layer and the third sub-section form the first sub-section.

4. The display panel according to claim 3, wherein: The display panel further includes: A plurality of light-emitting devices are arranged on the array substrate; along a direction perpendicular to the array substrate and away from the array substrate, the light-emitting devices include a stacked light-emitting functional layer and a cathode, the cathode is located on the cathode layer, and the orthographic projection of the second conductive layer on the array substrate partially overlaps with the orthographic projection of the plurality of light-emitting functional layers on the array substrate.

5. The display panel according to claim 1, wherein: The thickness of the cathode layer gradually decreases from the center of the display area to the boundary of the display area.

6. The display panel according to any one of claims 2 to 4, wherein: The material of the first sub-portion includes at least one of aluminum, iron, tin, magnesium, copper, silver and gold, and / or the material of the second sub-portion includes at least one of aluminum, iron, tin, magnesium, copper, silver and gold.

7. The display panel according to claim 1, wherein: The electrical conductivity of the first subsection is greater than the electrical conductivity of the second subsection.

8. The display panel according to claim 7, wherein: The material of the first sub-portion includes at least one of copper, silver, and gold, and the material of the second sub-portion includes at least one of aluminum, iron, tin, and magnesium.

9. The display panel according to claim 1, wherein: The conductivity of the cathode layer gradually decreases from the center of the display area to the boundary of the display area.

10. The display panel according to claim 9, wherein: The material of the cathode layer includes a main material and a doping material; The electrical conductivity of the main material is greater than the electrical conductivity of the doping material, and the ratio of the main material to the doping material decreases from the center of the display area to the boundary of the display area; or, The electrical conductivity of the main material is less than that of the doping material, and the ratio of the main material to the doping material increases from the center of the display area to the boundary of the display area.

11. The display panel according to any one of claims 7 to 10, wherein: The thickness of the first sub-portion is greater than or equal to the thickness of the second sub-portion.

12. A display device, comprising: A display panel as claimed in any one of claims 1 to 11.

13. A method for preparing a display panel, wherein: The display panel has a display area, and the preparation method includes: Providing an array substrate; the array substrate comprises a first area and a second area surrounding the first area, and the first area and the second area are both located in the display area; A first subsection is formed in the first region, and a second subsection is formed in the second region; the second subsection is connected to the first subsection to form a cathode layer; wherein the resistance per unit length of the first subsection is smaller than the resistance per unit length of the second subsection.

14. The preparation method according to claim 13, wherein: The forming of the first subsection in the first region and the forming of the second subsection in the second region comprises: forming a first conductive layer on the array substrate; the first conductive layer comprising a third sub-portion located in the first area and the second sub-portion located in the second area; A second conductive layer is formed on a side of the first conductive layer away from the array substrate; the orthographic projection of the second conductive layer on the array substrate coincides with the orthographic projection of the third sub-portion on the array substrate, and the second conductive layer and the third sub-portion form the first sub-portion.

15. The preparation method according to claim 14, wherein: The forming of a first conductive layer on the array substrate comprises: Placing a first mask plate on one side of the array substrate; an orthographic projection of a first opening of the first mask plate on the array substrate covers the first area and the second area; The first conductive layer is formed through the first opening.

16. The preparation method according to claim 14 or 15, wherein: The forming of a second conductive layer on a side of the first conductive layer away from the array substrate comprises: Covering the edge area of ​​the first opening of the first mask plate; The first mask plate shielding the edge area is placed on a side of the first conductive layer away from the array substrate; the orthographic projection of the first opening on the array substrate covers the first area and the second area, and the orthographic projection of the edge area on the array substrate covers the second area and exposes the first area; The second conductive layer is formed through the first opening.

17. The preparation method according to claim 14 or 15, wherein: The forming of a second conductive layer on a side of the first conductive layer away from the array substrate comprises: A first metal inhibition layer is formed on a side of the first conductive layer away from the array substrate; the first metal inhibition layer The orthographic projection on the array substrate covers the second area and exposes the first area; Placing the first mask plate on a side of the first conductive layer away from the array substrate; the orthographic projection of the first opening on the array substrate covers the first area and the second area; forming a second conductive layer through the first opening and the first metal inhibition layer; The first metal inhibition layer is removed.

18. The preparation method according to claim 14 or 15, wherein: The forming of a second conductive layer on a side of the first conductive layer away from the array substrate comprises: forming a metal promotion layer on the first conductive layer; the orthographic projection of the metal promotion layer on the array substrate covers the first area and exposes the second area; Placing the first mask plate on a side of the first conductive layer and the metal promotion layer away from the array substrate; the orthographic projection of the first opening on the array substrate covers the first area and the second area; A second conductive layer is formed through the first opening and the metal promotion layer; the metal promotion layer is configured so that an orthographic projection of the second conductive layer on the array substrate is located in the first region and the second region is exposed.

19. The preparation method according to claim 14 or 15, wherein: The forming of a second conductive layer on a side of the first conductive layer away from the array substrate comprises: Placing a second mask plate on a side of the first conductive layer away from the array substrate; an orthographic projection of a second opening of the second mask plate on the array substrate covers the first area and exposes the second area; The second conductive layer is formed through the second opening.

20. The preparation method according to claim 13, wherein: The forming of the first sub-section in the first region comprises: Placing a third mask plate on one side of the array substrate; the third mask plate has a third opening area, and the orthographic projection of the third opening area on the array substrate covers the first area and exposes the second area; The first sub-portion is formed by the third opening region.

21. The preparation method according to claim 13, wherein: The forming of the first sub-section in the first region comprises: forming a second metal inhibition layer on the array substrate; an orthographic projection of the second metal inhibition layer on the array substrate covers the second area and exposes the first area; forming a first sub-portion by the second metal inhibition layer; The second metal inhibition layer is removed.

22. The preparation method according to claim 20 or 21, wherein: The forming of the second sub-section in the second area comprises: Placing a fourth mask plate on one side of the array substrate; the fourth mask plate has a fourth opening area, and the orthographic projection of the fourth opening area on the array substrate covers the second area and exposes the first area; The second sub-portion is formed by the fourth opening area; wherein the thickness of the first sub-portion is greater than the thickness of the second sub-portion, and / or the electrical conductivity of the first sub-portion is greater than the electrical conductivity of the second sub-portion.

23. The preparation method according to claim 20 or 21, wherein: The forming of the second sub-section in the second area comprises: forming a third metal inhibition layer on the array substrate; an orthographic projection of the third metal inhibition layer on the array substrate covers the first area and exposes the second area; A second sub-section is formed by the third metal inhibition layer; wherein the thickness of the first sub-section is greater than the thickness of the second sub-section, and / or the conductivity of the first sub-section is greater than the conductivity of the first sub-section; The third metal inhibition layer is removed.

24. The preparation method according to claim 13, wherein: The forming of the first subsection in the first region and the forming of the second subsection in the second region comprises: Placing a fifth mask plate on one side of the array substrate; the fifth mask plate has a fifth opening area, and the fifth opening area is located in the display area; The area of ​​the fifth opening region is gradually increased, and a cathode material is evaporated onto the array substrate through the fifth opening region to form a cathode layer; wherein the thickness of the cathode layer gradually decreases from the center of the display region to the boundary of the display region.

25. The preparation method according to claim 24, wherein: While increasing the area of ​​the fifth opening region, the preparation method further comprises: Gradually reduce the conductivity of the evaporated cathode material; wherein the cathode material includes a main material and a doping material, and when the conductivity of the main material is greater than the conductivity of the doping material, gradually reduce the ratio of the main material to the doping material; when the conductivity of the main material is less than the conductivity of the doping material, gradually increase the ratio of the main material to the doping material.

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