Device and method for controlling the pulse duration of a laser or another light or radiation emitting device

Abstract

A device (1) with an implemented control loop for controlling the pulse duration of a laser or another light or radiation emitting device shall be provided. The device (1) comprises a pulse generator with an input clock (4), a delay cell (6) and a pulse combining element (8), the input clock (4) providing a clock pulse (CLK) and the delay cell providing a delayed clock pulse (CLKdel), both pulses are combined to a pulse signal (Vpulse), the device (1) further comprising a loop controller (10), a driving current generator (12) and a sensing current generator (14), the driving current generator (12) and the sensing current generator (14) are triggered by VA device (1) with an implemented control loop for controlling the pulse duration of a laser or another light or radiation emitting device shall be provided. The device (1) comprises a pulse generator with an input clock (4), a delay cell (6) and a pulse combining element (8), the input clock (4) providing a clock pulse (CLK) and the delay cell providing a delayed clock pulse (CLKdel), both pulses are combined to a pulse signal (Vpulse), the device (1) further comprising a loop controller (10), a driving current generator (12) and a sensing current generator (14), the driving current generator (12) and the sensing current generator (14) are triggered by Vpulse to provide a driving current pulse to the laser and a sensing current pulse to the loop controller (10) respectively, based on which combined with a reference input the delay cell (6) is controlled by the loop controller (10). to provide a driving current pulse to the laser and a sensing current pulse to the loop controller (10) respectively, based on which combined with a reference input the delay cell (6) is controlled by the loop controller (10).

Description

[0001] 2023PF00500 - 1 - DEVICE AND METHOD FOR CONTROLLING THE PULSE DURATION OF A LASER OR ANOTHER LIGHT OR RADIATION EMITTING DEVICE DESCRIPTION TECHNICAL FIELD The invention relates to a driver for a laser or another light or radiation emitting device, especially to the control of a short pulse width of a laser driver, particularly of a VCSEL driver. It also relates to a corresponding method of controlling the pulse duration of a laser or another light or radiation emitting device. BACKGROUND Within the meaning of this application, a laser is understood to be a laser (a device for light amplification by stimulated emission of radiation), in particular a VCSEL laser, but also any other light-emitting or radiation-emitting device. Specific optical sensors applications (e.g., time of flight (ToF)sensors) require the generation of very short optical pulses by a light source. A ToF device is used for measuring the three-dimensional depth by sensing the time it takes for a light pulse to travel from a light source to a reflective object or target and back to a light detector. A laser, in particular a VCSEL (vertical-cavity surface-emitting laser) is often the preferred light source for this application. In general, the pulse duration should be considerably shorter than the expected time-of-flight ToF to measure the latter accurately. For example, in one nanosecond, light travels approximately 30 centimeters. Consequently, to measure distances shorter than this, a laser driver compatible with VCSELs with sub-nanosecond pulses is needed. A straightforward way to implement such pulses would be to use a clock with a period twice the pulse duration. Such solution 2023PF00500 - 2 - would require a very fast clock, with a consequent high-power dissipation and a stability of the pulse duration that would be limited by the stability of the clock duty cycle. The need of a specified width stability over process, time, and external factors requires the implementation of a control loop inside a device for controlling the short pulse width of a laser driver. SUMMARY One objective underlying the present invention is to provide a device for controlling the pulse duration of a laser or another light or radiation emitting device. In particular, limiting the pulse duration by the stability of the duty cycle of a very fast clock shall be avoided. A corresponding method of controlling the pulse duration of a laser or another light or radiation emitting device shall also be provided. Up to this point and further below the expression ‘is connected to’ is preferably to be understood as two elements are connected if they are wired or signal-wise connected. The invention is based on the consideration that a closed control loop can stabilize the pulse width of combined pulses of a clock pulse and a delayed replica of the clock pulse over external variables. Furthermore, the pulse width can be trimmable over a wide range, if the delay cell providing the delayed replica of the clock pulse is controlled by a loop controller that takes as input a reference value that is used as a set-point to define the pulse width and a replica of the driving current pulse triggered by the combined pulse signal, wherein the replica of the driving current pulse is averaged and compared to the reference. According to claim 1, the device-related objective is met by device comprising a pulse generator, wherein the pulse generator comprises an input clock, a delay cell and a pulse combining element, wherein the input clock is configured to 2023PF00500 - 3 - provide a clock pulse (CLK) and the delay cell is configured to provide a delayed clock pulse (CLKdel), which is a replica of the clock pulse (CLK), and wherein the pulse combining element is configured to combine the clock pulse (CLK) and the delayed clock pulse (CLKdel) to a pulse signal (Vpulse), the device further comprising a loop controller, a driving current generator and a sensing current generator, wherein the device is connected to a laser, wherein the sensing current generator is configured to be triggered by the pulse signal (Vpulse) and to provide a sensing current pulse (Isense) to the loop controller (10) which is connected to the sensing current generator, wherein the driving current generator is configured to be triggered by the signal pulse (Vpulse) and to provide a driving current pulse (Ipulse) to the laser or other light or radiation emitting device and wherein the loop controller is connected to a reference input as well as to the delay cell and configured to control the delay cell, and wherein the reference input is configured to provide a reference value to the loop controller. This way, a control loop for obtaining a specified pulse width with stability over process, time and external factors is established in a cost- and size-efficient way by using the combination of a clock pulse and a delayed replica of it, the resulting pulse width of the combined pulse signal Vpulsebeing equal to the delay between both underlying signals. The driving current pulse Ipulserunning through the laser, triggering the laser to emit a short light pulse, is generated by a driving current generator, which is triggered by the pulse signal Vpulse. The sensing current generator is also triggered by the pulse signal Vpulseto provide a replica Isenseof the driving current pulse Ipulseto the loop controller. By controlling the delay by a loop controller 2023PF00500 - 4 - that takes as input a reference value that is used as a set- point to define the pulse duration and the sensing current pulse Isensethat is averaged and compared to the reference, the pulse width of the pulse signal Vpulsecan be controlled precisely. Since a scaled replica of the driving current pulse Ipulseis fed through the control loop, when the driving current generator is triggered by the pulse signal Vpulsethe stability of the pulse width is increased by the rebalancing character of the control loop. The control loop senses the duty cycle of the generated pulses and regulates the delay that defines the pulse width based on the input reference value REF. This way the device can generate very short current pulses (sub-nanosecond) to drive a laser or another light or radiation emitting device in a power efficient way synchronously to an input clock. Generating a shorter and stable in duration laser pulse allows to achieve higher accuracy and definition in a distance measurement. This is particularly important for measurements over short distances. The according method is defined in claim 7. In a preferable embodiment the reference input is or comprises bandgap voltage reference generator or a current reference generator. Thus, the trim current Itrimcan be controlled precisely and cost effective. Preferably, the laser driver is a vertical-cavity surface- emitting laser (VCSEL) driver. Due to their small size and low cost a whole system for generating short light pulses can be produced in a cost and size efficient way. In an advantageous implementation the current ratio between the driving current generator and the sensing current generator is N:1, with N > 1. This way the current flow through the control loop can be reduced beforehand, this allows to reach the desired optical power of the light pulses without a waste of power in the control loop. Higher values of N help to increase the power efficiency also in the case of high-power pulses. 2023PF00500 - 5 - Advantageously, a resistor is connected in series between the sensing current generator and the reference input. Since the width of the pulse signal Vpulsecorresponds with the resistance of the resistor (cf. the equation in the detailed description of Fig. 2), the range over which the pulse width is trimmable can be modified by implementing different resistors with different resistances. In an expedient embodiment the loop controller comprises a capacitor Csense, an operational amplifier and a reference voltage input VREF, wherein the delay cell, the pulse combining element, the driving current generator Mvcsel, the sensing current generator Msenseand the operational amplifier are connected in cascade and form a control loop. In the control loop the output of the operational amplifier is connected to the delay cell and configured to provide a control voltage Vctrlto the delay cell. The reference current input providing the trim current Itrimis connected to a node of the control loop between the sensing current generator and the operational amplifier. The capacitor Csenseis connected to the same node of the control loop and configured to be charged by the trim current Itrimand discharged by the sensing current pulse Isenseprovided by the sensing current generator Msense. A first input of the operational amplifier being connected to the reference voltage input Vrefand a second input being connected to the sensing current generator Msense. This way the reference input can provide a trim current Itrimto the control loop, which charges the capacitor Csense, wherein the driving current pulse Isensefrom the sensing current generator discharges the capacitor. When the average current from the sensing current pulse Isenseis equal to the average current Itrimfrom the reference input, a sensing voltage Vsenseis provided to an input of an operational amplifier, the second input being the reference voltage input VREF. The operational amplifier provides a control voltage Vctrlto the delay cell triggering the generation of the delayed clock 2023PF00500 - 6 - pulse CLKdelwhich again is combined with the clock pulse CLK to create a new pulse signal Vpulse. Changing the value of the current Itrimwill result in the control loop to modify the control voltage Vctrland therefore the pulse width of Vpulseto rebalance the control loop. This architecture has the advantage that common electronic components being low in cost and size can be used for implementing a rebalancing control loop. The according method is defined in claim 8. In terms of method, the invention relates to a method of controlling the pulse duration of a laser or another light or radiation emitting device with a device according to any one of the claims 1 to 6, wherein the input clock provides a clock pulse CLK and the delay cell provides a delayed clock pulse CLKdel, the delayed clock pulse CLKdelbeing a delayed replica of the clock pulse CLK. A pulse combining element combines the clock pulse CLK and the delayed clock pulse CLKdelto a pulse signal Vpulse, the pulse width of the resulting pulse signal Vpulsebeing a result of the delay between the clock pulse CLK and the clock pulse CLKdel. The pulse signal Vpulsetriggers the driving current generator MVCSELto provide a driving current pulse Ipulseto the laser. The pulse signal Vpulsealso triggers the sensing current generator Msenseto provide a sensing current pulse Isenseto the loop controller . The loop controller controls the delay cell based on an input from the reference input and the sensing current pulse Isenseand consequently regulates the delay of the delayed clock pulse CLKdel. In a preferred embodiment a device according to claim 6 is used for controlling the pulse duration of a laser or another light or radiation emitting device. In this case the reference input provides a trim current Itrimto the control loop, wherein the trim current Itrimcharges the capacitor Csense. The sensing current pulse Isensefrom the sensing current generator Msensedischarges the capacitor Csense. 2023PF00500 - 7 - When the average current from the sensing current pulse Isenseis equal to the average current Itrimfrom the reference input, a sensing voltage Vsenseis provided to a first input of the operational amplifier, the second input of the operational amplifier being a reference voltage input. The output of the operational amplifier provides a control voltage Vctrlto the delay cell triggering it to provide a new delayed clock pulse CLKdelto the pulse combining element, which combines the clock pulse CLK and the delayed clock pulse CLKdelto a new pulse signal Vpulse. What has been said with respect to the device may analogously be applied to the method, and therefore need not be repeated here. Device embodiments and details have a counterpart in the method and vice versa. These and other features, embodiments, objectives, and advantages of the invention will become apparent from the subsequent description. BRIEF DESCRIPTION OF THE DRAWINGS Exemplary embodiments of the invention are discussed below with reference to the accompanying drawings. FIG. 1 shows a schematic circuit of an exemplary device according to the invention for controlling the short pulse width of a laser driver. FIG. 2 shows a schematic circuit of a first exemplary embodiment of a device for controlling the short pulse width of a laser driver according to the present invention. FIG. 3 shows a schematic representation of the generation of the pulse signal Vpulseby combining a clock pulse and a delayed clock pulse. 2023PF00500 - 8 - Similar elements are designated with the same reference numerals throughout the description. DETAILED DESCRIPTION The device for controlling the short pulse width of a laser driver (in FIG. 1 the laser is a VCSEL laser referenced as VCSEL) shown in FIG. 1 as a schematic circuit comprises a pulse generator 2. The pulse generator 2 comprises an input clock 4 and delay cell 6. The input clock 4 provides a clock pulse CLK and the delay cell 6 provides a delayed clock pulse CLKdel, the delayed clock pulse CLKdelbeing a delayed replica of the clock pulse CLK. Both pulses are combined to generate a pulse signal Vpulse(cf. FIG. 3 for a schematic representation of the pulse signal generation). The combination of the clock pulses CLK and CLKdelis realized by a pulse combining element 8. Preferably, the pulse combining element 8 is a logical gate. Alternative pulse combining elements are, e.g., adders or multiplexers, but other pulse combining elements or circuits are also thinkable. In this embodiment the input clock 4 is connected to a first input of the pulse combining element 8 and the delay cell 6 is connected to a second input of the pulse combining element 8. The output of the pulse combining element 8 is connected to a driving current generator 12 and provides the pulse signal Vpulseto the driving current generator 12. The driving current generator 12 is connected to a laser VCSEL and generates a driving current pulse Ipulsethrough the VCSEL when triggered by the pulse signal Vpulse. The VCSEL is triggered by the driving current pulse Ipulseto emit a short light pulse. The sensing current generator 14 is connected to the loop controller 10 and configured to be triggered by the pulse signal Vpulseto provide a sensing current pulse Isenseto the loop controller 10. To control the delay cell 6 and consequently regulate the delay of the pulse CLKdelthat defines the width of the pulse signal Vpulse, the loop controller 10 is connected to the delay cell 6. The loop controller 10 controls the delay cell 2023PF00500 - 9 - 6 by providing a control signal Vctrlas indicated by the arrow at the end of the respective connection line in FIG. 1. The loop controller 10 takes as input a reference value REF that is used as a setpoint to define the width of the pulse signal Vpulseand the sensing current pulse Isensethat is averaged and compared to the reference value REF. A current ratio N:1 (with N > 1) between the driving current generator 12 and the sensing current generator 14 is introduced to give the possibility to have a higher peak current in the laser branch than in the control loop branch. This allows to reach the desired optical power without a waste of power in the control loop. FIG. 2 discloses an exemplary embodiment of a device for controlling the short pulse width of a VCSEL driver according to the present invention with a more detailed implementation of the loop controller 10. The loop controller 10 (which is shown in FIG. 1 in a generalized way) comprises a reference current generator acting as the reference input 18, a capacitor 20 and a resistor 26. The delay cell 6, a pulse combining element 8, the driving current generator 12, the sensing current generator 14 and the operational amplifier 22 are connected in cascade and form a control loop. The reference current generator provides a trim current Itrim. The sensing current pulse Isensefrom the sensing current generator 14, which is triggered by the pulse signal Vpulsewill discharge the capacitor 20 that is charged by the trim current Itrim. The steady state operation is reached when the average current provided by the sensing current generator Msenseis equal to the average current Itrim.When the steady state operation is reached, a sensing voltage Vsenseis provided to a first input of the operational amplifier 22, the second input being the reference voltage input 24. The operational amplifier 22 provides a control voltage to the delay cell 6, triggering the delay cell 6 to provide a delayed clock pulse CLKdelto the pulse combining element 8. Changing the value of the current Itrimwill result in the control loop to modify the control voltage Vctrland therefore 2023PF00500 - 10 - the pulse width tPLSto rebalance the control loop. The current Itrimacts as a reference for the control loop and defines the width of the pulse itself based on the following formula: In FIG. 3, the pulses are exemplarily shown each as a square or rectangular wave signal. Other forms of wave signals are also thinkable. The clock pulses CLK and consequently the delayed replica CLKdelare preferably square. The combination of the two pulses CLK and CLKdelresults in a pulse signal Vpulse, whose duty cycle is smaller than the ones of CLK and CLKdel. The smaller duty cycle of Vpulseis the result of the combination and therefore depends directly on the delay of the pulse CLKdelrelative to the pulse CLK. In other words, the pulse width of Vpulseis equal to the relative delay between CLK and CLKdel. Consequently, by controlling the variable delay cell 6, the pulse width of Vpulsecan be controlled precisely. Only if the delay between CLK and CLKdelis equal to their duty cycle, the resulting pulse signal Vpulseinhibits the same duty cycle as CLK and CLKdel.

[0002] 2023PF00500 - 11 - LIST OF REFERENCE SIGNS pulse generator 2 input clock 4 delay cell 6 pulse combining element 8 loop controller 10 driving current generator 12 sensing current generator 14 reference current input 18 capacitor 20 operational amplifier 22 reference voltage input 24 resistor 26 clock pulse CLK delayed clock pulse CLKdeldriving current pulse Ipulsesensing current pulse Isensetrim current ITrimreference value REF vertical-cavity surface-emitting laser VCSEL control voltage Vctrlpulse signal VPulsesense voltage Vsense

Claims

2023PF00500 - 12 - CLAIMS 1. Device (1) for controlling the pulse duration of a laser or another light or radiation emitting device comprising a pulse generator (2), wherein the pulse generator (2) comprises an input clock (4), a delay cell (6) and a pulse combining element (8), wherein the input clock (4) is configured to provide a clock pulse (CLK) and the delay cell (6) is configured to provide a delayed clock pulse (CLKdel), which is a replica of the clock pulse (CLK), and wherein the pulse combining element (8) is configured to combine (CLK) and (CLKdel) to a pulse signal (Vpulse), the device (1) further comprising a loop controller (10), a driving current generator (12) and a sensing current generator (14), and wherein the driving current generator (12) is connected to a laser or another light or radiation emitting device and configured to provide a driving current pulse to the laser or another light or radiation emitting device, wherein the driving current generator (12) is connected to the sensing current generator (12), wherein the driving current generator (12) and the sensing current generator (14) are configured to be triggered by the pulse signal (Vpulse), the sensing current generator (14) being connected to the loop controller (10) and configured to provide a sensing current pulse to the loop controller (10), wherein the loop controller (10) is connected to a reference input (18) as well as to the delay cell (6) and configured to control the delay cell (6), and wherein the reference input (18) is configured to provide a reference value (REF) to the loop controller (10).

2. Device (1) according to claim 1, wherein the laser or another light or radiation emitting device is a vertical- cavity surface-emitting laser (VCSEL) driver.

3. Device (1) according to any one of the preceding claims, wherein the reference input (18) is a bandgap voltage reference generator or a current reference generator.2023PF00500 - 13 - 4. Device (1) according to any one of the preceding claims, wherein a resistor (26) is connected in series between the sensing current generator (16) and the reference input (18).

5. Device (1) according to any one of the preceding claims, wherein the current ratio between the driving current generator (12) and the sensing current generator (14) is N:1, with N > 1.

6. Device (1) according to any one of the preceding claims, wherein the loop controller (10) comprises a capacitor (20), an operational amplifier (22) and a reference voltage input (24), and wherein the delay cell (6), the pulse combining element (8), the driving current generator (12), the sensing current generator (14) and the operational amplifier (22) are connected in cascade in the given order and form a control loop, wherein the output of the operational amplifier (22) is connected to the delay cell (6) and configured to provide a control voltage to the delay cell (6), and wherein the reference input (18) is connected to a node of the control loop between the sensing current generator (14) and the operational amplifier (22), and wherein the capacitor (20) is connected to the same node of the control loop and configured to be charged by the trim current provided by the reference current input (18) and discharged by the sensing current pulse provided by the sensing current generator (14), and wherein a first input of the operational amplifier (22) is connected to the reference voltage input (26) and a second input is connected to all the other circuits on that node..

7. Method of controlling the pulse duration of a laser or another light or radiation emitting device with a device (1) according to any one of the preceding claims, wherein the input clock (4) provides a clock pulse CLK and the delay cell (6) provides a delayed clock pulse (CLKdel), the delayed clock pulse (CLKdel) being a delayed replica of the clock pulse (CLK),2023PF00500 - 14 - wherein a pulse combining element (8) combines the clock pulse (CLK) and the delayed clock pulse (CLKdel) to a pulse signal (Vpulse), wherein the pulse signal (Vpulse) triggers the driving current generator (12) to provide a driving current pulse (Ipulse) to the laser or another light or radiation emitting device, the pulse signal (Vpulse) also triggers the sensing current generator (14) to provide a sensing current pulse to the loop controller (10), wherein the loop controller (10) controls the delay cell (6) based on an input from the reference input (18) and the sensing current pulse, the loop controller (10) consequently regulating the delay of the delayed clock pulse (CLKdel).

8. Method of controlling the pulse duration of a laser or another light or radiation emitting device according to claim 7 with a device (1) according to any of the claims 2 to 6, wherein the reference input (18) provides a trim current (Itrim) to the control loop, wherein the trim current (Itrim) charges the capacitor (20), wherein the sensing current pulse from the sensing current generator (14) discharges the capacitor (20), and wherein when the average current from the sensing current pulse is equal to the average current (Itrim) from the reference input (18), a sensing voltage (Vsense) is provided to a first input of the operational amplifier (22), the second input of the operational amplifier (22) being a reference voltage input (26), wherein the output of the operational amplifier (22) provides a control voltage (Vctrl) to the delay cell (6) triggering the delay cell (6) to provide a delayed clock pulse (CLKdel) to the pulse combining element (8), which combines the clock2023PF00500 - 15 - pulse (CLK) and the delayed clock pulse (CLKdel) to a new pulse signal Vpulse.

Images