Passive electronic component

Abstract

A passive electronic component 1A comprises: a substrate 10 having a first main surface 10a and a second main surface 10b facing each other in a first direction D1; and a plurality of capacitors 20 provided on the first main surface 10a side with respect to the substrate 10. The plurality of capacitors 20 include a first capacitor 20a and a second capacitor 20b separated from the first capacitor 20a in a second direction D2 perpendicular to the first direction D1. The first capacitor 20a includes a first capacitance formation part 21a including a first internal electrode layer 22a, a first dielectric layer 23a, and a second internal electrode layer 22b which are stacked in order from the substrate 10 side in the first direction D1. The second capacitor 20b has a second capacitance formation part 21b including a third internal electrode layer 22c, a second dielectric layer 23b, and a fourth internal electrode layer 22d which are stacked in order from the substrate 10 side in the first direction D1. At least a part of the second internal electrode layer 22b and at least a part of the third internal electrode layer 22c are in contact with the surface on the opposite side of the first dielectric layer 23a to the substrate 10.

Description

Passive Electronic Components

[0001] The present invention relates to passive electronic components.

[0002] Patent Document 1 discloses an electronic component having a plurality of conductor layers stacked on a substrate, the electronic component having a first capacitor formed by two of the plurality of conductor layers adjacent in the stacking direction and a dielectric film located between them, and a second capacitor formed by two of the plurality of conductor layers adjacent in the stacking direction and a dielectric film located between them, wherein the thicknesses of the dielectric film constituting the first capacitor and the dielectric film constituting the second capacitor are different from each other.

[0003] Japanese Patent Application Laid-Open No. 2022-130066

[0004] The electronic component described in Patent Document 1, for example, electronic component 1 described in FIG. 2 of Patent Document 1, has multiple capacitors, including a first capacitor formed by conductor pattern 25, first dielectric film 4, and conductor pattern 31, a second capacitor formed by conductor pattern 26, second dielectric film 5, and conductor pattern 32, and a third capacitor formed by conductor pattern 25, first dielectric film 4, second dielectric film 5, and conductor pattern 33.

[0005] The method for manufacturing the electronic component 1 described in FIG. 2 of Patent Document 1 is shown in FIGS.

[0006] In manufacturing the electronic component 1 shown in FIG. 2 of Patent Document 1, in order to form the second dielectric film 5 on the conductor pattern 26, the first dielectric film 4 previously formed on the conductor pattern 26 is removed by patterning, thereby exposing the conductor pattern 26, as shown in FIG. 9 of Patent Document 1. However, when the first dielectric film 4 formed on the conductor pattern 26 is removed by patterning, an impurity layer, such as a metal oxide layer or a metal fluoride layer, is formed on the surface of the conductor pattern 26. When the second dielectric film 5 and the conductor pattern 32 are sequentially formed on the conductor pattern 26 with the impurity layer formed on the surface of the conductor pattern 26, as shown in FIGS. 11 and 12 of Patent Document 1, the dielectric loss tangent (tan δ) of the impurity layer formed on the surface of the conductor pattern 26 in the resulting second capacitor is increased. As a result, the electronic component 1 shown in FIG. 2 of Patent Document 1 suffers from increased power loss in the second capacitor, resulting in an inability to exhibit excellent electrical performance, particularly in terms of high-frequency characteristics.

[0007] Furthermore, when manufacturing the electronic component 1 shown in FIG. 2 of Patent Document 1, as shown in FIG. 10 of Patent Document 1, a conductor pattern 31 is formed on the first region 25A of the conductor pattern 25 via a first dielectric film 4. The conductor pattern 31 is composed of a laminate of a seed layer S and a plating layer P. When forming the conductor pattern 31, the seed layer S is first formed on the entire surface of the first dielectric film 4, and then a resist layer is patterned on the seed layer S so as to expose the seed layer S in the region where the conductor pattern 31 is to be formed (the region overlapping the first region 25A of the conductor pattern 25). Next, electrolytic plating is performed using the seed layer S as a power source to form a plating layer P on the seed layer S. The resist layer is then removed, and the seed layer S exposed on the surface (the seed layer S in the region where the plating layer P is not formed) is removed, thereby forming the conductor pattern 31 composed of a laminate of the seed layer S and the plating layer P, as shown in FIG. 10 of Patent Document 1. However, in the above method, a seed layer S is first formed on the first dielectric film 4 on which the conductor pattern 31 is not formed, for example, on the first dielectric film 4 covering the second region 25B of the conductor pattern 25, and then the seed layer S is removed. Therefore, an impurity layer is formed on the surface of the first dielectric film 4 covering the second region 25B of the conductor pattern 25 due to process damage caused by removing the seed layer S. When a second dielectric film 5 and a conductor pattern 33 are sequentially formed on the first dielectric film 4 with the impurity layer formed on the surface of the first dielectric film 4 covering the second region 25B of the conductor pattern 25, as shown in FIGS. 11 and 12 of Patent Document 1, the resulting third capacitor has a large dielectric loss tangent in the impurity layer formed on the surface of the first dielectric film 4. Therefore, the electronic component 1 shown in FIG. 2 of Patent Document 1 suffers from large power loss in the third capacitor, resulting in poor electrical performance, particularly in terms of high-frequency characteristics.

[0008] As described above, the electronic component described in Patent Document 1 has room for improvement in terms of being able to exhibit electrical performance with excellent high-frequency characteristics in a configuration having a plurality of capacitors.

[0009] The present invention has been made to solve the above problems, and has an object to provide a passive electronic component having a configuration with multiple capacitors that can exhibit electrical performance with excellent high-frequency characteristics.

[0010] A passive electronic component of the present invention comprises a substrate having a first main surface and a second main surface facing each other in a first direction, and a plurality of capacitors provided on the first main surface side of the substrate, wherein the plurality of capacitors include a first capacitor and a second capacitor spaced apart from the first capacitor in a second direction perpendicular to the first direction, the first capacitor having a first capacitance forming portion including a first internal electrode layer, a first dielectric layer, and a second internal electrode layer stacked in order from the substrate side in the first direction, the second capacitor having a second capacitance forming portion including a third internal electrode layer, a second dielectric layer, and a fourth internal electrode layer stacked in order from the substrate side in the first direction, and at least a portion of the second internal electrode layer and at least a portion of the third internal electrode layer are in contact with a surface of the first dielectric layer opposite the substrate.

[0011] According to the present invention, it is possible to provide a passive electronic component having a configuration including a plurality of capacitors and capable of exhibiting electrical performance with excellent high frequency characteristics.

[0012] FIG. 1 is a plan view schematic diagram showing an example of a passive electronic component according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view schematic diagram showing an example of a cross section of the passive electronic component shown in FIG. 1 taken along line a1-a2. FIG. 3 is a cross-sectional view schematic diagram showing a step of preparing a substrate in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 4 is a cross-sectional view schematic diagram showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 5 is a cross-sectional view schematic diagram showing a step of forming a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 6 is a cross-sectional view schematic diagram showing a step of forming a first dielectric layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 7 is a cross-sectional view schematic diagram showing a step of forming a second internal electrode layer and a third internal electrode layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 8 is a cross-sectional view schematic diagram showing a step of forming a second dielectric layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 9 is a cross-sectional view schematic diagram showing a step of forming a fourth internal electrode layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 10 is a cross-sectional view schematically illustrating a step of forming a moisture-resistant protective layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 11 is a cross-sectional view schematically illustrating a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 12 is a cross-sectional view schematically illustrating a step of forming first external electrodes, second external electrodes, third external electrodes, and fourth external electrodes in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 13 is a plan view schematically illustrating another example of a passive electronic component according to the first embodiment of the present invention. FIG. 14 is a cross-sectional view schematically illustrating an example of a cross section of the passive electronic component shown in FIG. 13 taken along line a3-a4. FIG. 15 is a plan view schematically illustrating an example of a passive electronic component according to the second embodiment of the present invention. FIG. 16 is a cross-sectional view schematically illustrating an example of a cross section of the passive electronic component shown in FIG. 15 taken along line b1-b2. FIG. 17 is a plan view schematically illustrating another example of a passive electronic component according to the second embodiment of the present invention. Fig. 18 is a cross-sectional schematic diagram showing an example of a cross section taken along line b3-b4 of the passive electronic component shown in Fig. 17. Fig. 19 is an equivalent circuit diagram showing an example of a passive electronic component according to embodiment 3 of the present invention. Fig. 20 is a plan view schematic diagram showing an example of a passive electronic component according to embodiment 3 of the present invention.Fig. 21 is a cross-sectional schematic diagram showing an example of a cross section of the passive electronic component shown in Fig. 20 taken along line segment c1-c2. Fig. 22 is a cross-sectional schematic diagram showing an example of a cross section of the passive electronic component shown in Fig. 20 taken along line segment d1-d2. Fig. 23 is a cross-sectional schematic diagram showing an example of a cross section of the passive electronic component shown in Fig. 20 taken along line segment e1-e2. Fig. 24 is a plan view schematic diagram showing an example of a passive electronic component according to embodiment 4 of the present invention. Fig. 25 is a cross-sectional schematic diagram showing an example of a cross section of the passive electronic component shown in Fig. 24 taken along line segment f1-f2. Fig. 26 is a cross-sectional schematic diagram showing an example of a cross section of the passive electronic component shown in Fig. 24 taken along line segment g1-g2.

[0013] The passive electronic component of the present invention will be described below. Note that the present invention is not limited to the following configurations and may be modified as appropriate without departing from the spirit of the present invention. Furthermore, a combination of multiple individual preferred configurations described below also constitutes the present invention.

[0014] The following embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From embodiment 2 onwards, descriptions of matters common to embodiment 1 will be omitted, and differences will be mainly described. In particular, similar effects resulting from similar configurations will not be mentioned one after the other for each embodiment.

[0015] In the following description, when there is no need to particularly distinguish between the embodiments, they will simply be referred to as "passive electronic components of the present invention."

[0016] In the following, an electronic component having a capacitor will be shown as an example of the passive electronic component of the present invention. The passive electronic component of the present invention may be a capacitor itself.

[0017] The drawings shown below are schematic diagrams, and the dimensions, aspect ratio, scale, etc. may differ from those of the actual product.

[0018] In this specification, unless otherwise specified, terms indicating the relationship between elements (e.g., "parallel," "perpendicular," etc.) and terms indicating the shape of elements not only mean the literal strict form, but also mean a range that is substantially equivalent, for example, a range that includes a difference of about a few percent.

[0019] A passive electronic component of the present invention comprises a substrate having a first main surface and a second main surface facing each other in a first direction, and a plurality of capacitors provided on the first main surface side of the substrate, wherein the plurality of capacitors include a first capacitor and a second capacitor spaced apart from the first capacitor in a second direction perpendicular to the first direction, the first capacitor having a first capacitance forming portion including a first internal electrode layer, a first dielectric layer, and a second internal electrode layer stacked in order from the substrate side in the first direction, the second capacitor having a second capacitance forming portion including a third internal electrode layer, a second dielectric layer, and a fourth internal electrode layer stacked in order from the substrate side in the first direction, and at least a portion of the second internal electrode layer and at least a portion of the third internal electrode layer are in contact with a surface of the first dielectric layer opposite the substrate.

[0020] [Embodiment 1] Fig. 1 is a plan view schematically illustrating an example of a passive electronic component according to embodiment 1 of the present invention. Fig. 2 is a cross-sectional view schematically illustrating an example of a cross section of the passive electronic component shown in Fig. 1 taken along line a1-a2.

[0021] A passive electronic component 1A shown in FIGS. 1 and 2 includes a substrate 10 and a plurality of capacitors 20.

[0022] The substrate 10 has a first major surface 10a and a second major surface 10b facing each other in a first direction D1.

[0023] The substrate 10 is preferably a semiconductor substrate, and in this case, examples of the material for the substrate 10 include semiconductor materials such as silicon and gallium arsenide.

[0024] The substrate 10 may be an insulating substrate. In this case, examples of the material for the substrate 10 include insulating materials such as glass and alumina.

[0025] The plurality of capacitors 20 are provided on the first major surface 10 a side of the substrate 10 .

[0026] The plurality of capacitors 20 include a first capacitor 20a and a second capacitor 20b.

[0027] The first capacitor 20a has a first capacitance forming portion 21a.

[0028] The first capacitance forming portion 21a includes a first internal electrode layer 22a, a first dielectric layer 23a, and a second internal electrode layer 22b, which are stacked in this order in the first direction D1 from the substrate 10 side. In the first capacitance forming portion 21a, one capacitor element having an MIM structure is configured by the first internal electrode layer 22a and the second internal electrode layer 22b adjacent to each other in the first direction D1, and the first dielectric layer 23a sandwiched between the first internal electrode layer 22a and the second internal electrode layer 22b.

[0029] In the example shown in FIGS. 1 and 2, the entire second internal electrode layer 22b overlaps the first internal electrode layer 22a in the first direction D1, with the first dielectric layer 23a sandwiched therebetween.

[0030] In the first capacitor 20a, the first internal electrode layer 22a may extend more widely in a direction perpendicular to the first direction D1 (for example, the second direction D2 or the third direction D3) than the second internal electrode layer 22b.

[0031] The second capacitor 20b is spaced apart from the first capacitor 20a in a second direction D2 perpendicular to the first direction D1.

[0032] 1, the second direction D2 is a direction perpendicular to the first direction D1 that passes through a first external electrode 25a, a second external electrode 25b, a third external electrode 25c, and a fourth external electrode 25d (described later). Note that, in the example shown in Fig. 1, the third direction D3 corresponds to a direction perpendicular to the first direction D1 that is also perpendicular to the second direction D2.

[0033] As a result, in the example shown in FIG. 1, the first direction D1, the second direction D2, and the third direction D3 are perpendicular to one another.

[0034] 1, the second direction D2 corresponds to the longitudinal direction of the passive electronic component 1A, and the third direction D3 corresponds to the lateral direction of the passive electronic component 1A. Alternatively, the second direction D2 may correspond to the lateral direction of the passive electronic component 1A, and the third direction D3 may correspond to the longitudinal direction of the passive electronic component 1A.

[0035] The second capacitor 20b has a second capacitance forming portion 21b.

[0036] The second capacitance forming portion 21b includes a third internal electrode layer 22c, a second dielectric layer 23b, and a fourth internal electrode layer 22d, which are stacked in this order from the substrate 10 side in the first direction D1. In the second capacitance forming portion 21b, one capacitor element having an MIM structure is configured by the third internal electrode layer 22c and the fourth internal electrode layer 22d adjacent to each other in the first direction D1, and the second dielectric layer 23b sandwiched between the third internal electrode layer 22c and the fourth internal electrode layer 22d.

[0037] In the second capacitor 20b, the third internal electrode layer 22c may extend more widely in a direction perpendicular to the first direction D1 (for example, the second direction D2 or the third direction D3) than the fourth internal electrode layer 22d.

[0038] Examples of materials for the internal electrode layers include conductive materials such as metals such as copper, silver, gold, aluminum, and platinum, and alloys containing at least one of these metals.

[0039] The materials of the internal electrode layers may be the same as each other, may be different from each other, or may be partially different from each other.

[0040] Examples of the material for each dielectric layer include oxides such as silicon dioxide, aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride.

[0041] The materials of the dielectric layers may be the same as each other, may be different from each other, or may be partially different from each other.

[0042] It should be noted that the above-mentioned dielectric layers are not shown in FIG.

[0043] In the passive electronic component 1A, at least a part of the second internal electrode layer 22b and at least a part of the third internal electrode layer 22c are in contact with the surface of the first dielectric layer 23a opposite to the substrate 10.

[0044] 2, the first dielectric layer 23a sandwiched between the first internal electrode layer 22a and the second internal electrode layer 22b extends continuously from the first capacitance forming portion 21a to the second capacitance forming portion 21b so as to contact the surface of the third internal electrode layer 22c facing the substrate 10. That is, in the example shown in Fig. 2, the first dielectric layer 23a in contact with the surface of the second internal electrode layer 22b facing the substrate 10 extends continuously from the first capacitance forming portion 21a to the second capacitance forming portion 21b so as to contact the surface of the third internal electrode layer 22c facing the substrate 10. In this way, in the example shown in Fig. 2, the entire second internal electrode layer 22b and the entire third internal electrode layer 22c are in contact with the surface of the first dielectric layer 23a opposite to the substrate 10.

[0045] In the passive electronic component 1A, at least a part of the second internal electrode layer 22b and at least a part of the third internal electrode layer 22c are in contact with the surface of the first dielectric layer 23a opposite to the substrate 10, so that in the manufacturing process of the passive electronic component 1A, particularly when the second dielectric layer 23b and the fourth internal electrode layer 22d are stacked in order on the third internal electrode layer 22c to form the second capacitance forming portion 21b, an impurity layer that increases the dielectric loss tangent is not formed on the surface of the third internal electrode layer 22c and the second dielectric layer 23b opposite to the substrate 10. Specifically, this will be described in an example of a manufacturing method of the passive electronic component 1A described later.

[0046] In the passive electronic component 1A, impurity layers that increase the dielectric loss tangent are not formed on the surfaces of the third internal electrode layer 22c and the second dielectric layer 23b opposite the substrate 10 during the manufacturing process, and therefore power loss in the second capacitor 20b (second capacitance forming portion 21b) is not increased. Therefore, even though the passive electronic component 1A has a configuration including a plurality of capacitors (here, the first capacitor 20a and the second capacitor 20b), it can exhibit electrical performance with superior high-frequency characteristics to, for example, the electronic component described in Patent Document 1.

[0047] In the passive electronic component 1A, at least a portion of the second internal electrode layer 22b and at least a portion of the third internal electrode layer 22c are in contact with the surface of the first dielectric layer 23a opposite the substrate 10. Therefore, when the height in the first direction D1 is defined based on the first main surface 10a of the substrate 10, the first capacitance-forming portion 21a and the second capacitance-forming portion 21b are located at different heights. For example, the surface of the first internal electrode layer 22a of the first capacitance-forming portion 21a facing the substrate 10 and the surface of the third internal electrode layer 22c of the second capacitance-forming portion 21b facing the substrate 10 are located at different heights. In this way, in the passive electronic component 1A, the first capacitance-forming portion 21a and the second capacitance-forming portion 21b are located at different heights. This reduces electric field coupling and magnetic field coupling compared to when the first capacitance-forming portion 21a and the second capacitance-forming portion 21b are located at the same height, and as a result, crosstalk is more likely to be reduced.

[0048] It is preferable that the first dielectric layer 23a of the first capacitance forming portion 21a and the second dielectric layer 23b of the second capacitance forming portion 21b have different dimensions in the first direction D1, which makes it easier to set the capacitances (electrostatic capacitances) of the first capacitor 20a and the second capacitor 20b independently.

[0049] The dimension T1 in the first direction D1 of the first dielectric layer 23a of the first capacitance forming portion 21a refers to the dimension in the first direction D1 of the first dielectric layer 23a that constitutes the first capacitance forming portion 21a of the first capacitor 20a. Specifically, the dimension T1 in the first direction D1 of the first dielectric layer 23a of the first capacitance forming portion 21a refers to the dimension in the first direction D1 of the portion of the first dielectric layer 23a that is sandwiched between the first internal electrode layer 22a and the second internal electrode layer 22b.

[0050] The dimension T2 in the first direction D1 of the second dielectric layer 23b of the second capacitance forming portion 21b refers to the dimension in the first direction D1 of the second dielectric layer 23b that constitutes the second capacitance forming portion 21b of the second capacitor 20b. Specifically, the dimension T2 in the first direction D1 of the second dielectric layer 23b of the second capacitance forming portion 21b refers to the dimension in the first direction D1 of the portion of the second dielectric layer 23b that is sandwiched between the third internal electrode layer 22c and the fourth internal electrode layer 22d.

[0051] In the example shown in Figure 2, the dimension T1 in the first direction D1 of the first dielectric layer 23a of the first capacitance forming portion 21a is larger than the dimension T2 in the first direction D1 of the second dielectric layer 23b of the second capacitance forming portion 21b.

[0052] The dimension T1 in the first direction D1 of the first dielectric layer 23a of the first capacitance forming portion 21a may be smaller than the dimension T2 in the first direction D1 of the second dielectric layer 23b of the second capacitance forming portion 21b.

[0053] Furthermore, the dimension T1 in the first direction D1 of the first dielectric layer 23a of the first capacitance forming portion 21a may be the same as the dimension T2 in the first direction D1 of the second dielectric layer 23b of the second capacitance forming portion 21b.

[0054] It is preferable that the second dielectric layer 23b sandwiched between the third internal electrode layer 22c and the fourth internal electrode layer 22d extends continuously from the second capacitance forming portion 21b to the first capacitance forming portion 21a so as to cover the second internal electrode layer 22b from the side opposite the substrate 10.

[0055] The first dielectric layer 23a and the second dielectric layer 23b may be laminated in order from the substrate 10 side in the first direction D1 in a region between the first capacitor 20a (first capacitance forming portion 21a) and the second capacitor 20b (second capacitance forming portion 21b) in the second direction D2. In other words, the first dielectric layer 23a and the second dielectric layer 23b may be in contact with each other in the first direction D1 in a region between the first capacitance forming portion 21a and the second capacitance forming portion 21b in the second direction D2.

[0056] The first dielectric layer 23a and the second dielectric layer 23b may not be provided in the region R between the first capacitor 20a (first capacitance forming portion 21a) and the second capacitor 20b (second capacitance forming portion 21b) in the second direction D2. In this case, a decrease in the Q value (quality factor) of the passive electronic component 1A due to the electric field passing through the dielectric layers provided in the first capacitor 20a and the second capacitor 20b is suppressed.

[0057] The first capacitor 20a preferably further includes a first external electrode 25a connected to the first internal electrode layer 22a.

[0058] In the example shown in FIGS. 1 and 2, the first external electrode 25a is connected to a portion of the first internal electrode layer 22a that does not overlap with the second internal electrode layer 22b in the first direction D1.

[0059] The first capacitor 20a preferably further includes a second external electrode 25b connected to the second internal electrode layer 22b.

[0060] In the example shown in FIGS. 1 and 2, the second external electrode 25b is spaced apart from the first external electrode 25a in the second direction D2.

[0061] In the example shown in FIGS. 1 and 2, the second external electrode 25b is connected to a portion of the second internal electrode layer 22b that overlaps with the first internal electrode layer 22a in the first direction D1.

[0062] When the first capacitor 20a has the first external electrode 25a and the second external electrode 25b, the first capacitor 20a constitutes a two-terminal capacitor.

[0063] The second capacitor 20b preferably further includes a third external electrode 25c connected to the third internal electrode layer 22c.

[0064] In the example shown in FIGS. 1 and 2, the third external electrode 25c is connected to a portion of the third internal electrode layer 22c that does not overlap with the fourth internal electrode layer 22d in the first direction D1.

[0065] The second capacitor 20b preferably further includes a fourth external electrode 25d connected to the fourth internal electrode layer 22d.

[0066] In the example shown in FIGS. 1 and 2, the fourth external electrode 25d is spaced apart from the third external electrode 25c in the second direction D2.

[0067] In the example shown in FIGS. 1 and 2, the fourth external electrode 25d is connected to a portion of the fourth internal electrode layer 22d that overlaps with the third internal electrode layer 22c in the first direction D1.

[0068] When the second capacitor 20b has the third external electrode 25c and the fourth external electrode 25d, the second capacitor 20b constitutes a two-terminal capacitor.

[0069] When the first capacitor 20a has the first external electrode 25a and the second external electrode 25b, and the second capacitor 20b has the third external electrode 25c and the fourth external electrode 25d, the passive electronic component 1A can function alone.

[0070] Examples of materials for the external electrodes include conductive materials such as metals such as copper, nickel, silver, gold, aluminum, palladium, titanium, and tin, and alloys containing at least one of these metals.

[0071] The materials of the external electrodes may be the same as or different from one another, or may be partially different from one another.

[0072] Each external electrode may have a single-layer structure or a multi-layer structure.

[0073] When the external electrode has a multi-layer structure, the external electrode may have, in order from the substrate 10 side, a seed layer, a first plating layer, and a second plating layer.

[0074] The seed layer may be, for example, a laminated body in which a conductor layer made of titanium and a conductor layer made of copper are laminated in this order from the substrate 10 side.

[0075] The first plating layer may be, for example, a nickel plating layer.

[0076] Examples of the second plating layer include a gold plating layer and a tin plating layer.

[0077] The layer structures of the external electrodes may be the same as each other, may be different from each other, or may be partially different from each other.

[0078] When viewed from above in the first direction D1, the periphery of the second external electrode 25b is preferably located inside the periphery of the second internal electrode layer 22b, which minimizes the parasitic capacitance between the second external electrode 25b and the first internal electrode layer 22a, making it easier to increase the Q value of the passive electronic component 1A.

[0079] When viewed from above in the first direction D1, the periphery of the fourth external electrode 25 d is preferably located inside the periphery of the fourth internal electrode layer 22 d, which minimizes the parasitic capacitance between the fourth external electrode 25 d and the third internal electrode layer 22 c, making it easier to increase the Q value of the passive electronic component 1A.

[0080] When viewed from above in the first direction D1, it is preferable that the first external electrode 25a does not overlap the second internal electrode layer 22b, which minimizes the parasitic capacitance between the first external electrode 25a and the second internal electrode layer 22b, making it easier to increase the Q value of the passive electronic component 1A.

[0081] When viewed from above in the first direction D1, it is preferable that the third external electrode 25c does not overlap the fourth internal electrode layer 22d, which minimizes the parasitic capacitance between the third external electrode 25c and the fourth internal electrode layer 22d, and therefore the Q value of the passive electronic component 1A is likely to be increased.

[0082] It is preferable that the passive electronic component 1A further has an insulating layer 30 provided between the substrate 10 and the first capacitor 20a in the first direction D1, and between the substrate 10 and the second capacitor 20b in the first direction D1.

[0083] In the example shown in Figures 1 and 2, the insulating layer 30 extends continuously between the substrate 10 and the first capacitor 20a in the first direction D1 and between the substrate 10 and the second capacitor 20b in the first direction D1.

[0084] The insulating layer 30 preferably contacts the substrate 10 in the first direction D1.

[0085] The insulating layer 30 preferably contacts the first capacitor 20a in the first direction D1.

[0086] The insulating layer 30 preferably contacts the second capacitor 20b in the first direction D1.

[0087] The insulating layer 30 may be provided so as to cover the entire first major surface 10 a of the substrate 10 , or may be provided so as to cover a portion of the first major surface 10 a of the substrate 10 .

[0088] When the substrate 10 is a semiconductor substrate, the provision of the insulating layer 30 reduces the parasitic capacitance between the substrate 10 and the first capacitor 20a and the parasitic capacitance between the substrate 10 and the second capacitor 20b, thereby increasing the Q value of the passive electronic component 1A.

[0089] When the substrate 10 is an insulating substrate, the insulating layer 30 may not be provided. When the insulating layer 30 is not provided, it is preferable that the substrate 10 and the first capacitor 20a are in contact with each other in the first direction D1, and it is further preferable that the substrate 10 and the second capacitor 20b are in contact with each other in the first direction D1.

[0090] In plan view from the first direction D1, the periphery of the insulating layer 30 is preferably located outside the peripheries of all the internal electrode layers included in the first capacitor 20a and the second capacitor 20b.

[0091] Examples of materials for the insulating layer 30 include insulating materials such as oxides, such as silicon dioxide and aluminum oxide, and nitrides, such as silicon nitride.

[0092] The passive electronic component 1A preferably further includes a moisture-resistant protective layer 40 covering the first capacitance forming portion 21 a and the second capacitance forming portion 21 b. In this case, the moisture resistance of the first capacitance forming portion 21 a and the second capacitance forming portion 21 b is improved. Specifically, the provision of the moisture-resistant protective layer 40 prevents moisture from penetrating into the internal electrode layers of the first capacitance forming portion 21 a and the second capacitance forming portion 21 b, thereby suppressing corrosion of the internal electrode layers.

[0093] The moisture-resistant protective layer 40 preferably covers the entire internal electrode layer and dielectric layer of the first capacitor 20a except for the areas where the first external electrode 25a and second external electrode 25b are provided.

[0094] The moisture-resistant protective layer 40 preferably covers the entire internal electrode layer and dielectric layer of the second capacitor 20b except for the areas where the third external electrode 25c and fourth external electrode 25d are provided.

[0095] Examples of materials for the moisture-resistant protective layer 40 include moisture-resistant materials such as oxides such as silicon dioxide and nitrides such as silicon nitride.

[0096] In addition, the moisture-resistant protective layer 40 is not shown in FIG.

[0097] The passive electronic component 1A preferably further includes a resin protective layer 50 that covers the substrate 10, the first capacitance forming portion 21 a, and the second capacitance forming portion 21 b, thereby protecting the substrate 10, the first capacitance forming portion 21 a, and the second capacitance forming portion 21 b from moisture.

[0098] The resin protective layer 50 preferably covers the entire internal electrode layer and dielectric layer of the first capacitor 20a except for the areas where the first external electrode 25a and second external electrode 25b are provided.

[0099] The resin protective layer 50 preferably covers the entire internal electrode layers and dielectric layers of the second capacitor 20b except for the areas where the third external electrode 25c and fourth external electrode 25d are provided.

[0100] Examples of materials for the resin protective layer 50 include resin materials such as polyimide resin and resins in solder resist.

[0101] In addition, the resin protective layer 50 is not shown in FIG.

[0102] When the passive electronic component 1A has the moisture-resistant protective layer 40 and the resin protective layer 50, the resin protective layer 50 preferably covers the entire moisture-resistant protective layer 40.

[0103] When the passive electronic component 1A has a moisture-resistant protective layer 40 and a resin protective layer 50, the first external electrode 25a is preferably provided inside a through-hole 60ha that penetrates at least the moisture-resistant protective layer 40 and the resin protective layer 50 in the first direction D1. In other words, the first external electrode 25a is preferably connected to the first internal electrode layer 22a via the through-hole 60ha.

[0104] When the passive electronic component 1A has the moisture-resistant protective layer 40 and the resin protective layer 50, the second external electrode 25b is preferably provided inside a through-hole 60hb that penetrates in the first direction D1 at least the moisture-resistant protective layer 40 and the resin protective layer 50. In other words, the second external electrode 25b is preferably connected to the second internal electrode layer 22b via the through-hole 60hb.

[0105] When the passive electronic component 1A has the moisture-resistant protective layer 40 and the resin protective layer 50, the third external electrode 25c is preferably provided inside a through-hole 60hc that penetrates in the first direction D1 at least the moisture-resistant protective layer 40 and the resin protective layer 50. In other words, the third external electrode 25c is preferably connected to the third internal electrode layer 22c via the through-hole 60hc.

[0106] When the passive electronic component 1A has a moisture-resistant protective layer 40 and a resin protective layer 50, the fourth external electrode 25d is preferably provided inside a through-hole 60hd that penetrates in the first direction D1 at least the moisture-resistant protective layer 40 and the resin protective layer 50. In other words, the fourth external electrode 25d is preferably connected to the fourth internal electrode layer 22d via the through-hole 60hd.

[0107] The passive electronic component 1A is manufactured, for example, by the following method.

[0108] <Step of Preparing a Substrate> FIG. 3 is a schematic cross-sectional view showing the step of preparing a substrate in an example of the method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0109] As shown in FIG. 3, a substrate 10 is prepared.

[0110] <Step of Forming Insulating Layer> FIG. 4 is a schematic cross-sectional view showing the step of forming an insulating layer in an example of the method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0111] An insulating layer made of an insulating material is formed on the first main surface 10a of the substrate 10 by a method such as CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition).The insulating layer is then patterned by a combination of photolithography and etching to form an insulating layer 30 as shown in FIG.

[0112] <Step of Forming First Internal Electrode Layers> FIG. 5 is a cross-sectional view schematically showing the step of forming first internal electrode layers in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0113] An electrode layer made of a conductive material is formed by a CVD method, a PVD method, or the like so as to cover the structure shown in Fig. 4 from the first main surface 10a side of the substrate 10. Thereafter, this electrode layer is patterned by a combination of photolithography and etching methods to form a first internal electrode layer 22a as shown in Fig. 5.

[0114] <Step of Forming First Dielectric Layer> FIG. 6 is a cross-sectional view schematically illustrating the step of forming a first dielectric layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0115] A dielectric layer made of a dielectric material is formed by a CVD method, a PVD method, or the like so as to cover the structure shown in Fig. 5 from the first main surface 10a side of the substrate 10. Then, this dielectric layer is patterned using a combination of photolithography and etching to form a first dielectric layer 23a as shown in Fig. 6. Specifically, the first dielectric layer 23a is formed so as to cover the substrate 10, the first internal electrode layer 22a, and the insulating layer 30 from the first main surface 10a side of the substrate 10. At this time, a through hole 23ah is provided that penetrates the first dielectric layer 23a in the first direction D1 so as to expose a portion of the first internal electrode layer 22a.

[0116] In this process, when forming the first dielectric layer 23a on the first internal electrode layer 22a, no process such as removing the dielectric layer by patterning is performed on the region of the first internal electrode layer 22a that will later constitute the first capacitance forming portion 21a. Therefore, in this process, when forming the first dielectric layer 23a on the first internal electrode layer 22a, an impurity layer that would increase the dielectric loss tangent is not formed on the surface of the first internal electrode layer 22a that will later constitute the first capacitance forming portion 21a, opposite to the substrate 10.

[0117] <Process of forming second internal electrode layer and third internal electrode layer> Figure 7 is a cross-sectional schematic view showing the process of forming second internal electrode layer and third internal electrode layer in an example of a method for manufacturing a passive electronic component according to embodiment 1 of the present invention.

[0118] An electrode layer made of a conductive material is formed by a CVD method, a PVD method, or the like so as to cover the structure shown in Fig. 6 from the first main surface 10a side of the substrate 10. Thereafter, this electrode layer is patterned by a combination of photolithography and etching to form second internal electrode layers 22b and third internal electrode layers 22c as shown in Fig. 7. Specifically, the second internal electrode layer 22b is formed at a position adjacent to the first internal electrode layer 22a in the first direction D1 with the first dielectric layer 23a interposed therebetween, and the third internal electrode layer 22c is formed at a position not adjacent to the first internal electrode layer 22a in the first direction D1 with the first dielectric layer 23a interposed therebetween. As a result, at least a portion of the second internal electrode layer 22b (in the example shown in Figure 7, the entire second internal electrode layer 22b) and at least a portion of the third internal electrode layer 22c (in the example shown in Figure 7, the entire third internal electrode layer 22c) are in contact with the surface of the first dielectric layer 23a opposite the substrate 10.

[0119] In this process, when the second internal electrode layer 22b is formed on the first dielectric layer 23a, no process such as removing an electrode layer by patterning is performed on the region of the first dielectric layer 23a that will later constitute the first capacitance forming portion 21a (the region of the first dielectric layer 23a where the second internal electrode layer 22b will be formed). Therefore, in this process, when the second internal electrode layer 22b is formed on the first dielectric layer 23a, no impurity layer that will increase the dielectric loss tangent is formed on the surface of the first dielectric layer 23a that will later constitute the first capacitance forming portion 21a, opposite to the substrate 10.

[0120] In this step, it is preferable to form the second internal electrode layer 22b and the third internal electrode layer 22c on the first dielectric layer 23a at the same time. Note that in this step, the second internal electrode layer 22b and the third internal electrode layer 22c may be formed on the first dielectric layer 23a at different times.

[0121] Through the above steps, the first capacitance forming portion 21a is formed, in which the first internal electrode layer 22a, the first dielectric layer 23a, and the second internal electrode layer 22b are stacked in order from the substrate 10 side in the first direction D1.

[0122] <Step of Forming Second Dielectric Layer> FIG. 8 is a cross-sectional view schematically illustrating the step of forming a second dielectric layer in the example of the method for manufacturing the passive electronic component according to the first embodiment of the present invention.

[0123] A dielectric layer made of a dielectric material is formed by CVD, PVD, or the like so as to cover the structure shown in FIG. 7 from the first main surface 10a of the substrate 10. Then, this dielectric layer is patterned using a combination of photolithography and etching to form a second dielectric layer 23b as shown in FIG. 8. Specifically, the second dielectric layer 23b is formed so as to cover the second internal electrode layer 22b, the third internal electrode layer 22c, and the first dielectric layer 23a from the first main surface 10a of the substrate 10. At this time, a through hole 23bha is formed penetrating the second dielectric layer 23b in the first direction D1 at a position overlapping the through hole 23ah in the first direction D1 so as to expose a portion of the first internal electrode layer 22a. Furthermore, a through hole 23bhb is formed penetrating the second dielectric layer 23b in the first direction D1 so as to expose a portion of the second internal electrode layer 22b. Furthermore, a through-hole 23bhc is provided that penetrates the second dielectric layer 23b in the first direction D1 so as to expose a part of the third internal electrode layer 22c.

[0124] In this process, when the second dielectric layer 23b is formed on the third internal electrode layer 22c, no process such as removing the dielectric layer by patterning is performed on the region of the third internal electrode layer 22c that will later constitute the second capacitance forming portion 21b. Therefore, in this process, when the second dielectric layer 23b is formed on the third internal electrode layer 22c, no impurity layer that would increase the dielectric loss tangent is formed on the surface of the third internal electrode layer 22c that will later constitute the second capacitance forming portion 21b, opposite to the substrate 10.

[0125] <Step of Forming Fourth Internal Electrode Layer> FIG. 9 is a cross-sectional view schematically showing the step of forming a fourth internal electrode layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0126] An electrode layer made of a conductive material is formed by a CVD method, a PVD method, or the like so as to cover the structure shown in Fig. 8 from the first main surface 10a side of the substrate 10. Thereafter, this electrode layer is patterned by a combination of photolithography and etching to form a fourth internal electrode layer 22d as shown in Fig. 9. Specifically, the fourth internal electrode layer 22d is formed at a position adjacent to the third internal electrode layer 22c in the first direction D1, with the second dielectric layer 23b sandwiched therebetween.

[0127] In this process, when the fourth internal electrode layer 22d is formed on the second dielectric layer 23b, no process such as removing an electrode layer by patterning is performed on a region of the second dielectric layer 23b that will later constitute the second capacitance forming portion 21b (a region of the second dielectric layer 23b where the fourth internal electrode layer 22d is to be formed). Therefore, in this process, when the fourth internal electrode layer 22d is formed on the second dielectric layer 23b, an impurity layer that would increase the dielectric loss tangent is not formed on the surface of the second dielectric layer 23b that will later constitute the second capacitance forming portion 21b, opposite to the substrate 10.

[0128] Through the above steps, the second capacitance forming portion 21b is formed, in which the third internal electrode layer 22c, the second dielectric layer 23b, and the fourth internal electrode layer 22d are stacked in order from the substrate 10 side in the first direction D1.

[0129] In the above process, when the first capacitance forming portion 21a is formed by sequentially stacking the first dielectric layer 23a and the second internal electrode layer 22b on the first internal electrode layer 22a, an impurity layer that increases the dielectric loss tangent is not formed on the surfaces of the first internal electrode layer 22a and the first dielectric layer 23a opposite to the substrate 10. Therefore, in the passive electronic component 1A obtained later, the power loss in the first capacitor 20a (first capacitance forming portion 21a) is not increased.

[0130] Furthermore, in the above process, when the second capacitance forming portion 21b is formed by sequentially stacking the second dielectric layer 23b and the fourth internal electrode layer 22d on the third internal electrode layer 22c, an impurity layer that increases the dielectric loss tangent is not formed on the surfaces of the third internal electrode layer 22c and the second dielectric layer 23b opposite to the substrate 10. Therefore, in the passive electronic component 1A obtained later, the power loss in the second capacitor 20b (second capacitance forming portion 21b) is not increased.

[0131] As a result, the passive electronic component 1A obtained later can exhibit electrical performance with excellent high frequency characteristics by having a configuration including a plurality of capacitors (here, the first capacitor 20a and the second capacitor 20b).

[0132] <Step of Forming Moisture-Resistant Protective Layer> FIG. 10 is a cross-sectional view schematically illustrating a step of forming a moisture-resistant protective layer in an example of the method for manufacturing the passive electronic component according to the first embodiment of the present invention.

[0133] A moisture-resistant layer made of a moisture-resistant material is formed by CVD, PVD, or the like so as to cover the structure shown in FIG. 9 from the first main surface 10a of the substrate 10. Then, the moisture-resistant layer is patterned using a combination of photolithography and etching to form the moisture-resistant protective layer 40 as shown in FIG. 10 . Specifically, the moisture-resistant protective layer 40 is formed so as to cover the fourth internal electrode layer 22d and the second dielectric layer 23b from the first main surface 10a of the substrate 10. At this time, a through hole 40ha is formed penetrating the moisture-resistant protective layer 40 in the first direction D1 at a position overlapping the through hole 23ah and the through hole 23bha in the first direction D1 so as to expose a portion of the first internal electrode layer 22a. Furthermore, a through hole 40hb is formed penetrating the moisture-resistant protective layer 40 in the first direction D1 at a position overlapping the through hole 23bhb in the first direction D1 so as to expose a portion of the second internal electrode layer 22b. Furthermore, a through hole 40hc is provided through the moisture-resistant protective layer 40 in the first direction D1 at a position overlapping the through hole 23bhc in the first direction D1 so as to expose a part of the third internal electrode layer 22c. Furthermore, a through hole 40hd is provided through the moisture-resistant protective layer 40 in the first direction D1 so as to expose a part of the fourth internal electrode layer 22d.

[0134] <Step of Forming Resin Protective Layer> FIG. 11 is a cross-sectional view schematically illustrating the step of forming a resin protective layer in an example of the method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0135] A resin layer made of a resin material is formed by spin coating or the like so as to cover the structure shown in Fig. 10 from the first main surface 10a side of the substrate 10. Thereafter, the resin layer is patterned using only photolithography if the resin material of the resin layer is photosensitive, or using a combination of photolithography and etching if the resin material of the resin layer is non-photosensitive, thereby forming a resin protective layer 50 as shown in Fig. 11. Specifically, the resin protective layer 50 is formed so as to cover the moisture-resistant protective layer 40 from the first main surface 10a side of the substrate 10. At this time, a through hole 50ha is provided penetrating the resin protective layer 50 in the first direction D1 at a position overlapping the through hole 23ah, the through hole 23bha, and the through hole 40ha in the first direction D1 so as to expose a portion of the first internal electrode layer 22a. Furthermore, a through hole 50hb penetrating the resin protective layer 50 in the first direction D1 is provided at a position overlapping the through hole 23bhb and the through hole 40hb in the first direction D1 so as to expose a portion of the second internal electrode layer 22b. Further, a through hole 50hc penetrating the resin protective layer 50 in the first direction D1 is provided at a position overlapping the through hole 23bhc and the through hole 40hc in the first direction D1 so as to expose a portion of the third internal electrode layer 22c. Furthermore, a through hole 50hd penetrating the resin protective layer 50 in the first direction D1 is provided at a position overlapping the through hole 40hd in the first direction D1 so as to expose a portion of the fourth internal electrode layer 22d.

[0136] Through the above steps, a through hole 60ha is formed by connecting the through hole 23ah, the through hole 23bha, the through hole 40ha, and the through hole 50ha in the first direction D1 so as to expose a portion of the first internal electrode layer 22a. Furthermore, a through hole 60hb is formed by connecting the through hole 23bhb, the through hole 40hb, and the through hole 50hb in the first direction D1 so as to expose a portion of the second internal electrode layer 22b. Furthermore, a through hole 60hc is formed by connecting the through hole 23bhc, the through hole 40hc, and the through hole 50hc in the first direction D1 so as to expose a portion of the third internal electrode layer 22c. Furthermore, a through hole 60hd is formed by connecting the through hole 40hd and the through hole 50hd in the first direction D1 so as to expose a portion of the fourth internal electrode layer 22d.

[0137] <Steps of forming the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode> Figure 12 is a schematic cross-sectional view showing the steps of forming the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode in an example of a method for manufacturing a passive electronic component according to embodiment 1 of the present invention.

[0138] 12 , a first external electrode 25a is formed inside the through hole 60ha, a second external electrode 25b is formed inside the through hole 60hb, a third external electrode 25c is formed inside the through hole 60hc, and a fourth external electrode 25d is formed inside the through hole 60hd by plating, etching, etc. As a result, the first external electrode 25a is connected to the first internal electrode layer 22a via the through hole 60ha, the second external electrode 25b is connected to the second internal electrode layer 22b via the through hole 60hb, the third external electrode 25c is connected to the third internal electrode layer 22c via the through hole 60hc, and the fourth external electrode 25d is connected to the fourth internal electrode layer 22d via the through hole 60hd.

[0139] Through the above steps, a first capacitor 20a is formed, which has a first capacitance forming portion 21a, a first external electrode 25a, and a second external electrode 25b. Also, a second capacitor 20b is formed, which has a second capacitance forming portion 21b, a third external electrode 25c, and a fourth external electrode 25d.

[0140] In this way, the passive electronic component 1A is manufactured.

[0141] In the passive electronic component according to the first embodiment of the present invention, the shape of the internal electrode layers and the positions of the external electrodes may be different from those shown in FIGS.

[0142] Fig. 13 is a plan view schematically illustrating another example of the passive electronic component according to the first embodiment of the present invention. Fig. 14 is a cross-sectional view schematically illustrating an example of a cross section taken along line a3-a4 of the passive electronic component shown in Fig. 13.

[0143] In the passive electronic component 1B shown in FIGS. 13 and 14, a portion of the second internal electrode layer 22b overlaps the first internal electrode layer 22a in the first direction D1, with the first dielectric layer 23a sandwiched therebetween.

[0144] In the example shown in Fig. 14, a step is provided on the surface of the second internal electrode layer 22b facing the substrate 10. Also, in the example shown in Fig. 14, a step is provided on the surface of the second internal electrode layer 22b opposite to the substrate 10. That is, in the example shown in Fig. 14, when the height in the first direction D1 is defined with reference to the first main surface 10a of the substrate 10, the second internal electrode layer 22b is bent so that a portion on one end side in the second direction D2 has a different height from a portion on the other end side in the second direction D2.

[0145] In the passive electronic component 1B, a part of the fourth internal electrode layer 22d overlaps the third internal electrode layer 22c in the first direction D1, with the second dielectric layer 23b sandwiched therebetween.

[0146] In the example shown in Fig. 14, a step is provided on the surface of the fourth internal electrode layer 22d facing the substrate 10. Also, in the example shown in Fig. 14, a step is provided on the surface of the fourth internal electrode layer 22d opposite to the substrate 10. That is, in the example shown in Fig. 14, when the height in the first direction D1 is defined with reference to the first main surface 10a of the substrate 10, the fourth internal electrode layer 22d is bent so that a portion on one end side in the second direction D2 has a different height from a portion on the other end side in the second direction D2.

[0147] In the passive electronic component 1B, the second external electrode 25b is connected to a portion of the second internal electrode layer 22b that does not overlap the first internal electrode layer 22a in the first direction D1.

[0148] In the passive electronic component 1B, the fourth external electrode 25d is connected to a portion of the fourth internal electrode layer 22d that does not overlap the third internal electrode layer 22c in the first direction D1.

[0149] [Embodiment 2] In a passive electronic component of embodiment 2 of the present invention, unlike the passive electronic component of embodiment 1 of the present invention, the second capacitance forming portion further includes a first dielectric layer and a fifth internal electrode layer stacked in this order on the substrate side in the first direction relative to the third internal electrode layer.

[0150] Fig. 15 is a plan view schematically illustrating an example of a passive electronic component according to embodiment 2 of the present invention. Fig. 16 is a cross-sectional view schematically illustrating an example of a cross section of the passive electronic component shown in Fig. 15 taken along line b1-b2.

[0151] 15 and 16 , the second capacitance forming portion 21 b further includes a first dielectric layer 23 a and a fifth internal electrode layer 22 e that are stacked in this order on the substrate 10 side in the first direction D1 with respect to the third internal electrode layer 22 c. As a result, in the second capacitance forming portion 21 b, a capacitor element formed by the third internal electrode layer 22 c, the second dielectric layer 23 b, and the fourth internal electrode layer 22 d and a capacitor element formed by the third internal electrode layer 22 c, the first dielectric layer 23 a, and the fifth internal electrode layer 22 e are connected in series.

[0152] In the second capacitance forming portion 21b of the passive electronic component 2A, a capacitor element including the first dielectric layer 23a and a capacitor element including the second dielectric layer 23b are connected in series, thereby realizing a capacitance equivalent to that of a capacitor element having a laminate of the first dielectric layer 23a and the second dielectric layer 23b as a dielectric layer.

[0153] In the second capacitance forming portion 21b of the passive electronic component 2A, the configuration in which the two capacitor elements described above are connected in series reduces the electric field leaking from the end of the internal electrode layer (for example, the end in the second direction D2). Therefore, in the second capacitance forming portion 21b of the passive electronic component 2A, not only is the parasitic capacitance between the internal electrode layers reduced, but a decrease in the Q value due to the parasitic capacitance is also suppressed.

[0154] In the second capacitance forming portion 21b of the passive electronic component 2A, the configuration in which the two capacitor elements are connected in series as described above reduces the capacitance deviation compared to a configuration in which only one capacitor element is connected. In the capacitance forming portion, the greater the number of capacitor elements connected in series, the smaller the capacitance deviation tends to be.

[0155] In the second capacitance forming portion 21b of the passive electronic component 2A, the two capacitor elements described above are connected in series in the first direction D1, which makes it possible to miniaturize the second capacitor 20b and, in turn, the passive electronic component 2A compared to when the two capacitor elements are connected in series in a direction perpendicular to the first direction D1, for example, in the second direction D2.

[0156] In the second capacitor 20b of the passive electronic component 2A, the fifth internal electrode layer 22e may extend more in a direction perpendicular to the first direction D1 (e.g., the second direction D2 or the third direction D3) than the third internal electrode layer 22c and the fourth internal electrode layer 22d.

[0157] In the passive electronic component 2A, similar to the passive electronic component 1A (see FIGS. 1 and 2), the first capacitor 20a preferably further includes a first external electrode 25a connected to the first internal electrode layer 22a.

[0158] In the passive electronic component 2A, similarly to the passive electronic component 1A, the first capacitor 20a preferably further includes a second external electrode 25b connected to the second internal electrode layer 22b.

[0159] In the passive electronic component 2A, unlike the passive electronic component 1A, the second capacitor 20b preferably further includes a third external electrode 25c connected to the fifth internal electrode layer 22e.

[0160] In the example shown in Figures 15 and 16, the third external electrode 25c is connected to a portion of the fifth internal electrode layer 22e that does not overlap with the third internal electrode layer 22c and the fourth internal electrode layer 22d in the first direction D1.

[0161] In the passive electronic component 2A, it is preferable that the third external electrode 25c does not overlap the third internal electrode layer 22c and the fourth internal electrode layer 22d when viewed in a plan view from the first direction D1. In this case, the parasitic capacitance between the third external electrode 25c and the third internal electrode layer 22c and the parasitic capacitance between the third external electrode 25c and the fourth internal electrode layer 22d are minimized, which makes it easier to increase the Q value of the passive electronic component 2A.

[0162] In the passive electronic component 2A, similarly to the passive electronic component 1A, the second capacitor 20b preferably further includes a fourth external electrode 25d connected to the fourth internal electrode layer 22d.

[0163] In the passive electronic component 2A, when viewed from above in the first direction D1, the periphery of the fourth external electrode 25d is preferably located more inward than the periphery of the fourth internal electrode layer 22d. In this case, the parasitic capacitance between the fourth external electrode 25d and the third internal electrode layer 22c and the parasitic capacitance between the fourth external electrode 25d and the fifth internal electrode layer 22e are minimized, which makes it easier to increase the Q value of the passive electronic component 2A.

[0164] The passive electronic component 2A is manufactured in the same manner as the passive electronic component 1A, except that, for example, the fifth internal electrode layer 22e is also formed in the step of forming the first internal electrode layer 22a. When forming the fifth internal electrode layer 22e in the step of forming the first internal electrode layer 22a, it is preferable that the first internal electrode layer 22a and the fifth internal electrode layer 22e are formed at the same timing, but they may be formed at different timings.

[0165] In the passive electronic component according to the second embodiment of the present invention, the shape of the internal electrode layers may be different from the examples shown in Figures 15 and 16. Furthermore, in the passive electronic component according to the second embodiment of the present invention, the position of the external electrodes may be different from the examples shown in Figures 15 and 16.

[0166] Fig. 17 is a plan view schematically illustrating another example of a passive electronic component according to Embodiment 2 of the present invention. Fig. 18 is a cross-sectional view schematically illustrating an example of a cross section taken along line b3-b4 of the passive electronic component shown in Fig. 17.

[0167] In the passive electronic component 2B shown in FIGS. 17 and 18, a portion of the second internal electrode layer 22b overlaps the first internal electrode layer 22a in the first direction D1, with the first dielectric layer 23a sandwiched therebetween.

[0168] In the example shown in Fig. 18, a step is provided on the surface of the second internal electrode layer 22b facing the substrate 10. Also, in the example shown in Fig. 18, a step is provided on the surface of the second internal electrode layer 22b opposite to the substrate 10. That is, in the example shown in Fig. 18, when the height in the first direction D1 is defined with reference to the first main surface 10a of the substrate 10, the second internal electrode layer 22b is bent so that a portion on one end side in the second direction D2 has a different height from a portion on the other end side in the second direction D2.

[0169] In the passive electronic component 2B, a part of the fourth internal electrode layer 22d overlaps the third internal electrode layer 22c in the first direction D1, with the second dielectric layer 23b sandwiched therebetween.

[0170] In the example shown in Fig. 18, a step is provided on the surface of the fourth internal electrode layer 22d facing the substrate 10. Also, in the example shown in Fig. 18, a step is provided on the surface of the fourth internal electrode layer 22d opposite to the substrate 10. That is, in the example shown in Fig. 18, when the height in the first direction D1 is defined with reference to the first main surface 10a of the substrate 10, the fourth internal electrode layer 22d is bent so that a portion on one end side in the second direction D2 has a different height from a portion on the other end side in the second direction D2.

[0171] In the passive electronic component 2B, the second external electrode 25b is connected to a portion of the second internal electrode layer 22b that does not overlap the first internal electrode layer 22a in the first direction D1.

[0172] In the passive electronic component 2B, the fourth external electrode 25d is connected to a portion of the fourth internal electrode layer 22d that does not overlap the third internal electrode layer 22c in the first direction D1.

[0173] Third Embodiment A passive electronic component according to a third embodiment of the present invention differs from the passive electronic component according to the second embodiment of the present invention in that it further includes an inductor formed by winding an internal wiring including at least one conductor layer.

[0174] In the passive electronic component of the third embodiment of the present invention, the direction of the winding axis of the internal wiring is perpendicular to the first main surface of the substrate, and all of the conductor layers each independently contain the same material as the first internal electrode layer, the second internal electrode layer, the third internal electrode layer, the fourth internal electrode layer, the fifth internal electrode layer, the first external electrode, the second external electrode, the third external electrode, or the fourth external electrode.

[0175] Fig. 19 is an equivalent circuit diagram showing an example of a passive electronic component according to embodiment 3 of the present invention. Fig. 20 is a plan view schematic diagram showing an example of a passive electronic component according to embodiment 3 of the present invention. Fig. 21 is a cross-sectional schematic diagram showing an example of a cross section of the passive electronic component shown in Fig. 20 taken along line segment c1-c2. Fig. 22 is a cross-sectional schematic diagram showing an example of a cross section of the passive electronic component shown in Fig. 20 taken along line segment d1-d2. Fig. 23 is a cross-sectional schematic diagram showing an example of a cross section of the passive electronic component shown in Fig. 20 taken along line segment e1-e2.

[0176] The passive electronic component 3A shown in FIGS. 19, 20, 21, 22, and 23 further includes an inductor 100 in addition to the substrate 10, the first capacitor 20a, and the second capacitor 20b.

[0177] The first capacitor 20a and the second capacitor 20b are connected in series. Specifically, the first outer electrode 25a of the first capacitor 20a and the fourth outer electrode 25d of the second capacitor 20b are connected to each other, thereby connecting the first capacitor 20a and the second capacitor 20b in series.

[0178] The first capacitor 20a is electrically led out to the outside of the passive electronic component 3A via the second external electrode 25b.

[0179] The second capacitor 20b is electrically led out to the outside of the passive electronic component 3A via a third external electrode 25c.

[0180] One end of the inductor 100 is connected to the connection between the first capacitor 20 a and the second capacitor 20 b. Specifically, one end of the inductor 100 is connected to the connection between the first outer electrode 25 a of the first capacitor 20 a and the fourth outer electrode 25 d of the second capacitor 20 b.

[0181] As described above, the inductor 100 is connected to both the first capacitor 20 a and the second capacitor 20 b. Note that the inductor 100 may be connected to either the first capacitor 20 a or the second capacitor 20 b. In other words, the inductor 100 may be connected to at least one of the first capacitor 20 a and the second capacitor 20 b.

[0182] The other end of the inductor 100 is connected to the fifth external electrode 25e, so that the inductor 100 is electrically led out to the outside of the passive electronic component 3A via the fifth external electrode 25e.

[0183] The inductor 100 is formed by winding an internal wiring 110 .

[0184] The internal wiring 110 is wound spirally along the direction of the winding axis.

[0185] The direction of the winding axis of the internal wiring 110 is perpendicular to the first main surface 10 a of the substrate 10 .

[0186] 20, 22, and 23, the direction of the winding axis of the internal wiring 110 is parallel to the first direction D1. In other words, the internal wiring 110 is wound in a spiral shape when viewed from the first direction D1.

[0187] The internal wiring 110 includes at least one conductor layer.

[0188] In the examples shown in FIGS. 20, 22, and 23, the internal wiring 110 includes three conductor layers: a first conductor layer 111a, a second conductor layer 111b, and a third conductor layer 111c.

[0189] In the examples shown in Figures 20, 22, and 23, the first conductor layer 111a and the laminate of the second conductor layer 111b and the third conductor layer 111c are connected in sequence along the path of the internal wiring 110 extending from one end side of the inductor 100 (the side of the first capacitor 20a and the second capacitor 20b) to the other end side of the inductor 100 (the side opposite the first capacitor 20a and the second capacitor 20b).

[0190] All of the conductor layers included in the internal wiring 110 each independently contain the same material as the first internal electrode layer 22a, the second internal electrode layer 22b, the third internal electrode layer 22c, the fourth internal electrode layer 22d, the fifth internal electrode layer 22e, the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d.

[0191] 20, 21, 22, and 23, the first conductor layer 111a contains the same material as the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d. The second conductor layer 111b contains the same material as the second internal electrode layer 22b or the third internal electrode layer 22c. The third conductor layer 111c contains the same material as the first internal electrode layer 22a or the fifth internal electrode layer 22e.

[0192] As described above, in the passive electronic component 3A, all of the conductor layers included in the internal wiring 110 of the inductor 100 contain the same material as the internal electrode layers or external electrodes included in the first capacitor 20a and the second capacitor 20b. This allows all of the conductor layers to be formed at the same time as the internal electrode layers or external electrodes during the manufacturing process of the passive electronic component 3A. Specifically, the first conductor layer 111a can be formed at the same time as the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d. The second conductor layer 111b can be formed at the same time as the second internal electrode layer 22b or the third internal electrode layer 22c. Furthermore, the third conductor layer 111c can be formed at the same time as the first internal electrode layer 22a or the fifth internal electrode layer 22e. Therefore, during the manufacturing process of the passive electronic component 3A, the inductor 100 can be formed at the same time as the first capacitor 20a and the second capacitor 20b.

[0193] As described above, in the manufacturing process of the passive electronic component 3A, the inductor 100 can be formed at the same time as the first capacitor 20 a and the second capacitor 20 b, so the conductor layer included in the internal wiring 110 of the inductor 100 can be formed to be as thick as the internal electrode layers included in the first capacitor 20 a and the second capacitor 20 b. Therefore, in the passive electronic component 3A, it is possible to increase the Q value of the inductor 100.

[0194] The passive electronic component 3A is manufactured in the same manner as the passive electronic component 2A, except that, for example, the third conductor layer 111c is formed in the process of forming the first internal electrode layer 22a or the fifth internal electrode layer 22e, the second conductor layer 111b is formed in the process of forming the second internal electrode layer 22b or the third internal electrode layer 22c, and the first conductor layer 111a is formed in the process of forming the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d.

[0195] In the passive electronic component according to the third embodiment of the present invention, the number of conductor layers included in the internal wiring of the inductor is not limited to the above-mentioned three layers, as long as it is at least one layer.

[0196] In the passive electronic component of embodiment 3 of the present invention, the combination of materials of all the conductor layers included in the internal wiring of the inductor is not limited to the above-mentioned combinations, as long as it is a combination selected from the first internal electrode layer, the second internal electrode layer, the third internal electrode layer, the fourth internal electrode layer, the fifth internal electrode layer, the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode.

[0197] [Fourth Embodiment] A passive electronic component according to a fourth embodiment of the present invention differs from the passive electronic component according to the second embodiment of the present invention in that it further includes an inductor formed by winding an internal wiring including a plurality of conductor layers.

[0198] In the passive electronic component of the fourth embodiment of the present invention, the direction of the winding axis of the internal wiring is parallel to the first main surface of the substrate, and all of the conductor layers each independently contain the same material as the first internal electrode layer, the second internal electrode layer, the third internal electrode layer, the fourth internal electrode layer, the fifth internal electrode layer, the first external electrode, the second external electrode, the third external electrode, or the fourth external electrode.

[0199] Fig. 24 is a plan view schematic diagram showing an example of a passive electronic component according to embodiment 4 of the present invention. Fig. 25 is a cross-sectional view schematic diagram showing an example of a cross-section along line f1-f2 of the passive electronic component shown in Fig. 24. Fig. 26 is a cross-sectional view schematic diagram showing an example of a cross-section along line g1-g2 of the passive electronic component shown in Fig. 24.

[0200] The passive electronic component 4A shown in FIGS. 24, 25, and 26 further includes an inductor 200 in addition to the substrate 10, the first capacitor 20a, and the second capacitor 20b.

[0201] The configurations of the first capacitor 20a and the second capacitor 20b in the passive electronic component 4A are similar to the configurations of the first capacitor 20a and the second capacitor 20b in the passive electronic component 3A.

[0202] One end of the inductor 200 is connected to the connection between the first capacitor 20a and the second capacitor 20b. Specifically, one end of the inductor 200 is connected to the connection between the first outer electrode 25a of the first capacitor 20a and the fourth outer electrode 25d of the second capacitor 20b.

[0203] As described above, the inductor 200 is connected to both the first capacitor 20a and the second capacitor 20b. Note that the inductor 200 may be connected to either the first capacitor 20a or the second capacitor 20b. In other words, the inductor 200 may be connected to at least one of the first capacitor 20a and the second capacitor 20b.

[0204] The other end of the inductor 200 is electrically led out to the outside of the passive electronic component 4A.

[0205] The inductor 200 is formed by winding an internal wiring 210 .

[0206] The internal wiring 210 is wound spirally along the direction of the winding axis.

[0207] The direction of the winding axis of the internal wiring 210 is parallel to the first main surface 10 a of the substrate 10 .

[0208] 24 and 26, the direction of the winding axis of the internal wiring 210 is parallel to the second direction D2. In other words, the internal wiring 210 is wound in a spiral shape when viewed from the second direction D2.

[0209] The internal wiring 210 includes multiple conductor layers.

[0210] In the example shown in Figures 24 and 26, the internal wiring 210 includes nine conductor layers: a first conductor layer 211a, a second conductor layer 211b, a third conductor layer 211c, a fourth conductor layer 211d, a fifth conductor layer 211e, a sixth conductor layer 211f, a seventh conductor layer 211g, an eighth conductor layer 211h, and a ninth conductor layer 211j.

[0211] In the example shown in Figures 24 and 26, along the path of the internal wiring 210 extending from one end side of the inductor 200 (the side of the first capacitor 20a and the second capacitor 20b) to the other end side of the inductor 200 (the side opposite the first capacitor 20a and the second capacitor 20b), a laminate of the first conductor layer 211a, the second conductor layer 211b, the third conductor layer 211c, and the fourth conductor layer 211d, a laminate of the fifth conductor layer 211e, the sixth conductor layer 211f, the seventh conductor layer 211g, and the eighth conductor layer 211h, and the ninth conductor layer 211j are connected in order.

[0212] All of the conductor layers included in the internal wiring 210 each independently contain the same material as the first internal electrode layer 22a, the second internal electrode layer 22b, the third internal electrode layer 22c, the fourth internal electrode layer 22d, the fifth internal electrode layer 22e, the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d.

[0213] In the examples shown in Figures 24, 25, and 26, the first conductor layer 211a contains the same material as the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d. The second conductor layer 211b contains the same material as the fourth internal electrode layer 22d. The third conductor layer 211c contains the same material as the second internal electrode layer 22b or the third internal electrode layer 22c. The fourth conductor layer 211d contains the same material as the first internal electrode layer 22a or the fifth internal electrode layer 22e. The fifth conductor layer 211e contains the same material as the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d. The sixth conductor layer 211f contains the same material as the fourth internal electrode layer 22d. The seventh conductor layer 211g contains the same material as the second internal electrode layer 22b or the third internal electrode layer 22c. The eighth conductor layer 211h contains the same material as the first internal electrode layer 22a or the fifth internal electrode layer 22e. The ninth conductor layer 211j contains the same material as the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d.

[0214] As described above, in the passive electronic component 4A, all of the conductor layers included in the internal wiring 210 of the inductor 200 contain the same material as the internal electrode layers or external electrodes included in the first capacitor 20a and the second capacitor 20b. This allows all of the conductor layers to be formed at the same time as the internal electrode layers or external electrodes during the manufacturing process of the passive electronic component 4A. Specifically, the first conductor layer 211a can be formed at the same time as the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d. The second conductor layer 211b can be formed at the same time as the fourth internal electrode layer 22d. The third conductor layer 211c can be formed at the same time as the second internal electrode layer 22b or the third internal electrode layer 22c. The fourth conductor layer 211d can be formed at the same time as the first internal electrode layer 22a or the fifth internal electrode layer 22e. Furthermore, the fifth conductor layer 211e can be formed at the same time as the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d. The sixth conductor layer 211f can be formed at the same time as the fourth internal electrode layer 22d. The seventh conductor layer 211g can be formed at the same time as the second internal electrode layer 22b or the third internal electrode layer 22c. The eighth conductor layer 211h can be formed at the same time as the first internal electrode layer 22a or the fifth internal electrode layer 22e. Furthermore, the ninth conductor layer 211j can be formed at the same time as the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d. Therefore, in the manufacturing process of the passive electronic component 4A, the inductor 200 can be formed at the same time as the first capacitor 20a and the second capacitor 20b.

[0215] As described above, in the manufacturing process of the passive electronic component 4A, the inductor 200 can be formed at the same time as the first capacitor 20a and the second capacitor 20b, so the conductor layer included in the internal wiring 210 of the inductor 200 can be formed to be as thick as the internal electrode layers included in the first capacitor 20a and the second capacitor 20b. Therefore, in the passive electronic component 4A, it is possible to increase the Q value of the inductor 200.

[0216] Furthermore, in passive electronic component 4A, the winding axis of internal wiring 210 of inductor 200 is parallel to first main surface 10a of substrate 10, and therefore the amount of magnetic flux penetrating substrate 10 is reduced compared to passive electronic component 3A, in which the winding axis of internal wiring 110 of inductor 100 is perpendicular to first main surface 10a of substrate 10. Therefore, in passive electronic component 4A, it is possible to increase the Q value of inductor 200.

[0217] The passive electronic component 4A is manufactured in the same manner as the passive electronic component 2A, except that, for example, the fourth conductor layer 211d and the eighth conductor layer 211h are formed in the process of forming the first internal electrode layer 22a or the fifth internal electrode layer 22e, the third conductor layer 211c and the seventh conductor layer 211g are formed in the process of forming the second internal electrode layer 22b or the third internal electrode layer 22c, the second conductor layer 211b and the sixth conductor layer 211f are formed in the process of forming the fourth internal electrode layer 22d, and the first conductor layer 211a, the fifth conductor layer 211e, and the ninth conductor layer 211j are formed in the process of forming the first external electrode 25a, the second external electrode 25b, the third external electrode 25c, or the fourth external electrode 25d.

[0218] In the passive electronic component according to the fourth embodiment of the present invention, the number of conductor layers included in the internal wiring of the inductor is not limited to the above-mentioned nine layers, as long as it is a plurality of layers.

[0219] In the passive electronic component of the fourth embodiment of the present invention, the combination of materials of all the conductor layers included in the internal wiring of the inductor is not limited to the above-mentioned combinations, as long as it is a combination selected from the first internal electrode layer, the second internal electrode layer, the third internal electrode layer, the fourth internal electrode layer, the fifth internal electrode layer, the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode.

[0220] In the above embodiment, the case where the entire second internal electrode layer and the entire third internal electrode layer are in contact with the surface of the first dielectric layer opposite the substrate has been exemplified, but it is sufficient that at least a portion of the second internal electrode layer and at least a portion of the third internal electrode layer are in contact with the surface of the first dielectric layer opposite the substrate. That is, the portion in contact with the surface of the first dielectric layer opposite the substrate may be a combination of a portion of the second internal electrode layer and a portion of the third internal electrode layer, a combination of the entire second internal electrode layer and a portion of the third internal electrode layer, a combination of a portion of the second internal electrode layer and the entire third internal electrode layer, or a combination of the entire second internal electrode layer and the entire third internal electrode layer. For example, in the passive electronic component 1B shown in FIG. 14 , if a portion of the second internal electrode layer 22 b that does not overlap the first internal electrode layer 22 a in the first direction D1 is in contact with the insulating layer 30 without the first dielectric layer 23 a therebetween, a portion of the second internal electrode layer 22 b will be in contact with the surface of the first dielectric layer 23 a opposite the substrate 10. Furthermore, in the passive electronic component 1B shown in Figure 14, when a portion of the third internal electrode layer 22c that does not overlap with the fourth internal electrode layer 22d in the first direction D1 contacts the insulating layer 30 without going through the first dielectric layer 23a, a part of the third internal electrode layer 22c contacts the surface of the first dielectric layer 23a opposite the substrate 10.

[0221] In the above embodiments, an example has been given of a case where one passive electronic component has two capacitors including a first capacitor and a second capacitor as the plurality of capacitors, but one passive electronic component may also have three or more capacitors including a first capacitor and a second capacitor.

[0222] In the passive electronic component of the present invention, for all capacitors (including the first capacitor and the second capacitor), each capacitor element constituting the capacitance forming portion preferably includes a single dielectric layer, rather than a laminate of multiple dielectric layers. In the example shown in Fig. 2, one capacitor element constituting the first capacitance forming portion 21a of the first capacitor 20a includes one first dielectric layer 23a. Also, in the example shown in Fig. 2, one capacitor element constituting the second capacitance forming portion 21b of the second capacitor 20b includes one second dielectric layer 23b.

[0223] When the passive electronic component of the present invention has an insulating layer, the insulating layer is preferably provided between the substrate and all of the capacitors (including the first capacitor and the second capacitor) in the first direction.

[0224] When the passive electronic component of the present invention has a moisture-resistant protective layer, the moisture-resistant protective layer preferably covers the capacitance forming portions of all the capacitors (including the first capacitor and the second capacitor).

[0225] When the passive electronic component of the present invention has a resin protective layer, the resin protective layer preferably covers the substrate and the capacitance forming portions of all the capacitors (including the first capacitor and the second capacitor).

[0226] The present specification discloses the following:

[0227] <1> A passive electronic component comprising: a substrate having a first main surface and a second main surface opposing each other in a first direction; and a plurality of capacitors provided on the first main surface side of the substrate, wherein the plurality of capacitors include a first capacitor and a second capacitor spaced apart from the first capacitor in a second direction perpendicular to the first direction, wherein the first capacitor has a first capacitance forming portion including a first internal electrode layer, a first dielectric layer, and a second internal electrode layer stacked in this order from the substrate side in the first direction, and the second capacitor has a second capacitance forming portion including a third internal electrode layer, a second dielectric layer, and a fourth internal electrode layer stacked in this order from the substrate side in the first direction, and at least a portion of the second internal electrode layer and at least a portion of the third internal electrode layer are in contact with a surface of the first dielectric layer on a side opposite to the substrate.

[0228] <2> The passive electronic component according to <1>, wherein the first dielectric layer of the first capacitance forming portion and the second dielectric layer of the second capacitance forming portion have different dimensions in the first direction.

[0229] <3> The passive electronic component according to <1> or <2>, wherein the first capacitor further has a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer, and the second capacitor further has a third external electrode connected to the third internal electrode layer and a fourth external electrode connected to the fourth internal electrode layer.

[0230] <4> The passive electronic component according to <1> or <2>, wherein the second capacitance forming portion further includes the first dielectric layer and a fifth internal electrode layer stacked in this order on the substrate side in the first direction with respect to the third internal electrode layer.

[0231] <5> The passive electronic component according to <4>, wherein the first capacitor further has a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer, and the second capacitor further has a third external electrode connected to the fifth internal electrode layer and a fourth external electrode connected to the fourth internal electrode layer.

[0232] <6> The passive electronic component according to <3> or <5>, wherein, when viewed in plan from the first direction, a periphery of the second external electrode is located inside a periphery of the second internal electrode layer.

[0233] <7> The passive electronic component according to <3> or <5>, wherein, when viewed in plan from the first direction, a periphery of the fourth external electrode is located inside a periphery of the fourth internal electrode layer.

[0234] <8> The passive electronic component according to <5>, further comprising an inductor formed by winding internal wiring including at least one conductor layer, wherein a direction of a winding axis of the internal wiring is perpendicular to the first main surface of the substrate, and all of the conductor layers each independently contain the same material as the first internal electrode layer, the second internal electrode layer, the third internal electrode layer, the fourth internal electrode layer, the fifth internal electrode layer, the first external electrode, the second external electrode, the third external electrode, or the fourth external electrode.

[0235] <9> The passive electronic component according to <5>, further comprising an inductor formed by winding internal wiring including a plurality of conductor layers, wherein a direction of a winding axis of the internal wiring is parallel to the first main surface of the substrate, and all of the conductor layers each independently contain the same material as the first internal electrode layer, the second internal electrode layer, the third internal electrode layer, the fourth internal electrode layer, the fifth internal electrode layer, the first external electrode, the second external electrode, the third external electrode, or the fourth external electrode.

[0236] <10> The passive electronic component according to any one of <1> to <9>, further comprising an insulating layer provided between the substrate and the first capacitor in the first direction and between the substrate and the second capacitor in the first direction.

[0237] <11> The passive electronic component according to any one of <1> to <10>, further comprising a moisture-resistant protective layer covering the first capacitance forming portion and the second capacitance forming portion.

[0238] <12> The passive electronic component according to any one of <1> to <11>, further comprising a resin protective layer that covers the substrate, the first capacitance forming portion, and the second capacitance forming portion.

[0239] 1A, 1B, 2A, 2B, 3A, 4A Passive electronic component 10 Substrate 10a First main surface of substrate 10b Second main surface of substrate 20 Capacitor 20a First capacitor 20b Second capacitor 21a First capacitance forming portion 21b Second capacitance forming portion 22a First internal electrode layer 22b Second internal electrode layer 22c Third internal electrode layer 22d Fourth internal electrode layer 22e Fifth internal electrode layer 23a First dielectric layer 23b Second dielectric layer 25a First external electrode 25b Second external electrode 25c Third external electrode 25d Fourth external electrode 25e Fifth external electrode 30 Insulating layer 40 Moisture-resistant protective layer 50 Resin protective layer 23ah, 23bha, 23bhb, 23bhc, 40ha, 40hb, 40hc, 40hd, 50ha, 50hb, 50hc, 50hd, 60ha, 60hb, 60hc, 60hd Through holes 100, 200 Inductors 110, 210 Internal wiring 111a, 211a First conductor layer 111b, 211b Second conductor layer 111c, 211c Third conductor layer 211d Fourth conductor layer 211e Fifth conductor layer 211f Sixth conductor layer 211g Seventh conductor layer 211h Eighth conductor layer 211j Ninth conductor layer D1 First direction D2 Second direction D3 Third direction R Region between the first capacitor (first capacitance forming portion) and the second capacitor (second capacitance forming portion) in the second direction T1: Dimension of the first dielectric layer of the first capacitance forming portion in the first direction T2: Dimension of the second dielectric layer of the second capacitance forming portion in the first direction

Claims

1. A passive electronic component comprising: a substrate having a first main surface and a second main surface opposing each other in a first direction; and a plurality of capacitors provided on the first main surface side of the substrate, wherein the plurality of capacitors include a first capacitor and a second capacitor spaced from the first capacitor in a second direction perpendicular to the first direction, wherein the first capacitor has a first capacitance forming portion including a first internal electrode layer, a first dielectric layer, and a second internal electrode layer stacked in order from the substrate side in the first direction, and the second capacitor has a second capacitance forming portion including a third internal electrode layer, a second dielectric layer, and a fourth internal electrode layer stacked in order from the substrate side in the first direction, and at least a portion of the second internal electrode layer and at least a portion of the third internal electrode layer are in contact with a surface of the first dielectric layer opposite the substrate.

2. A passive electronic component as described in claim 1, wherein the first dielectric layer of the first capacitance forming portion and the second dielectric layer of the second capacitance forming portion have different dimensions in the first direction.

3. A passive electronic component as described in claim 1 or 2, wherein the first capacitor further has a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer, and the second capacitor further has a third external electrode connected to the third internal electrode layer and a fourth external electrode connected to the fourth internal electrode layer.

4. A passive electronic component as described in claim 1 or 2, wherein the second capacitance forming portion further includes the first dielectric layer and a fifth internal electrode layer stacked in sequence on the substrate side in the first direction relative to the third internal electrode layer.

5. A passive electronic component as described in claim 4, wherein the first capacitor further has a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer, and the second capacitor further has a third external electrode connected to the fifth internal electrode layer and a fourth external electrode connected to the fourth internal electrode layer.

6. A passive electronic component as described in claim 3 or 5, wherein, when viewed in a plane from the first direction, the periphery of the second external electrode is located inside the periphery of the second internal electrode layer.

7. A passive electronic component as described in claim 3 or 5, wherein, when viewed in a plane from the first direction, the periphery of the fourth external electrode is located inside the periphery of the fourth internal electrode layer.

8. A passive electronic component as described in claim 5, further comprising an inductor formed by winding internal wiring including at least one conductor layer, wherein the direction of the winding axis of the internal wiring is perpendicular to the first main surface of the substrate, and all of the conductor layers each independently contain the same material as the first internal electrode layer, the second internal electrode layer, the third internal electrode layer, the fourth internal electrode layer, the fifth internal electrode layer, the first external electrode, the second external electrode, the third external electrode, or the fourth external electrode.

9. A passive electronic component as described in claim 5, further comprising an inductor formed by winding internal wiring including a plurality of conductor layers, wherein a direction of a winding axis of the internal wiring is parallel to the first main surface of the substrate, and all of the conductor layers each independently contain the same material as the first internal electrode layer, the second internal electrode layer, the third internal electrode layer, the fourth internal electrode layer, the fifth internal electrode layer, the first external electrode, the second external electrode, the third external electrode, or the fourth external electrode.

10. A passive electronic component according to any one of claims 1 to 9, further comprising an insulating layer provided between the substrate and the first capacitor in the first direction, and between the substrate and the second capacitor in the first direction.

11. A passive electronic component according to any one of claims 1 to 10, further comprising a moisture-resistant protective layer covering said first capacitance forming portion and said second capacitance forming portion.

12. A passive electronic component according to any one of claims 1 to 11, further comprising a resin protective layer that covers the substrate, the first capacitance forming portion, and the second capacitance forming portion.

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