Comparator circuit

Abstract

A comparator circuit comprising an adder that generates an output voltage, a hold capacitor that holds the output voltage output from the adder, a comparator that receives the output voltage held in the hold capacitor from one input terminal and performs a comparison operation using the received output voltage, a cutoff switch provided in a connection path between the adder and the one input terminal of the comparator, and a reset switch that is connected between the cutoff switch and the hold capacitor and that resets the potential of the hold capacitor.

Description

comparison circuit

[0001] The present invention relates to a comparison circuit.

[0002] Conventionally, in a comparison circuit mounted on a ΔΣ AD converter or the like, a technique has been devised in which a cutoff switch is provided in the connection path between the preceding circuit and the input terminal of the comparator, and the connection path is cut off when the comparator performs a comparison operation, thereby preventing the kickback noise of the comparator from being transmitted to the preceding circuit (see, for example, Patent Documents 1 and 2 below).

[0003] JP 2009-232184 A JP 2002-237743 A

[0004] However, in the conventional technology, the initial charge amount of the holding capacitance for holding the voltage input to the comparator is indefinite, so when the preceding circuit is an adder, the input voltage to the comparator becomes indefinite and there is a risk that the input voltage to the comparator will deviate from the operating range of the comparator.

[0005] A comparison circuit according to one embodiment includes an adder that generates an output voltage, a holding capacitor that holds the output voltage output from the adder, a comparator that receives the output voltage held in the holding capacitor from one of its input terminals and performs a comparison operation using the output voltage, a cut-off switch provided in a connection path between the adder and one of the input terminals of the comparator, and a reset switch connected between the cut-off switch and the holding capacitor that resets the potential of the holding capacitor.

[0006] According to the comparison circuit of one embodiment, the initial charge amount of the holding capacitor can be made constant by resetting the potential of the holding capacitor with the reset switch.

[0007] FIG. 1 shows an example of the configuration of a hybrid AD converter according to an embodiment; FIG. 2 shows an example of the operation of the hybrid AD converter according to an embodiment; FIG. 3 shows an example of the operation of the hybrid AD converter according to an embodiment; FIG. 4 shows a first example of the circuit configuration of a comparison circuit according to an embodiment; FIG. 5 shows a timing chart illustrating the operation timing of each control signal in the hybrid AD converter according to an embodiment; FIG. 6 shows an example of the signal-to-quantization noise ratio (SQNR) in the comparison circuit according to an embodiment; FIG. 7 shows an example of the signal-to-quantization noise ratio (SQNR) in the comparison circuit according to an embodiment;

[0008] Hereinafter, an embodiment will be described with reference to the drawings.

[0009] (Configuration of Hybrid AD Converter 100) Fig. 1 is a diagram showing an example of the configuration of a hybrid AD converter 100 according to an embodiment. The hybrid AD converter 100 shown in Fig. 1 can convert an analog signal (e.g., an output signal from a current detection resistor, a sensor, etc.) into a digital signal.

[0010] As shown in FIG. 1 , the hybrid AD converter 100 includes an input terminal 101, an output terminal 102, a switch 110A, a switch 110B, a line 115A, a line 115B, an adder 120, a delay integrator 130, an adder 140, a quantizer 150, a DA converter (Digital to Analog Converter) 160, a DEMUX (demultiplexer) 170, an integrator 180A, a shift calculator 180B, a calculator 180C, and a controller 190.

[0011] The input terminal 101 receives an analog signal U (V / V ｒｅｆ ) (for example, output signals from a current detection resistor, a sensor, etc.) are input.

[0012] The output terminal 102 is connected to the output side of the calculation unit 180C. The output terminal 102 outputs the analog signal U (V / V ｒｅｆ) is AD converted to generate a digital signal (total output D), and the digital signal is output.

[0013] The switch 110A is provided between the input terminal 101 and the adder 120. The switch 110A is controlled to be turned on and off by the control unit 190. The switch 110A is switched on in the first step and switched off in the second step.

[0014] The switch 110B is provided on the line 115B. The switch 110B is controlled to be turned on and off by the control unit 190. The switch 110B is switched off in the first step, and is switched on in the second step.

[0015] The line 115A is a line that connects the input side of the switch 110A to the first input terminal IN1 of the adder 140, and is a line that connects the input side of the switch 110A to the first input terminal IN1 of the adder 140. ｒｅｆ ) is input to adder 140.

[0016] The line 115B is a feedback loop that connects the output side of the delay integrator 130 and one positive input terminal of the adder 120. The line 115B is provided with a switch 110B.

[0017] The line 115C is a feedback loop that connects the output side of the quantizer 150 and the negative input terminal of the adder 120. A DA converter 160 is provided on the line 115C.

[0018] The adder 120 has two input terminals and one output terminal. One of the two input terminals is a + input terminal, and the other is a - input terminal. The + input terminal receives the input without inverting the sign, and the - input terminal receives the input with the sign inverted.

[0019] The switches 110A and 110B are connected to one positive input terminal of the adder 120. The negative input terminal of the adder 120 is connected to the line 115C.

[0020] In the first step, when switch 110A is on and switch 110B is off, adder 120 adds analog signal U input to switch 110A to an inverted output obtained by inverting the sign of the output of DA converter 160. That is, in the first step, adder 120 subtracts the output of DA converter 160 from analog signal U input to switch 110A.

[0021] Furthermore, when switch 110A is off and switch 110B is on in the second step, adder 120 adds the output of delay integrator 130 to an inverted output obtained by inverting the sign of the output of DA converter 160. That is, in the second step, adder 120 subtracts the output of DA converter 160 from the output of delay integrator 130.

[0022] The delay integrator 130 is provided between the adder 120 and the adder 140. The delay integrator 130 includes an adder 131 and a holding unit 132. The holding unit 132 holds the output of the adder 131 from one cycle before. The output terminal of the holding unit 132 is connected to one input terminal of the adder 131 via a feedback loop in the delay integrator 130 and to a second input terminal IN2 of the adder 140. The other input terminal of the adder 131 is connected to the output terminal of the adder 120, and the output terminal is connected to the input terminal of the holding unit 132. The adder 131 adds the output of the holding unit 132 and the output of the adder 120 and outputs the sum to the holding unit 132. The holding unit 132 holds the output of the adder 131 at the end of each cycle in the first step and the second step. Therefore, in the next cycle, the holding unit 132 holds the output of the adder 131 from one cycle before. Furthermore, the value held by the holding unit 132 is reset at the end of the second step.

[0023] The adder 140 has three input terminals (a first input terminal IN1, a second input terminal IN2, and a third input terminal IN3). The first input terminal IN1 of the adder 140 is connected to the input side of the switch 110A, the second input terminal IN2 is connected to the output terminal of the holding unit 132 of the delay integrator 130, and the third input terminal IN3 is connected to the reference voltage V ｒｅｆ, and the output terminal is connected to the input terminal of the quantizer 150.

[0024] The quantizer 150 has an input terminal connected to the output terminal of the adder 140, and an output terminal connected to the input terminal of the DA converter 160 and the input terminal of the DEMUX 170. The quantizer 150 quantizes the analog signal input from the adder 140 and outputs a digital code. The quantizer 150 can perform quantization at three levels (1, 0, -1).

[0025] The adder 140 and the quantizer 150 constitute the comparison circuit 10. Specifically, the comparison circuits 10 have the same configuration (however, the input voltage V ｒｅｆ The comparator circuit 10 includes a first component 10A and a second component 10B (each of which has a different sign), and an adder 140 and a quantizer 150 are provided in the first component 10A and the second component 10B. Each of the first component 10A and the second component 10B functions as a two-level quantizer by itself. However, the comparator circuit 10 functions as a three-level quantizer by combining the two-level output signal output from the quantizer 150 of the first component 10A and the two-level output signal output from the quantizer 150 of the second component 10B and outputting a three-level (1, 0, -1) output signal.

[0026] The DA converter 160 is inserted in series into the line 115C, which is a feedback loop connecting the output side of the quantizer 150 and the negative terminal of the adder 120. The DA converter 160 converts the output (digital code) of the quantizer 150 into an analog signal and outputs it. The DA converter 160 has three levels (+V ｒｅｆ (V), 0(V), -V ｒｅｆ (V)) can perform analog conversion.

[0027] The DEMUX 170 has an input terminal connected to the output terminal of the quantizer 150 and two output terminals connected to an integrator 180A and a shift operation unit 180B, and connects the input terminal to one of the two output terminals. This switching is performed by the control unit 190. The input terminal of the DEMUX 170 is connected to the integrator 180A in the first step, and to the shift operation unit 180B in the second step.

[0028] In the first step, the integrator 180A integrates the output (digital code) of the quantizer 150 input via the DEMUX 170, and outputs the result to the calculator 180C.

[0029] In the second step, the shift operation unit 180B performs a shift operation on the output (digital code) of the quantizer 150 input via the DEMUX 170, and outputs the resultant output (second output) to the operation unit 180C.

[0030] The calculation unit 180C adds the output (first output) of the integrator unit 180A in the first step to the output (second output) of the shift calculation unit 180B in the second step, and outputs a sum output D of the first output and the second output.

[0031] The control unit 190 is configured by a digital circuit (ASIC), and performs operations such as switching the switches 110A and 110B on and off, resetting the holding unit 132 of the delay integrator 130, and switching the DEMUX 170. The control unit 190 may also be configured by a microcontroller (MCU).

[0032] (Operation of Hybrid AD Converter 100) FIGS. 2 and 3 are diagrams for explaining the operation of the hybrid AD converter 100 according to one embodiment.

[0033] 2, in the first step, the switch 110A is turned on and the switch 110B is turned off in the hybrid AD converter 100. As a result, in the first step, the hybrid AD converter 100 converts the analog signal U(V / V ｒｅｆ) and the output of the delay integrator 130 (the output of the holding unit 132) are added by the adder 140, quantized into three levels by the quantizer 150, and fed back to the adder 120 by the DAC 160. By repeating this cycle, in the first step, the hybrid AD converter 100 operates as an incremental AD converter. The output of the quantizer 150 in each cycle in the first step is integrated by the integrating unit 180A.

[0034] The number of cycles for repeating the operation in the first step is K. In this case, the quantizer 150 outputs K digital codes, Q1[1], ..., Q1[K]. Therefore, the output D1 of the integrator 180A is expressed by the following equation (1): K=2 Ｍ In the first step, an output D1 of M+1 bits is obtained.

[0035]

[0036] 3 , in the second step of the hybrid AD converter 100, the switch 110A is turned off and the switch 110B is turned on. As a result, in the second step of the hybrid AD converter 100, the value X held in the holding unit 132 of the delay integrator 130 in the Kth cycle of the first step is quantized in three levels by the quantizer 150, and the digital code output from the quantizer 150 is converted into an analog code in three levels by the DAC 160. By repeating such a cycle for N cycles, the hybrid AD converter 100 operates as a cyclic AD converter.

[0037] When the cyclic operation is performed N cycles in the second step, the quantizer 150 outputs N digital codes Q2[1], ..., Q2[N]. Therefore, the output D2 of the shift operation unit 180B is expressed by the following equation (2). By performing the cyclic operation N cycles, an output D2 of N+1 bits is obtained.

[0038]

[0039] As a result, the total output D output by the calculation unit 180C is expressed by the following equation (3).

[0040]

[0041] (First Example of Circuit Configuration of Comparison Circuit 10) FIG. 4 is a diagram showing a first example of the circuit configuration of the comparison circuit 10 according to one embodiment. FIG. 4 shows an example in which the circuit configuration of the comparison circuit 10 is a single-ended configuration. As shown in FIG. 4, the comparison circuit 10 has a first component 10A and a second component 10B. The first component 10A of the comparison circuit 10 includes a comparator 11 and an adder 20.

[0042] The second component 10B of the comparison circuit 10 has the same configuration as the first component 10A, that is, includes a comparator 11 and an adder 20. However, the first component 10A and the second component 10B have different input voltages V ｒｅｆ The positive and negative signs are different.

[0043] The first component 10A has a first input terminal IN1 to V ｉｎｔ is input, and V is output from the second input terminal IN2. ｉｎ is input, and a negative reference voltage V is output from the third input terminal IN3. ｒｅｆｎ is entered.

[0044] The second component 10B has a first input terminal IN1 to V ｉｎｔ is input, and V is output from the second input terminal IN2. ｉｎ is input, and a positive reference voltage V is output from the third input terminal IN3. ｒｅｆｐ is entered.

[0045] The comparator 11 receives the output voltage V ａｄｄ The comparator 11 compares the output voltage V input from the + input terminal with a reference voltage V input from the - input terminal (the other input terminal), and outputs a binary signal Q indicating the comparison result. ａｄｄ is higher than the reference voltage input from the - input terminal, the comparator 11 outputs a high-level binary signal Q. Conversely, the comparator 11 outputs a high-level binary signal Q when the output voltage V ａｄｄ is lower than the reference voltage input from the - input terminal, a low level binary signal Q is output.

[0046] The adder 20 has a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a switched capacitor circuit 21, a switched capacitor circuit 22, a switched capacitor circuit 23, an input voltage selector switch SW15, and a switch SW24.

[0047] The first input terminal IN1 is connected to the output voltage V ｉｎｔ The second input terminal IN2 is connected to the input terminal 101 of the hybrid AD converter 100, and the voltage V ｉｎ The third input terminal IN3 receives a reference voltage V ｒｅｆ is entered.

[0048] The switched capacitor circuit 21 has a capacitance C ａ１ and capacitance C ａ１ and a switch SW11 provided between the first input terminal IN1 and the first input terminal IN2; ａ１ and a switch SW21 provided between the power supply and the ground potential.

[0049] The switched capacitor circuit 22 has a capacitance C ｂ２ and capacitance C ｂ２ and a switch SW12 provided between the first input terminal IN1 and the second input terminal IN2, and a capacitor C ｂ２ and a switch SW22 provided between the power supply and the ground potential.

[0050] The switched capacitor circuit 23 has a capacitance C ｔｈ and capacitance C ｔｈ and a switch SW13 provided between the third input terminal IN3 and the third input terminal IN4; ｔｈ and a switch SW23 provided between the power supply and the ground potential.

[0051] The adder 20 has a capacitance C ａ１ , capacity C ｂ２ , and capacitance C ｔｈ The charge stored in the ａｄｄ and generates the output voltage V ａｄｄ Output.

[0052] The input voltage changeover switch SW15 is connected to the first input terminal IN1 and the switched capacitor circuit 22 (switch SW12 and capacitance C ｂ２ It is located between the

[0053] The switch SW24 has a capacitance C ａ１ , capacity C ｂ２ , and capacitance C ｔｈ and the ground potential.

[0054] (Operation of the Comparator Circuit 10) FIG. 5 is a timing chart showing the operation timing of each control signal in the hybrid AD converter 100 according to one embodiment.

[0055] The comparison circuit 10 configured as described above switches, for each cycle, between a "standby mode" in which the comparator 11 does not perform a comparison operation and a "comparison mode" in which the comparator 11 performs a comparison operation. Specifically, the comparison circuit 10 switches to the "standby mode" when the control signal Φ1 is on and the control signal Φ2 is off. The comparison circuit 10 also switches to the "comparison mode" when the control signal Φ1 is off and the control signal Φ2 is on.

[0056] In the comparison circuit 10, when the comparator 11 is in a "standby mode" in which it does not perform a comparison operation, the control signal Φ1 switches the switches SW11 to SW13 on and the control signal Φ2 switches the switches SW21 to SW24 off, thereby causing the adder 20 to calculate the output voltage V ａｄｄ can be generated and output.

[0057] In the comparison circuit 10, when the comparator 11 is in a comparison mode in which it performs a comparison operation, the switches SW11 to SW13 are turned off by a control signal Φ1, and the switches SW21 to SW24 are turned on by a control signal Φ2, so that the comparator 11 receives the output voltage V ａｄｄ The comparator 100 performs a comparison operation to compare the voltage Vcc with a reference voltage input from the - input terminal, and outputs a binary signal Q indicating the comparison result.

[0058] As a result, the comparator circuit 10 outputs the output voltage Vａｄｄ The comparator 11 can quantize an analog signal into a two-level digital signal, i.e., the comparator 11 functions as a two-level quantizer.

[0059] However, as shown in FIG. 5, in the first step in which the hybrid AD converter 100 operates as an incremental AD converter, the input voltage changeover switch SW15 is switched off by the control signal step2·Φ1, and the switch SW12 is switched on every cycle by the control signal step1·Φ1, and the capacitance C ｂ２ Input voltage V ｉｎ is entered.

[0060] In addition, in the second step in which the hybrid AD converter 100 operates as a cyclic AD converter, the switch SW12 is switched off by the control signal step1·Φ1, and the input voltage changeover switch SW15 is switched on for each cycle by the control signal step2·Φ1, thereby reducing the capacitance C ｂ２ The output voltage V of the delay integrator 130 ｉｎｔ is entered.

[0061] In the comparison circuit 10, the first component 10A receives a negative reference voltage V ｒｅｆｎ By inputting, the positive reference voltage V ｒｅｆ The comparator circuit 10 outputs a binary signal Q of two levels (1, 0) based on the second component 10B. The comparator circuit 10 also outputs a positive reference voltage V ｒｅｆｐ By inputting, the negative reference voltage V ｒｅｆ The negative polarity binary signal Q having two levels (1, 0) is output based on the above.

[0062] Therefore, the comparator circuit 10 can output a two-level (1, 0) positive binary signal Q output from the first component 10A and a two-level (1, 0) negative binary signal Q output from the second component 10B as a three-level digital signal. That is, the comparator circuit 10 functions as a three-level quantizer.

[0063] Specifically, in the first step in which the hybrid AD converter 100 operates as an incremental AD converter, the adder output V ａｄｄ [V] is calculated by the following formula (4).

[0064]

[0065] Here, C ｂ２ =C ａ１ When , the adder output V ａｄｄ [V] is calculated by the following formula (5).

[0066]

[0067] Therefore, the output signal Q0 of the comparator 11 is calculated by the following equation (6).

[0068]

[0069] That is, in the first step, a negative reference voltage V ｒｅｆｎ The reference voltage V of the comparator 11 of the first component 10A is input. ｔｈ１ is +(C ｔｈ / C ａ１ ) V ｒｅｆ [V].

[0070] In the first step, a positive reference voltage V ｒｅｆｐ The reference voltage V of the comparator 11 of the second component 10B is input. ｔｈ１ is -(C ｔｈ / C ａ１ ) V ｒｅｆ [V].

[0071] Therefore, the comparator circuit 10 functions as a three-level quantizer in the first step by having the first component part 10A and the second component part 10B.

[0072] In the second step in which the hybrid AD converter 100 operates as a cyclic AD converter, the adder output V ａｄｄ [V] is calculated by the following formula (7).

[0073]

[0074] At this time, the adder output V ａｄｄ [V] is calculated by the following formula (8).

[0075]

[0076] Therefore, the output signal Q0 of the comparator 11 is calculated by the following equation (9).

[0077]

[0078] That is, in the second step, the negative reference voltage V ｒｅｆｎ The reference voltage V of the comparator 11 of the first component 10A is input. ｔｈ２ is +(C ｔｈ / (C ｂ２ +C ａ１ ))V ｒｅｆ [V].

[0079] In the second step, the positive reference voltage V ｒｅｆｐ The reference voltage V of the comparator 11 of the second component 10B is input. ｔｈ２ is -(C ｔｈ / (C ｂ２ +C ａ１ ))V ｒｅｆ [V].

[0080] Therefore, the comparator circuit 10 functions as a three-level quantizer in the second step as well, by having the first component 10A and the second component 10B.

[0081] (Effects of the Comparator Circuit 10) FIGS. 6 and 7 are diagrams showing an example of the signal-to-quantization noise ratio (SQNR) in the comparator circuit 10 according to one embodiment.

[0082] The graph shown in FIG. 6 shows the reference voltage ±V of the comparator 11 in the first step in which the hybrid AD converter 100 operates as an incremental AD converter. ｔｈ１ [V / V ｒｅｆ ] and the signal-to-quantization noise ratio (SQNR).

[0083] In the first step, the reference voltage of the comparator 11 is set to ±V ｔｈ１ [V / V ｒｅｆ ], the input full scale range FSR = 2V ｒｅｆ ×c １ / b １ The signal-to-quantization noise ratio (SQNR) for is calculated by the following equation (10).

[0084]

[0085] In the above formula (10), M １ indicates the number of clocks in the first step. １ indicates the feedback coefficient of the DAC. １ ,arg ２ ) function is arg １ and arg ２ In the first step, b １ is the input coefficient of the analog signal U to the integrator.

[0086] In the above formula (10), M １ = 1024, b １ When V = 1, the signal to quantization noise ratio (SQNR) is as shown in the graph of FIG. ｔｈ１ NiC １ / b １ / 2[V / V ｒｅｆ ] was found to provide the highest signal to quantization noise ratio (SQNR).

[0087] The graph shown in FIG. 7 shows the reference voltage ±V of the comparator 11 in the second step in which the hybrid AD converter 100 operates as a cyclic AD converter. ｔｈ２ [V / V ｒｅｆ ] and the signal-to-quantization noise ratio (SQNR).

[0088] In the second step, the reference voltage of the comparator 11 is set to ±V ｔｈ２ [V / V ｒｅｆ ], the input full scale range FSR = 2V ｒｅｆ ×c １ / b １The signal-to-quantization noise ratio (SQNR) for is calculated by the following equation (11).

[0089]

[0090] In the above formula (11), n ２ indicates the number of clocks in the second step. １ indicates the feedback coefficient of the DAC. １ ,arg ２ ) function is arg １ and arg ２ In the second step, b １ is the feedback coefficient of the delay integrator 130. That is, b １ is the input coefficient of the analog signal U in the first step, and is the feedback coefficient of the delay integrator 130 in the second step.

[0091] In the above formula (11), n ２ = 6, b １ When V = 1, the signal-to-quantization noise ratio (SQNR) is as shown in the graph of FIG. 7, and the reference voltage V of the comparator 11 is ｔｈ２ NiC １ / b １ / 4 [V / V ｒｅｆ ] was found to provide the highest signal to quantization noise ratio (SQNR).

[0092] Here, in the first step, the reference voltage ±V of the comparator 11 ｔｈ１ [V / V ｒｅｆ ] is the signal to quantization noise ratio (SQNR) that maximizes c １ / b １ / 2[V / V ｒｅｆ ], C ｂ２ =C ａ１ And C ｔｈ / C ａ１ =c １ / b １ C so that it becomes / 2 ｔｈ =c １ / b １ / 2 x C ａ１ That is, C ｂ２ :Cａ１ :C ｔｈ =1:1:c １ / b １ / 2 would be sufficient.

[0093] In the second step, the reference voltage ±V of the comparator 11 ｔｈ２ [V / V ｒｅｆ ] is the signal to quantization noise ratio (SQNR) that maximizes c １ / b １ / 4 [V / V ｒｅｆ ], (C ｔｈ / (C ｂ２ +C ａ１ )) = c １ / b １ C so that it becomes / 4 ｔｈ = c １ / b １ / 4×(C ｂ２ +C ａ１ ) That is, C ｂ２ +C ａ１ :C ｔｈ = 1:c １ / b １ / 4, and as in the first step, C ｂ２ =C ａ１ In this case, C ｂ２ :C ａ１ :C ｔｈ =1:1:c １ / b １ / 2 would be sufficient.

[0094] That is, in both the first and second steps, to maximize the signal-to-quantization-noise ratio (SQNR), C ｂ２ :C ａ１ :C ｔｈ = 1:1:c １ / b １ For example, c １ / b １ When = 1, C ｂ２ : C ａ１ : C ｔｈ = 2:2:1. １ / b １ When = 1 / 2, C ｂ２ : C ａ１ : C ｔｈ = 4:4:1.１ / b １ When = 1 / 4, C ｂ２ : C ａ１ : C ｔｈ = 8:8:1.

[0095] Therefore, the comparison circuit 10 according to the embodiment uses a plurality of capacitances C ｂ２， C ａ１， C ｔｈ The optimum reference voltage of the comparator 11 can be changed simply by switching the input voltage changeover switch SW15 without changing the capacitance value of the comparator 11.

[0096] Generally, capacitance ratio mismatch is smaller than resistance ratio mismatch, so the comparison circuit 10 of one embodiment can reduce the addition error compared to a configuration in which the reference voltage of the comparator is changed depending on the resistance ratio of multiple resistors.

[0097] (Second Example of Circuit Configuration of Comparator Circuit 10) Fig. 8 is a diagram showing a second example of the circuit configuration of the comparator circuit 10 according to one embodiment. Fig. 8 shows an example in which the circuit configuration of the comparator circuit 10 is a differential configuration.

[0098] The comparison circuit 10 shown in FIG. ｒｅｆ By inputting, the positive reference voltage V ｔｈ A first signal processing unit 10-1 outputs a two-level (1, 0) binary signal Q based on the positive reference voltage V ｒｅｆ By inputting, the negative reference voltage V ｔｈ and a second signal processing unit 10-2 that outputs a two-level (1, 0) binary signal Q based on the above.

[0099] The first signal processing unit 10-1 and the second signal processing unit 10-2 each include an adder 20 and a comparator 11.

[0100] In addition, the adder 20 of each of the first signal processing unit 10-1 and the second signal processing unit 10-2 has a first component 20A and a second component 20B. Both the first component 20A and the second component 20B have the same configuration as the configuration of the adder 20 shown in FIG.

[0101] As a result, the first component 20 A of the adder 20 generates a voltage to be input to the + input terminal of the comparator 11 , and the second component 20 B of the adder 20 generates a − input signal of the comparator 11 .

[0102] The comparison circuit 10 shown in FIG. 8 uses a first signal processing unit 10-1 to generate a positive reference voltage V ｔｈ A two-level (1, 0) binary signal Q based on １ The second signal processing unit 10-2 can output a negative reference voltage V ｔｈ A two-level (1, 0) negative binary signal Q ０ can be output.

[0103] Therefore, the comparison circuit 10 shown in FIG. 8 receives the two-level binary signal Q output from the first signal processing section 10-1. １ and the two-level binary signal Q output from the second signal processing unit 10-2. ０ 8 can be output as a three-level digital signal. That is, the comparison circuit 10 shown in FIG. 8 functions as a three-level quantizer.

[0104] The comparison circuit 10 shown in FIG. 8 can suppress a decrease in the signal-to-quantization noise ratio (SQNR) when quantizing a differential configuration.

[0105] (Circuit Configuration of Comparator Circuit 200) Fig. 9 is a diagram showing the circuit configuration of a comparator circuit 200 according to an embodiment. The comparator circuit 200 shown in Fig. 9 uses an output voltage V ａｄｄ The comparison circuit 200 compares the analog signals (A, B, C, D, D, E ...

[0106] As shown in FIG. 9, the comparison circuit 200 includes a comparator 201, an adder 210, a holding capacitor C ｈｏｌｄ , a cutoff switch SW14, and a reset switch SW25.

[0107] The comparator 201 receives the output voltage V ａｄｄ The comparator 201 compares the output voltage V input from the + input terminal with a reference voltage V input from the - input terminal (the other input terminal), and outputs a binary signal Q indicating the comparison result. ａｄｄ is higher than the reference voltage input from the negative input terminal, the comparator 201 outputs a high-level binary signal Q. Conversely, the comparator 201 outputs a high-level binary signal Q when the output voltage V ａｄｄ is lower than the reference voltage input from the - input terminal, it outputs a low-level binary signal Q. As with the comparator 11 described above, the reference voltage of the comparator 201 is determined by the capacitance ratio of a plurality of capacitors.

[0108] The adder 210 has a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a switched capacitor circuit 211, a switched capacitor circuit 212, a switched capacitor circuit 213, and a switch SW24.

[0109] The first input terminal IN1 is connected to a voltage V ｉｎｔ The second input terminal IN2 receives a voltage V ｉｎ The third input terminal IN3 receives a voltage V ｒｅｆ is entered.

[0110] The switched capacitor circuit 211 has a capacitance C ａ１ and capacitance C ａ１ and a switch SW11 provided between the first input terminal IN1 and the first input terminal IN2; ａ１ and a switch SW21 connected between the first input terminal IN1.

[0111] The switched capacitor circuit 212 has a capacitance C ｂ２ and capacitance C ｂ２ and a switch SW12 provided between the first input terminal IN1 and the second input terminal IN2, and a capacitor C ｂ２ and a switch SW22 connected between the first input terminal IN1 and the second input terminal IN2.

[0112] The switched capacitor circuit 213 has a capacitance C ｔｈand capacitance C ｔｈ and a switch SW13 provided between the third input terminal IN3 and the third input terminal IN4; ｔｈ and a switch SW23 connected between the first input terminal IN1 and the third input terminal IN3.

[0113] The switch SW24 has a capacitance C ａ１ , capacity C ｂ２ , and capacitance C ｔｈ and the ground potential.

[0114] The adder 210 has a capacitance C ａ１ , capacity C ｂ２ , and capacitance C ｔｈ The charge stored in the ａｄｄ and generates the output voltage V ａｄｄ Output.

[0115] Hold capacitance C ｈｏｌｄ One end of the holding capacitor C is connected to the connection path 202 between the adder 210 and the positive input terminal of the comparator 201, and the other end is connected to the ground potential. ｈｏｌｄ is the output voltage V output from the adder 210 ａｄｄ Hold.

[0116] The cutoff switch SW14 is provided on the connection path 202 between the adder 210 and the + input terminal of the comparator 201. When the cutoff switch SW14 is switched on, it connects the connection path 202. When the cutoff switch SW14 is switched off, it cuts off the connection path 202.

[0117] The reset switch SW25 has one end connected to the cutoff switch SW14 on the connection path 202 and the holding capacitor C ｈｏｌｄ The reset switch SW25 is connected between the holding capacitor C ｈｏｌｄ Reset the potential of

[0118] (Operation of the Comparison Circuit 200) In the comparison circuit 200 configured as described above, when the comparator 201 is in a "standby mode" in which it does not perform a comparison operation, the switches SW11 to SW14 are switched on and the switches SW21 to SW25 are switched off, and the adder 210 calculates the output voltage V ａｄｄ and outputs the output voltage V ａｄｄ , and the holding capacitance C ｈｏｌｄ The output voltage V output from the adder 210 can be ａｄｄ [V] is calculated by the following formula (12).

[0119]

[0120] When the comparator 201 is in a comparison mode in which it performs a comparison operation, the comparator circuit 200 switches the switches SW11 to SW14 off and the switches SW21 to SW25 on, and the comparator 201 connects the hold capacitor C ｈｏｌｄ The output voltage V is input via the + input terminal ａｄｄ The comparator 100 performs a comparison operation to compare the voltage Vcc with a reference voltage input from the - input terminal, and outputs a binary signal Q indicating the comparison result.

[0121] As a result, the comparator circuit 200 outputs the output voltage V ａｄｄ (analog signal) can be quantized into a two-level (1, -1) digital signal. That is, the comparator 201 functions as a two-level quantizer.

[0122] The comparison circuit 200 may have a configuration including a first component 200A and a second component 200B having similar configurations, similar to the comparison circuit 10 described above. In this case, the first component 200A of the comparison circuit 200 receives a negative reference voltage Vrefn from the third input terminal IN3, and can output a two-level (1, 0) binary signal Q based on the positive reference voltage Vref. In this case, the second component 200B of the comparison circuit 200 receives a positive reference voltage Vrefp from the third input terminal IN3, and can output a two-level (1, 0) negative binary signal Q based on the negative reference voltage Vref.

[0123] Therefore, in this case, the comparison circuit 200 can output a two-level (1, 0) positive binary signal Q output from the first component 200A and a two-level (1, 0) negative binary signal Q output from the second component 200B as a three-level digital signal. That is, the comparison circuit 200 can function as a three-level quantizer.

[0124] Here, in one embodiment of the comparison circuit 200, when the comparator 201 is in a "comparison mode" in which the comparator 201 performs a comparison operation, the cut-off switch SW14 is switched off, thereby cutting off the connection path 202 between the adder 210 and the + input terminal of the comparator 201.

[0125] This allows the comparison circuit 200 according to one embodiment to prevent kickback noise from the comparator 201 from being transmitted to the adder 210 when the comparator 201 is in the "comparison mode."

[0126] Furthermore, in the comparison circuit 200 according to the embodiment, when the comparator 201 is in the “standby mode”, the holding capacitance C ｈｏｌｄ The output voltage V output from the adder 210 ａｄｄ Before the holding capacitor C is charged, the reset switch SW25 is turned on, and the holding capacitor C ｈｏｌｄ Reset the potential of

[0127] As a result, the comparison circuit 200 according to the embodiment has a holding capacitance Cｈｏｌｄ Since the initial charge amount can be kept constant, the input voltage input from the adder 210 to the comparator 201 can be kept constant. Therefore, the comparison circuit 200 according to one embodiment can prevent the input voltage of the comparator 201 from deviating from the operating range of the comparator 201.

[0128] The adder 210 includes an input voltage changeover switch SW15. The input voltage changeover switch SW15 is connected to a first input terminal IN1 and a switched capacitor circuit 212 (a switch SW12 and a capacitance C ｂ２ When the input voltage changeover switch SW15 is turned off, the adder 210 is connected to the capacitance C ｂ２ The voltage V input from the second input terminal IN2 ｉｎ When the input voltage selector switch SW15 is turned on, the capacitance C ｂ２ The voltage V input from the first input terminal IN1 ｉｎｔ Therefore, the comparison circuit 200 according to the embodiment can input a plurality of capacitances C ｂ２， C ａ１， C ｔｈ The optimum reference voltage of the comparator 201 can be changed by simply switching the input voltage changeover switch SW15 without changing the capacitance value of the comparator 201.

[0129] 10 is a diagram showing a modification of the circuit configuration of the comparison circuit 200 according to one embodiment. A comparison circuit 200-2 shown in FIG.

[0130] Similar to the comparison circuit 200, the comparison circuit 200-2 shown in FIG. 10 uses an output voltage V ａｄｄ The comparison circuit 200-2 compares the analog signals (analog signals) and outputs a binary signal Q (digital signal) indicating the comparison result. For example, the comparison circuit 200-2 can be used in a ΔΣ AD converter or the like. The comparison circuit 200-2 can also be used as the comparison circuit 10 included in the hybrid AD converter 100 according to one embodiment.

[0131] As shown in FIG. 10, the comparison circuit 200-2 includes an adder 210-2 and a quantizer 220.

[0132] Similar to the adder 210, the adder 210-2 has a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a switched capacitor circuit 211, a switched capacitor circuit 212, a switched capacitor circuit 213, and a switch SW24.

[0133] However, the adder 210-2 differs from the adder 210 in the configuration of the switched capacitor circuit 213.

[0134] In the switched capacitor circuit 213 of the adder 210-2, the switch SW13 has a capacitance C ａ１ and capacitance C ｂ２ and the output terminal OUT.

[0135] In addition, in the switched capacitor circuit 213 of the adder 210-2, the capacitance C ｔｈ has one end connected between the switch SW13 and the output terminal OUT on the connection path 203, and the other end connected to the ground potential.

[0136] In the switched capacitor circuit 213 of the adder 210-2, one end of the switch SW23 is connected between the switch SW13 on the connection path 203 and the output terminal OUT, and the other end is connected to the input terminal IN3.

[0137] The output terminal OUT of the switched capacitor circuit 213 of the adder 210 - 2 is connected to the positive input terminal of the comparator 221 provided in the quantizer 220 .

[0138] In the adder 210-2, the switch SW24 has a capacitance C ａ１ and capacitance C ｂ２ and the switch SW13 included in the switched capacitor circuit 213.

[0139] The adder 210-2 has a capacitance C ａ１ , capacity C ｂ２ , and capacitance C ｔｈThe charge stored in the ａｄｄ and generates the output voltage V ａｄｄ Output.

[0140] As described above, the comparison circuit 200-2 has the adder 210-2, and thus the holding capacitance C ｈｏｌｄ , the cutoff switch SW14, and the reset switch SW25 are not included.

[0141] Instead, the comparison circuit 200-2 has a capacitance C ｔｈ functions as a "third capacitance", the switch SW13 functions as a "shutoff switch", and the switch SW23 functions as a "reset switch". ａ１ functions as a "first capacitance" and capacitance C ｂ２ functions as a "second capacitance."

[0142] The quantizer 220 has a comparator 221 and a D flip-flop 222. The + input terminal (one of the input terminals) of the comparator 221 is connected to the output terminal OUT of the adder 210-2. The comparator 221 converts the output voltage V ａｄｄ The comparator 221 compares the output voltage V input from the + input terminal with a reference voltage V input from the - input terminal (the other input terminal), and outputs a binary signal Q indicating the comparison result. ａｄｄ is higher than the reference voltage input from the - input terminal, the comparator 221 outputs a high-level binary signal Q. Conversely, when the output voltage Vadd input from the + input terminal is lower than the reference voltage input from the - input terminal, the comparator 221 outputs a low-level binary signal Q. Note that, similar to the comparator 11 described above, the reference voltage of the comparator 221 is determined by the capacitance ratio of a plurality of capacitors.

[0143] The output terminal of the comparator 221 is connected to the data input terminal of the D flip-flop 222. When the control signal Φ2 input from the clock input terminal is Lo, the D flip-flop 222 holds the input value of the data input terminal, and when the control signal Φ2 input from the clock input terminal is Hi, the D flip-flop 222 updates its output according to the input value of the data input terminal.

[0144] (Operation of Comparison Circuit 200-2) In the comparison circuit 200-2 configured as described above, when the comparator 221 is in a "standby mode" in which it does not perform a comparison operation, the switches SW11 to SW13 are switched on and the switches SW21 to SW24 are switched off, and the adder 210-2 outputs the output voltage V ａｄｄ The output voltage Vadd output from the adder 210-2 can be output to the comparator 221.

[0145] At this time, the output voltage of the adder 210-2 is calculated by the above equation (4).

[0146] When the comparator 221 is in a comparison mode in which it performs a comparison operation, the comparator circuit 200-2 switches SW11 to SW13 off and switches SW21 to SW24 on, and the comparator 221 converts the output voltage V ａｄｄ The D flip-flop 222 then outputs the binary signal Q, which is input from the data input terminal, at the timing when the control signal Φ2 becomes Hi.

[0147] As a result, the quantizer 220 outputs the output voltage V ａｄｄ (analog signal) can be quantized into a two-level (1, -1) digital signal, that is, the quantizer 220 functions as a two-level quantizer.

[0148] Here, in the comparison circuit 200-2 according to one modification, when the comparator 221 is in a “comparison mode” in which the comparator 221 performs a comparison operation, the switch SW13 (shutoff switch) included in the switched capacitor circuit 213 is turned off, thereby reducing the capacitance C ａ１ and capacitance C ｂ２ The connection path 203 between the output side of the amplifier and the output terminal OUT is cut off.

[0149] As a result, in the comparison circuit 200-2 according to the modified example, when the comparator 221 is in the “comparison mode”, the kickback noise of the comparator 221 is input to the capacitance C ａ１ and capacitance C ｂ２ This can be done so that it does not get transmitted to others.

[0150] In addition, in the comparison circuit 200-2 according to the modified example, when the comparator 221 is in a “comparison mode” in which the comparator 221 performs a comparison operation, the switch SW23 (reset switch) of the switched capacitor circuit 213 is turned on, thereby turning on the capacitance C ｔｈ (third capacitance) with respect to the reference voltage V ｒｅｆ can be applied as an initial voltage, i.e., capacitance C ｔｈ The potential of the reference voltage V ｒｅｆ (initial voltage).

[0151] As a result, the comparison circuit 200-2 according to the modification has a capacitance C ｔｈ Since the initial charge amount can be kept constant, it is possible to keep constant the input voltage input from the adder 210-2 to the comparator 221. Therefore, according to the comparison circuit 200-2 of one modification, it is possible to prevent the input voltage of the comparator 221 from deviating from the operating range of the comparator 221.

[0152] The comparison circuit 200-2 can be configured to include a first component 200A and a second component 200B having similar configurations, similar to the comparison circuit 10 described above. In this case, the comparison circuit 200-2 can output a two-level (1, 0) binary signal Q based on the positive reference voltage Vref when the first component 200A receives a negative reference voltage Vrefn from the third input terminal IN3. In addition, in this case, the comparison circuit 200-2 can output a two-level (1, 0) binary signal Q based on the negative reference voltage Vref when the second component 200B receives a positive reference voltage Vrefp from the third input terminal IN3.

[0153] Therefore, in this case, the comparison circuit 200-2 can output the two-level (1, 0) positive binary signal Q output from the first component 200A and the two-level (1, 0) negative binary signal Q output from the second component 200B as a three-level digital signal. In other words, the comparison circuit 200-2 can function as a three-level quantizer.

[0154] The comparison circuit 200-2 also includes an input voltage changeover switch SW15. The input voltage changeover switch SW15 is connected between the first input terminal IN1 and the switched capacitor circuit 212 (the switch SW12 and the capacitance C ｂ２ When the input voltage selector switch SW15 is turned off, the comparator circuit 200-2 is connected to the capacitance C ｂ２ The voltage V input from the second input terminal IN2 ｉｎ When the input voltage selector switch SW15 is turned on, the capacitance C ｂ２ The voltage V input from the first input terminal IN1 ｉｎｔ Therefore, the comparison circuit 200-2 can input a plurality of capacitances C ｂ２， C ａ１， C ｔｈ The optimum reference voltage of the comparator 221 can be changed by simply switching the input voltage changeover switch SW15 without changing the capacitance value of the comparator 221.

[0155] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0156] This international application claims priority based on Japanese Patent Application No. 2023-146407, filed on September 8, 2023, the entire contents of which are incorporated herein by reference.

[0157] 10 Comparison circuit 10A First component 10B Second component 10-1 First signal processing unit 10-2 Second signal processing unit 11 Comparator 20 Adder IN1 First input terminal IN2 Second input terminal IN3 Third input terminal 21 to 23 Switched capacitor circuit 100 Hybrid AD converter 101 Input terminal 102 Output terminal 110A Switch 110B Switch 115A Line 115B Line 120 Adder 130 Delay integrator 140 Adder 150 Quantizer 160 DA converter 170 DEMUX 180A Integration unit 180B Shift calculation unit 180C Calculation unit 190 Control unit 200, 200-2 Comparison circuit 201 Comparator 202, 203 Connection path 210, 210-2 Adder 211 to 213 Switched capacitor circuit 220 Quantizer 221 Comparator 222 D flip-flop OUT Output terminal C ａ１ , C ｂ２ , C ｔｈ Capacity C ｈｏｌｄ Hold capacitance SW11 to SW13, SW21 to SW24 switches SW14 Shut-off switch SW15 Input voltage selector switch SW25 Reset switch V ａｄｄ Output voltage V ｉｎ , V ｉｎｔ , V ｒｅｆ Voltage Q Binary signal Φ1, Φ2, step1・Φ1, step2・Φ1 Control signal

Claims

1. A comparison circuit comprising: an adder that generates an output voltage; a hold capacitance that holds the output voltage output from the adder; a comparator that receives the output voltage held in the hold capacitance from one of its input terminals and performs a comparison operation using the output voltage; a cutoff switch provided in a connection path between the adder and the one of the input terminals of the comparator; and a reset switch connected between the cutoff switch and the hold capacitance, for resetting the potential of the hold capacitance.

2. The comparison circuit according to claim 1, wherein when the comparator performs the comparison operation, the cutoff switch is switched off to cut off the connection path and cut off kickback noise of the comparator.

3. The comparison circuit according to claim 2, characterized in that the potential of the holding capacitance is reset by switching on the reset switch before the output voltage output from the adder is charged to the holding capacitance.

4. A comparison circuit comprising: an adder that generates an output voltage; and a comparator that receives the output voltage from the adder through one of its input terminals and performs a comparison operation using the output voltage, wherein the adder comprises: a first capacitance and a second capacitance; a third capacitance provided in a connection path between the output sides of the first capacitance and the second capacitance and the one input terminal of the comparator; an input terminal to which a voltage to be applied to the third capacitance is input; a cutoff switch provided in the connection path; and a reset switch provided between the connection path and the input terminal.

5. The comparison circuit according to claim 4, wherein when the comparator performs the comparison operation, the cutoff switch is switched off to cut off the connection path, thereby cutting off kickback noise of the comparator.

6. The comparison circuit according to claim 5, characterized in that when the comparator performs the comparison operation, the reset switch is switched on, thereby resetting the potential of the third capacitor to the voltage input from the input terminal.

7. A comparison circuit as described in claim 3, comprising: a first capacitance to which a first input voltage is applied; a second capacitance to which a second input voltage is applied; and a third capacitance to which a third input voltage is applied, wherein the output voltage is generated based on a capacitance ratio between the first capacitance, the second capacitance, the third capacitance and the holding capacitance, and based on the first input voltage, the second input voltage and the third input voltage.

8. The comparison circuit according to claim 3, comprising: a first capacitance to which a first input voltage is applied; and a second capacitance to which a second input voltage is applied; a third input voltage is applied to the reset switch; and the output voltage is generated based on a capacitance ratio between the first capacitance, the second capacitance and the holding capacitance, and based on the first input voltage, the second input voltage and the third input voltage.

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