Buck converter having quasi-fixed-frequency constant-on-time architecture, and on-timing circuit

Abstract

Provided in the embodiments of the present disclosure are a buck converter having a quasi-fixed-frequency constant-on-time architecture, and an on-timing circuit. The on-timing circuit comprises: a current generation module, a transition delay cancellation module, a capacitor and a comparator, wherein the current generation module is configured to generate, after an upper power transistor is turned on, a charging current which is directly proportional to the voltage of a switch node; the transition delay cancellation module is configured to generate, on the basis of a variable resistance unit and the capacitor, a first delay for canceling a transition delay of the comparator, wherein the magnitude of the resistance value of the variable resistance unit is controlled by means of an input voltage; the capacitor is configured to be charged using the charging current after the upper power transistor is turned on; and the comparator is configured to compare with the magnitude of a first voltage the magnitude of a ramp voltage corresponding to a ramp voltage node, and to generate a turn-off signal, wherein the first voltage is a reference voltage which is proportional to an output voltage. The problem of great operating frequency changes in a buck converter having a quasi-fixed-frequency constant-on-time architecture is solved.

Description

Buck converter with quasi-constant frequency constant on-time architecture and on-time timing circuit

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese invention patent application with application number 202311175838.X, filed with the National Intellectual Property Administration of China on September 12, 2023, entitled “Buck converter and on-time timing circuit with quasi-constant frequency constant on-time architecture”, all disclosed contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a buck converter and a conduction timing circuit with a quasi-constant-frequency constant on-time architecture. Background Art

[0004] In a quasi-constant frequency constant on-time buck converter, the on-time is usually t on It is directly proportional to the output voltage Vo and inversely proportional to the input voltage Vi. Figure 1 shows the circuit structure of a commonly used on-time timing circuit in a quasi-constant-frequency constant on-time buck converter. The negative input of the comparator is coupled to the output voltage, the positive input is coupled to the voltage across capacitor Con, and the charging current Ion is the ratio of the input voltage to Ron. Based on the capacitor voltage-current relationship, we can obtain: (Vi / Ron) × Ton = Con × Vo. Theoretically, the on-time of the upper power transistor, Ton, is calculated as (Con × Vo × Ron) / Vi. From the expression for Ton, we can see that it is directly proportional to Vo and inversely proportional to Vi. However, the calculation of Ton also requires the comparator comp's flip delay, Tcomp. This comparator flip delay varies with the voltage of Vi, and Tcomp affects Ton's ability to linearly follow the changes in Vi and Vo. This is especially true when Vi and Vo vary over a wide range. If Vi is very high and Vo is very low, i.e., at a small duty cycle, Ton can reach tens of nanoseconds, and the comparator flip delay is also tens of nanoseconds. If Vi is very low and Vo and Vi are close, i.e., at a large duty cycle, the comparator flip delay can reach hundreds of nanoseconds. The greater the comparator flip delay's contribution to the actual on-time, the more severe the Ton nonlinearity. This results in significant frequency variations across the entire voltage range for the entire buck converter system with a quasi-constant-frequency constant on-time architecture, hindering peripheral applications. Therefore, implementing the on-time timing according to the on-time timing circuit shown in Figure 1 will cause the operating frequency of the entire buck converter system with a quasi-constant-frequency constant on-time architecture to vary significantly across the entire voltage range.

[0005] In addition, according to the volt-second balance principle of the buck converter, the following equation is obtained in practical application: (V i -I load ·Rhs -V o )·T on =V o ·T off ,

[0006] Among them I load is the output load current, R hs is the on-resistance of the upper power tube, T off is the off time of the upper power tube. Transforming the above equation, we can get: (V i -I load ·R hs )·T on =V o ·T off +V o ·T on =V o ·T S ,

[0007] It can be seen that if I load When the change is large, the conduction loss of the upper power tube I load ×R hs The change of cannot be ignored, that is, at this time, Ton is not inversely proportional to the input voltage Vi, but is proportional to (Vi-I load ×R hs ), but the Ton obtained by the conduction timing circuit in Figure 1 is still inversely proportional to Vi, without considering I load The impact on Ton, so the actual Ton is load When the change is large, it will also change a lot, resulting in a large change in the operating frequency.

[0008] In summary, the problem of large operating frequency variation in the buck converter with a quasi-constant-frequency constant on-time architecture needs to be solved urgently.

[0009] Summary of the Invention

[0010] The embodiments described herein provide a buck converter with a quasi-constant-frequency constant on-time architecture and a conduction timing circuit to solve the problem of large operating frequency variation in the buck converter with a quasi-constant-frequency constant on-time architecture.

[0011] According to a first aspect of the present disclosure, a turn-on timing circuit is provided for a buck converter with a quasi-constant-frequency constant turn-on time architecture, which can output a turn-off signal for turning off the upper power tube of the buck converter. The turn-on timing circuit includes: a current generating module, a flip delay compensation module, a capacitor, and a comparator, wherein the input end of the current generating module is coupled to the switch node of the buck converter, the output end of the current generating module is coupled to the ramp voltage node, the switch node is the node where the upper power tube and the inductor in the buck converter are coupled, and the current generating module is configured to generate a charging current proportional to the voltage of the switch node after the upper power tube is turned on; the input end of the flip delay compensation module is coupled to the ramp voltage node, and the flip delay compensation module is coupled to the ramp voltage node. The output end of the cancellation module is coupled to one end of the capacitor, and the flip delay cancellation module is configured to generate a first delay for offsetting the flip delay of the comparator based on the variable resistance unit and the capacitor, and the resistance value of the variable resistance unit is controlled by the input voltage of the buck converter; the other end of the capacitor is coupled to the ground end, and the capacitor is configured to be charged with the charging current after the upper power tube is turned on; the positive input end of the comparator is coupled to the ramp voltage node, and the negative input end of the comparator is coupled to the first voltage. The comparator is configured to compare the ramp voltage corresponding to the ramp voltage node with the first voltage and generate the shutdown signal, and the first voltage is a reference voltage proportional to the output voltage of the buck converter.

[0012] Optionally, the current generating module includes: a first current generating module and a second current generating module, wherein the first current generating module is configured to generate a first current based on the voltage of the switching node and the voltage of the ramp voltage node; the second current generating module is configured to generate a second current based on the voltage of the ramp voltage node, and the sum of the first current and the second current is the charging current.

[0013] Optionally, the flip delay compensation module includes: a decoder unit and a variable resistor unit, wherein the decoder unit is configured to generate a switch control signal according to the input voltage; and the variable resistor unit is configured to adjust the resistance of the variable resistor unit according to the switch control signal.

[0014] Optionally, the first current generating module includes: a first resistor and a first switch, wherein one end of the first resistor is coupled to the switch node, the other end of the first resistor is coupled to one end of the first switch, and the other end of the first resistor generates the first current; the other end of the first switch is coupled to the ramp voltage node, and the first switch is closed after the upper power tube is turned on, and is opened after the upper power tube is turned off.

[0015] Optionally, the second current generating module includes: first to sixth transistors, a first current source, and a second resistor, wherein the first transistor and the second transistor form a first current mirror, the source of the first transistor and the source of the second transistor are both coupled to the power supply voltage, the gate of the first transistor and the gate of the second transistor are both coupled to the drain of the first transistor, the drain of the second transistor is coupled to the ramp voltage node, and the drain of the second transistor generates the second current; the third transistor and the fourth transistor form a second current mirror, the gate of the third transistor and the gate of the fourth transistor are both coupled to the third transistor. the drain of the first transistor is coupled to the drain of the body tube, the drain of the third transistor is coupled to one end of the first current source, the drain of the fourth transistor is coupled to the drain of the first transistor; the source of the fifth transistor is coupled to the source of the third transistor, the gate of the fifth transistor is coupled to the ramp voltage node, and the drain of the fifth transistor is coupled to the ground terminal; the source of the sixth transistor is coupled to the source of the fourth transistor, the gate of the sixth transistor is coupled to the drain of the sixth transistor, and the drain of the sixth transistor is coupled to one end of the second resistor; the other end of the second resistor is coupled to the ground terminal, and the other end of the first current source is coupled to the power supply voltage.

[0016] Optionally, the variable resistance unit includes n resistors and n switches, wherein the n resistors are connected in series in sequence, and a switch is connected in parallel on both sides of each resistor.

[0017] Optionally, the decoder unit includes an n-bit decoder, and the switch control signal includes n switch signals, wherein the input end of the n-bit decoder receives the input voltage, and the output end of the n-bit decoder outputs the n switch signals, and the n switch signals control the opening and closing of the n switches, and each switch corresponds to a switch signal.

[0018] Optionally, the resistance of the variable resistor unit is in inverse proportion to the input voltage.

[0019] Optionally, the resistance of the first resistor is equal to the resistance of the second resistor.

[0020] Optionally, the conduction timing circuit further includes a second switch, wherein the second switch is coupled between the slope voltage node and the ground terminal, and the second switch is opened after the first switch is closed, and is closed after the first switch is opened.

[0021] Optionally, the current mirror ratios of the first current mirror and the second current mirror are both 1.

[0022] According to a second aspect of the present disclosure, a buck converter with a quasi-constant-frequency constant on-time architecture is provided, comprising the on-time timing circuit described in any one of the first aspects.

[0023] In the conduction timing circuit of the embodiment of the present disclosure, the first delay generated by the flip delay compensation module is used to offset the flip delay of the comparator, thereby eliminating the influence of the flip delay of the comparator on the conduction time Ton; and since when the upper power tube is turned on, the voltage of the switch node is the input voltage minus the conduction loss of the upper power tube (Vi-I load ×R hs ), so the current generating module generates a charging current proportional to the voltage of the switch node to charge the capacitor, which can make the on-time inversely proportional to the voltage of the switch node, that is, make the on-time inversely proportional to (Vi-I load ×R hs ), and compared to existing on-timer circuits, the on-timer circuit of the present disclosure takes into account the effect of the load current on Ton. In summary, compared to existing on-timer circuits, the on-timer circuit of the embodiment of the present disclosure can ensure minimal changes in the system operating frequency under a wide range of input voltages, output voltages, and different loads, better meeting the needs of peripheral applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0025] FIG1 shows a schematic block diagram of an existing conduction timing circuit;

[0026] FIG2 shows a schematic block diagram of a conduction timing circuit according to an embodiment of the present disclosure;

[0027] FIG3 shows a schematic circuit diagram of another conduction timing circuit according to an embodiment of the present disclosure;

[0028] FIG4 shows an exemplary circuit diagram of a current generating module in a conduction timing circuit according to an embodiment of the present disclosure;

[0029] FIG5 shows an exemplary circuit diagram of a flip delay compensation module in a conduction timing circuit according to an embodiment of the present disclosure;

[0030] FIG6 shows a schematic circuit diagram of another conduction timing circuit according to an embodiment of the present disclosure;

[0031] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant technology, and will not be interpreted in an idealized or overly formal form unless otherwise clearly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together should refer to the parts being directly combined together or combined through one or more intermediate components. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0034] In order to solve the problem that the existing on-time timing circuit causes large changes in the operating frequency of a buck converter with a quasi-constant frequency constant on-time architecture under a wide range of input voltage, output voltage, and different loads, a new on-time timing circuit structure is proposed. The on-time timing circuit of the embodiment of the present disclosure makes the on-time proportional to the output voltage and inversely proportional to the switch node voltage, so that the frequency change caused by the change in the conduction loss of the upper power tube is weakened; in addition, a delay that changes with the input voltage is added to the circuit to offset the comparator flip delay that changes with the input voltage, and finally a timing circuit that can linearly follow the changes in the switch node voltage and output voltage is obtained, achieving a small change in the system operating frequency under a wide range of Vi, Vo and different loads, better meeting the requirements of peripheral applications. The on-time timing circuit of the present disclosure is described in detail below.

[0035] FIG2 shows a schematic block diagram of a conduction timing circuit 100 according to an embodiment of the present disclosure. The conduction timing circuit 100 is used in a buck converter with a quasi-constant frequency constant conduction time architecture, and can output a shutdown signal On_timer_out for shutting down the upper power tube of the buck converter. It should be noted that FIG2 also shows other structures of the buck converter (which can be a Buck converter), including an upper power tube hs, a lower power tube ls, an inductor L, an output capacitor Cload, and a load current I load As shown in FIG2 , the conduction timing circuit 100 includes: a current generating module 110 , a flip delay compensation module 120 , a capacitor C1 , and a comparator comp.

[0036] The input end of the current generating module 110 is coupled to the switch node SW of the buck converter, and the output end of the current generating module 110 is coupled to the ramp voltage node Vramp. The switch node SW is the node where the upper power tube hs and the inductor L in the buck converter are coupled. The current generating module 110 is configured to generate a charging current Ic1 proportional to the voltage of the switch node SW after the upper power tube hs is turned on; the charging current Ic1 is used to charge the capacitor C1. The function of the charging current Ic1 is the same as that of Ion in Figure 1, both of which are used to charge the capacitor. Since the voltage V SW It is the input voltage Vi minus the conduction loss of the upper power tube hs, that is, V SW =Vi-I load ×R hs , where I load is the load current, R hs The on-resistance of the upper power tube is 1, so the current generating module 110 generates a charging current Ic1 proportional to the voltage of the switch node SW to charge the capacitor C1, which can make the on-time Ton proportional to the voltage V SW Inversely proportional to the conduction time Ton and (Vi-I load ×R hs ), therefore, compared with the existing conduction timing circuit, the embodiment of the present disclosure takes into account the influence of the load current on the conduction time Ton.

[0037] The input end of the flip delay compensation module 120 is coupled to the ramp voltage node Vramp, and the output end of the flip delay compensation module 120 is coupled to one end of the capacitor C1. The flip delay compensation module 120 is configured to generate a first delay for comparator comp flip delay based on the variable resistor unit 122 (shown in FIG3 ) and the capacitor C1. The resistance value of the variable resistor unit 122 is controlled by the input voltage Vi of the buck converter. The first delay is generated to eliminate the influence of the flip delay of the comparator comp on the on-time Ton.

[0038] The other end of the capacitor C1 is coupled to the ground, and the capacitor C1 is configured to be charged by the charging current Ic1 after the upper power transistor hs is turned on;

[0039] The positive input terminal of the comparator comp is coupled to the ramp voltage node Vramp, the negative input terminal of the comparator comp is coupled to the first voltage V1, and the comparator comp is configured to compare the ramp voltage V corresponding to the ramp voltage node Vramp. rampThe first voltage V1 is a reference voltage proportional to the output voltage Vo of the buck converter. Specifically, when the ramp voltage V ramp When the voltage is greater than the first voltage V1, a shutdown signal On_timer_out is generated, causing the logic control unit in the buck converter to control the shutdown of the upper power transistor hs according to the shutdown signal On_timer_out. The first voltage V1 is set to be proportional to the output voltage Vo to ensure that the on-time Ton is proportional to the output voltage Vo.

[0040] In the conduction timing circuit of the embodiment of the present disclosure, the first delay generated by the flip delay cancellation module 120 is used to offset the flip delay of the comparator comp, thereby eliminating the influence of the flip delay of the comparator comp on the conduction time Ton; and since when the upper power transistor hs is turned on, the voltage of the switch node SW is the input voltage Vi minus the conduction loss of the upper power transistor hs (Vi-I load ×R hs ), so the current generating module 110 generates a charging current Ic1 proportional to the voltage of the switch node SW to charge the capacitor C1, which can make the on-time inversely proportional to the voltage of the switch node SW, that is, the on-time is inversely proportional to (Vi-I load ×R hs ), and compared to existing on-time timing circuits that take into account the effect of load current on Ton, the resulting on-time is directly proportional to the voltage at the switch node SW and inversely proportional to the output voltage Vo. Compared to existing on-time timing circuits, the on-time timing circuit of the disclosed embodiment eliminates the effects of comparator comp flip delay and load current variations on the on-time. This enables the on-time timing circuit to maintain minimal variation in the system operating frequency over a wide range of input voltages Vi, output voltages Vo, and loads, better meeting the requirements of peripheral applications.

[0041] Furthermore, as shown in FIG3 , the current generating module 110 includes: a first current generating module 111 and a second current generating module 112 , wherein the first current generating module 111 is configured to generate a current according to the voltage V SW , the voltage of the ramp voltage node Vramp generates a first current I1; the second current generating module 112 is configured to generate a second current I2 according to the voltage of the ramp voltage node Vramp, and the sum of the first current I1 and the second current I2 is the charging current Ic1.

[0042] Specifically, as shown in Figure 4, the first current generating module 111 includes: a first resistor Rs1 and a first switch T1, wherein one end of the first resistor Rs1 is coupled to the switch node SW, the other end of the first resistor Rs1 is coupled to one end of the first switch T1, and the other end of the first resistor Rs1 generates a first current I1; the other end of the first switch T1 is coupled to the ramp voltage node Vramp, and the first switch T1 is closed after the upper power tube hs is turned on and is opened after the upper power tube hs is turned off.

[0043] As shown in FIG4 , the second current generating module 112 includes: first to sixth transistors, a first current source I3, and a second resistor Rs2, wherein the first transistor Mp1 and the second transistor Mp2 form a first current mirror, the source of the first transistor Mp1 and the source of the second transistor Mp2 are both coupled to the power supply voltage vdd, the gate of the first transistor Mp1 and the gate of the second transistor Mp2 are both coupled to the drain of the first transistor Mp1, the drain of the second transistor Mp2 is coupled to the ramp voltage node Vramp, and the drain of the second transistor Mp2 generates a second current I2; the third transistor Mn1 and the fourth transistor Mn2 form a second current mirror, the gate of the third transistor Mn1 and the gate of the fourth transistor Mn2 are both coupled The first and second current mirrors are connected to the drain of the third transistor Mn1, the drain of the third transistor Mn1 being coupled to one terminal of the first current source I3, and the drain of the fourth transistor Mn2 being coupled to the drain of the first transistor Mp1. The source of the fifth transistor Mp3 is coupled to the source of the third transistor Mn1, the gate of the fifth transistor Mp3 is coupled to the ramp voltage node Vramp, and the drain of the fifth transistor Mp3 is coupled to ground. The source of the sixth transistor Mp4 is coupled to the source of the fourth transistor Mn2, the gate of the sixth transistor Mp4 is coupled to the drain of the sixth transistor Mp4, and the drain of the sixth transistor Mp4 is coupled to one terminal of the second resistor Rs2. The other terminal of the second resistor Rs2 is coupled to ground, and the other terminal of the first current source I3 is coupled to the power supply voltage vdd. It should be noted that the resistance of the first resistor Rs1 is equal to the resistance of the second resistor Rs2, and the current mirror ratios of the first and second current mirrors are both 1. The fifth transistor Mp3 and the sixth transistor Mp4 are also identical transistors. In addition, the first transistor Mp1, the second transistor Mp2, the fifth transistor Mp3, and the sixth transistor Mp4 may be P-type MOS transistors, and the third transistor Mn1 and the fourth transistor Mn2 may be N-type MOS transistors.

[0044] Furthermore, as shown in FIG3 , the flip delay compensation module 120 includes: a decoder unit 121 and a variable resistor unit 122 , wherein the decoder unit 121 is configured to generate a switch control signal S according to the input voltage Vi; and the variable resistor unit 122 is configured to adjust the resistance value of the variable resistor unit 122 according to the switch control signal S.

[0045] Specifically, as shown in FIG5 , the variable resistance unit 122 includes n resistors (R1, R2, …, Rn) and n switches (s10, s20, …, sn0), wherein the n resistors are connected in series in sequence, and a switch is connected in parallel on both sides of each resistor. The decoder unit 121 includes an n-bit decoder 1211, and the switch control signal S includes n switch signals (s1, s2, …, sn), wherein the input end of the n-bit decoder 1211 receives the input voltage Vi, and the output end of the n-bit decoder 1211 outputs n switch signals (s1, s2, …, sn), and the n switch signals (s1, s2, …, sn) control the opening and closing of n switches (s10, s20, …, sn0), and each switch corresponds to a switch signal. Specifically, s1 controls s10, s2 controls s20, and so on, sn controls sn0. The resistance value R of the variable resistance unit 122 is S The size of R is inversely proportional to the input voltage Vi. That is, the larger Vi is, the larger R S The smaller the Vi, the smaller the R S The bigger.

[0046] The principle of the conduction timing circuit in the embodiment of the present disclosure is analyzed with reference to FIG3-5 : When the upper power tube hs is turned on, the first switch T1 is closed. According to the circuit structure in FIG4 , the first current I1 at this time is:

[0047] According to the circuit structure in Figure 4, we can also get: V ramp +V Mp3 +V Mn1 =V Rs2 +V Mp4 +V Mn2 , (2)

[0048] Among them, V Mn1 、V Mn2 、V Mp3 、V Mp4 are the voltages of the third transistor Mn1, the fourth transistor Mn2, the fifth transistor Mp3, and the sixth transistor Mp4, respectively. Rs2 is the voltage of the second resistor;

[0049] Since the current mirror ratios of the first current mirror and the second current mirror are both 1, and the fifth transistor Mp3 and the sixth transistor Mp4 are the same transistors, we can obtain: V Mp3 =V Mp4 、V Mn1 =V Mn2 (3)

[0050] Substituting the two equations in (3) into (2) we can get: V ramp =V Rs2(4)

[0051] Therefore, the second current I2 can be obtained as: I2=I MP1 =V Rs2 / Rs2=V ramp / Rs2 (5)

[0052] Since Rs1=Rs2, the charging current Ic1 is obtained according to equations (1) and (5):

[0053] When the upper power tube hs is turned on, according to the circuit diagram of FIG3 , the voltage V SW =Vi-I load ×R hs , where I load is the load current, R hs is the on-resistance of the upper power tube hs.

[0054] According to the circuit diagram of Figure 3-5, it can be obtained that the following equation is satisfied at the end of the conduction timing:

[0055] Among them, R S is the equivalent resistance of the variable resistance unit 122, V c1 is the voltage across capacitor C1, and according to the relationship between the current and voltage of the capacitor, we can get:

[0056] Substituting formula (8) into formula (7) yields:

[0057] Transforming formula (9) yields:

[0058] The actual on-time also needs to add the comparator's flip delay Tcomp, so equation (10) becomes:

[0059] In the formula, Tcomp will change with Vi, R S C1 also changes with Vi. If the two are equal, that is, R S C1 = Tcomp, the effect of Tcomp on Ton can be offset. Assuming V1 = k·Vo, equation (11) becomes:

[0060] Furthermore, the general expression of Ton obtained according to the volt-second balance principle of the buck converter is as follows:

[0061] Where T Sis the switching period of the buck converter, and Equation (12) is transformed into Equation (13) until:

[0062] Comparing equations (14) and (13), we can obtain T in the embodiment of the present disclosure: S For: T S =k·Rs1·C1, (15)

[0063] According to formula (15), it can be seen that T in the embodiment of the present disclosure S Don't follow me load When the values ​​of k, Rs1 and C1 are constant, T S is a constant, so the operating frequency can be kept constant. It should be noted that the constant operating frequency here is not absolutely constant, but can be considered constant relative to the changes in the background technology. However, in practice, it may also be affected by the non-ideality of some components such as inductors. The embodiment of the present disclosure is mainly aimed at eliminating the impact of the flip delay time and load current on Ton.

[0064] In addition, the R of the variable resistance unit 122 S The determination of R and the setting of the resistance in the variable resistance unit 122 are described as follows: S C1 = Tcomp, which can determine R S =Tcomp / C1, C1 is a constant, Tcomp will change with the change of Vi, and the larger Vi is, the smaller Tcomp is. S After Tcomp and C1 are determined, R S . R S It also changes with Vi, so according to R S The change can be set to R1, R2, ..., Rn. An example is given to illustrate. Assume that there are 10 values ​​of Vi, corresponding to 10 values ​​of Tcomp, and then 10 R can be obtained by calculation. S The value of R S The number of resistors in the variable resistor unit 122 and the value of each resistor can be set. For example, it can be set to 10 resistors, and the value of each resistor is set to one of the resistors R S When the circuit is working, which R S The value of the resistor will open the switch corresponding to that resistor, and close the switches of other resistors. Or you can also set the value of each R S The embodiment of the present disclosure does not limit the number and resistance value of the resistors in the variable resistor unit 122.

[0065] Furthermore, as shown in FIG6 , the on-timer circuit 100 further includes a second switch T2, wherein the second switch T2 is coupled between the ramp voltage node Vramp and ground. The second switch T2 is opened after the first switch T1 is closed, and is closed after the first switch T1 is opened. Since the on-timer ends after the high power transistor hs is turned off, the first switch T1 needs to be opened and the second switch T2 needs to be closed.

[0066] Embodiments of the present disclosure also provide a buck converter with a quasi-constant-frequency, constant on-time architecture, including the on-time timing circuit of the aforementioned embodiment. After the buck converter's upper power transistor is turned on, the on-time timing circuit begins timing. When the on-time timing circuit outputs a shutdown signal, the on-time timing ends, and the buck converter shuts off the upper power transistor in response to the shutdown signal. In applications with a wide range of input voltages Vi, output voltages Vo, and varying loads, the buck converter with a quasi-constant-frequency, constant on-time architecture of the embodiments of the present disclosure can also maintain minimal variations in the system operating frequency, better meeting the requirements of peripheral applications.

[0067] In summary, the conduction timing circuit in the embodiment of the present disclosure can obtain a time constant according to Vi, Vo, I load The effect of small changes in operating frequency.

[0068] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus and method according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart, can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0069] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0070] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

[0071] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A conduction timing circuit, used for a buck converter with a quasi-constant frequency constant conduction time architecture, capable of outputting a shutdown signal for shutting down an upper power tube of the buck converter, characterized in that: The conduction timing circuit includes: a current generating module, a flip delay compensation module, a capacitor, and a comparator. The input end of the current generating module is coupled to the switch node of the buck converter, the output end of the current generating module is coupled to the ramp voltage node, the switch node is the node where the upper power tube and the inductor in the buck converter are coupled, and the current generating module is configured to generate a charging current proportional to the voltage of the switch node after the upper power tube is turned on; The input end of the flip delay compensation module is coupled to the ramp voltage node, the output end of the flip delay compensation module is coupled to one end of the capacitor, the flip delay compensation module is configured to generate a first delay for comparator flip delay compensation according to a variable resistance unit and the capacitor, and the resistance value of the variable resistance unit is controlled by the input voltage of the buck converter; The other end of the capacitor is coupled to the ground end, and the capacitor is configured to be charged by the charging current after the upper power tube is turned on; The positive input terminal of the comparator is coupled to the slope voltage node, and the negative input terminal of the comparator is coupled to a first voltage. The comparator is configured to compare the slope voltage corresponding to the slope voltage node with the first voltage and generate the shutdown signal. The first voltage is a reference voltage proportional to the output voltage of the buck converter.

2. The conduction timing circuit according to claim 1, characterized in that: The current generating module comprises: a first current generating module and a second current generating module. Wherein, the first current generating module is configured to generate a first current according to the voltage of the switch node and the voltage of the ramp voltage node; The second current generating module is configured to generate a second current according to the voltage of the ramp voltage node, and the sum of the first current and the second current is the charging current.

3. The conduction timing circuit according to claim 1, characterized in that: The flip delay compensation module includes: a decoder unit, a variable resistor unit, Wherein, the decoder unit is configured to generate a switch control signal according to the input voltage; The variable resistance unit is configured to adjust the resistance value of the variable resistance unit according to the switch control signal.

4. The conduction timing circuit according to claim 2, characterized in that: The first current generating module includes: a first resistor, a first switch, Wherein, one end of the first resistor is coupled to the switch node, the other end of the first resistor is coupled to one end of the first switch, and the other end of the first resistor generates the first current; The other end of the first switch is coupled to the slope voltage node, and the first switch is closed after the upper power tube is turned on, and is opened after the upper power tube is turned off.

5. The conduction timing circuit according to claim 4, characterized in that: The second current generating module includes: first to sixth transistors, a first current source, and a second resistor. The first transistor and the second transistor form a first current mirror, the source of the first transistor and the source of the second transistor are both coupled to a power supply voltage, the gate of the first transistor and the gate of the second transistor are both coupled to the drain of the first transistor, the drain of the second transistor is coupled to the ramp voltage node, and the drain of the second transistor generates the second current; A third transistor and a fourth transistor form a second current mirror, a gate of the third transistor and a gate of the fourth transistor are both coupled to a drain of the third transistor, the drain of the third transistor is coupled to one end of the first current source, and the drain of the fourth transistor is coupled to the drain of the first transistor; A source of the fifth transistor is coupled to the source of the third transistor, a gate of the fifth transistor is coupled to the ramp voltage node, and a drain of the fifth transistor is coupled to the ground terminal; The source of the sixth transistor is coupled to the source of the fourth transistor. The gate is coupled to the drain of the sixth transistor, and the drain of the sixth transistor is coupled to one end of the second resistor; The other end of the second resistor is coupled to the ground, and the other end of the first current source is coupled to the power supply voltage.

6. The conduction timing circuit according to claim 3, characterized in that: The variable resistance unit includes n resistors and n switches. Among them, n resistors are connected in series in sequence, and a switch is connected in parallel on both sides of each resistor.

7. The conduction timing circuit according to claim 6, characterized in that: The decoder unit includes an n-bit decoder, the switch control signal includes n switch signals, The input end of the n-bit decoder receives the input voltage, and the output end of the n-bit decoder outputs the n switch signals, the n switch signals control the opening and closing of the n switches, and each switch corresponds to a switch signal.

8. The conduction timing circuit according to claim 1, characterized in that: The resistance of the variable resistance unit is in inverse proportion to the input voltage.

9. The conduction timing circuit according to claim 5, characterized in that: The resistance value of the first resistor is equal to the resistance value of the second resistor.

10. The conduction timing circuit according to claim 4, characterized in that: The on-timer circuit further includes a second switch, wherein the second switch is coupled between the slope voltage node and the ground terminal, and the second switch is opened after the first switch is closed, and is closed after the first switch is opened.

11. The conduction timing circuit according to claim 5, characterized in that: The current mirror ratios of the first current mirror and the second current mirror are both 1.

12. A buck converter with a quasi-constant frequency constant on-time architecture, characterized in that: The invention comprises a conduction timing circuit according to any one of claims 1 to 11.

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