Data read and write method, and device and storage medium

Abstract

Provided in the embodiments of the present application are a data read and write method, and a device and a storage medium. When a read instruction for a storage device connected to a host end occurs at the host end, it can be determined whether there is a target write instruction that needs to be executed in association with the read instruction, so as to detect a reading-after-writing situation in a timely manner; and, according to a specified association format, such read instructions and write instructions that need to be executed in association with the read instructions can be scheduled to the same instruction queue. In this way, the storage device can correctly detect the reading-after-writing situation from a plurality of instruction queues provided by the host end, temporarily suspend such detected read instructions, and then resume corresponding read instructions after confirming that the related write instructions have been executed. Accordingly, in a multi-queue concurrent read and write scenario, an associated execution relationship between instructions in the case of reading after writing can still be correctly maintained, so as to ensure that the latest data can be read from a storage device by means of read instructions and ensure the data read and write consistency, and thus improving the performance of the storage device.

Description

Data reading and writing method, device and storage medium Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a data reading and writing method, device, and storage medium. Background Art

[0002] Compared to hard disk drives (HDDs), solid-state drives (SSDs) not only eliminate complex mechanical design and reduce power consumption and size, but also offer performance improvements in latency and throughput. Consequently, SSDs have become widely used in various cloud service areas.

[0003] SSDs that support multi-queue, high-concurrency read and write operations can effectively alleviate I / O performance bottlenecks, making them popular in high-performance applications such as databases. However, with the increasing degree of write and read parallelism, read operations often occur before a write operation to a specific address is complete. This results in the read operation not receiving the latest data, leading to data inconsistency.

[0004] Summary of the Invention

[0005] Various aspects of the present application provide a data reading and writing method, device, and storage medium to improve data consistency when performing multi-queue reading and writing on a storage device.

[0006] The present invention provides a data reading and writing method applicable to a host side, wherein the host side is connected to a storage device, and the method includes:

[0007] In the case of detecting a read instruction for the storage device, determining whether there is a target write instruction that needs to be executed in association with the read instruction;

[0008] If so, dispatching the read instruction and the target write instruction to a target queue according to a specified association format, wherein the target queue is any one of a plurality of instruction queues for transmitting read / write instructions to the storage device;

[0009] The read instruction and the target write instruction are provided to the storage device through the target queue, so that the storage device can perceive the write instruction that affects the read instruction based on the associated format and execute the read instruction after completing the corresponding write instruction.

[0010] The present application also provides a data reading and writing method applicable to a storage device connected to a host. The method includes:

[0011] For any read instruction included in the plurality of instruction queues provided by the host side, if it is determined that the read instruction has a write instruction that needs to be associated with it, temporarily suspending the read instruction;

[0012] searching, in the plurality of instruction queues, for a target write instruction to be executed in association with the read instruction according to a specified association format;

[0013] After monitoring that the target write instruction is executed, the read instruction is restored so that the read instruction reads the data written by the target write instruction.

[0014] An embodiment of the present application further provides an electronic device, including a memory, a processor, and a communication component;

[0015] The memory is configured to store one or more computer instructions;

[0016] The processor is coupled to the memory and the communication component, and is configured to execute the one or more computer instructions for executing the aforementioned data reading and writing method.

[0017] An embodiment of the present application also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the aforementioned data reading and writing method.

[0018] In an embodiment of the present application, when a read instruction for a storage device connected thereto occurs on the host side, it can be determined whether there is a target write instruction that needs to be executed in association with the read instruction, and the situation of appended read after write can be detected in time; on this basis, such read instructions and the write instructions that need to be executed in association with them can be scheduled to the same instruction queue according to the specified association format. In this way, the storage device can correctly perceive the situation of appended read after write in the multiple instruction queues provided by the host side, and temporarily suspend such perceived read instructions, and resume the corresponding read instructions after determining that the relevant write instructions have been completed. Accordingly, through the above-mentioned cooperation between the host side and the storage device connected thereto, in the scenario of concurrent reading and writing of multiple queues, the associated execution relationship between the instructions in the case of appended read after write can still be correctly maintained to ensure that the read instruction can read the latest data from the storage device, ensure data read and write consistency, and thus improve the performance of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] FIG1 is a logic diagram of existing multi-queue concurrent reading and writing of a solid-state drive;

[0021] FIG2 is a schematic diagram of the structure of an address mapping table for supporting data reading and writing;

[0022] FIG3 is a schematic flow chart of a data reading and writing method on a host side provided by an exemplary embodiment of the present application;

[0023] FIG4 is a schematic diagram of an exemplary working logic of a host side in an exemplary embodiment of the present application;

[0024] FIG5 is a flow chart of an exemplary implementation scheme of adding a designated tag to a read instruction and a target write instruction on the host side;

[0025] FIG6 is a schematic diagram of an exemplary flow chart of an exemplary scheduling solution;

[0026] FIG7 is a schematic flow chart of a data reading and writing method on a storage device side provided by another exemplary embodiment of the present application;

[0027] FIG8 is a schematic diagram of the working logic of a storage device in an exemplary embodiment of the present application;

[0028] FIG9 a is a schematic diagram of a flow chart of an exemplary data reading and writing solution on the storage device side;

[0029] FIG9 b is a logical diagram of an exemplary data reading and writing solution on the storage device side;

[0030] FIG10 is a schematic structural diagram of an electronic device provided by yet another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0031] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] The technical solution provided in this application is described below with reference to the accompanying drawings.

[0033] Figure 1 is a logical diagram of existing multi-queue concurrent read / write operations on SSDs. As shown in Figure 1, when reading and writing data to an SSD, the host can use a multi-queue concurrent method to transmit read / write commands to the SSD. Referring to Figure 1, the host can place read / write commands for the SSD into multiple command queues, and the SSD will execute the commands in the multiple command queues sequentially in a first-in, first-out order.

[0034] As write and read parallelism increases, the probability of address overlap between read and write instructions becomes increasingly higher. According to the existing processing scheme shown in FIG1 , when a write instruction for a certain access address has not yet been completed, if a read instruction for the access address is appended, data inconsistency may occur. FIG2 is a schematic diagram of the structure of an address mapping table for supporting data reading and writing. The address mapping table, which can also be called a page table, is used to convert the access address in the read / write instruction into a physical address to access the corresponding physical storage location. Referring to FIG2 , the address mapping table contains the mapping relationship between the access address (also called the logical address, logical block address, LBA) and the physical address (physical block address, PBA). When the write instruction has not yet been completed, whether the read instruction appended for the same access address can read the correct data depends on the execution status of the corresponding write instruction when the read instruction is parsed.

[0035] If the write instruction has not yet reached the SSD, there may be several situations shown in Figure 2 when the read instruction is parsed: the access address pointed to by the read instruction is not mapped to a valid physical address in the address mapping table, then the read instruction will read invalid data (for example, all zeros, etc.); the access address pointed to by the read instruction is mapped to a valid physical address in the address mapping table, then the read instruction reads old data. In either case, the read instruction will not be able to read the correct new data, resulting in inconsistent data reading and writing. If the write instruction has already reached the SSD, affected by factors such as queue depth and read time interval, there is still a high probability that the read instruction will not be able to read the correct new data.

[0036] To this end, this embodiment proposes a data read and write solution for ensuring that a read instruction can read the data written by a write instruction in the case of a post-write read. The post-write read refers to the aforementioned situation where a read instruction for the same access address is issued shortly after a write instruction is issued.

[0037] The data read and write solution proposed in this embodiment can be implemented by the host side in conjunction with the storage device connected to it. The following describes the operating logic of the host side and the operating logic of the storage device respectively. Considering that the focus of this embodiment is on the accuracy of the read instruction, for the sake of convenience, this embodiment will explain the technical solution from the perspective of any read instruction generated by the host side.

[0038] FIG3 is a flow chart of a data reading and writing method on a host side provided by an exemplary embodiment of the present application. Referring to FIG3 , the method may include:

[0039] Step 300: When a read instruction for a storage device is detected, determine whether there is a target write instruction that needs to be executed in association with the read instruction;

[0040] Step 301: If so, dispatch the read instruction and the target write instruction to a target queue according to a specified association format. The target queue is any one of multiple instruction queues for transmitting read / write instructions to a storage device.

[0041] Step 302: Provide the read instruction and the target write instruction to the storage device through the target queue.

[0042] It is worth noting that the storage device in this embodiment can be the solid-state hard disk mentioned above, and of course it can also be other storage devices that can be connected to the host side and support multi-queue concurrent reading and writing. This embodiment does not limit this. In this embodiment, the host side can use Queue Pair (QP) technology to support multi-queue concurrent reading and writing. Among them, QP is a virtual interface between hardware and software. In the queue structure provided by QP, the tasks (WQE) issued by the software to the hardware are stored in sequence. The WQE contains information such as where to retrieve the data, how long it is, and to which destination it is sent. In this embodiment, multiple instruction queues can use the aforementioned QP queue, and the QP queue carries the read / write instructions that need to be transmitted to the storage device side.

[0043] In addition, the host side in this embodiment may be installed with a storage engine for processing storage transactions, and the storage engine may include a driver component corresponding to the storage device connected thereto (for example, an NVMe (Non Volatile Memory Express) driver component, etc.). Based on this, in this embodiment, the storage engine in the host side may be modified so that the host side executes the data reading and writing method provided in this embodiment.

[0044] Referring to Figure 3, in step 300, the host side can monitor the read instructions for the storage device and determine whether there is a target write instruction that needs to be executed in association with the read instruction. Among them, needing to be executed in association with the read instruction means that if it is not executed in association, it will affect the correctness of the reading result of the read instruction. In this embodiment, the host side can monitor the read instructions initiated by the application on it for the storage device in real time. Here, the host side can support a single application to perform concurrent reading and writing on the storage device, and of course it can also support multiple applications to perform concurrent reading and writing on the storage device. In this way, in step 300, whenever a new read instruction is detected, it can be determined whether there is a target write instruction that needs to be executed in association with the read instruction. Here, it is necessary to search for a target write instruction that needs to be executed in association with the read instruction from the write instructions that occurred before the currently monitored read instruction and have not yet been processed. Therefore, in step 300, it can be determined whether the currently monitored read instruction belongs to the case of appending read after write.

[0045] FIG4 is a schematic diagram of an exemplary working logic of the host side in an exemplary embodiment of the present application. Referring to FIG4 , in an optional implementation, the host side may record the access address pointed to by the write instruction when detecting a write instruction to the storage device, so that a write address record may be formed. In actual applications, the write address record may be maintained by means of a data table or the like. Moreover, the write address record may be dynamically updated, that is, the access address involved may be recorded in a timely manner after a new write instruction is detected, and the access address involved may be deleted in a timely manner after the write instruction has been processed. Based on this, in this implementation, the host side may determine the access address pointed to by the read instruction when detecting a read instruction to the storage device; if the access address exists in the write address record, the pending write instruction pointing to the access address is determined as the target write instruction to be executed in association with the read instruction. In this way, based on the dynamically maintained write address record, when a read instruction is detected, it may be determined by address comparison whether there is a target write instruction to be executed in association with the read instruction.

[0046] Referring to Figure 3, if there is a target write instruction that needs to be executed in conjunction with a read instruction, then in step 301, the read instruction and the target write instruction can be scheduled into a target queue according to a specified association format. The target queue can be any one of multiple instruction queues. As mentioned above, multiple instruction queues can be used between the host and the storage device to transmit read / write instructions. In step 301, the read instruction and its corresponding target write instruction can be written into the same instruction queue according to the specified association format.

[0047] The specified association format can be used to reflect the association execution relationship between the read instruction and its corresponding target write instruction. In this embodiment, multiple association formats can be used to reflect the association execution relationship between the read instruction and its corresponding target write instruction.

[0048] In an optional implementation, a designated tag for indicating the existence of an instruction that needs to be executed in association may be added to each of the read instruction and the target write instruction; and the read instruction and the target write instruction may be scheduled to the target queue according to the designated relative position relationship.

[0049] Exemplarily, the designated mark may adopt a flag bit. In some practical applications, a numerical value may be configured for the flag bit, such as 1, which can be used to represent the existence of an instruction that needs to be executed in association. In this case, when there is a target write instruction that needs to be executed in association with the read instruction, a flag bit may be added for the relevant read instruction and write instruction respectively, while no flag bit is added for the read instruction and write instruction that do not need to be executed in association. Of course, in other practical applications, two kinds of data may also be configured for the flag bit, one numerical value is used to represent the existence of an instruction that needs to be executed in association, and the other numerical value can be used to represent the absence of an instruction that needs to be executed in association. For example, 1 and 0, where 1 is used to represent the existence of an instruction that needs to be executed in association, and 1 is used to represent the absence of an instruction that needs to be executed in association. In this case, a flag bit may be added for each read instruction and each write instruction, but the presence of an instruction that needs to be executed in association is marked by different values ​​of the flag bit.

[0050] In addition to the flag bit, the designated flag can also be implemented in other forms, such as adding a special field, etc., which are not further examples here. By adding the designated flag, it is possible to effectively distinguish between one type of instructions that need to be associated with the execution and another type of instructions that do not need to be associated with the execution.

[0051] Figure 5 is a flowchart illustrating an exemplary implementation of a host-side method for adding designated tags to read and target write instructions. Referring to Figure 5, host-side write instructions to a storage device are directly placed into a write queue by the storage engine's scheduler. Read instructions, however, must compare their access addresses with those of pending write instructions. If the access addresses differ, they are scheduled as independent read and write events. If the access addresses are the same, designated tags must be added to both the read instruction and its corresponding target write instruction in the read and write queues.

[0052] In this optional implementation, in addition to adding designated marks to the read instruction and its corresponding target write instruction respectively, the relative position relationship can also be specified to schedule the read instruction and the target write instruction into the target queue. As mentioned above, the host side transmits read / write instructions to the storage device through multiple instruction queues, that is, all pending read instructions and pending write instructions monitored by the host side need to be scheduled into the instruction queue. In this optional implementation, the position of the read instruction and its corresponding target write instruction in the instruction queue after being scheduled is specified. On the one hand, the read instruction and its corresponding target write instruction need to be in the same instruction queue, and on the other hand, the two need to satisfy the specified relative position relationship in the same instruction queue.

[0053] The specified relative position relationship can be used to correctly indicate the write instruction that should be executed in association with the read instruction in the target queue, so that the associated execution relationship between the read instruction and its corresponding target write instruction can be correctly transmitted to the storage device.

[0054] Preferably, the specified relative position relationship can be: the read instruction is located at the next placement position after its corresponding target write instruction. That is, in the target queue, the read instruction is adjacent to and after its corresponding target write instruction. It should be understood that the relative position relationship here is exemplary, and this embodiment is not limited thereto. For example, the read instruction and its corresponding target write instruction may not be adjacent to each other but may be separated by a predetermined number of placement positions, etc. Further specific examples are not provided here.

[0055] In order to ensure that the read instruction and its corresponding target write instruction can be scheduled to the target queue according to the specified relative position relationship, in an exemplary scheduling scheme: the scheduling timing of the read instruction with post-write appended read situation can be adjusted without interfering with the scheduling process of the write instruction.

[0056] In this exemplary scheduling scheme, when a target write instruction arrives at the exit of a write queue, the target write instruction is scheduled into the target queue; a target placement position is determined for the read instruction in the target queue based on relative position; and the read instruction is scheduled into the target placement position in the target queue. The write queue is used to store pending write instructions from the host, and pending write instructions contained in the write queue are scheduled into multiple instruction queues in a first-in, first-out order.

[0057] FIG6 is a schematic diagram of an exemplary flow of the exemplary scheduling scheme. Referring to FIG6 , in the exemplary scheduling scheme: the host side can fetch instructions from the read queue and the write queue for processing respectively, and check the flag bit of the current instruction. If the flag bit is not 1, the scheduling is assigned to a QP (queue pair) queue; if the flag bit is 1, it is distinguished as a read / write instruction; if it is a read instruction, it is placed in the host side's read instruction temporary queue, waiting to be processed together when the subsequent associated write instruction is scheduled; if it is a write instruction, it is checked whether the associated read instruction with the same LBA is in the read instruction temporary queue. If it is in the read instruction temporary queue, the associated write instruction is taken out and placed in the same QP queue with the read instruction in the order of write first and read later. If the associated read instruction is not found in the read instruction temporary queue, the associated read instruction is searched in the current read queue. Once found, it is placed in a QP queue with the associated write instruction in the order of write first and read later. If it cannot be found in the read queue, a system error can be reported and the current processing flow exits.

[0058] In actual applications, after the host side detects a new write instruction, it can place the write instruction in the write queue, and the pending write instruction arriving at the queue exit will be scheduled to multiple instruction queues. It is worth noting here that for the aforementioned target write instruction, a specified tag will be added while it is in the write queue. Based on this, in this exemplary scheduling scheme, the host side can perceive whether the pending write instruction currently arriving at the queue exit has an instruction that needs to be associated with execution by identifying the specified tag. Naturally, when the aforementioned target write instruction arrives at the queue exit, it can be identified that there is an instruction that needs to be associated with execution, and the scheduling of related read instructions can be triggered for it; and for other pending write instructions that do not have instructions that need to be associated with execution, the scheduling of related read instructions will not be triggered additionally, and the conventional write instruction scheduling can be completed.

[0059] Here, there is a possibility that a read instruction has reached its scheduling opportunity before its corresponding target write instruction arrives at the write queue exit. This situation may cause the read instruction to be prematurely scheduled to multiple instruction queues, failing to meet the specified relative position relationship. Regarding this, referring to Figure 4, in an improved solution, a read queue and a read instruction temporary storage queue are also provided on the host side. The pending read instructions contained in the read queue are scheduled to multiple instruction queues in a first-in, first-out order; while the read instructions contained in the read instruction temporary storage queue must wait for a trigger before being scheduled. Based on this, in this improved solution, if a read instruction arrives at the read queue exit before the target write instruction arrives at the write queue exit, the read instruction is scheduled to the read instruction temporary storage queue. Thus, if a read instruction is found in the read instruction temporary storage queue, scheduling of the read instruction is triggered, so that the read instruction is scheduled to the target placement position in the target queue. If the read instruction is not found in the read instruction temporary storage queue, the read instruction is extracted from the read queue and scheduled to the target placement position in the target queue.

[0060] That is, in this improved solution, the write instructions to be processed can be scheduled in sequence based on the write queue. In this way, it is also possible to accurately identify whether the read instruction reaching the read queue exit is a read instruction with a post-write appended read situation by specifying an identifier. If so, the read instruction can be first scheduled to the read instruction temporary queue, waiting for its corresponding target write instruction to arrive at the write queue exit before being scheduled to the target queue together with the target write instruction; if not, the read instruction can be directly scheduled to multiple instruction queues without having to be scheduled to the read instruction temporary queue first.

[0061] In this way, through the read instruction temporary queue, the scheduling timing of read instructions with post-write additional read situations can be effectively adjusted to ensure that such read instructions can wait until their corresponding target write instructions are scheduled to the target queue together, thereby ensuring that the associated execution relationship between the read instruction and its corresponding target write instruction is correctly transmitted to the storage device.

[0062] In conjunction with FIG4 , an exemplary application scenario is provided below, and the data reading and writing logic of the host side is exemplarily described in this application scenario.

[0063] Referring to Figure 4 , the host can place read and write instructions from multiple applications into a read queue and a write queue, respectively, in the order they are received, and process them using a first-in, first-out method. After recording the write LBA (i.e., access address) required for each new write instruction, it can be placed into the write queue. For each new read instruction, before entering the read queue, its requested read LBA (i.e., access address) can be compared with the LBAs involved in each write instruction in the write queue. If there are no identical LBAs, the read instruction enters the read queue; conversely, if there are identical LBAs, i.e., a post-write read occurs, the write LBA (LBA_wr m in Figure 4 ) is linked to the read LBA (LBA_rd x in Figure 4 ) and marked in the read queue. A specific method can be to place a flag bit in each corresponding read instruction and write instruction. If an associated execution relationship exists, the flag bit of the read LBA is set to 1. The write instructions in the write queue can be distributed to various instruction queues according to the scheduling rules (such as first-in-first-out); when a write instruction with an instruction that needs to be associated and executed enters the instruction queue, it is necessary to first search for the associated read instruction in the read instruction cache queue (that is, the LBA of the operation is the same); if it cannot be found, then continue to search for the required read instruction in the read queue. After finding the required read instruction, it can be scheduled to the same instruction queue as the write instruction and placed in the position after the write instruction. When scheduling each read instruction in the read queue, the flag bit must be checked at the exit of the read queue. If the flag bit is 0, it can be assigned to each instruction queue by the scheduler. If the flag bit is 1, it indicates that the read instruction at the exit has a write instruction that needs to be associated and pointed to, and the write instruction is still queued in the write queue; at this time, the read instruction can be placed in the read temporary queue, and when the write instruction with its associated execution arrives at the exit of the write queue and is processed, the two can be placed in the same instruction queue together. In this way, in the application scenario provided by FIG. 4 , the write instruction and the read instruction that need to be executed in association can be transmitted to the storage device in the correct association execution order, thereby ensuring that both can be executed by the storage device in the correct execution order.

[0064] FIG7 is a flowchart of a data reading and writing method on a storage device side provided by another exemplary embodiment of the present application.

[0065] Referring to FIG. 7 , the method may include:

[0066] Step 700: For any read instruction included in the plurality of instruction queues provided by the host, if it is determined that the read instruction has a write instruction that needs to be associated with it, the read instruction is temporarily suspended;

[0067] Step 701: Search multiple instruction queues for a target write instruction to be executed in association with a read instruction according to a specified association format;

[0068] Step 702: After monitoring that the target write instruction is executed, restore the read instruction so that the read instruction reads the data written by the target write instruction.

[0069] FIG8 is a schematic diagram of the operating logic of a storage device in an exemplary embodiment of the present application. Referring to FIG8 , the storage device in this embodiment may run a front-end process that communicates with a storage engine on the host side. Based on this, this embodiment may improve the front-end process so that the storage device executes the data reading and writing method provided by this embodiment. The front-end process may access multiple instruction queues provided by the host side and receive read / write instructions from the multiple instruction queues. The multiple instruction queues are generated by the host side according to the aforementioned data reading and writing method.

[0070] In this embodiment, the data read and write logic on the storage device side is described from the perspective of any read instruction. Referring to Figure 7, in step 700, for any read instruction included in the multiple instruction queues provided by the host, if it is determined that the read instruction has an associated write instruction that needs to be executed, the read instruction is temporarily suspended.

[0071] As mentioned above, the host can distinguish between instructions that undergo a post-write read and instructions that do not undergo a post-write read by adding a designated tag. To this end, in step 700, it can detect whether the read instruction carries a designated tag, which is used to indicate the presence of an instruction that needs to be executed in association. If it does, and the designated tag points to the same access address as the read instruction, it is determined that a write instruction needs to be executed in association with the read instruction exists. The designated tag is added by the host to the read instruction after determining that a write instruction needs to be executed in association with the read instruction exists. The specific implementation of the designated tag will not be repeated here.

[0072] Of course, as mentioned above, the host can implement various designated tags. Therefore, the storage device and the host can agree on the identification method to be used as needed. Here, the storage device can use the agreed-upon identification method with the host to determine whether the current read instruction has a write instruction that needs to be executed. If so, the read instruction will be temporarily suspended. Temporary suspension can be understood as pausing execution, and execution will resume after a subsequent trigger.

[0073] In an optional implementation, such read instructions can be dispatched from the instruction queue in which they are located to a read temporary queue; wherein, the read instructions in the read temporary queue need to wait until a trigger condition is met before being executed, and the trigger condition includes that the write instruction to be executed in association with the read instruction has been executed. Referring to Figure 8, in this implementation, a read temporary queue is added to the storage device to store read instructions that need to be temporarily suspended. It should be understood that, referring to Figure 8, for write instructions read from multiple instruction queues, the storage device can place the write instructions in the write execution queue as shown in Figure 8, and execute them in a first-in-first-out order; and for read instructions that do not need to be temporarily suspended, they will also be placed in the read execution queue and executed in a first-in-first-out order.

[0074] Of course, in this embodiment, other implementations may be used to temporarily suspend this type of read instruction, and no further examples are given here.

[0075] Continuing with FIG. 7 , in step 701, a target write instruction to be executed in association with a read instruction may be searched for in a plurality of instruction queues according to a specified association format. The storage device and the host may pre-agreed on the association format to be followed. The host may schedule the relevant read / write instructions to the plurality of instruction queues according to the agreed association format. Accordingly, the storage device may accurately search for the target write instruction to be executed in association with the read instruction from the plurality of instructions according to the agreed association format.

[0076] An exemplary scheduling scheme on the host side is adopted: the host side adds a specified tag to the read instruction and the target write instruction to be executed in association; according to the specified relative position relationship, the read instruction and the target write instruction are scheduled into the same instruction queue. In step 701: the storage device can search the instruction queue where the read instruction is located for a write instruction that meets the specified relative position relationship; if the found write instruction carries the specified tag and points to the same access address as the read instruction, the found write instruction is determined to be the target write instruction. Through this verification operation, the storage device can accurately find the target write instruction to be executed in association for the read instruction from multiple instruction queues.

[0077] It should be understood that during the execution of step 701, the read instruction remains temporarily suspended. The storage device can monitor the execution of the target write instruction after finding the target write instruction for the read instruction. Referring to FIG7 , in step 702, after monitoring the completion of the target write instruction, the read instruction can be resumed so that the read instruction can read the data written by the target write instruction.

[0078] Among them, following the aforementioned optional implementation method of temporarily suspending the read instruction based on the read temporary queue, in step 702, after monitoring the completion of the target write instruction, the corresponding read instruction in the read cache queue can be triggered to resume the read instruction.

[0079] In addition, when executing a target write instruction, the storage device can write the target data to the memory of the storage device; in the address mapping table, the physical address corresponding to the target data is updated to point to the address of the target data storage location in the memory to complete the associated write instruction. Preferably, the storage device can use low power double data rate (LPDDR) memory.

[0080] That is, the storage device no longer directly writes the target data to the final storage location, but first writes the target data to the memory. Since the read and write speed of the memory is usually higher than the final storage location of the storage device, combined with the update of the address mapping table, the read instruction can be responded to with lower latency through the memory of the storage device, so that the read instruction can read the data written by the associated write instruction more quickly.

[0081] Here, a memory address translation table may be added to the storage device, and the mapping relationship between the memory logical address and the memory physical address may be recorded in the memory address translation table. Based on this, the physical address corresponding to the target data may be updated to the memory logical address corresponding to the target data in the memory of the storage device in the aforementioned address mapping table. In this way, when the storage device executes a read instruction, it may first map the access address pointed to by the read instruction to the memory logical address of the target data in the memory based on the address translation table, and then convert the memory logical address to the memory physical address based on the memory address translation table, so that the read instruction can read the required data from the memory physical address.

[0082] Furthermore, the storage device can asynchronously write the target data from the storage device's memory to the storage device's flash memory. After the target data is written to the storage device's flash memory, the physical address corresponding to the target data in the address mapping table is updated to the physical address of the target data in the flash memory. In other words, the target data can be asynchronously transferred from the memory to the final storage location, and the address mapping table is also updated with the physical address corresponding to the final storage location for later use.

[0083] For example, Figure 8 is a schematic diagram of an exemplary logic for executing a write instruction on the storage device side. Referring to Figure 8 , while the storage device is executing a write instruction, data can be written to the LPDDR data cache (i.e., memory) and then asynchronously written to the NAND flash memory, updating the address mapping table. After the data is written to the LPDDR, a short LDPPR address translation table is maintained in addition to the address mapping table. As shown in Figure 8 , the physical address PBA mapped to the entry in the mapping table corresponding to the access address LBA=w is the memory logical address in the LPDDR address table. Based on the LPDDR address translation table, going to this memory logical address (e.g., DDRT=w) can read the LPDDR memory physical address DDRP=b. Using this memory physical address to read the LPDDR memory, the correct data is retrieved and returned to the host. When the SSD backend successfully writes the data to the NAND flash memory using the physical address PBA assigned by the address mapping table, the entry in the address mapping table is also updated to the NAND physical address. For data after the asynchronous write is completed, a read instruction can directly read the NAND physical PBA (e.g., PBA=t) from the address mapping table and go to the NAND physical PBA PBA to retrieve the required data.

[0084] Figure 9a is a flow chart of an exemplary data read / write solution on the storage device side, and Figure 9b is a logic diagram of an exemplary data read / write solution on the storage device side. Figures 9a and 9b collectively present the aforementioned related optional implementations. Referring to Figures 9a and 9b, after the front-end process of the storage device receives read / write instructions from multiple instruction queues, it first determines whether it is a read or write instruction. If it is a write instruction, it is placed in the write execution queue to initiate the write operation. The write operation involves writing data to the storage device's memory and updating the address mapping table. At this point, the data is still in the storage device's memory, so the corresponding access address in the address mapping table is mapped to the address pointing to the data's storage location in the memory, i.e., the physical address in the memory. After the data is asynchronously written from the storage device's memory to the flash memory, the address mapping table is further updated, and the corresponding access address is mapped to the data's physical address in the flash memory. The storage device executes the write instruction as soon as possible after receiving it. When a read instruction is received, it first checks whether its flag bit is 1.

[0085] If the flag bit of the read instruction is not 1, it is executed as an independent read instruction, placed in the read execution queue, and executed in first-in, first-out mode. During execution, the physical address (memory physical address or flash physical address) mapped to the access address in the address mapping table is searched, and the corresponding physical address is read. Of course, during this period, the storage device can also perform error correction and data verification on the read data; after the verification passes, the data is sent back to the host to complete the read instruction.

[0086] If the flag bit of the read instruction is 1, then there is a write instruction that needs to be associated with the read instruction. In the instruction queue where the read instruction is located, the flag bit of the previous write instruction is checked to see if it is 1 and whether it points to the same access address as the read instruction. If so, the association is determined to be correct and the read instruction is placed in the read cache queue. After the associated write instruction is successfully executed, the read instruction is executed. If the association is incorrect, the association error is reported.

[0087] In summary, when a read instruction for the storage device connected to it occurs on the host side, it can be determined whether there is a target write instruction that needs to be executed in association with the read instruction, and the situation of appended read after write can be detected in time; on this basis, such read instructions and the write instructions that need to be executed in association with them can be scheduled to the same instruction queue according to the specified association format. In this way, the storage device can correctly perceive the situation of appended read after write in the multiple instruction queues provided by the host side, and temporarily suspend such perceived read instructions, and resume the corresponding read instructions after determining that the relevant write instructions have been completed. Accordingly, through the above-mentioned cooperation between the host side and the storage device connected to it, in the scenario of concurrent reading and writing in multiple queues, the associated execution relationship between the instructions in the case of appended read after write can still be correctly maintained to ensure that the read instruction can read the latest data from the storage device, ensure data read and write consistency, and thus improve the performance of the storage device.

[0088] It should be noted that some of the processes described in the above embodiments and the accompanying drawings include multiple operations that appear in a specific order. However, it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel. The sequence numbers of the operations, such as 301 and 302, are used to distinguish between different operations and do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel.

[0089] FIG10 is a schematic diagram of the structure of an electronic device provided by another exemplary embodiment of the present application. As shown in FIG10 , the electronic device may include: a memory 10 , a processor 11 , and a communication component 12 .

[0090] In some possible designs, the electronic device provided in FIG10 is implemented as the host terminal in the aforementioned embodiments. In this case, the host terminal may be connected to a storage device, a processor 11 coupled to the memory 10 and the communication component 12, and configured to execute a computer program in the memory 10 for:

[0091] In the case of detecting a read instruction for the storage device, determining whether there is a target write instruction that needs to be executed in association with the read instruction;

[0092] If so, dispatching the read instruction and the target write instruction to a target queue according to a specified association format, wherein the target queue is any one of a plurality of instruction queues for transmitting read / write instructions to the storage device;

[0093] The read instruction and the target write instruction are provided to the storage device through the target queue, so that the storage device can perceive the write instruction that affects the read instruction based on the associated format and execute the read instruction after completing the corresponding write instruction.

[0094] In an optional embodiment, when the processor 11 determines whether there is a target write instruction to be executed in association with the read instruction, it may be configured as follows:

[0095] Determining the access address pointed to by the read instruction;

[0096] If the access address exists in the write address record, determining the pending write instruction pointing to the access address as the target write instruction;

[0097] The write address record includes an access address identified from the write instruction to be processed.

[0098] In an optional embodiment, when the processor 11 schedules the read instruction and the target write instruction to the target queue according to the specified association format, it can be configured as follows:

[0099] Adding a designated tag for indicating that there are instructions that need to be executed in association to the read instruction and the target write instruction respectively;

[0100] The read instruction and the target write instruction are scheduled into the target queue according to a specified relative position relationship.

[0101] In an optional embodiment, when the processor 11 schedules the read instruction and the target write instruction to the target queue according to the specified relative position relationship, it can be configured as follows:

[0102] When the target write instruction arrives at the exit of the write queue, scheduling the target write instruction into the target queue;

[0103] determining a target placement position for the read instruction in the target queue according to the relative position relationship;

[0104] Dispatching the read instruction to the target placement position in the target queue;

[0105] The pending write instructions contained in the write queue are dispatched to the multiple instruction queues in a first-in-first-out order.

[0106] In an optional embodiment, the processor 11 is further configured to:

[0107] If the read instruction has arrived at the exit of the read queue before the target write instruction arrives at the exit of the write queue, the read instruction is scheduled to the read instruction temporary queue, and the read instructions contained in the read instruction temporary queue need to wait for triggering before being scheduled;

[0108] Scheduling the read instruction to the target placement position in the target queue includes:

[0109] If the read instruction is found in the read instruction temporary queue, triggering the scheduling of the read instruction to schedule the read instruction to the target placement position in the target queue;

[0110] If the read instruction is not found in the read instruction temporary queue, extracting the read instruction from the read queue and dispatching it to the target placement position in the target queue;

[0111] The to-be-processed read instructions contained in the read queue are dispatched to the multiple instruction queues in a first-in-first-out order.

[0112] In an optional embodiment, the relative position relationship includes the read instruction being located at a subsequent placement position of its corresponding target write instruction.

[0113] In some other possible designs, the electronic device in FIG10 may be implemented as the storage device in the aforementioned embodiment. In this case, the storage device may be connected to the host side, and the processor 11, coupled with the memory 10 and the communication component 12, is configured to execute the computer program in the memory 10 to:

[0114] For any read instruction included in the plurality of instruction queues provided by the host side, if it is determined that the read instruction has a write instruction that needs to be associated with it, temporarily suspending the read instruction;

[0115] searching, in the plurality of instruction queues, for a target write instruction to be executed in association with the read instruction according to a specified association format;

[0116] After monitoring that the target write instruction is executed, the read instruction is restored so that the read instruction reads the data written by the target write instruction.

[0117] In an optional embodiment, when temporarily suspending the read instruction, the processor 11 may be configured to:

[0118] Dispatching the read instruction from the instruction queue where the read instruction is located to the read temporary queue;

[0119] The read instructions in the read temporary queue need to wait for a trigger condition to be met before being executed, and the trigger condition includes that a write instruction that needs to be executed in association with the read instruction has been executed.

[0120] In an optional embodiment, the processor 11 is further configured to:

[0121] Detecting whether the read instruction carries a specified tag, where the specified tag is used to indicate the presence of an instruction that needs to be associated and executed;

[0122] If it is carried, it is determined that there is a write instruction that needs to be executed in association with the read instruction;

[0123] The designated mark is added to the read instruction by the host side after determining that there is a write instruction that needs to be executed in association with the read instruction.

[0124] In an optional embodiment, when the processor 11 searches for a target write instruction to be executed in association with the read instruction in the plurality of instruction queues according to a specified association format, the following settings may be configured:

[0125] According to the specified relative position relationship, searching the instruction queue where the read instruction is located for a write instruction that meets the relative position relationship;

[0126] If the found write instruction carries the specified tag and points to the same access address as the read instruction, determining the found write instruction as the target write instruction;

[0127] The designated tag is added to the target write instruction by the host side after determining that the target write instruction needs to be executed in association with the read instruction.

[0128] In an optional embodiment, the processor 11 is further configured to:

[0129] During the execution of the target write instruction, the target data to be written is written into the memory of the storage device;

[0130] In the address mapping table, the physical address corresponding to the target data is updated to point to the address of the storage location of the target data in the memory, so as to complete the associated write instruction;

[0131] In an optional embodiment, the processor 11 is further configured to:

[0132] Asynchronously writing the target data from the memory of the storage device to the flash memory of the storage device;

[0133] After the target data is written into the flash memory of the storage device, the physical address corresponding to the target data is updated in the address mapping table to the physical address of the target data in the flash memory.

[0134] Furthermore, as shown in Figure 10 , the electronic device further includes other components such as a power supply component 13. Figure 10 schematically shows some components, which does not mean that the electronic device cannot include other components besides those shown in Figure 10 .

[0135] It is worth noting that the technical details in the above-mentioned embodiments of the electronic device can be referred to the relevant descriptions of the host side and the storage device in the aforementioned method embodiments respectively. In order to save space, they will not be repeated here, but this should not cause any loss of the protection scope of this application.

[0136] Accordingly, an embodiment of the present application further provides a computer-readable storage medium storing a computer program, which, when executed, can implement the steps that can be performed by the electronic device in the above method embodiment.

[0137] The memory in FIG10 is configured to store computer programs and can be configured to store various other data to support operations on the computing platform. Examples of such data include instructions for any application or method operating on the computing platform, contact data, phone book data, messages, pictures, videos, etc. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0138] The communication component in Figure 10 above is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G / LTE, 5G and other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0139] The power supply assembly in Figure 10 provides power to various components of the device in which the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply assembly is located.

[0140] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0141] The present application is described with reference to the flow chart and / or block diagram of the method, device (system), and computer program product according to the embodiment of the present application. It should be understood that each flow process and / or box in the flow chart and / or block diagram and the combination of the flow process and / or box in the flow chart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processing machine or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one flow chart flow or multiple flows and / or one box or multiple boxes of the block diagram.

[0142] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0143] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0144] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0145] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0146] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0147] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0148] The foregoing is an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included in the protection scope of the present application.

Claims

1. A data reading and writing method, applicable to a host end, wherein the host end is connected to a storage device, and the method comprises: In the case of monitoring a read instruction for the storage device, determining whether there is a target write instruction that needs to be executed in association with the read instruction; If so, scheduling the read instruction and the target write instruction to a target queue according to a specified association format, wherein the target queue is any one of a plurality of instruction queues for transmitting read / write instructions to the storage device; The read instruction and the target write instruction are provided to the storage device through the target queue, so that the storage device can perceive the write instruction that affects the read instruction based on the associated format and execute the read instruction after completing the corresponding write instruction.

2. The method according to claim 1, determining whether there is a target write instruction that needs to be executed in association with the read instruction, comprising: Determining the access address pointed to by the read instruction; If the access address exists in the write address record, determining the pending write instruction pointing to the access address as the target write instruction; The write address record includes an access address identified from the write instruction to be processed.

3. The method according to claim 1, scheduling the read instruction and the target write instruction into a target queue according to a specified association format, comprising: Adding a designated mark for indicating the existence of instructions to be associated and executed respectively to the read instruction and the target write instruction; The read instruction and the target write instruction are scheduled to the target queue according to the specified relative position relationship.

4. The method according to claim 3, scheduling the read instruction and the target write instruction to the target queue according to the specified relative position relationship, comprising: When the target write instruction arrives at the exit of the write queue, scheduling the target write instruction into the target queue; Determining a target placement position for the read instruction in the target queue according to the relative position relationship; Dispatching the read instruction to the target placement position in the target queue; The pending write instructions contained in the write queue are dispatched to the multiple instruction queues in a first-in-first-out order.

5. The method according to claim 4, further comprising: If the read instruction has arrived at the exit of the read queue before the target write instruction arrives at the exit of the write queue, the read instruction is scheduled to the read instruction temporary storage queue, and the read instructions contained in the read instruction temporary storage queue need to wait for triggering before being scheduled; Scheduling the read instruction to the target placement position in the target queue includes: If the read instruction is found in the read instruction temporary storage queue, triggering the scheduling of the read instruction to schedule the read instruction to the target placement position in the target queue; If the read instruction is not found in the read instruction temporary queue, extracting the read instruction from the read queue and dispatching it to the target placement position in the target queue; The to-be-processed read instructions contained in the read queue are dispatched to the multiple instruction queues in a first-in-first-out order. 6 . The method according to claim 3 , wherein the relative position relationship comprises that the read instruction is located at a subsequent placement position of the corresponding target write instruction.

7. A data reading and writing method, applicable to a storage device, wherein the storage device is connected to a host end, the method comprising: For any read instruction included in the plurality of instruction queues provided by the host, if it is determined that the read instruction has a write instruction that needs to be associated with the read instruction, the read instruction is temporarily suspended; According to a specified association format, searching the plurality of instruction queues for a target write instruction to be executed in association with the read instruction; After monitoring that the target write instruction is executed, the read instruction is restored so that the read instruction reads the data written by the target write instruction.

8. The method according to claim 7, temporarily suspending the read instruction, comprising: Dispatching the read instruction from the instruction queue where the read instruction is located to the read temporary storage queue; The read instructions in the read temporary queue need to wait for a trigger condition to be met before being executed, and the trigger condition includes that a write instruction that needs to be executed in association with the read instruction has been executed.

9. The method according to claim 7, further comprising: Detecting whether the read instruction carries a specified tag, where the specified tag is used to indicate the existence of an instruction to be associated and executed; If it is carried, it is determined that there is a write instruction that needs to be executed in association with the read instruction; The designated mark is added to the read instruction by the host after determining that there is a write instruction that needs to be executed in association with the read instruction.

10. The method according to claim 7, searching the target write instruction to be executed in association with the read instruction in the plurality of instruction queues according to a specified association format, comprising: According to the specified relative position relationship, searching the instruction queue where the read instruction is located for a write instruction that meets the relative position relationship; If the found write instruction carries the specified tag and points to the same access address as the read instruction, determining the found write instruction as the target write instruction; The designated mark is added to the target write instruction by the host after determining that the target write instruction needs to be executed in association with the read instruction.

11. The method according to claim 7, further comprising: During the execution of the target write instruction, the target data to be written is written into the memory of the storage device; In the address mapping table, the physical address corresponding to the target data is updated to an address pointing to a storage location of the target data in the memory, so as to complete the associated write instruction.

12. The method according to claim 11, further comprising: Asynchronously writing the target data from the memory of the storage device to the flash memory of the storage device; After the target data is written into the flash memory of the storage device, in the address mapping table, the physical address corresponding to the target data is updated to the physical address of the target data in the flash memory.

13. An electronic device comprising a memory, a processor and a communication component; The memory is configured to store one or more computer instructions; The processor is coupled to the memory and the communication component, and is configured to execute the one or more computer instructions for executing the data reading and writing method according to any one of claims 1-12.

14. A computer-readable storage medium storing computer instructions, which, when executed by one or more processors, causes the one or more processors to execute the data reading and writing method according to any one of claims 1 to 12.

Images