Context merge with global event and dead draw merge

Abstract

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for context merge with global event and dead draw merge. A graphics processor may detect whether each of a set of draw calls is included in a subset of dead draw calls or a subset of alive draw calls. The graphics processor may store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events and store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events.

Description

CONTEXT MERGE WITH GLOBAL EVENT AND DEAD DRAW MERGECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of Indian Patent Application Serial No. 202321061588, entitled “CONTEXT MERGE WITH GLOBAL EVENT AND DEAD DRAW MERGE” and filed on September 13, 2023, which is expressly incorporated by reference herein in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to processing systems, and more particularly, to one or more techniques for graphics processing.INTRODUCTION

[0003] Computing devices often perform graphics and / or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs are configured to execute a graphics processing pipeline that includes one or more processing stages, which operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize the GPU during execution. A display processor may be configured to convert digital information received from a CPU to analog values and may issue commands to a display panel for displaying the visual content. A device that provides content for visual presentation on a display may utilize a CPU, a GPU, and / or a display processor.

[0004] Currently, there is a need for improved graphics processing. For instance, context slots may be groups of resources that include context registers, constant random access memory (RAM), and other resources in shader system. Global events and dead draws may occupy context slots in various GPU blocks, including a shader system.Accordingly, there is a need for improving resource utilization efficiency with regard to context slots in a shader system.BRIEF SUMMARY

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006] In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus includes a memory; and at least one processor coupled to the memory and, based at least in part on information stored in the memory, the at least one processor is configured to: obtain information regarding at least one of a set of draw calls or a set of global events, where the set of draw calls and the set of global events are associated with the graphics processing or compute processing. The apparatus may be further configured to detect a subset of dead draw calls and a subset of alive draw calls in the set of draw calls. The apparatus may be further configured to store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events. The apparatus may be further configured to store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events. The apparatus may be further configured to process a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events.

[0007] To the accomplishment of the foregoing and related ends, the one or more aspects include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a block diagram that illustrates an example content generation system in accordance with one or more techniques of this disclosure.

[0009] FIG. 2 illustrates an example graphics processor in accordance with one or more techniques of this disclosure.

[0010] FIG. 3 illustrates an example image or surface in accordance with one or more techniques of this disclosure.

[0011] FIG. 4 illustrates a diagram corresponding to an example technique for providing shared constants in accordance with one or more techniques of this disclosure.

[0012] FIG. 5 is a diagram illustrating an example workflow for processing draw call(s) and global event(s) in accordance with one or more techniques of this disclosure.

[0013] FIG. 6 is a diagram illustrating context slots for storing draw call(s) and global event(s) in accordance with one or more techniques of this disclosure.

[0014] FIG. 7 is a communication flow diagram illustrating example communications between a graphics processor, a CPU, and a memory in accordance with one or more techniques of this disclosure.

[0015] FIG. 8 is a flowchart of an example method of graphics processing in accordance with one or more techniques of this disclosure.

[0016] FIG. 9 is a flowchart of an example method of graphics processing in accordance with one or more techniques of this disclosure.DETAILED DESCRIPTION

[0017] Various aspects of systems, apparatuses, computer program products, and methods are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number ofthe aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.

[0018] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, processing systems, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description. The detailed description and drawings are merely illustrative of this disclosure rather than limiting, the scope of this disclosure being defined by the appended claims and equivalents thereof.

[0019] Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, and the like (collectively referred to as “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0020] By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems-on-chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in theprocessing system may execute software. Software can be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

[0021] The term application may refer to software. As described herein, one or more techniques may refer to an application (e.g., software) being configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., on-chip memory of a processor, system memory, or any other memory). Hardware described herein, such as a processor may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware may access the code from a memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or subcomponents of a single component.

[0022] In one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.

[0023] As used herein, instances of the term “content” may refer to “graphical content,” an “image,” etc., regardless of whether the terms are used as an adjective, noun, or other parts of speech. In some examples, the term “graphical content,” as used herein, mayrefer to a content produced by one or more processes of a graphics processing pipeline. In further examples, the term “graphical content,” as used herein, may refer to a content produced by a processing unit configured to perform graphics processing. In still further examples, as used herein, the term “graphical content” may refer to a content produced by a graphics processing unit.

[0024] Context slots may be groups of resources that include context registers, constant random access memory (RAM), and other resources in shader system. Global events and dead draws may occupy context slots in various GPU blocks, including a shader system. Accordingly, there is a need for improving resource utilization efficiency with regard to context slots in a shader system. Aspects provided herein may enable merge of dead draw call(s) and global event(s) in a context slot for a shader system to decrease the total amount of resources used for processing a workload at the shader. Some aspects may be based on accumulate and merge all consecutive global events and dead draw calls with a subsequent alive draw so that one alive draw call, one or more global events, and one or more dead draw calls would share one fragment shader context slot in the shader system. The dead draw calls may be identified from the full draw rejection information from various units, such as from the low-resolution Z (LRZ) or other units, and this information can be fed to the high level sequencer (HLSQ) where a table may be built to be used to skip state programming and to reuse the fragment shader context slot in the shader processor (SP). The vertex fetcher (VFD) may also be used to provide dead or alive information to the SP vertex shader context slot.

[0025] The examples describe herein may refer to a use and functionality of a graphics processing unit (GPU). As used herein, a GPU can be any type of graphics processor, and a graphics processor can be any type of processor that is designed or configured to process graphics content. For example, a graphics processor or GPU can be a specialized electronic circuit that is designed for processing graphics content. As an additional example, a graphics processor or GPU can be a general purpose processor that is configured to process graphics content.

[0026] FIG. 1 is a block diagram that illustrates an example content generation system 100 configured to implement one or more techniques of this disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of aSOC. The device 104 may include one or more components configured to perform one or more techniques of this disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include a number of components (e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131). Display(s) 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays, which may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentment thereon. In other examples, the first and second display may receive the same frames for presentment thereon. In further examples, the results of the graphics processing may not be displayed on the device, e.g., the first display and the second display may not receive any frames for presentment thereon. Instead, the frames or graphics processing results may be transferred to another device. In some aspects, this may be referred to as split-rendering.

[0027] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing using a graphics processing pipeline 107. The content encoder / decoder 122 may include an internal memory 123. In some examples, the device 104 may include a processor, which may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before the frames are displayed by the one or more displays 131. While the processor in the example content generation system 100 is configured as a display processor 127, it should be understood that the display processor 127 is one example of the processor and that other types of processors, controllers, etc., may be used as substitute for the display processor 127. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, anaugmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0028] Memory external to the processing unit 120 and the content encoder / decoder 122, such as system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to external memory, such as the system memory 124. The processing unit 120 may be communicatively coupled to the system memory 124 over a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the internal memory 121 over the bus or via a different connection.

[0029] The content encoder / decoder 122 may be configured to receive graphical content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store received encoded or decoded graphical content. The content encoder / decoder 122 may be configured to receive encoded or decoded graphical content, e.g., from the system memory 124 and / or the communication interface 126, in the form of encoded pixel data. The content encoder / decoder 122 may be configured to encode or decode any graphical content.

[0030] The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or the system memory 124 may include RAM, static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable ROM (EPROM), EEPROM, flash memory, a magnetic data media or an optical storage media, or any other type of memory. The internal memory 121 or the system memory 124 may be a non-transitory storage medium according to some examples. The term “non- transitory” may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that internal memory 121 or the system memory 124 is non-movable or that its contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.

[0031] The processing unit 120 may be a CPU, a GPU, GPGPU, or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into a motherboard of the device 104. In further examples, the processing unit 120 may be present on a graphics card that is installedin a port of the motherboard of the device 104, or may be otherwise incorporated within a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, ASICs, FPGAs, arithmetic logic units (ALUs), DSPs, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 121, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

[0032] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into a motherboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the content encoder / decoder 122 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 123, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

[0033] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information, e.g., eye or head position information, rendering commands, and / or location information, from another device. The transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may beconfigured to transmit information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving function and / or transmitting function described herein with respect to the device 104.

[0034] Referring again to FIG. 1, in certain aspects, the processing unit 120 may include a global event and dead draw merger 198 configured to obtain information regarding at least one of a set of draw calls or a set of global events, where the set of draw calls and the set of global events are associated with the graphics processing or compute processing. In some aspects, the global event and dead draw merger 198 may be configured to detect a subset of dead draw calls and a subset of alive draw calls in the set of draw calls. In some aspects, the global event and dead draw merger 198 may be configured to store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events. In some aspects, the global event and dead draw merger 198 may be configured to store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events. In some aspects, the global event and dead draw merger 198 may be configured to process a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events. Although the following description may be focused on graphics processing, the concepts described herein may be applicable to other similar processing techniques.

[0035] A device, such as the device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer such as a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device such as a portable video game device or a personal digital assistant (PDA), a wearable computing device such as a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-vehiclecomputer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein may be described as performed by a particular component (e.g., a GPU) but in other embodiments, may be performed using other components (e.g., a CPU) consistent with the disclosed embodiments.

[0036] Graphics processors can process multiple types of data or data packets in a GPU pipeline. For instance, in some aspects, a graphics processor can process two types of data or data packets, e.g., context register packets and draw call data. A context register packet can be a set of global state information, e.g., information regarding a global register, shading program, or constant data, which can regulate how a graphics context will be processed. For example, context register packets can include information regarding a color format. In some aspects of context register packets, there can be a bit or bits that indicate which workload belongs to a context register. Also, there can be multiple functions or programming running at the same time and / or in parallel. For example, functions or programming can describe a certain operation, e.g., the color mode or color format. Accordingly, a context register can define multiple states of a graphics processor.

[0037] Context states can be utilized to determine how an individual processing unit functions, e.g., a VFD, a vertex shader (VS), a shader processor, or a geometry processor, and / or in what mode the processing unit functions. In order to do so, graphics processors can use context registers and programming data. In some aspects, a graphics processor can generate a workload, e.g., a vertex or pixel workload, in the pipeline based on the context register definition of a mode or state. Certain processing units, e.g., a VFD, can use these states to determine certain functions, e.g., how a vertex is assembled. As these modes or states can change, graphics processors may need to change the corresponding context. Additionally, the workload that corresponds to the mode or state may follow the changing mode or state.

[0038] FIG. 2 illustrates an example graphics processor 200 in accordance with one or more techniques of this disclosure. As shown in FIG. 2, graphics processor 200 includes command processor (CP) 210, draw call packets 212, VFD 220, VS 222, vertex cache (VPC) 224, triangle setup engine (TSE) 226, rasterizer (RAS) 228, Z process engine (ZPE) 230, pixel interpolator (PI) 232, fragment shader (FS) 234, render backend (RB) 236, L2 cache (UCHE) 238, and system memory 240. Although FIG. 2 displays that graphics processor 200 includes processing units 220-238, graphics processor 200can include a number of additional processing units. Additionally, processing units 220-238 are merely an example and any combination or order of processing units can be used by graphics processors according to the present disclosure. Graphics processor 200 also includes command buffer 250, context register packets 260, and context states 261.

[0039] As shown in FIG. 2, a graphics processor can utilize a CP, e.g., CP 210, or hardware accelerator to parse a command buffer into context register packets, e.g., context register packets 260, and / or draw call data packets, e.g., draw call packets 212. The CP 210 can then send the context register packets 260 or draw call packets 212 through separate paths to the processing units or blocks in the graphics processor. Further, the command buffer 250 can alternate different states of context registers and draw calls. For example, a command buffer can simultaneously store the following information: context register of context N, draw call(s) of context N, context register of context N+l, and draw call(s) of context N+l.

[0040] Graphics processors (e.g., GPUs) can render images in a variety of different ways. In some instances, graphics processors can render an image using direct rendering and / or tiled rendering. In tiled rendering GPUs, an image can be divided or separated into different sections or tiles. After the division of the image, each section or tile can be rendered separately. Tiled rendering GPUs can divide computer graphics images into a grid format, such that each portion of the grid, i.e., a tile, is separately rendered. In some aspects of tiled rendering, during a binning pass, an image can be divided into different bins or tiles. In some aspects, during the binning pass, a visibility stream can be constructed where visible primitives or draw calls can be identified. A rendering pass may be performed after the binning pass. In contrast to tiled rendering, direct rendering does not divide the frame into smaller bins or tiles. Rather, in direct rendering, the entire frame is rendered at a single time (i.e., without a binning pass). Additionally, some types of graphics processors can allow for both tiled rendering and direct rendering (e.g., flex rendering).

[0041] In some aspects, graphics processors can apply the drawing or rendering process to different bins or tiles. For instance, a graphics processor can render to one bin, and perform all the draws for the primitives or pixels in the bin. During the process of rendering to a bin, the render targets can be located in GPU internal memory (GMEM). In some instances, after rendering to one bin, the content of the render targets can be moved to a system memory and the GMEM can be freed for renderingthe next bin. Additionally, a graphics processor can render to another bin, and perform the draws for the primitives or pixels in that bin. Therefore, in some aspects, there might be a small number of bins, e.g., four bins, that cover all of the draws in one surface. Further, graphics processors can cycle through all of the draws in one bin, but perform the draws for the draw calls that are visible, i.e., draw calls that include visible geometry. In some aspects, a visibility stream can be generated, e.g., in a binning pass, to determine the visibility information of each primitive in an image or scene. For instance, this visibility stream can identify whether a certain primitive is visible or not. In some aspects, this information can be used to remove primitives that are not visible so that the non-visible primitives are not rendered, e.g., in the rendering pass. Also, at least some of the primitives that are identified as visible can be rendered in the rendering pass.

[0042] In some aspects of tiled rendering, there can be multiple processing phases or passes. For instance, the rendering can be performed in two passes, e.g., a binning, a visibility or bin-visibility pass and a rendering or bin-rendering pass. During a visibility pass, a graphics processor can input a rendering workload, record the positions of the primitives or triangles, and then determine which primitives or triangles fall into which bin or area. In some aspects of a visibility pass, graphics processors can also identify or mark the visibility of each primitive or triangle in a visibility stream. During a rendering pass, a graphics processor can input the visibility stream and process one bin or area at a time. In some aspects, the visibility stream can be analyzed to determine which primitives, or vertices of primitives, are visible or not visible. As such, the primitives, or vertices of primitives, that are visible may be processed. By doing so, graphics processors can reduce the unnecessary workload of processing or rendering primitives or triangles that are not visible.

[0043] In some aspects, during a visibility pass, certain types of primitive geometry, e.g., position-only geometry, may be processed. Additionally, depending on the position or location of the primitives or triangles, the primitives may be sorted into different bins or areas. In some instances, sorting primitives or triangles into different bins may be performed by determining visibility information for these primitives or triangles. For example, graphics processors may determine or write visibility information of each primitive in each bin or area, e.g., in a system memory. This visibility information can be used to determine or generate a visibility stream. In a rendering pass, the primitives in each bin can be rendered separately. In these instances, thevisibility stream can be fetched from memory and used to remove primitives which are not visible for that bin.

[0044] Some aspects of graphics processors or GPU architectures can provide a number of different options for rendering, e.g., software rendering and hardware rendering. In software rendering, a driver or CPU can replicate an entire frame geometry by processing each view one time. Additionally, some different states may be changed depending on the view. As such, in software rendering, the software can replicate the entire workload by changing some states that may be utilized to render for each viewpoint in an image. In certain aspects, as graphics processors may be submitting the same workload multiple times for each viewpoint in an image, there may be an increased amount of overhead. In hardware rendering, the hardware or GPU may be responsible for replicating or processing the geometry for each viewpoint in an image. Accordingly, the hardware can manage the replication or processing of the primitives or triangles for each viewpoint in an image.

[0045] FIG. 3 illustrates image or surface 300, including multiple primitives divided into multiple bins in accordance with one or more techniques of this disclosure. As shown in FIG. 3, image or surface 300 includes area 302, which includes primitives 321, 322, 323, and 324. The primitives 321, 322, 323, and 324 are divided or placed into different bins, e.g., bins 310, 311, 312, 313, 314, and 315. FIG. 3 illustrates an example of tiled rendering using multiple viewpoints for the primitives 321-324. For instance, primitives 321-324 are in first viewpoint 350 and second viewpoint 351. As such, the graphics processor processing or rendering the image or surface 300 including area 302 can utilize multiple viewpoints or multi -view rendering.

[0046] A primitive may also be referred to as a “matrix multiplication compute kernel” or “kernel” which may map one or more data outputs to a fiber, which represent a basic unit of a “wave” (sometimes referred to as a “warp”). A “chunk” of data outputs may map to a group of fibers, which may represent a wave (or warp). One or more waves may represent a workgroup, which represents a basic compute workload unit. The term “workload” may refer to a set of one or more waves. In some examples, one input matrix, both input matrices, and / or the output matrix generated by performing the matrix multiplication may be large and be greater in size than resources available at the streaming processor. In some such examples, one or more of the input matrices and / or the output matrix may be split into slices (or “chunks”) to fit into a compute kernel workgroup. In some examples, the size of the compute kernel workgroup maybe based on physical resources of the streaming processor. For example, the size of the compute kernel workgroup may depend on a size of a general purpose register of the streaming processor, a size of a local buffer of the streaming processor, and / or the resources associated with a fiber. A compute kernel associated with a dead draw call may be referred to as “a dead compute kernel.”

[0047] As indicated herein, graphics processors or GPUs can use a tiled rendering architecture to reduce power consumption or save memory bandwidth. As further stated above, this rendering method can divide the scene into multiple bins, as well as include a visibility pass that identifies the triangles that are visible in each bin. Thus, in tiled rendering, a full screen can be divided into multiple bins or tiles. The scene can then be rendered multiple times, e.g., one or more times for each bin.

[0048] In aspects of graphics rendering, some graphics applications may render to a single target, i.e., a render target, one or more times. For instance, in graphics rendering, a frame buffer on a system memory may be updated multiple times. The frame buffer can be a portion of memory or random access memory (RAM), e.g., containing a bitmap or storage, to help store display data for a GPU. The frame buffer can also be a memory buffer containing a complete frame of data. Additionally, the frame buffer can be a logic buffer. In some aspects, updating the frame buffer can be performed in bin or tile rendering, where, as discussed above, a surface is divided into multiple bins or tiles and then each bin or tile can be separately rendered. Further, in tiled rendering, the frame buffer can be partitioned into multiple bins or tiles.

[0049] As indicated herein, in some aspects, such as in bin or tiled rendering architecture, frame buffers can have data stored or written to them repeatedly, e.g., when rendering from different types of memory. This can be referred to as resolving and unresolving the frame buffer or system memory. For example, when storing or writing to one frame buffer and then switching to another frame buffer, the data or information on the frame buffer can be resolved from the GMEM at the GPU to the system memory, i.e., memory in the double data rate (DDR) RAM or dynamic RAM (DRAM).

[0050] In some aspects, the system memory can also be system-on-chip (SoC) memory or another chip-based memory to store data or information, e.g., on a device or smart phone. The system memory can also be physical data storage that is shared by the CPU and / or the GPU. In some aspects, the system memory can be a DRAM chip, e.g., on a device or smart phone. Accordingly, SoC memory can be a chip-based manner in which to store data.

[0051] In some aspects, the GMEM can be on-chip memory at the graphics processor, which can be implemented by static RAM (SRAM). Additionally, GMEM can be stored on a device, e.g., a smart phone. As indicated herein, data or information can be transferred between the system memory or DRAM and the GMEM, e.g., at a device. In some aspects, the system memory or DRAM can be at the CPU or GPU. Additionally, data can be stored at the DDR or DRAM. In some aspects, such as in bin or tiled rendering, a small portion of the memory can be stored at the graphics processor, e.g., at the GMEM. In some instances, storing data at the GMEM may utilize a larger processing workload and / or consume more power compared to storing data at the frame buffer or system memory.

[0052] As described herein, graphics processors can use a tiled rendering architecture to reduce power consumption or save memory bandwidth. As further stated above, this rendering method can divide the scene into multiple bins, as well as include a visibility pass that identifies the triangles that are visible in each bin. Thus, in tiled rendering, a full screen can be divided into multiple bins or tiles. The scene can then be rendered multiple times, e.g., once for each bin. As indicated above, graphics processors can cycle through each draw call in one bin and perform the draw calls that are visible. As used herein, the term “draw call” may refer to a process in which a CPU submits data to the graphics processor(s) and then issue commands to cause the graphics processors to render an object. In some aspects, draw calls that fall into a given bin may be considered to be and may be referred to as “live draw calls” or “alive draw calls,” while draw calls that fall outside the bin may be considered to be and may be referred to as “dead draw calls.”

[0053] A mechanism may be provided to back-pressure the GPU hardware pipeline’s next batch in a cluster, such as over the time that the performance counters of all blocks in that cluster are not read out and sent to a memory interface for a current batch. In order to do so, a driver may be used to provide a clear breakpoint in the command stream between two workloads, for which it may scope the performance. These breakpoints may be referred to as “global events,” which may be inserted after each draw call or stage. These global events may already be existing context-done for draw calls and may be newly introduced soft-events for stages. Additionally, the workloads may be draw calls, as well as different types of stages, e.g., visibility pass, resolve pass, etc.

[0054] As an example, a single batch per cluster may be allowed by a command processor (CP) to be executed at one time. For this time, all blocks in a cluster may not have completed a batch and a debug controller (DBGC) may not have read out the performance counters of these blocks from a register backbone management (RBBM). Also, the CP may not send the next batch programming to that cluster’s blocks. GPU blocks may not start on a next batch execution until the complete programming is received by that block from the CP.

[0055] After finishing the workload, each block in the GPU hardware pipeline may send a copy of the global event at the end of a workload (e.g., context-done for draw calls and soft-events for stages) to the DBGC indicating that a workload batch is completed by this block and the DBGC may start reading performance counters associated with this block from the RBBM. The DBGC may make use of its existing trace buffer to buffer up the performance counters read from the RBBM for a block before sending them to a memory interface or to a trace bus.

[0056] After the DBGC reads all the performance counters associated with a block from the RBBM, it may send an indication to the CP, which states the DBGC completed reading all the performance counters for a respective block in a cluster. After the CP receives an indication for all blocks in a cluster from the DBGC, it may unblock the next batch of programming for that cluster of blocks. This may continually occur for all batches.

[0057] As used herein, the term “context slot” refers to a group of resources associated with a shader that includes context register, constant RAM, or other resources associated with the shader. FIG. 4 illustrates a diagram 400 corresponding to an example technique for providing shared constants in accordance with one or more techniques of this disclosure. In examples, shader processing may be associated with a shader code corresponding to GPU instructions, resources (e.g., textures, surfaces, etc.) that may receive data for rendering a frame, and / or constant data that may be loaded by an application.

[0058] Constant data (e.g., cl-c8) may be constant across an entire draw call and may utilize a block of dedicated constant RAM 410. While a same shader may be executed from draw call to draw call to render a portion of a frame, constants 1-8 indicated via the constant data cl-c8 may be changed for rendering different items / features within the frame, as the constants 1-8 may indicate, e.g., a relationship between lighting and the items / features within the frame. In some aspects, new constant data may be loaded tothe constant RAM 410 for each draw call. For example, a driver may be configured to update the constant data cl-c8 used for each of the draw calls / shaders. The constants 1-8 may be stored in a constant buffer (e.g., constant RAM 410) and the shader may index to the constant buffer to load the constants 1-8. In some cases, constants 1-8 may be stored in multiple constant buffers. By generating a constant buffer, updates to the constants 1-8 may be performed on the CPU, since the driver may be configured to perform the updates.

[0059] Some graphics application program interfaces (APIs) may be configured to generate shared constants (e.g., Valuel and Value2 in the diagram 400) that may be shared across different shader stages. For example, a pixel shader configured to color pixels based on textures, lighting algorithms, etc. may have shared constants with a vertex shader configured to rasterize primitives or triangles in a frame that includes the pixels. Shared constants may also be referred to as root constants or push constants, which may be pushed directly from the application 402 to the graphics processor with a low overhead. In some examples, the application 402 may include instructions such as SetSharedConstant (location A, Valuel) and SetSharedConstant (location D, Value2) to indicate shared constants using the register data A-F. A shader foobar (foo) 404 from the application 402 may reference the shared constants based on instructions such as rO = rl + sharedConstantA and r2 = r3 * sharedConstantD. After a first draw call is executed for the application 402 based on the instructions, the application 402 may change an indication of the shared constants (e.g., SetSharedConstant (location A, Valuel) may be changed to SetSharedConstant (location A, Value3)) and a second draw call may be executed for the application 402.

[0060] Depending on a configuration of the graphics API, shared constants may be 32-bit constants that may range in number from 32 to 128 (e.g., compared to regular / unshared constants that may range in number up to 512 for some hardware configurations). As an example, some shaders may utilize more than 512 constants.

[0061] The context registers 406 may be similar to pipeline registers for a draw state, since the context registers 406 may be pipelined via GPU hardware. After the shared constants are loaded into context registers 406 (e.g., register A and register D), the information may remain the same unless / until the context registers 406 are updated by the driver.

[0062] The shader hardware may also include a HLSQ that prepares information for the SP to execute. The HLSQ may execute an early preamble / preamble shader, which maybe a portion of shader code that is executed before a main portion of the shader is executed. The preamble shader may include a store shared constant (STSC) instruction that may copy the shared constants (e.g., Valuel in register A and Value2 in register D) from the context registers 406 to the constant RAM 410 (e.g., constant 2 and constant 3). In examples, a shader foo preamble 408 may be executed on the shader hardware based on STSC instructions such as movToConstRam (sharedConstantRegA, constantRam2) and movToConstRam (sharedConstantRegD, constantRam3).

[0063] The preamble shader may not be configured to determine substantive information / values indicated by the shared constants. Rather, the preamble shader may determine that certain registers, such as register A and register D, include shared constants that are associated with information for executing a particular draw call. Thus, the STSC instruction of the preamble shader may be executed to copy the shared constants included in the certain registers into the constant RAM 410. Other instructions in the preamble shader may include loading the regular / unshared constant data into the constant RAM 410. The constant RAM 410 may serve as a cache that is setup before the SP executes the main shader. Since the shader may be configuring shared constants for a next invocation of the shader while a current invocation of the shader is executing, pipelining may be performed so that the current invocation of the shader is not impacted by configuring the next invocation of the shader.

[0064] The HLSQ that moves data from the context registers 406 to the constant store / constant RAM 410 may execute the preamble shader once before every draw call. Constant data cl-c8 may be loaded into the constant RAM 410 for a particular draw call and, on a next draw call, constant data corresponding to the next draw call may be loaded into the constant RAM 410. The preamble shader may copy the register data A-F from the context registers 406 into the constant RAM 410 based on the STSC instruction.

[0065] A shader compiler may be configured to determine which shared constants are to be used by the shader and may move the determined shared constants from the register data A-F into the constant RAM 410. After the register data A-F is loaded into constant storage for the graphics processor, shader execution may be performed as usual regardless of whether the constants 1-8 are shared constants or regular constants. That is, after a shader constant state is loaded in the shader constant RAM, the shader constant state may be moved to working constant RAM similar to other constant dataused for shader execution. By allowing the shader compiler to determine the shared constants that may be used for shader execution, such constants may be loaded on an individual basis without having to load an entire block of shared constants.

[0066] FIG. 5 is a diagram 500 illustrating an example workflow for processing draw call(s) and global event(s) in accordance with one or more techniques of this disclosure.

[0067] As illustrated in FIG. 5, after obtaining a set of draw calls, a first depth buffer, such as a low-resolution Z (LRZ) module 502, may process the set of draw calls and detect alive draw calls that fall inside a bin and dead draw calls that fall outside the bin. A depth buffer may also be referred to as a Z-buffer and may be a type of data buffer to represent depth information of objects in a three dimensional (3D) space from a particular perspective. LRZ may be a procedure where the LRZ module 502 may store depth data associated with a block of pixels rather than for each pixel of each of a plurality of tiles using a low resolution buffer. The low resolution buffer may be a two-dimensional buffer with a plurality of storage locations. Each storage location in the low resolution buffer may correspond to a block of pixels. In some examples, the number of storage locations within the low resolution buffer may be fewer than the number of pixels. An LRZ data may be depth data for a block of pixels (e.g., a 2^2 block of pixels) that contains the backmost depth value for the given block of pixels. A tile may be associated with one or more LRZ data. For example, given a tile that is an 8x8 block of pixel, the tile may include 16 LRZ data that are each associated with a given 2x2 pixel block of the tile, and each of the 16 LRZ data may contain the backmost depth value for the associated 2x2 pixel block of the tile. The LRZ module 502 may detect dead draw calls that fall outside the bin and do not need to be executed / processed by the SP 512 and alive draw calls that fall inside the bin. The result of the detection may be transmitted to a HLSQ data parsing (DP) unit 508 or a shader processor control module (SPCM) 510 that may be in control of the SP 512 so that the result of the detection may be stored. The result of the detection may also be transmitted to an early-Z module 504.

[0068] The HLSQ state management block 524 may be responsible for managing context slots so that the context slots may be used for wave construction (e.g., by the SP 512 and the SPCM 510). The HLSQ state management block 524 may receive global event information and associated context information from the CP 520 and may provide state programming information regarding graphics processor state programming commands. As an example, a graphics processor may execute various commands,such as commands issued to the graphics processor by an application processor (e.g., a CPU). The commands that may be executed by a graphics processor may include, e.g., draw call commands, graphics processor state programming commands, memory transfer commands, general-purpose computing commands, kernel execution commands, or the like.

[0069] After processing the set of draw calls using the LRZ module 502, the set of draw calls may be further processed by an early-Z module 504. The early-Z module 504 may use early-Z algorithm to perform an early depth check to remove overdrawn fragments before the graphics processor wastes effort running the shaders for them. The early-Z module 504 may test a fragment or a tile (group of fragments) against the depth buffer (before a fragment shader or an SP 512). The early-Z module 504 may be able to detect dead draw calls that fall outside the bin and do not need to be executed / processed by the SP 512 and alive draw calls that fall inside the bin.

[0070] The output of the early-Z module 504, which may include final dead or alive information with respect to the draw calls, may be fed into a rendering backend (RB) sampler 506, which may be used for pixel operations. In some aspects, the RB sampler 506 may send the workload(s) and respective red (R) green (G) blue (B) (RGB) information regarding the pixels and positions to the HLSQ DP, the HLSQ may respond to the sent workload(s) and construct the workload(s) into waves that may be transmitted to the SP 512. The SP 512 may process the waves and send them to the RB color (RB-C) or late-Z module 514 configured to perform blending and transmit information to the frame buffer.

[0071] In some aspects, the output of the early-Z module 504, which may include final dead or alive information with respect to the draw calls, may be fed into the HLSQ DP unit 508 or the SPCM 510. Based on the final dead or alive information, the HLSQ DP unit 508 or the SPCM 510 may store the dead draw call(s), the alive draw call(s), and the global event information in various context slots (e.g., in constant RAM associated with the various context slots) based on having each context slot storing information for an alive draw call, one or more dead draw calls, and one or more global event(s). Information regarding various dead draw call(s), alive draw call(s), and global event(s), may be fed into the HLSQ DP unit 508 or the SPCM 510 sequentially and the information regarding various dead draw call(s), alive draw call(s), and global event(s) may be stored in one or more context slots sequentially based on having eachcontext slot storing information for an alive draw call, one or more dead draw calls, and one or more global event(s).

[0072] For example, in some aspects, the HLSQ DP unit 508 or the SPCM 510 may consider a first context slot as full after storing a first alive draw call in the first context. In some aspects, draw calls or global events after the first alive draw call may be stored in a subsequent context slot. In some aspects, the HLSQ DP unit 508 or the SPCM 510 consider a context slot as not full before storing an alive draw call in the context slot. Therefore, the HLSQ DP unit 508 or the SPCM 510 may keep storing information regarding dead draw calls and global event in the context slot until the HLSQ DP unit 508 or the SPCM 510 processes an alive draw call and store information regarding the alive draw call in the context slot.

[0073] In some aspects, instead of the HLSQ DP unit 508 or the SPCM 510, the output of the early-Z module 504, which may include final dead or alive information with respect to the draw calls, may be fed into the HLSQ state management block 524. Because the HLSQ state management block 524 may also receive global event information and associated context information from the CP 520, in some aspects, the HLSQ state management block 524 may store the dead draw call(s), the alive draw call(s), and the global event information. For example, in some aspects, the HLSQ state management block 524 may consider a first context slot as full after storing a first alive draw call in the first context. In some aspects, draw calls or global events after the first alive draw call may be stored in a subsequent context slot. In some aspects, the HLSQ state management block 524 may consider a context slot as not full before storing an alive draw call in the context slot. Therefore, the HLSQ state management block 524 may keep storing information regarding dead draw calls and global event in the context slot until the HLSQ state management block 524 processes (e.g., received information regarding) an alive draw call and store information regarding the alive draw call in the context slot.

[0074] FIG. 6 is a diagram 600 illustrating context slots for storing draw call(s) and global event(s) in accordance with one or more techniques of this disclosure. As illustrated in FIG. 6, for a first SP, SP0 602, information 606A regarding a first draw call may be indicating an alive draw call and may be stored in (e.g., in constant RAM associated with the first context slot 604A) a first context slot 604A associated with the SP0 602. After storing the information 606A regarding the alive draw call in the first context slot 604A, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state managementblock 524 may consider the first context slot 604A as full and store subsequent information in different context slot(s).

[0075] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive global event information 608 after receiving information 606A regarding an alive draw call and may store the global event information 608 in a second context slot 604B associated with the SP0 602 (e.g., in constant RAM associated with the second context slot 604B). Because the second context slot 604B has not stored information regarding any alive draw call after storing the global event information 608, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may continue to store information in the second context slot 604B.

[0076] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive information 606B regarding a dead draw call after receiving the global event information 608. The SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may store the information 606B regarding a dead draw call in the second context slot 604B. Because the second context slot 604B has not stored information regarding any alive draw call after storing the information 606B regarding a dead draw call, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may continue to store information in the second context slot 604B.

[0077] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive information 606C regarding a dead draw call after receiving the information 606B regarding a dead draw call. The SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may store the information 606C regarding a dead draw call in the second context slot 604B. Because the second context slot 604B has not stored information regarding any alive draw call after storing the information 606C regarding a dead draw call, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may continue to store information in the second context slot 604B.

[0078] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive information 606D regarding an alive draw call after receiving the information 606C regarding a dead draw call. The SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may store the information 606D regarding an alive draw call in the second context slot 604B.Because the second context slot 604B has stored information regarding an alive draw call after storing the 606D regarding an alive draw call, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may not continue to store information in the second context slot 604B.

[0079] As illustrated in FIG. 6, for a second SP, SP1 612, information 616A regarding a first draw call may be indicating an alive draw call and may be stored in (e.g., in constant RAM associated with the first context slot 614A) a first context slot 614A associated with the SP1 612. After storing the information 616A regarding the alive draw call in the first context slot 614A, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may consider the first context slot 614A as full and store subsequent information in different context slot(s).

[0080] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive global event information 618 after receiving information 616A and may store the global event information 618 in a second context slot 614B associated with the SP1 612 (e.g., in constant RAM associated with the second context slot 614B). Because the second context slot 614B has not stored information regarding any alive draw call after storing the global event information 618, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may continue to store information in the second context slot 614B.

[0081] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive information 616B regarding an alive draw call after receiving the global event information 618. The SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may store the information 616B regarding the alive draw call in the second context slot 614B. After storing the information 616B regarding the alive draw call in the second context slot 614B, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may consider the second context slot 614B as full and may not store further draw call or global event information in the second context slot 614B.

[0082] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive information 616C regarding a dead draw call after receiving the information 616B regarding the alive draw call. The SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may store the information 616C regarding a dead draw call in a third context slot 614C associated with SP1 612. Because the third context slot 614C has not stored informationregarding any alive draw call after storing the information 616C regarding a dead draw call, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may continue to store information in the third context slot 614C.

[0083] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive information 616D regarding a dead draw call after receiving the information 616C regarding a dead draw call. The SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may store the information 616D regarding a dead draw call in the third context slot 614C associated with SP1 612. Because the third context slot 614C has not stored information regarding any alive draw call after storing the information 616D regarding a dead draw call, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may continue to store information in the third context slot 614C.

[0084] As illustrated in FIG. 6, for a third SP, SP2 622, information 626A regarding a first draw call may be indicating an alive draw call and may be stored in a first context slot 624A associated with the SP2 622. After storing the information 626A regarding an alive draw call in the first context slot 624A, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may consider the first context slot 624A as full and store subsequent information in different context slot(s).

[0085] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive global event information 628 after receiving information 626A and may store the global event information 628 in a second context slot 624B associated with the SP2 622 (e.g., in constant RAM associated with the second context slot 624B). Because the second context slot 624B has not stored information regarding any alive draw call after storing the global event information 628 in a second context slot 624B, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may continue to store information in the second context slot 624B.

[0086] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive information 626B regarding a dead draw call after receiving the global event information 628. The SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may store the information 626B regarding the dead draw call in the second context slot 624B. Because the second context slot 624B has not stored information regarding any alive draw call after storing the information 626B regarding a dead draw call in a second context slot 604B,the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may continue to store information in the second context slot 624B.

[0087] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive information 626C regarding an alive draw call after receiving the information 626B regarding a dead draw call. The SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may store the information 626C regarding the alive draw call in the second context slot 624B. After storing the information 626C regarding the alive draw call in the second context slot 624B, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may consider the second context slot 624B as full and may not store further draw call or global event information in the second context slot 624B.

[0088] In some aspects, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may receive information 626D regarding a dead draw call after receiving the information 626C regarding the alive draw call. The SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may store the information 626D regarding a dead draw call in a third context slot 624C associated with SP2 622. Because the third context slot 624C has not stored information regarding any alive draw call after storing the information 626D regarding a dead draw call, the SPCM 510, the HLSQ DP unit 508, or the HLSQ state management block 524 may continue to store information in the third context slot 624C.

[0089] FIG. 7 is a communication flow diagram 700 illustrating example communications between a graphics processor, a CPU, and a memory in accordance with one or more techniques of this disclosure.

[0090] As shown in FIG. 7, the diagram 700 includes example communications between a graphics processor 702 (or other graphics processor, such as a GPU), a CPU 704 (or other central processor) or another graphics processor component, and memory 706 (e.g., GMEM or SYSMEM), in accordance with one or more techniques of this disclosure.

[0091] At 710, the graphics processor 702 may obtain (e.g., from the CPU 704) an indication 712 of at least one of a set of draw calls or a set of global events, where the set of draw calls and the set of global events are associated with the graphics processing or compute processing. In some aspects, the set of draw calls and the set of global events are configured for execution by an SP at a GPU, such as the graphics processor 702.

[0092] At 720, the graphics processor 702 may detect a subset of dead draw calls and a subset of alive draw calls in the set of draw calls. In some aspects, to detect the subset of dead draw calls and the subset of alive draw calls in the set of draw calls, the graphics processor 702 may perform, at a first graphics component, a first detection of whether each of the set of draw calls is the dead draw call or the alive draw call and perform, at a second graphics component, a second detection of whether each of the set of draw calls is the dead draw call or the alive draw call. In some aspects, the first graphics component is a first depth buffer and the second graphics component is a second depth buffer. In some aspects, the first depth buffer is a low resolution Z buffer and the second depth buffer is an early Z buffer. In some aspects, the set of draw calls is a set of compute draw calls, and to detect the subset of dead draw calls and the subset of alive draw calls in the set of draw calls, the graphics processor 702 may detect whether each of the set of compute draw calls is a dead compute draw call or an alive compute draw call. In some aspects, the dead compute draw call is a dead compute kernel, and where the dead compute kernel is associated with a subset of shader processors (SPs) in a set of SPs.

[0093] At 730, the graphics processor 702 may store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events. In some aspects, to store the information for the subset of dead draw calls and the information for the set of global events, the graphics processor 702 may combine, in the first context slot, the information for the subset of dead draw calls with the information for the set of global events.

[0094] At 740, the graphics processor 702 may store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events. In some aspects, to store the information for the alive draw call, the graphics processor 702 may combine, in the first context slot, the information for the alive draw call with the information for the subset of dead draw calls and the information for the set of global events. In some aspects, to combine, in the first context slot, the information for the alive draw call with the information, the graphics processor 702 may reuse storage space in the first context slot for the information for the alive draw call.

[0095] At 770, the graphics processor 702 may perform, based on the stored information for the alive draw call, at least one of a cache warm-up operation or a data preloading operation for the alive draw call.

[0096] At 780, the graphics processor 702 may refrain from performing, based on the stored information, at least one of a cache warm-up operation or a data preloading operation for the subset of dead draw calls.

[0097] At 750, the graphics processor 702 may process a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events.

[0098] At 760, the graphics processor 702 may output an indication of the processed set of workloads for the alive draw call. In some aspects, the graphics processor 702 may output the indication by transmitting the indication, e.g., to the CPU 704 at 764. In some aspects, the graphics processor 702 may output the indication by storing the indication in, e.g., in the memory 706 or a cache at 766. In some aspects, the graphics processor 702 may output the indication by transmitting the indication to at least one graphics component, such as a render backend (RB) in a graphics processing unit (GPU) or a vertex position cache (VPC) in the GPU.

[0099] FIG. 8 is a flowchart 800 of an example method of graphics processing in accordance with one or more techniques of this disclosure. The method may be performed by an apparatus, such as an apparatus for graphics processing, a GPU, a CPU, a shader processor, a wireless communication device, and the like, as used in connection with the aspects of FIGs. 1-7.

[0100] At 802, the apparatus may obtain information regarding at least one of a set of draw calls or a set of global events, where the set of draw calls and the set of global events are associated with the graphics processing or compute processing. For example, referring to FIG. 5, to start the process, the apparatus may obtain information regarding at least one of a set of draw calls or a set of global events (e.g., via the CP 520), where the set of draw calls and the set of global events are associated with the graphics processing or compute processing. Further, 802 may be performed by processing unit 120 in FIG. 1. As another example, as described in 710 of FIG. 7, the graphics processor 702 may obtain an indication 712 of at least one of a set of draw calls or a set of global events, where the set of draw calls and the set of global events are associated with the graphics processing or compute processing.

[0101] At 804, the apparatus may detect a subset of dead draw calls and a subset of alive draw calls in the set of draw calls. For example, referring to FIG. 5, the apparatus may detect (e.g., based on LRZ module 502 and early-Z module 504), a subset of dead draw calls and a subset of alive draw calls in the set of draw calls. Further, 804 maybe performed by processing unit 120 in FIG. 1. As another example, as described in 720 of FIG. 7, the graphics processor 702 may detect a subset of dead draw calls and a subset of alive draw calls in the set of draw calls.

[0102] At 806, the apparatus may store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events. For example, referring to FIG. 5, the apparatus (e.g., by utilizing the HLSQ DP unit 508) may store, in a first context slot (e.g., 604B) of a set of context slots, information for the subset of dead draw calls (e.g., 606B and 606C) and information for the set of global events (e.g., 608). Further, 806 may be performed by processing unit 120 in FIG. 1. As another example, as described in 730 of FIG. 7, the graphics processor 702 may store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events.

[0103] At 808, the apparatus may store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events. For example, referring to FIG. 5, the apparatus (e.g., by utilizing the HLSQ DP unit 508) may store, in the first context slot, information for an alive draw call (e.g., 606D) in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events. Further, 808 may be performed by processing unit 120 in FIG. 1. As another example, as described in 740 of FIG. 7, the graphics processor 702 may store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events.

[0104] At 810, the apparatus may process a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events. For example, referring to FIG. 5, the apparatus may process (e.g., using the SP 512) a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events. Further, 810 may be performed by processing unit 120 in FIG. 1. As another example, as described in 750 of FIG. 7, the graphics processor 702 may process a set of workloads for the alive draw call based on thestored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events.

[0105] FIG. 9 is a flowchart 900 of an example method of graphics processing in accordance with one or more techniques of this disclosure. The method may be performed by an apparatus, such as an apparatus for graphics processing, a GPU, a CPU, a shader processor, a wireless communication device, and the like, as used in connection with the aspects of FIGs. 1-7.

[0106] At 902, the apparatus may obtain information regarding at least one of a set of draw calls or a set of global events, where the set of draw calls and the set of global events are associated with the graphics processing or compute processing. For example, referring to FIG. 5, to start the process, the apparatus may obtain information regarding at least one of a set of draw calls or a set of global events (e.g., via the CP 520), where the set of draw calls and the set of global events are associated with the graphics processing or compute processing. Further, 902 may be performed by processing unit 120 in FIG. 1. In some aspects, the set of draw calls and the set of global events are configured for execution by a shader processor (SP) (e.g., SP 512) at a graphics processor. As another example, as described in 710 of FIG. 7, the graphics processor 702 may obtain an indication 712 of at least one of a set of draw calls or a set of global events, where the set of draw calls and the set of global events are associated with the graphics processing or compute processing.

[0107] At 904, the apparatus may detect a subset of dead draw calls and a subset of alive draw calls in the set of draw calls. For example, referring to FIG. 5, the apparatus may detect (e.g., based on LRZ module 502 and early-Z module 504), a subset of dead draw calls and a subset of alive draw calls in the set of draw calls. Further, 904 may be performed by processing unit 120 in FIG. 1. In some aspects, as part of 904, to detect the subset of dead draw calls and the subset of alive draw calls in the set of draw calls, at 942, the apparatus may perform, at a first graphics component (e.g., LRZ module 502), a first detection of whether each of the set of draw calls is the dead draw call or the alive draw call. In some aspects, as part of 904, to detect the subset of dead draw calls and the subset of alive draw calls in the set of draw calls, at 944, the apparatus may perform, at a second graphics component (e.g., early-Z module 504), a second detection of whether each of the set of draw calls is the dead draw call or the alive draw call. In some aspects, the first graphics component is a first depth buffer and the second graphics component is a second depth buffer. In some aspects,the first depth buffer is a low resolution Z buffer and the second depth buffer is an early-Z buffer. In some aspects, the set of draw calls is a set of compute draw calls, and to detect the subset of dead draw calls and the subset of alive draw calls in the set of draw calls, at 946, the apparatus may detect whether each of the set of compute draw calls is a dead compute draw call or an alive compute draw call. In some aspects, the dead compute draw call is a dead compute kernel, and where the dead compute kernel is associated with a subset of shader processors (SPs) in a set of SPs. Further, 942, 944, and 946 may be performed by processing unit 120 in FIG. 1. As another example, as described in 720 of FIG. 7, the graphics processor 702 may detect a subset of dead draw calls and a subset of alive draw calls in the set of draw calls.

[0108] At 906, the apparatus may store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events. For example, referring to FIG. 5, the apparatus (e.g., by utilizing the HLSQ DP unit 508) may store, in a first context slot (e.g., 604B) of a set of context slots, information for the subset of dead draw calls (e.g., 606B and 606C) and information for the set of global events (e.g., 608). Further, 906 may be performed by processing unit 120 in FIG. 1. In some aspects, to store the information for the subset of dead draw calls and the information for the set of global events, as part of 906, at 962, the apparatus may combine, in the first context slot, the information for the subset of dead draw calls with the information for the set of global events. For example, as illustrated in FIG. 6, in the context slot 604B, the information for the subset of dead draw calls (e.g., 606C and 606B) may be combined with the information for the set of global events (e.g., 608). Further, 962 may be performed by processing unit 120 in FIG. 1. As another example, as described in 730 of FIG. 7, the graphics processor 702 may store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events.

[0109] In some aspects, the apparatus may refrain from performing, based on the stored information, at least one of a cache warm-up operation or a data preloading operation for the subset of dead draw calls.

[0110] At 908, the apparatus may store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events. For example, referring to FIG. 5, the apparatus (e.g., by utilizing the HLSQ DP unit 508) may store, in the first context slot, information for an alive draw call (e.g., 606D) inthe subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events. Further, 908 may be performed by processing unit 120 in FIG. 1. In some aspects, to store the information for the alive draw call, as part of 908, at 982, the apparatus may combine, in the first context slot, the information for the alive draw call with the information for the subset of dead draw calls and the information for the set of global events. For example, as illustrated in FIG. 6, in the context slot 604B, the information for the alive draw call (e.g., 606D) may be combined with the information for the subset of dead draw calls (e.g., 606C and 606B) and combined with the information for the set of global events (e.g., 608). In some aspects, as part of 982, at 984, the apparatus may reuse storage space (e.g., storage space associated with the context slot 604B) in the first context slot for the information for the alive draw call. Further, 982 and 984 may be performed by processing unit 120 in FIG. 1. As another example, as described in 740 of FIG. 7, the graphics processor 702 may store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events.[OHl] At 910, the apparatus may process a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events. For example, referring to FIG. 5, the apparatus may process (e.g., using the SP 512) a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events. Further, 910 may be performed by processing unit 120 in FIG. 1. As another example, as described in 750 of FIG. 7, the graphics processor 702 may process a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events.

[0112] In some aspects, at 912, the apparatus may output an indication of the processed set of workloads for the alive draw call. As part of 912, in some aspects, at 914, the apparatus may transmit, to at least one graphics component, the indication of the processed set of workloads for the alive draw call. In some aspects, the at least one graphics component includes at least one of: a render backend (RB) (e.g., RB color (RB-C) or late-Z module 514) in a graphics processor or a vertex position cache(VPC) in the graphics processor. As part of 912, in some aspects, at 916, the apparatus may store, in a first memory or a cache, the indication of the processed set of workloads for the alive draw call. In some aspects, the first memory is a system memory or a global memory, and where the cache is a system cache or a global cache. Further, 912, 914, and 916 may be performed by processing unit 120 in FIG. 1. As another example, as described in 760 of FIG. 7, the graphics processor 702 may output an indication of the processed set of workloads for the alive draw call.

[0113] In some aspects, at 918, the apparatus may perform, based on the stored information for the alive draw call, at least one of a cache warm-up operation or a data preloading operation for the alive draw call. For example, the SP 512 may perform, based on the stored information for the alive draw call, at least one of a cache warm-up operation or a data preloading operation for the alive draw call. Further, 918 may be performed by processing unit 120 in FIG. 1. As another example, as described in 770 of FIG. 7, the graphics processor 702 may perform, based on the stored information for the alive draw call, at least one of a cache warm-up operation or a data preloading operation for the alive draw call.

[0114] In configurations, a method or an apparatus for graphics processing is provided. The apparatus may be a graphics processor (e.g., a GPU), a CPU, or some other processor that may perform graphics processing. In aspects, the apparatus may be the processing unit 120 within the device 104, or may be some other hardware within the device 104 or another device. The apparatus may include means for obtaining information regarding at least one of a set of draw calls or a set of global events, where the set of draw calls and the set of global events are associated with the graphics processing or compute processing. The apparatus may further include means for detecting a subset of dead draw calls and a subset of alive draw calls in the set of draw calls. The apparatus may further include means for storing, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events. The apparatus may further include means for storing, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events. The apparatus may further include means for processing a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events. The apparatus may further includemeans for outputting an indication of the processed set of workloads for the alive draw call. The apparatus may further include means for transmitting, to at least one graphics component, the indication of the processed set of workloads for the alive draw call. The apparatus may further include means for storing, in a first memory or a cache, the indication of the processed set of workloads for the alive draw call. The apparatus may further include means for performing, at a first graphics component, a first detection of whether each of the set of draw calls is the dead draw call or the alive draw call. The apparatus may further include means for performing, at a second graphics component, a second detection of whether each of the set of draw calls is the dead draw call or the alive draw call. The apparatus may further include means for detecting whether each of the set of compute draw calls is a dead compute draw call or an alive compute draw call. The apparatus may further include means for combining, in the first context slot, the information for the subset of dead draw calls with the information for the set of global events. The apparatus may further include means for refraining from performing, based on the stored information, at least one of a cache warm-up operation or a data preloading operation for the subset of dead draw calls. The apparatus may further include means for combining, in the first context slot, the information for the alive draw call with the information for the subset of dead draw calls and the information for the set of global events. The apparatus may further include means for reusing storage space in the first context slot for the information for the alive draw call. The apparatus may further include means for performing, based on the stored information for the alive draw call, at least one of a cache warm-up operation or a data preloading operation for the alive draw call.

[0115] It is understood that the specific order or hierarchy of blocks / steps in the processes, flowcharts, and / or call flow diagrams disclosed herein is an illustration of example approaches. Based upon design preferences, it is understood that the specific order or hierarchy of the blocks / steps in the processes, flowcharts, and / or call flow diagrams may be rearranged. Further, some blocks / steps may be combined and / or omitted. Other blocks / steps may also be added. The accompanying method claims present elements of the various blocks / steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0116] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined hereinmay be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, where reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0117] Unless specifically stated otherwise, the term “some” refers to one or more and the term “or” may be interpreted as “and / or” where context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ include any combination of A, B, and / or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. The words “module,” “mechanism,” “element,” “device,” and the like may not be a substitute for the word “means.” As such, no claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.” Unless stated otherwise, the phrase “a processor” may refer to “any of one or more processors” (e.g., one processor of one or more processors, a number (greater than one) of processors in the one or more processors, or all of the one or more processors) and the phrase “a memory” may refer to “any of one or more memories” (e.g., one memory of one or more memories, a number (greater than one) of memories in the one or more memories, or all of the one or more memories).

[0118] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although theterm “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

[0119] Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to: (1) tangible computer-readable storage media, which is non-transitory; or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, compact disc-read only memory (CD-ROM), or other optical disk storage, magnetic disk storage, or other magnetic storage devices. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs usually reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0120] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set. Various components, modules or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of inter-operative hardware units, including one or more processors as described above, in conjunction with suitable software and / or firmware. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques may be fully implemented in one or more circuits or logic elements.

[0121] The following aspects are illustrative only and may be combined with other aspects or teachings described herein, without limitation.

[0122] Aspect 1 is a method of graphics processing, including: obtaining information regarding at least one of a set of draw calls or a set of global events, where the set of draw calls and the set of global events are associated with the graphics processing or compute processing; detecting a subset of dead draw calls and a subset of alive draw calls in the set of draw calls; storing, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events; storing, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events; processing a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events.

[0123] Aspect 2 may be combined with aspect 1 and further includes outputting an indication of the processed set of workloads for the alive draw call.

[0124] Aspect 3 may be combined with aspect 2 and includes that outputting the indication of the processed set of workloads for the alive draw call includes transmitting, to at least one graphics component, the indication of the processed set of workloads for the alive draw call.

[0125] Aspect 4 may be combined with aspect 3 and includes that the at least one graphics component includes at least one of: a render backend (RB) in a graphics processor or a vertex position cache (VPC) in the graphics processor.

[0126] Aspect 5 may be combined with any of aspects 2-4 and includes that outputting the indication of the processed set of workloads for the alive draw call includes storing, in a first memory or a cache, the indication of the processed set of workloads for the alive draw call.

[0127] Aspect 6 may be combined with aspect 5 and includes that the first memory is a system memory or a global memory, and wherein the cache is a system cache or a global cache.

[0128] Aspect 7 may be combined with any of aspects 1-6 and includes that the set of draw calls and the set of global events are configured for execution by a shader processor (SP) at a graphics processor.

[0129] Aspect 8 may be combined with any of aspects 1-7 and includes that detecting the subset of dead draw calls and the subset of alive draw calls in the set of draw calls includes performing, at a first graphics component, a first detection of whether each of the set of draw calls is the dead draw call or the alive draw call and performing, at a second graphics component, a second detection of whether each of the set of draw calls is the dead draw call or the alive draw call.

[0130] Aspect 9 may be combined with aspect 8 and includes that the first graphics component is a first depth buffer and the second graphics component is a second depth buffer.

[0131] Aspect 10 may be combined with aspect 9 and includes that the first depth buffer is a low resolution Z buffer and the second depth buffer is an early-Z buffer.

[0132] Aspect 11 may be combined with any of aspects 1-10 and includes that the set of draw calls is a set of compute draw calls and detecting the subset of dead draw calls and the subset of alive draw calls in the set of draw calls includes detect whether each of the set of compute draw calls is a dead compute draw call or an alive compute draw call.

[0133] Aspect 12 may be combined with aspect 11 and includes that the dead compute draw call is a dead compute kernel, and where the dead compute kernel is associated with a subset of shader processors (SPs) in a set of SPs.

[0134] Aspect 13 may be combined with any of aspects 1-12 and includes that storing the information for the subset of dead draw calls and the information for the set of global events includes combining, in the first context slot, the information for the subset of dead draw calls with the information for the set of global events.

[0135] Aspect 14 may be combined with any of aspects 1-13 and includes refraining from performing, based on the stored information, at least one of a cache warm-up operation or a data preloading operation for the subset of dead draw calls.

[0136] Aspect 15 may be combined with any of aspects 1-14 and includes that storing the information for the alive draw call includes combining, in the first context slot, the information for the alive draw call with the information for the subset of dead draw calls and the information for the set of global events.

[0137] Aspect 16 may be combined with aspect 15 and includes that combining the information for the alive draw call with the information for the subset of dead draw calls and the information for the set of global events includes reusing storage space in the first context slot for the information for the alive draw call.

[0138] Aspect 17 may be combined with any of aspects 1-16 and includes performing, based on the stored information for the alive draw call, at least one of a cache warm-up operation or a data preloading operation for the alive draw call.

[0139] Aspect 18 may be combined with any of aspects 1-17 and includes that the set of workloads for the alive draw call includes at least one of a set of graphics workloads or a set of compute workloads.

[0140] Aspect 19 is an apparatus for graphics processing including at least one processor coupled to a memory and configured to implement a method as in any of aspects 1- 18.

[0141] Aspect 20 may be combined with aspect 19 and includes that the apparatus is a wireless communication device.

[0142] Aspect 21 is an apparatus for graphics processing including means for implementing a method as in any of aspects 1-18.

[0143] Aspect 22 is a computer-readable medium (e.g., a non-transitory computer-readable medium) storing computer executable code, the code when executed by at least one processor causes the at least one processor to implement a method as in any of aspects 1-18.

[0144] Various aspects have been described herein. These and other aspects are within the scope of the following claims.

Claims

CLAIMSWHAT IS CLAIMED IS:

1. An apparatus for graphics processing, comprising: a memory; and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to: obtain information regarding at least one of a set of draw calls and a set of global events, wherein the set of draw calls and the set of global events are associated with the graphics processing or compute processing; detect a subset of dead draw calls and a subset of alive draw calls in the set of draw calls; store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events; store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events; and process a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events.

2. The apparatus of claim 1, wherein the processor is further configured to: output an indication of the processed set of workloads for the alive draw call.

3. The apparatus of claim 2, wherein to output the indication of the processed set of workloads for the alive draw call, the processor is configured to: transmit, to at least one graphics component, the indication of the processed set of workloads for the alive draw call.

4. The apparatus of claim 3, wherein the at least one graphics component includes at least one of: a render backend (RB) in a graphics processor or a vertex position cache (VPC) in the graphics processor.

5. The apparatus of claim 2, wherein to output the indication of the processed set of workloads for the alive draw call, the processor is configured to: store, in a first memory or a cache, the indication of the processed set of workloads for the alive draw call.

6. The apparatus of claim 5, wherein the first memory is a system memory or a global memory, and wherein the cache is a system cache or a global cache.

7. The apparatus of claim 1, wherein the set of draw calls and the set of global events are configured for execution by a shader processor (SP) at a graphics processor.

8. The apparatus of claim 1, wherein to detect the subset of dead draw calls and the subset of alive draw calls in the set of draw calls, the processor is configured to: perform, at a first graphics component, a first detection of whether each of the set of draw calls is the dead draw call or the alive draw call; and perform, at a second graphics component, a second detection of whether each of the set of draw calls is the dead draw call or the alive draw call.

9. The apparatus of claim 8, wherein the first graphics component is a first depth buffer and the second graphics component is a second depth buffer.

10. The apparatus of claim 9, wherein the first depth buffer is a low resolution Z buffer and the second depth buffer is an early-Z buffer.

11. The apparatus of claim 1, wherein the set of draw calls is a set of compute draw calls, wherein to detect the subset of dead draw calls and the subset of alive draw calls in the set of draw calls, the processor is configured to:detect whether each of the set of compute draw calls is a dead compute draw call or an alive compute draw call.

12. The apparatus of claim 11, wherein the dead compute draw call is a dead compute kernel, and wherein the dead compute kernel is associated with a subset of shader processors (SPs) in a set of SPs.

13. The apparatus of claim 1, wherein to store the information for the subset of dead draw calls and the information for the set of global events, the processor is configured to: combine, in the first context slot, the information for the subset of dead draw calls with the information for the set of global events.

14. The apparatus of claim 1, wherein the processor is further configured to: refrain from performing, based on the stored information, at least one of a cache warm-up operation or a data preloading operation for the subset of dead draw calls.

15. The apparatus of claim 1, wherein to store the information for the alive draw call, the processor is configured to: combine, in the first context slot, the information for the alive draw call with the information for the subset of dead draw calls and the information for the set of global events.

16. The apparatus of claim 15, wherein to combine the information for the alive draw call with the information for the subset of dead draw calls and the information for the set of global events, the processor is configured to: reuse storage space in the first context slot for the information for the alive draw call.

17. The apparatus of claim 1, wherein the processor is further configured to: perform, based on the stored information for the alive draw call, at least one of a cache warm-up operation or a data preloading operation for the alive draw call.

18. The apparatus of claim 1, wherein the set of workloads for the alive draw call comprises at least one of a set of graphics workloads or a set of compute workloads.

19. The apparatus of claim 1, wherein the apparatus is a wireless communication device.

20. A method for graphics processing, comprising: obtaining information regarding at least one of a set of draw calls or a set of global events, wherein the set of draw calls and the set of global events are associated with the graphics processing or compute processing; detecting a subset of dead draw calls and a subset of alive draw calls in the set of draw calls; storing, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events; storing, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events; and processing a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events.

21. The method of claim 20, further comprising: outputting an indication of the processed set of workloads for the alive draw call.

22. The method of claim 21, wherein outputting the indication of the processed set of workloads for the alive draw call further comprises: transmitting, to at least one graphics component, the indication of the processed set of workloads for the alive draw call.

23. The method of claim 22, wherein the at least one graphics component includes at least one of: a render backend (RB) in a graphics processor or a vertex position cache (VPC) in the graphics processor.

24. The method of claim 21, wherein outputting the indication of the processed set of workloads for the alive draw call further comprises: storing, in a first memory or a cache, the indication of the processed set of workloads for the alive draw call.

25. The method of claim 24, wherein the first memory is a system memory or a global memory, and wherein the cache is a system cache or a global cache.

26. The method of claim 20, wherein the set of draw calls and the set of global events are configured for execution by a shader processor (SP) at a graphics processor.

27. The method of claim 20, wherein detecting the subset of dead draw calls and the subset of alive draw calls in the set of draw calls further comprises: performing, at a first graphics component, a first detection of whether each of the set of draw calls is the dead draw call or the alive draw call; and performing, at a second graphics component, a second detection of whether each of the set of draw calls is the dead draw call or the alive draw call.

28. The method of claim 27, wherein the first graphics component is a first depth buffer and the second graphics component is a second depth buffer.

29. The method of claim 28, wherein the first depth buffer is a low resolution Z buffer and the second depth buffer is an early-Z buffer.

30. A computer-readable medium storing computer executable code for graphics processing, the code when executed by at least one processor, causes the at least one processor to:obtain information regarding at least one of a set of draw calls or a set of global events, wherein the set of draw calls and the set of global events are associated with the graphics processing or compute processing; detect a subset of dead draw calls and a subset of alive draw calls in the set of draw calls; store, in a first context slot of a set of context slots, information for the subset of dead draw calls and information for the set of global events; store, in the first context slot, information for an alive draw call in the subset of alive draw calls along with the stored information for the subset of dead draw calls and the stored information for the set of global events; and process a set of workloads for the alive draw call based on the stored information for the alive draw call, the stored information for the subset of dead draw calls, and the stored information for the set of global events.

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