Array substrate, display apparatus, and manufacturing method for array substrate

Abstract

An array substrate (10), comprising: a first conductive layer (2) having a first auxiliary electrode (21), a second conductive layer (4) having a second auxiliary electrode (41), a third conductive layer (6) having a pixel electrode (61), and an isolation layer (7) having a hollowed-out region (71). The orthographic projection of the first auxiliary electrode (21), the orthographic projection of the second auxiliary electrode (41), and the orthographic projection of the pixel electrode (61) all have an overlapping region, and the pixel electrode (61) is electrically connected to the first auxiliary electrode (21); and the orthographic projection of the hollowed-out region (71) and the orthographic projection of the second auxiliary electrode (41) have an overlapping region. The beneficial effects are: the first auxiliary electrode (21) and the second auxiliary electrode (41), and the pixel electrode (61) and the second auxiliary electrode (41) form a plurality of storage capacitors connected in parallel, thereby increasing the total storage capacitance while increasing the number of pixel regions (AA).

Description

Array substrate, display device, and method for manufacturing array substrate Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display device, and a method for manufacturing the array substrate. Background Art

[0002] Electronic paper is a new type of display device, mainly used in devices such as electronic labels, flashcards, billboards, and e-readers. The display effect of electronic paper is close to that of natural paper, which can reduce visual fatigue when reading.

[0003] In related art, electronic paper typically includes an array substrate and a cover plate positioned opposite each other, and an electrophoretic layer positioned between the array substrate and the cover plate. The array substrate has a plurality of pixels arranged in an array, and each pixel includes a pixel electrode and an auxiliary electrode insulated from the pixel electrode. The pixel electrode and the auxiliary electrode form a storage capacitor during display to maintain the stability of the voltage applied to the pixel electrode.

[0004] However, as the number of pixels per inch (PPI) in array substrates continues to increase, the size of each pixel electrode in the array substrate continues to decrease, resulting in a continuous decrease in the overlap area between the pixel electrode and the auxiliary electrode. This in turn causes a continuous decrease in the capacitance of the storage capacitor formed between the pixel electrode and the auxiliary electrode. This affects the stability of the voltage applied to the pixel electrode, resulting in poor display quality in electronic paper produced using this array substrate.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] The present disclosure aims to provide an array substrate, a display device and a method for manufacturing the array substrate, which can increase the capacitance of the storage capacitor of the array substrate and avoid the phenomenon of ghosting during display.

[0008] According to one aspect of the present disclosure, there is provided an array substrate, comprising:

[0009] substrate;

[0010] a first conductive layer, located on one side of the substrate and having a first auxiliary electrode;

[0011] a first insulating layer, located on a side of the first conductive layer facing away from the substrate and covering at least the first auxiliary electrode;

[0012] a second conductive layer, located on a side of the first insulating layer facing away from the substrate, and having a second auxiliary electrode;

[0013] a second insulating layer, located on a side of the second conductive layer facing away from the substrate and covering at least the second auxiliary electrode;

[0014] a third conductive layer, located on a side of the second insulating layer facing away from the substrate, and having a pixel electrode, wherein an orthographic projection of the first auxiliary electrode, an orthographic projection of the second auxiliary electrode, and an orthographic projection of the pixel electrode all overlap, and the pixel electrode is electrically connected to the first auxiliary electrode;

[0015] The isolation layer is located between the second conductive layer and the third conductive layer and has a hollow area, and an orthographic projection of the hollow area overlaps with an orthographic projection of the second auxiliary electrode.

[0016] According to any array substrate described in the present disclosure, the array substrate includes a transistor and a connecting line, the transistor includes a source and a drain, the source and the drain are connected to the connecting line, the connecting line is electrically connected to the first auxiliary electrode through a first via hole penetrating the first insulating layer, and is electrically connected to the pixel electrode through a second via hole penetrating the second insulating layer.

[0017] According to any array substrate described in the present disclosure, the thickness of the isolation layer is greater than the thickness of the second insulating layer, and the orthographic projection of the hollowed-out area is located outside the orthographic projection of the source and drain, and the orthographic projection of the pixel electrode covers the orthographic projection of the source and drain.

[0018] According to any array substrate described in the present disclosure, the source and drain electrodes and the connecting lines are located in the second conductive layer.

[0019] According to any array substrate described in the present disclosure, the distance between the connecting line and the second auxiliary electrode is greater than or equal to 4 microns.

[0020] According to any one of the array substrates of the present disclosure, the transistor includes an active portion, and the active portion is located in the second conductive layer;

[0021] The array substrate further includes a fourth conductive layer, which is located between the second conductive layer and the second insulating layer. The source and drain electrodes and the connecting wires are located in the fourth conductive layer, and the source and drain electrodes are overlapped with the active portion.

[0022] According to any array substrate described in the present disclosure, the orthographic projection of the hollowed-out area is located outside the orthographic projection of the second via hole, and the second via hole passes through the isolation layer.

[0023] According to any array substrate described in the present disclosure, the orthographic projection of the hollowed-out area covers the orthographic projection of the second via hole.

[0024] According to any one of the array substrates of the present disclosure, the orthographic projection of the first via hole is located outside the orthographic projection of the second via hole;

[0025] The second auxiliary electrode has a first step surface facing the connecting line in the first direction, and a second step surface adjacent to the first step surface in the second direction. In the first direction, the first via is located between the second via and the second auxiliary electrode, and the first dimension of the first step surface and the second via in the first direction is greater than the second dimension of the second step surface in the first direction. The first direction intersects with the second direction.

[0026] According to any one of the array substrates described in the present disclosure, an orthographic projection of the first via hole and an orthographic projection of the second via hole have an overlapping area;

[0027] The second auxiliary electrode has a first step surface facing the connecting line in the first direction, and a second step surface adjacent to the first step surface in the second direction, and a first dimension of the first step surface and the second via in the first direction is smaller than a second dimension of the second step surface in the first direction.

[0028] According to any array substrate described in the present disclosure, the center lines of the first via hole and the second via hole along the thickness direction of the substrate coincide with each other.

[0029] According to any array substrate described in the present disclosure, the transistor further includes a gate, and the gate is located in the first conductive layer.

[0030] According to any array substrate described in the present disclosure, the first conductive layer has a gate line extending along the second direction and connected to the gate, the second conductive layer has a data line extending along the first direction and connected to the source and drain, and an auxiliary electrode line connected to the second auxiliary electrode.

[0031] According to any array substrate described in the present disclosure, the array substrate has a plurality of pixel areas arranged in an array, and each pixel area is provided with one transistor, or two transistors connected in series.

[0032] According to any array substrate described in the present disclosure, the isolation layer is located between the second conductive layer and the second insulating layer.

[0033] According to any array substrate described in the present disclosure, the orthographic projection of the hollowed-out area covers the orthographic projection of the second auxiliary electrode, and the first auxiliary electrode, the second auxiliary electrode and the pixel electrode constitute two storage capacitors connected in parallel.

[0034] According to any array substrate described in the present disclosure, the orthographic projection of the second auxiliary electrode extends out of the orthographic projection of the hollowed-out area, and the first auxiliary electrode, the second auxiliary electrode and the pixel electrode constitute three storage capacitors connected in parallel.

[0035] According to one aspect of the present disclosure, a display device is provided, comprising a cover plate and the array substrate described in the above aspect, wherein the cover plate is arranged opposite to the array substrate;

[0036] The display device further includes an electrophoretic layer located between the array substrate and the cover plate.

[0037] According to one aspect of the present disclosure, a method for manufacturing an array substrate is provided, the method comprising:

[0038] providing a substrate;

[0039] forming a first conductive layer on one side of the substrate, wherein the first conductive layer has a first auxiliary electrode;

[0040] forming a first insulating layer on a side of the first conductive layer facing away from the substrate, wherein the first insulating layer at least covers the first auxiliary electrode;

[0041] forming a second conductive layer on a side of the first insulating layer facing away from the substrate, wherein the second conductive layer has a second auxiliary electrode;

[0042] forming a second insulating layer on a side of the second conductive layer facing away from the substrate, wherein the second insulating layer at least covers the second auxiliary electrode;

[0043] A third conductive layer is formed on a side of the second insulating layer facing away from the substrate, the third conductive layer having a pixel electrode, an orthographic projection of the first auxiliary electrode, an orthographic projection of the second auxiliary electrode, and an orthographic projection of the pixel electrode all overlap, and the pixel electrode is electrically connected to the first auxiliary electrode;

[0044] An isolation layer is formed between the second conductive layer and the third conductive layer, wherein the isolation layer has a hollow region, and an orthographic projection of the hollow region overlaps with an orthographic projection of the second auxiliary electrode.

[0045] The embodiments of the present disclosure include at least the following technical effects:

[0046] In the embodiment of the present disclosure, since the first auxiliary electrode is electrically connected to the pixel electrode, when the display device having the array substrate is displaying, the voltage applied to the first auxiliary electrode is the same as the voltage applied to the pixel electrode, both being the pixel voltage. That is, the first auxiliary electrode is also equivalent to the pixel electrode. In this way, as shown in FIG2 or FIG3, the first auxiliary electrode and the second auxiliary electrode can form a first storage capacitor, the pixel electrode and the second auxiliary electrode can form a second storage capacitor in the hollowed-out area of ​​the isolation layer, and the pixel electrode and the second auxiliary electrode can form a third storage capacitor in the non-hollowed-out area of ​​the isolation layer. The first storage capacitor, the second storage capacitor, and the third storage capacitor are connected in parallel, thereby increasing the number of pixel areas on the array substrate while increasing the total storage capacitance of the pixel circuit. Furthermore, for a display device having the array substrate, it is possible to increase the PPI while ensuring a storage capacitor with a larger capacitance value to avoid the phenomenon of smearing during display.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0049] FIG1 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure.

[0050] FIG2 is a schematic cross-sectional view of another display device provided in an embodiment of the present disclosure.

[0051] FIG3 is a schematic diagram of a top view of the structure of an array substrate in a pixel area provided by an embodiment of the present disclosure.

[0052] FIG4 is a schematic top view of the structure of a conductive layer in a pixel area included in an array substrate provided in an embodiment of the present disclosure.

[0053] FIG5 is a schematic diagram of the cross-sectional structure of an array substrate provided by an embodiment of the present disclosure along the section line B1 - B2 shown in FIG4 .

[0054] FIG6 is a schematic diagram of the cross-sectional structure of another array substrate provided by an embodiment of the present disclosure along the section line B1 - B2 shown in FIG4 .

[0055] FIG7 is a schematic cross-sectional view of another array substrate provided in an embodiment of the present disclosure.

[0056] FIG8 is a schematic top view of the structure of a conductive layer in a pixel area included in another array substrate provided in an embodiment of the present disclosure.

[0057] FIG9 is a schematic diagram of the cross-sectional structure of another array substrate provided by an embodiment of the present disclosure along the section line B1 - B2 shown in FIG8 .

[0058] FIG10 is a schematic diagram of the cross-sectional structure of another array substrate provided by an embodiment of the present disclosure along the section line B1 - B2 shown in FIG4 .

[0059] FIG11 is a schematic diagram of the cross-sectional structure of another array substrate provided by an embodiment of the present disclosure along the section line B1 - B2 shown in FIG4 .

[0060] FIG12 is a schematic diagram of a top view of the structure of a second conductive layer and an isolation layer provided in an embodiment of the present disclosure.

[0061] FIG13 is a schematic top view of another structure of a second conductive layer and an isolation layer provided in an embodiment of the present disclosure.

[0062] FIG14 is a schematic top view of another structure of a second conductive layer and an isolation layer provided in an embodiment of the present disclosure.

[0063] FIG15 is a schematic flow chart of a method for manufacturing an array substrate provided in an embodiment of the present disclosure.

[0064] Reference numerals:

[0065] 10. Array substrate; 20. Cover plate; 30. Electrophoretic layer;

[0066] Poly, active layer; Ga, gate metal layer; SD, source and drain metal layer; ITO, pixel electrode layer;

[0067] AA, pixel area; T, transistor; L1, connecting line; Gate, gate line; Date, data line; L2, auxiliary electrode line;

[0068] Tg, gate; Tp, active part; Tsd, source and drain;

[0069] Cst1, first storage capacitor; Cst2, second storage capacitor; Cst3, third storage capacitor;

[0070] 1. Substrate; 2. First conductive layer; 3. First insulating layer; 4. Second conductive layer; 5. Second insulating layer; 6. Third conductive layer; 7. Isolation layer; 8. Fourth conductive layer; 9. Third insulating layer;

[0071] 21. First auxiliary electrode; 31. First via hole; 41. Second auxiliary electrode; 411. First step surface; 412. Second step surface; 51. Second via hole; 61. Pixel electrode; 71. Hollow area. DETAILED DESCRIPTION

[0072] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0073] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0074] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0075] A transistor is a device consisting of at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain terminal or drain region) and the source (source terminal or source region), through which current can flow. The channel region is the area where current primarily flows.

[0076] The first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain. The functions of "source" and "drain" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation.

[0077] An embodiment of the present disclosure provides a display device, as shown in FIG. 1 or FIG. 2 , which includes a cover plate 20 and an array substrate 10 that are oppositely disposed, and an electrophoretic layer 30 located between the array substrate 10 and the cover plate 20 .

[0078] As shown in FIG3 , the array substrate 10 has a plurality of pixel areas AA distributed in an array, each pixel area AA having a pixel electrode 61 and an auxiliary electrode (not shown in the figure), and the pixel electrode 61 and the auxiliary electrode can form a storage capacitor during display to maintain the stability of the voltage loaded on the pixel electrode 61, thereby realizing the display of the picture.

[0079] The display device may be electronic paper, for example, a price tag product, a word card product, a reader product, etc.

[0080] In related art, taking price tags as an example, because price tags have a low PPI requirement, each pixel area AA on the array substrate 10 is larger. This facilitates the placement of pixel electrodes 61 and auxiliary electrodes with a larger overlapping area, thereby increasing the capacitance of the storage capacitor and meeting driving requirements. However, to increase the PPI of price tags, the size of each pixel area AA is compressed, resulting in a smaller overlapping area between the pixel electrode 61 and the auxiliary electrode, and thus a smaller capacitance of the storage capacitor. In this case, when the electronic ink of the electrophoretic layer 30 is driven for display based on the reduced capacitance of the storage capacitor, the electronic ink is driven more slowly, resulting in a display artifact called smearing.

[0081] Taking e-reader products as an example, due to their high PPI, each pixel area AA on the array substrate 10 is smaller, which in turn reduces the overlap area between the pixel electrode 61 and the auxiliary electrode, resulting in a smaller storage capacitor value. In this case, when the electronic ink in the electrophoretic layer 30 is driven by the smaller storage capacitor value for display, the slower driving of the electronic ink will cause display smearing.

[0082] In order to avoid the problem of display ghosting during display of a display device, the present disclosure provides an array substrate 10, which can effectively increase the capacitance value of the storage capacitor, so that for a display device having the array substrate 10, the problem of display ghosting during display can be avoided, thereby improving the yield of the product.

[0083] Among them, the array substrates shown in Figures 1 and 2 are cross-sectional views obtained by cutting along the section line B1-B2 shown in Figure 3. As shown in Figure 1 or 2, the array substrate 10 includes a substrate 1 and a driving layer (not shown in the figure) located on one side of the substrate 1, and the driving layer includes a plurality of pixel circuits distributed in an array.

[0084] The substrate 1 included in the array substrate 10 may be made of an inorganic material or an organic material. For example, in some embodiments, the substrate 1 may be made of a glass material such as soda-lime glass, quartz glass, or sapphire glass, or may be made of a metal material such as stainless steel, aluminum, or nickel. In other embodiments, the substrate 1 may be made of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

[0085] Alternatively, the substrate 1 may be a single layer material or a composite of multiple layers. For example, in some embodiments, the substrate 1 includes a base film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0086] The pixel circuit included in the driving layer may include at least one transistor T and a storage capacitor. The transistor T may be a thin film transistor, which may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor. The thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0087] Among them, the storage capacitor may include multiple plates located in different film layers of the driving layer, as shown in Figure 1, Figure 2 or Figure 4, and the transistor T includes a gate Tg, an active portion Tp and a source-drain electrode Tsd (source and drain) located in different film layers of the driving layer, the gate Tg is insulated from the active portion Tp, and the active portion Tp includes a channel region that overlaps with the gate Tg in the thickness direction of the substrate 1, and two connecting portions located on both sides of the channel region, the two connecting portions being electrically connected to the source and drain respectively. The channel region can maintain semiconductor characteristics, and the two connecting portions can be partially conductive or fully conductive.

[0088] It is understood that when a pixel circuit includes multiple transistors T, the types of any two transistors T may be the same or different. For example, in some embodiments, some transistors T in a pixel circuit may be N-type transistors T, and some transistors T may be P-type transistors T.

[0089] As shown in FIG1 or FIG2 , the drive layer included in the array substrate 10 includes an active layer Poly, a gate metal layer Ga, a source / drain metal layer SD, and a pixel electrode layer ITO, which are stacked and distributed on one side of the substrate 1. The order of the film layers of the active layer Poly and the gate metal layer Ga is determined in combination with the type of transistor T included in the pixel circuit. Taking the transistor T as a top-gate structure as an example, as shown in FIG5 or FIG6 , the drive layer includes the active layer Poly, the gate metal layer Ga, the source / drain metal layer SD, and the pixel electrode layer ITO, which are stacked in sequence on the substrate 1; taking the transistor T as a bottom-gate structure as an example, as shown in FIG1 or FIG2 , the drive layer includes the gate metal layer Ga, the active layer Poly, the source / drain metal layer SD, and the pixel electrode layer ITO, which are stacked in sequence on the substrate 1.

[0090] Among them, the active layer Poly is used to form the active part Tp of each transistor T. The material of the active layer Poly can be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material or other types of semiconductor materials. Based on the influence of the PPI of the electrophoretic display device, amorphous silicon semiconductor material can be preferably used to make the active layer Poly; the gate metal layer Ga is used to form the scanning line and the gate Tg of each transistor T; the source and drain metal layer SD can form the data line Date, the connecting line L1, etc., as well as the source and drain Tsd (source and drain) of each transistor T; the pixel electrode layer ITO is used to form the pixel electrode 61 located in each pixel area AA.

[0091] Among them, the driving layer also includes an insulating layer (gate Tg insulating layer) located between the gate metal layer Ga and the active layer Poly, and an insulating layer (passivation layer) located between the source and drain metal layer SD and the pixel electrode layer ITO, so as to achieve insulation between the active part Tp of each transistor T and the gate Tg, and insulation between the source and drain Tsd of each transistor T and the pixel electrode 61.

[0092] It should be noted that, for the case where the transistor T has a bottom-gate structure, since the source and drain electrodes Tsd of the transistor T are electrically connected to the active portion Tp, a source and drain metal layer SD may be provided directly stacked on the active layer Poly, as shown in FIG1 or FIG2 , so as to achieve overlapping of the source and drain electrodes Tsd of each transistor T with the active portion Tp; for the case where the transistor T has a top-gate structure, as shown in FIG5 or FIG6 , the driving layer further includes a third insulating layer 9 located between the gate metal layer Ga and the source and drain metal layer SD, so as to achieve insulation of the gate electrode Tg and the source and drain electrodes Tsd of each transistor T.

[0093] In the present disclosure, as shown in FIG. 2 or FIG. 5 , the array substrate 10 includes: a substrate 1 , a first conductive layer 2 , a first insulating layer 3 , a second conductive layer 4 , a second insulating layer 5 , a third conductive layer 6 and an isolation layer 7 .

[0094] Among them, the first conductive layer 2 is located on one side of the substrate 1 and has a first auxiliary electrode 21; the first insulating layer 3 is located on the side of the first conductive layer 2 away from the substrate 1 and at least covers the first auxiliary electrode 21; the second conductive layer 4 is located on the side of the first insulating layer 3 away from the substrate 1 and has a second auxiliary electrode 41; the second insulating layer 5 is located on the side of the second conductive layer 4 away from the substrate 1 and at least covers the second auxiliary electrode 41; the third conductive layer 6 is located on the side of the second insulating layer 5 away from the substrate 1 and has a pixel electrode 61, and the orthographic projection of the first auxiliary electrode 21, the orthographic projection of the second auxiliary electrode 41, and the orthographic projection of the pixel electrode 61 all have overlapping areas, and the pixel electrode 61 is electrically connected to the first auxiliary electrode 21; the isolation layer 7 is located between the second conductive layer 4 and the third conductive layer 6, and has a hollow area 71, and the orthographic projection of the hollow area 71 has an overlapping area with the orthographic projection of the second auxiliary electrode 41.

[0095] In the present disclosure, because the first auxiliary electrode 21 is electrically connected to the pixel electrode 61, when a display device including the array substrate 10 is displaying, the voltage applied to the first auxiliary electrode 21 is the same as the voltage applied to the pixel electrode 61, both being pixel voltages. In other words, the first auxiliary electrode 21 also functions as the pixel electrode 61. In this manner, multiple storage capacitors connected in parallel can be formed by the first auxiliary electrode 21, the second auxiliary electrode 41, and the pixel electrode 61, thereby increasing the number of pixel areas AA on the array substrate 10 while also increasing the total capacitance of the pixel circuit. Furthermore, a display device including the array substrate 10 can achieve a higher PPI while maintaining a larger total capacitance, thereby avoiding smearing during display.

[0096] Among them, for the multiple storage capacitors formed, in some embodiments, the orthographic projection of the hollowed-out area 71 may cover the orthographic projection of the second auxiliary electrode 41. In this case, the first auxiliary electrode 21, the second auxiliary electrode 41, and the pixel electrode 61 constitute two storage capacitors in parallel. Specifically, as shown in Figure 7, the first auxiliary electrode 21 and the second auxiliary electrode 41 form a first storage capacitor Cst1, and the pixel electrode 61 and the second auxiliary electrode 41 form a second storage capacitor Cst2 in the hollowed-out area 71 of the isolation layer 7, and the first storage capacitor Cst1 and the second storage capacitor Cst2 are connected in parallel.

[0097] In other embodiments, the orthographic projection of the second auxiliary electrode 41 may extend out of the orthographic projection of the hollowed-out area 71. In this case, the first auxiliary electrode 21, the second auxiliary electrode 41, and the pixel electrode 61 constitute three storage capacitors in parallel. Specifically, as shown in FIG2 or FIG5 , the first auxiliary electrode 21 and the second auxiliary electrode 41 may form a first storage capacitor Cst1, the pixel electrode 61 and the second auxiliary electrode 41 may form a second storage capacitor Cst2 in the hollowed-out area 71 of the isolation layer 7, and the pixel electrode 61 and the second auxiliary electrode 41 may form a third storage capacitor Cst3 in the non-hollowed-out area of ​​the isolation layer 7 (i.e., the periphery of the hollowed-out area 71). The first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 are connected in parallel.

[0098] The total capacitance of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 connected in parallel may be the sum of the capacitances of the individual storage capacitors. The first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 may be calculated using the following first, second, and third formulas, respectively.

[0099] First formula: (S1×ε1×ε0) / D1

[0100] Second formula: (S2×ε2×ε0) / D2

[0101] The third formula: S3 / [D2 / (ε2×ε0)+D3 / (ε3×ε0)]

[0102] In the above first, second and third formulas, ε0 is the dielectric constant of vacuum, ε1 is the dielectric constant of the first insulating layer 3, D1 is the film thickness of the first insulating layer 3, S1 is the overlapping area between the first auxiliary electrode 21 and the second auxiliary electrode 41, ε2 is the dielectric constant of the second insulating layer 5, D2 is the film thickness of the second insulating layer 5, S2 is the overlapping area between the second auxiliary electrode 41 and the pixel electrode 61 in the hollowed-out area 71 (there is only the second insulating layer 5 between the second auxiliary electrode 41 and the pixel electrode 61 shown in Figure 5), ε3 is the dielectric constant of the isolation layer 7, D3 is the film thickness of the isolation layer 7, and S2 is the overlapping area between the second auxiliary electrode 41 and the pixel electrode 61 in the non-hollowed-out area (there are the second insulating layer 5 and the isolation layer 7 between the second auxiliary electrode 41 and the pixel electrode 61 shown in Figure 5).

[0103] It should be noted that, in the above formula, the sum of S2 and S3 is the area S4 of the overlapping region between the second auxiliary electrode 41 and the pixel electrode 61 in the thickness direction of the substrate 1 , ie, S4=S2+S3.

[0104] It can be seen from the above calculation formula that the first storage capacitor Cst1 is mainly related to the film thickness of the first insulating layer 3 and the overlapping area of ​​the first auxiliary electrode 21 and the second auxiliary electrode 41. In this way, the maximum overlapping area of ​​the first auxiliary electrode 21 and the second auxiliary electrode 41 can be set during the design; the second storage capacitor Cst2 and the third storage capacitor Cst3 are related to the film thickness of the second insulating layer 5, the film thickness of the isolation layer 7, the size of the hollow area 71 on the isolation layer 7, and the overlapping area of ​​the second auxiliary electrode 41 and the pixel electrode 61. In this way, the maximum hollow area 71 of the isolation layer 7 can be set during the design.

[0105] Among them, combined with the film layer structure of the driving layer described above, the third conductive layer 6 included in the array substrate 10 can be a pixel electrode layer ITO, and for the first conductive layer 2 and the second conductive layer 4 included in the array substrate 10, taking the transistor T with a top gate structure as an example, as shown in Figures 5 and 6, the first conductive layer 2 can be an active layer Poly or a gate metal layer Ga, and the second conductive layer 4 can be a source and drain metal layer SD, and has a source and drain Tsd of each transistor T. As shown in Figure 5, taking the first conductive layer 2 as the active layer Poly as an example, the first conductive layer 2 has an active portion Tp of each transistor T, and the array substrate 10 also includes a fourth conductive layer 8 located on the side of the first conductive layer 2 away from the substrate 1 and insulated from the first conductive layer 2. The fourth conductive layer 8 is a gate metal layer Ga and has a gate Tg of each transistor T; and as shown in Figure 6, taking the first conductive layer 2 as the gate metal layer Ga as an example, the first conductive layer 2 has a gate Tg of each transistor T, and the array substrate 10 also includes a fourth conductive layer 8 located on the side of the first conductive layer 2 close to the substrate 1 and insulated from the first conductive layer 2. The fourth conductive layer 8 is an active layer Poly and has an active portion Tp of each transistor T.

[0106] Taking a bottom-gate transistor T as an example, as shown in Figures 1 and 2 , the first conductive layer 2 is a gate metal layer Ga and has a gate Tg of each transistor T, and the second conductive layer 4 is an active layer Poly or a source-drain metal layer SD. As shown in Figure 1 , taking the second conductive layer 4 as the active layer Poly as an example, in this case, the second conductive layer 4 has an active portion Tp of each transistor T, and the array substrate 10 further includes a fourth conductive layer 8 located on the side of the second conductive layer 4 facing away from the substrate 1. The fourth conductive layer 8 is a source-drain metal layer SD and has a source and drain Tsd of each transistor T. As shown in Figure 2 , taking the second conductive layer 4 as the source-drain metal layer SD as an example, the first conductive layer 2 has a source and drain Tsd of each transistor T, and the array substrate 10 further includes a fourth conductive layer 8 located on the side of the second conductive layer 4 close to the substrate 1. The fourth conductive layer 8 is an active layer Poly and has an active portion Tp of each transistor T.

[0107] It can be understood that, in combination with the film layer structure of the array substrate 10 shown in Figures 1 and 2, and the film layer structure of the array substrate 10 shown in Figures 5 and 6, when the transistor T is set to a bottom gate structure, the setting of one insulating layer can be reduced, thereby facilitating the ultra-thinning of the array substrate 10.

[0108] In some embodiments, when the first conductive layer 2 is a gate metal layer Ga and the second conductive layer 4 is a source / drain metal layer SD, as shown in FIG4 , the first conductive layer 2 includes a gate line Gate extending along a second direction Y and connected to the gate electrode Tg, and the second conductive layer 4 includes a data line Date extending along a first direction X and connected to the source / drain electrode Tsd, as well as an auxiliary electrode line L2 connected to the second auxiliary electrode 41. Thus, by placing the auxiliary electrode line L2 above the gate line Gate, the data line Date is prevented from crossing over both the gate line Gate and the auxiliary electrode line L2, thereby reducing the risk of the data line Date being broken or narrowed due to the crossing. Furthermore, when the auxiliary electrode line L2 crosses the gate line Gate, voltage is applied to both ends of the auxiliary electrode line L2 along its extension direction. Therefore, even if the auxiliary electrode line L2 is broken or narrowed in a certain area, the voltage applied to the second auxiliary electrode 41 is not affected, thereby improving the yield of the array substrate 10.

[0109] In the embodiment of the present disclosure, the array substrate 10 has a plurality of pixel areas AA arranged in an array. Each pixel area AA is provided with a transistor T as shown in FIG. 8 or FIG. 9 , or is provided with two transistors T connected in series as shown in FIG. 2 or FIG. 4 .

[0110] Compared to the case where two transistors T are provided in pixel area AA, when one transistor T is provided in pixel area AA, the on-state current of transistor T can be effectively increased (approximately twice the on-state current of two transistors T), thereby improving the charging efficiency of each storage capacitor, thereby avoiding the display smear phenomenon caused by the low charging efficiency of each storage capacitor. In addition, compared to the case where two transistors T are included as shown in Figures 2 or 4, as shown in Figures 8 or 9, when one transistor T is provided in pixel area AA, it is convenient to reduce the size of the area occupied by transistor T in pixel area AA, thereby facilitating the increase in the size of the area occupied by each storage capacitor, so as to provide a plate with a larger orthographic projection area, thereby increasing the total capacitance value of each storage capacitor.

[0111] For the transistor T in each pixel area AA, the source and drain Tsd (source or drain) of the transistor T is electrically connected to the first auxiliary electrode 21 and the pixel electrode 61. At this time, the first auxiliary electrode 21 and the pixel electrode 61 can be directly electrically connected first, and then electrically connected to the source and drain Tsd of the transistor T through the first auxiliary electrode 21 or the pixel electrode 61. Alternatively, the first auxiliary electrode 21 and the pixel electrode 61 can be electrically connected to the source and drain Tsd (source or drain) of the transistor T.

[0112] In some embodiments, as shown in FIG. 2 or FIG. 5 , the array substrate 10 includes a connection line L1, and the source and drain electrodes Tsd (source or drain) of the transistor T are connected to the connection line L1. The connection line L1 is electrically connected to the first auxiliary electrode 21 and the pixel electrode 61. In this way, while the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 are connected in parallel, the transistor T is electrically connected to each storage capacitor.

[0113] Among them, the source and drain electrodes Tsd of the transistor T are located in the source and drain metal layer SD, and the connecting line L1 can be set in the same layer as the source and drain electrodes Tsd of the transistor T and form an integrated structure to ensure that the source and drain electrodes Tsd of the transistor T are directly connected to the connecting line L1, thereby simplifying the manufacturing process of the source and drain electrodes Tsd of the transistor T and the connecting line L1.

[0114] In combination with the film layer structure described above, as shown in Figure 1, the second conductive layer 4 is an active layer Poly, that is, the active part Tp of the transistor T is located in the second conductive layer 4. At this time, the array substrate 10 includes a fourth conductive layer 8 as a source-drain metal layer SD, the source and drain electrodes Tsd of the transistor T, and the connecting line L1 are located in the fourth conductive layer 8, and the source and drain electrodes Tsd of the transistor T are directly connected to the active part Tp of the transistor T; as shown in Figure 2, the second conductive layer 4 is a source-drain metal layer SD, the source and drain electrodes Tsd and the connecting line L1 of the transistor T are both located in the second conductive layer 4. At this time, the array substrate 10 includes a fourth conductive layer 8 as an active layer Poly, the active part Tp of the transistor T is located in the fourth conductive layer 8, and the source and drain electrodes Tsd of the transistor T are directly connected to the active part Tp of the transistor T.

[0115] Among them, as shown in Figure 1, for the case where the connecting line L1 and the second auxiliary electrode 41 are in different layers (the connecting line L1 is located in the fourth conductive layer 8 (source-drain metal layer SD), and the second auxiliary electrode 41 is located in the second conductive layer 4 (active layer Poly)), in order to avoid the situation where the connecting line L1 overlaps with the second auxiliary electrode 41, the spacing between the connecting line L1 and the second auxiliary electrode 41 can be set to be greater than or equal to 4 microns. In this way, the effective exposure area of ​​the fourth conductive layer 8 can be effectively guaranteed, thereby preventing the connecting line L1 from overlapping the second auxiliary electrode 41. For example, the spacing between the connecting line L1 and the second auxiliary electrode 41 is 4 microns, 5 microns, 6 microns, etc. Of course, with the further development of exposure technology, the spacing between the connecting line L1 and the second auxiliary electrode 41 may also be slightly less than 4 microns, as long as the connecting line L1 can be prevented from overlapping the second auxiliary electrode 41 after the fourth conductive layer 8 is exposed.

[0116] Among them, as shown in Figure 2, for the case where the connecting line L1 and the second auxiliary electrode 41 are in the same layer (both are located in the second conductive layer 4 (source-drain metal layer SD)), in order to ensure that there is no electrical conduction between the connecting line L1 and the second auxiliary electrode 41, the spacing between the connecting line L1 and the second auxiliary electrode 41 can be set to be greater than or equal to 4 microns. In this way, the effective exposure distance between the connecting line L1 and the second auxiliary electrode 41 can be guaranteed to avoid electrical conduction between the connecting line L1 and the second auxiliary electrode 41. For example, the spacing between the connecting line L1 and the second auxiliary electrode 41 is 4 microns, 5 microns, 6 microns, etc. Of course, with the further development of exposure technology, the spacing between the connecting line L1 and the second auxiliary electrode 41 can also be slightly less than 4 microns, as long as electrical conduction between the connecting line L1 and the second auxiliary electrode 41 can be avoided after the second conductive layer 4 is exposed.

[0117] In the embodiment of the present disclosure, when the connecting line L1 is electrically connected to the first auxiliary electrode 21 and the pixel electrode 61 respectively, it can be as shown in Figure 2 or Figure 5, that is, the connecting line L1 is electrically connected to the first auxiliary electrode 21 through the first via hole 31 passing through the first insulating layer 3, and is electrically connected to the pixel electrode 61 through the second via hole 51 passing through the second insulating layer 5.

[0118] Among them, for the case where the first insulating layer 3 has a first via 31 and the second insulating layer 5 has a second via 51, it can be as shown in Figure 2 or Figure 5, where the orthographic projection of the first via 31 is located outside the orthographic projection of the second via 51; it can also be as shown in Figure 10 or Figure 11, where the orthographic projection of the first via 31 and the orthographic projection of the second via 51 have an overlapping area.

[0119] As shown in FIG12 or FIG13 , the second auxiliary electrode 41 has a first step surface 411 facing the connection line L1 in a first direction X, and a second step surface 412 adjacent to the first step surface 411 in a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y.

[0120] The first dimension M1 between the first stepped surface 411 and the second via 51 in the first direction X is defined as a first dimension M1. The second dimension M2 between the second stepped surface 412 in the first direction X is defined as a second dimension M2. Both the first dimension M1 and the second dimension M2 are greater than 0. When the orthographic projection of the first via 31 is located outside the orthographic projection of the second via 51, as shown in FIG12 , the first via 31 is located between the second via 51 and the second auxiliary electrode 41 in the first direction X, and the first dimension M1 is greater than the second dimension M2. When the orthographic projections of the first via 31 and the second via 51 overlap, as shown in FIG13 , the first dimension M1 is smaller than the second dimension M2.

[0121] Therefore, compared with the situation shown in Figure 12 where the orthographic projection of the first via 31 is located outside the orthographic projection of the second via 51, as shown in Figure 13, the situation where the orthographic projection of the first via 31 and the orthographic projection of the second via 51 have overlapping areas can effectively reduce the size of the connecting line L1 in the first direction X. At the same time, while ensuring the spacing between the connecting line L1 and the second auxiliary electrode 41, the size of the corresponding area of ​​the first step surface 411 in the first direction X can be effectively increased. In this way, it is convenient to increase the effective overlapping area of ​​multiple storage capacitors, thereby increasing the capacitance value of each storage capacitor.

[0122] Furthermore, the first via 31 and the second via 51 can be arranged to coincide with each other along the center lines of the thickness direction of the substrate 1, so that the size of the connecting line L1 in the first direction X can be minimized to the maximum extent, thereby further increasing the size of the corresponding area of ​​the first step surface 411 in the first direction X, thereby increasing the capacitance value of each storage capacitor.

[0123] In the embodiment of the present disclosure, the isolation layer 7 included in the array substrate 10 can be located between the second conductive layer 4 and the second insulating layer 5 as shown in FIG. 10 or 11 , or between the second insulating layer 5 and the third conductive layer 6 .

[0124] The isolation layer 7 can be made of inorganic material or organic resin, and the hollowed area 71 on the isolation layer 7 can be removed by exposure and etching. The isolation layer 7 can be reused as a flat layer or dielectric layer based on organic resin material.

[0125] 10 or 11 , the thickness of the isolation layer 7 is greater than the thickness of the second insulating layer 5 , and the orthographic projection of the hollowed-out area 71 is located outside the orthographic projection of the source and drain electrodes Tsd, and the orthographic projection of the pixel electrode 61 covers the orthographic projection of the source and drain electrodes Tsd.

[0126] In this manner, by providing the pixel electrode 61 to cover the source and drain Tsd of the transistor T, electric field disturbances in the region of the pixel area AA where the transistor T is provided are avoided, thereby effectively ensuring efficient driving of the electronic ink of the electrophoretic layer 30 and preventing the occurrence of localized graying during display. Furthermore, when the pixel electrode 61 covers the source and drain Tsd of the transistor T, the provision of the isolation layer 7 effectively increases the distance between the pixel electrode 61 of the third conductive layer 6 and the region of the pixel area AA where the transistor T is provided, in the thickness direction of the substrate 1, thereby preventing the formation of an integrated capacitor, thereby avoiding an increase in load and the generation of leakage current.

[0127] Optionally, the pixel electrode 61 is a rectangular structure (i.e., there is no groove at the edge of the pixel electrode 61). For example, as shown in FIG3 , the pixel electrode 61 covers the entire pixel area AA to effectively ensure the driving of the electronic ink in the area corresponding to the pixel electrode 61 on the electrophoretic layer 30.

[0128] In the present disclosure, in combination with the above-mentioned case where the second insulating layer 5 has the second via 51, it can be as shown in Figure 10, where the orthographic projection of the hollowed-out area 71 on the isolation layer 7 is located outside the orthographic projection of the second via 51. At this time, the second via 51 penetrates the isolation layer 7 while penetrating the second insulating layer 5 to ensure the electrical connection between the pixel electrode 61 and the connecting line L1; of course, it can also be as shown in Figure 11, where the orthographic projection of the hollowed-out area 71 on the isolation layer 7 covers the orthographic projection of the second via 51. At this time, there is only the second insulating layer 5 between the pixel electrode 61 and the connecting line L1. Therefore, the second via 51 only needs to penetrate the second insulating layer 5 to realize the connection between the pixel electrode 61 and the connecting line L1.

[0129] Among them, compared with the situation shown in Figure 13 where the orthographic projection of the hollowed-out area 71 on the isolation layer 7 is located outside the orthographic projection of the second via 51, as shown in Figure 14, the situation where the orthographic projection of the hollowed-out area 71 on the isolation layer 7 covers the second via 51 effectively increases the hollowed-out area 71 on the isolation layer 7, thereby facilitating the effective overlapping area of ​​the second auxiliary electrode 41 and the pixel electrode 61 in the hollowed-out area 71, thereby effectively increasing the capacitance value of the second storage capacitor Cst2.

[0130] It should be noted that the orthographic projections referred to in this disclosure all refer to projections onto the substrate along the thickness direction of the substrate. For the isolation layer 7 shown in Figures 12, 13, and 14, the areas shown are all cutout areas. In Figures 12 and 13, the larger cutout areas are used to form the hollowed-out regions 71, while the smaller cutout areas are used to achieve electrical connection between the pixel electrode 61 and the connecting line L1. In Figure 14, the entire cutout area forms the hollowed-out region 71 while achieving electrical connection between the pixel electrode 61 and the connecting line L1.

[0131] The embodiment of the present disclosure further provides a method for manufacturing an array substrate, as shown in FIG15 , the method includes the following steps S1510 to S1570 .

[0132] Step S1510: providing a substrate;

[0133] Step S1520: forming a first conductive layer on one side of the substrate, wherein the first conductive layer has a first auxiliary electrode;

[0134] Step S1530: forming a first insulating layer on a side of the first conductive layer facing away from the substrate, wherein the first insulating layer at least covers the first auxiliary electrode;

[0135] Step S1540: forming a second conductive layer on a side of the first insulating layer facing away from the substrate, wherein the second conductive layer has a second auxiliary electrode;

[0136] Step S1550: forming a second insulating layer on a side of the second conductive layer facing away from the substrate, wherein the second insulating layer at least covers the second auxiliary electrode;

[0137] Step S1560: forming a third conductive layer on a side of the second insulating layer facing away from the substrate, wherein the third conductive layer has a pixel electrode, and the orthographic projections of the first auxiliary electrode, the second auxiliary electrode, and the pixel electrode all overlap, and the pixel electrode is electrically connected to the first auxiliary electrode.

[0138] And step S1570, forming an isolation layer between the second conductive layer and the third conductive layer, the isolation layer having a hollowed-out area, and an orthographic projection of the hollowed-out area overlaps with an orthographic projection of the second auxiliary electrode.

[0139] As such, since the first auxiliary electrode is electrically connected to the pixel electrode, when a display device having this array substrate is displaying, the voltage applied to the first auxiliary electrode is the same as the voltage applied to the pixel electrode, both being the pixel voltage. That is, the first auxiliary electrode also acts as a pixel electrode. Thus, the first auxiliary electrode and the second auxiliary electrode can form a first storage capacitor, the pixel electrode and the second auxiliary electrode can form a second storage capacitor in the hollowed-out region of the isolation layer, and the pixel electrode and the second auxiliary electrode can form a third storage capacitor in the non-hollowed-out region of the isolation layer. The first, second, and third storage capacitors are connected in parallel, thereby increasing the total storage capacitance of the pixel circuit while increasing the number of pixel regions on the array substrate. Furthermore, for a display device having this array substrate, it is possible to increase the PPI while ensuring a larger storage capacitor value, thereby avoiding the phenomenon of smearing during display.

[0140] The specific structure of the array substrate manufactured by the above method can be referred to the above embodiment, and will not be described in detail in the embodiments of the present disclosure.

[0141] It should be noted that although the above method describes the various steps of the array substrate manufacturing method of the present disclosure in a specific order, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0142] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. An array substrate, characterized in that: include: substrate; A first conductive layer, located on one side of the substrate and having a first auxiliary electrode; a first insulating layer, located on a side of the first conductive layer away from the substrate and at least covering the first auxiliary electrode; a second conductive layer, located on a side of the first insulating layer away from the substrate, and having a second auxiliary electrode; a second insulating layer, located on a side of the second conductive layer away from the substrate and at least covering the second auxiliary electrode; a third conductive layer, located on a side of the second insulating layer away from the substrate, and having a pixel electrode, wherein an orthographic projection of the first auxiliary electrode, an orthographic projection of the second auxiliary electrode, and an orthographic projection of the pixel electrode all have overlapping areas, and the pixel electrode is electrically connected to the first auxiliary electrode; The isolation layer is located between the second conductive layer and the third conductive layer and has a hollowed-out area, and an orthographic projection of the hollowed-out area overlaps with an orthographic projection of the second auxiliary electrode.

2. The array substrate according to claim 1, characterized in that: The array substrate includes a transistor and a connecting line, the transistor includes a source and a drain, the source and the drain are connected to the connecting line, the connecting line is electrically connected to the first auxiliary electrode through a first via hole penetrating the first insulating layer, and is electrically connected to the pixel electrode through a second via hole penetrating the second insulating layer.

3. The array substrate according to claim 2, characterized in that: The thickness of the isolation layer is greater than that of the second insulating layer, and the orthographic projection of the hollowed-out area is located at the periphery of the orthographic projection of the source and drain electrodes, and the orthographic projection of the pixel electrode covers the orthographic projection of the source and drain electrodes.

4. The array substrate according to claim 2, characterized in that: The source and drain electrodes and the connecting wires are located in the second conductive layer.

5. The array substrate according to claim 4, characterized in that: The distance between the connecting line and the second auxiliary electrode is greater than or equal to 4 micrometers.

6. The array substrate according to claim 2, characterized in that: The transistor includes an active portion, wherein the active portion is located in the second conductive layer; The array substrate further includes a fourth conductive layer, the fourth conductive layer is located between the second conductive layer and the second insulating layer, the source and drain electrodes and the connecting wires are located in the fourth conductive layer, and the The source and drain are overlapped with the active portion.

7. The array substrate according to any one of claims 2 to 6, characterized in that: The orthographic projection of the hollowed-out area is outside the orthographic projection of the second via hole, and the second via hole penetrates the isolation layer.

8. The array substrate according to any one of claims 2 to 6, characterized in that: The orthographic projection of the hollowed-out area covers the orthographic projection of the second via hole.

9. The array substrate according to any one of claims 2 to 6, characterized in that: The orthographic projection of the first via hole is located at the periphery of the orthographic projection of the second via hole; The second auxiliary electrode has a first step surface facing the connecting line in the first direction, and a second step surface adjacent to the first step surface in the second direction. In the first direction, the first via is located between the second via and the second auxiliary electrode, and a first size of the first step surface and the second via in the first direction is greater than a second size of the second step surface in the first direction, and the first direction intersects with the second direction.

10. The array substrate according to any one of claims 2 to 6, characterized in that: The orthographic projection of the first via hole and the orthographic projection of the second via hole have an overlapping area; The second auxiliary electrode has a first step surface facing the connecting line in the first direction, and a second step surface adjacent to the first step surface in the second direction, and a first dimension of the first step surface and the second via in the first direction is smaller than a second dimension of the second step surface in the first direction.

11. The array substrate according to claim 10, characterized in that: Center lines of the first via hole and the second via hole along the thickness direction of the substrate coincide with each other.

12. The array substrate according to any one of claims 2 to 6, characterized in that: The transistor further includes a gate, and the gate is located in the first conductive layer.

13. The array substrate according to claim 12, wherein: The first conductive layer has a gate line extending along the second direction and connected to the gate electrode, the second conductive layer has a data line extending along the first direction and connected to the source and drain electrode, and an auxiliary electrode line connected to the second auxiliary electrode.

14. The array substrate according to any one of claims 2 to 6, characterized in that: The array substrate has a plurality of pixel areas arranged in an array, and each pixel area is provided with one transistor or two transistors connected in series.

15. The array substrate according to any one of claims 1 to 6, characterized in that: The isolation layer is located between the second conductive layer and the second insulating layer.

16. The array substrate according to any one of claims 1 to 6, characterized in that: The orthographic projection of the hollowed-out area covers the orthographic projection of the second auxiliary electrode, and the first auxiliary electrode, the second auxiliary electrode and the pixel electrode form two storage capacitors connected in parallel.

17. The array substrate according to any one of claims 1 to 6, characterized in that: The orthographic projection of the second auxiliary electrode extends out of the orthographic projection of the hollowed-out area, and the first auxiliary electrode, the second auxiliary electrode and the pixel electrode form three storage capacitors connected in parallel.

18. A display device, characterized in that: It comprises a cover plate and the array substrate according to any one of claims 1 to 17, wherein the cover plate is arranged opposite to the array substrate; The display device further includes an electrophoretic layer located between the array substrate and the cover plate.

19. A method for manufacturing an array substrate, characterized in that: The method comprises: providing a substrate; A first conductive layer is formed on one side of the substrate, wherein the first conductive layer has a first auxiliary electrode; forming a first insulating layer on a side of the first conductive layer away from the substrate, wherein the first insulating layer at least covers the first auxiliary electrode; Forming a second conductive layer on a side of the first insulating layer away from the substrate, wherein the second conductive layer has a second auxiliary electrode; forming a second insulating layer on a side of the second conductive layer facing away from the substrate, wherein the second insulating layer at least covers the second auxiliary electrode; A third conductive layer is formed on a side of the second insulating layer away from the substrate, the third conductive layer has a pixel electrode, an orthographic projection of the first auxiliary electrode, an orthographic projection of the second auxiliary electrode, and an orthographic projection of the pixel electrode all have overlapping areas, and the pixel electrode is electrically connected to the first auxiliary electrode; An isolation layer is formed between the second conductive layer and the third conductive layer, wherein the isolation layer has a hollowed-out area, and an orthographic projection of the hollowed-out area overlaps with an orthographic projection of the second auxiliary electrode.

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