Image management method, chip, image transmission method and electronic device

Abstract

The present application relates to the field of data transmission and provides an image management method, a chip, an image transmission method and an electronic device. The image management method comprises: in response to writing an image block, allocating an address granule to the image block, each address granule corresponding to a different cache region in a cache; storing the image block into the cache region corresponding to the address granule; if the cache region corresponding to the address granule is fully filled with data of the image block, writing into a preset information memory the address of the cache region corresponding to the address granule, the information memory being configured to provide to an acquirer of the image block the address of the cache region corresponding to the address granule and, on the basis of the address of the cache region corresponding to the address granule, the acquirer being configured to acquire the image block from the cache. The image management method can reduce chip area required for temporarily storing image blocks during image transmission processes.

Description

Image management method, chip, image transmission method and electronic device Technical Field

[0001] The present application relates to the field of image transmission, and more specifically, to an image management method, a chip, an image transmission method, and an electronic device. Background Art

[0002] Image data is compressed during image transmission to improve transmission efficiency. Image compression typically involves converting image data into image blocks, which are then arranged in a linear sequence before being read out.

[0003] Arranging image blocks in a linear order requires a large amount of storage space to temporarily store them. Currently, registers are used for this purpose. When the image width of the image blocks to be stored is large, or when the number of rows of image blocks is large, the storage space required for the image blocks increases, and the number of registers required increases. However, excessive registers occupy a large chip area, impacting subsequent circuit design and wiring. Furthermore, when writing multiple rows of image blocks simultaneously, additional storage space is required to store the addresses of each row of data, further increasing the register area.

[0004] Summary of the Invention

[0005] The present application aims to provide an image management method, a chip, an image transmission method and an electronic device to reduce the chip area required for a circuit for temporarily storing image blocks during image data transmission.

[0006] In a first aspect, an embodiment of the present application provides an image management method, comprising: in response to the writing of an image block, allocating an address granule to the image block; each of the address granules corresponds to a different cache area in a cache, and the address granule is data recording the address of the corresponding cache area; the cache includes multiple cache areas of a first preset size; the image block is stored in the cache area corresponding to the address granule; if the cache area corresponding to the address granule is fully stored with the data of the image block, the address of the cache area corresponding to the address granule is written into a preset information storage; the information storage is configured to provide the address of the cache area corresponding to the address granule to the acquirer of the image block; the acquirer is configured to obtain the image block from the cache based on the address of the cache area corresponding to the address granule.

[0007] Compared to registers, buffers require less chip area to store the same amount of image blocks. In embodiments of the present application, using a buffer to store image blocks can reduce the chip area occupied by the circuitry that temporarily stores image blocks during image transmission. Buffers can be directly controlled by the processor. Compared to registers, buffers store larger amounts of data and require control via read and write instructions. If image blocks stored in the buffer are not recorded, problems such as overwriting and duplicate reads may occur. Therefore, in embodiments of the present application, address granules can be used to record the storage and reading of image blocks. If the address of the cache area corresponding to the address granule is within a preset information memory, it indicates that the image block stored in the cache area can be read and that the image block corresponding to the address granule cannot be overwritten by new data. Therefore, when multiple rows of image blocks are written consecutively or simultaneously in a short period of time, the address granules can ensure that the image blocks are accurately output, reducing the possibility of data loss. Thus, by using address granules and a buffer, it is possible to achieve normal storage, management, and output of image blocks while reducing chip area.

[0008] In one embodiment, before allocating address granules to the image block, the method further includes: determining configuration parameters of the cache according to a preset conversion format; the configuration parameters are used to configure the cache; the preset conversion format is a preset compression format of the image block, and the preset conversion format includes the maximum image width of the image block, and the arrangement of the Y component and UV component of the pixels in the image block; the Y component is the brightness of the pixel, and the UV component is the chroma of the pixel; the configuration parameters of the cache include the number, width and depth of cache units in the cache; multiple cache units constitute the cache, and the total storage space of the multiple cache units is divided into multiple cache areas.

[0009] During the image transmission process, the format of the image block obtained by converting the image data can be predetermined. In the embodiment of the present application, the configuration parameters of the buffer can be determined according to the format of the image block. Thus, the configured buffer can be able to meet the current image transmission requirements while using a smaller buffer storage space to achieve image transmission, thereby rationally utilizing storage resources, so that the buffer resources can be applied to other scenarios and reduce resource waste.

[0010] In one embodiment, after determining the configuration parameters of the cache according to the preset conversion format, the method further includes: setting the number of address granules and the first preset size based on the configuration parameters of the cache and the preset conversion format.

[0011] In an embodiment of the present application, the number of address granules and the first preset size can be dynamically configured according to the configuration parameters of the cache and the preset conversion format, so that the number of address granules and the first preset size can be consistent with the image block format and cache configuration in the current image transmission process, thereby reducing the waste of storage space caused by the inconsistency between the first preset size and the image block format, improving the utilization rate of the cache area of ​​the cache, and thus reducing the chip area occupied by the cache.

[0012] In one embodiment, the information memory includes multiple information memories corresponding to the Y component and multiple information memories corresponding to the UV component; writing the address of the cache area corresponding to the address granule into a preset information memory includes: according to the type of pixel point component written into the cache area, writing the address corresponding to the cache area into the information memory corresponding to the component type; the pixel point component type includes the Y component and the UV component.

[0013] In the embodiments of the present application, different cache areas are used to store different pixel components, and different information memories are used to store the addresses of the cache areas corresponding to different pixel components. Thus, the addresses of the Y and UV components corresponding to the caches are obtained from the different information memories, and then the corresponding Y or UV components are obtained from the corresponding cache areas in the caches based on the addresses. By storing the Y and UV components separately, it is easier to accurately distinguish the Y and UV components to obtain the required component types, reducing the difficulty of managing image blocks and the possibility of confusion.

[0014] In one embodiment, after writing the granule information of the address granule into a preset information memory, the method further includes: providing the acquirer with the address of the cache area corresponding to the address granule via the information memory, so that the acquirer reads the image block from the cache area based on the address of the cache area corresponding to the address granule; and in response to the image block in the cache area being read out, releasing the address granule corresponding to the cache area, wherein the released address granule indicates that the cache area corresponding to the address granule allows the writing of a new image block.

[0015] In the embodiments of the present application, after an image block is read from the cache area, the address granule corresponding to that cache area is released. This address granule can then be reallocated to a newly written image block, allowing the newly written image block to be stored in the cache area. By storing and releasing address granules in the information memory, image block address management is achieved, reducing the risk of image blocks being overwritten and lost by new image blocks, thereby improving image transmission accuracy. Furthermore, address granules occupy less space, allowing image block address management to be implemented using a smaller chip area.

[0016] In one embodiment, the image block includes a UV component, which is the chromaticity of a pixel; the information memory includes a plurality of memory cells; before releasing the address granule, the method further includes: if it is determined based on an initial format of the image block when it is written and a target format when it is written that the read UV component needs to be reused, then the address of the cache area corresponding to the address granule is rewritten into the next information memory cell.

[0017] The transmission process of an image block may involve compression and image block format conversion, which makes the initial format and the target format different. Compression and conversion mainly involve UV components. Therefore, if the image block needs to be restored or converted into the target format, the UV component needs to be reused. In the embodiment of the present application, if the UV component needs to be reused, the address of the cache area corresponding to the address particle is rewritten into the next information storage device. Therefore, for the same UV component, there is no need to store it twice in the cache due to reuse. It is only necessary to write the address to the next information storage device and use the address of the next information storage device to read it again. Compared with the cache device for storing image blocks, the information storage device for storing addresses occupies a smaller chip area, which can reduce the problem of excessive chip area caused by reuse of UV components.

[0018] In one embodiment, the image block to be written includes multiple image blocks. Before assigning address granules to the image blocks, the method further includes: shifting the multiple input image blocks and splicing them into image blocks of a second preset size. Correspondingly, after providing the acquirer with the address of the cache area corresponding to the address granule through the information storage, the method further includes: shifting the image blocks in the cache area corresponding to the address granule to restore the arrangement order of the image blocks to the order when they were input.

[0019] In an embodiment of the present application, multiple image blocks are shifted and spliced ​​to unify the size of the input image blocks, so that image blocks of different sizes can be written in the same size to meet the usage requirements of different scenarios and expand the scope of use. At the same time, the difficulty of managing image blocks of different sizes is reduced, and the use of circuits for managing image blocks of different sizes is reduced, thereby reducing the occupied chip area.

[0020] In a second aspect, an embodiment of the present application provides an image management chip, comprising: a cache, comprising multiple cache areas of a first preset size; an address resource pool, storing multiple address granules, and different address granules correspond to different cache areas; the address granules are data recording the addresses of corresponding cache areas; a write cache module, connected to the address resource pool and the cache; multiple information memories, each of which is connected to the write cache module; the write cache module is configured to receive written image blocks; the address resource pool is configured to allocate address granules to the image blocks in response to the writing of the image blocks; the write cache module is also configured to store the image blocks in the cache areas corresponding to the address granules; and the write cache module is further configured to write the addresses of the cache areas corresponding to the address granules into the information memory if the cache areas corresponding to the address granules are full of the data of the image blocks; the information memory is configured to provide the addresses of the cache areas corresponding to the address granules to the acquirer of the image blocks; the acquirer is configured to acquire the image blocks from the cache based on the addresses of the cache areas corresponding to the address granules.

[0021] In one embodiment, the buffer is configured to determine the configuration parameters of the buffer according to a preset conversion format; the configuration parameters are used to configure the buffer; the preset conversion format is a preset compression format of the image block, and the preset conversion format includes the maximum image width of the image block, the arrangement of the Y component and the UV component of the pixel points in the image block; the Y component is the brightness of the pixel point, and the UV component is the chroma of the pixel point; the configuration parameters of the buffer include the number, width and depth of the cache units in the buffer; multiple cache units constitute the buffer, and the total storage space of the multiple cache units is divided into multiple cache areas.

[0022] In one embodiment, the buffer is further configured to set the number of address granules and the first preset size based on configuration parameters of the buffer and the preset conversion format.

[0023] In one embodiment, the multiple information memories include multiple information memories corresponding to the Y component and multiple information memories corresponding to the UV component; the write cache module is further configured to also include: according to the type of pixel point component written into the cache area, writing the address corresponding to the cache area into the information memory corresponding to the component type; the pixel point component type includes the Y component and the UV component.

[0024] In one embodiment, the image management device further includes: a read cache module, configured to be connected to the cache, the address resource pool and the information storage device respectively; wherein the read cache module is configured as the acquirer; the read cache module is further configured to obtain the address of the cache area corresponding to the address granule stored in the information storage device, so as to read and output the image block in the cache area corresponding to the address granule from the cache device based on the address of the cache area corresponding to the address granule; the read cache module is further configured to release the address granule corresponding to the cache area in response to the image block in the cache area being read out, and the released address granule indicates that the cache area corresponding to the address granule allows new image blocks to be written.

[0025] In one embodiment, the image block includes a UV component, which is the chromaticity of a pixel point; the buffer is further configured to: if it is determined based on the initial format of the image block when it is written and the target format when it is written, whether the read UV component needs to be reused, then rewrite the address of the cache area corresponding to the address granule into the next information storage.

[0026] In one embodiment, the image management chip further includes: an input data shift module, configured to be connected to the write cache module, for receiving written image blocks, and shifting and splicing the input multiple image blocks into image blocks of a second preset size; an output data shift module, connected to the read cache module, for shifting the image blocks output by the read cache module to restore the pixels in the image blocks to the order of input.

[0027] In a third aspect, an embodiment of the present application provides an image transmission method, comprising: after compressing image data into image blocks, a first device stores the image blocks based on an image management chip as described in any one of the second aspects; and a second device sends a read instruction to the image management chip to read the image blocks from the image management chip.

[0028] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: an image management chip as described in any one of the second aspects.

[0029] In the embodiments of the present application, the use of a buffer to store image blocks can reduce the chip area occupied by the circuitry that temporarily stores image blocks during image transmission. Address granules are used to record the storage and readout of image blocks. When multiple rows of image blocks are written consecutively or simultaneously within a short period of time, the address granules can ensure accurate output of the image blocks, reducing the possibility of data loss. Thus, by using address granules and a buffer, it is possible to achieve normal storage, management, and output of image blocks while reducing chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0031] FIG1 is a schematic diagram of an image management chip provided in one embodiment of the present application;

[0032] FIG2 is a schematic diagram of an expansion of an image management chip provided in one embodiment of the present application;

[0033] FIG3 is a schematic diagram of an image block provided by an embodiment of the present application;

[0034] FIG4 is a schematic diagram of a row of image blocks provided by an embodiment of the present application

[0035] FIG5 is a flowchart of an image management method provided by an embodiment of the present application;

[0036] FIG6 is a schematic diagram of a cache unit provided in an embodiment of the present application;

[0037] FIG7 is a schematic diagram of a Y component provided in an embodiment of the present application;

[0038] FIG8 is a schematic diagram of UV components provided by an embodiment of the present application;

[0039] FIG9 is a schematic diagram of multiple rows of image blocks provided by an embodiment of the present application;

[0040] FIG10 is a schematic diagram of writing multiple rows of image blocks according to an embodiment of the present application;

[0041] FIG11 is a schematic diagram of address granularity redistribution in a first scenario provided by an embodiment of the present application;

[0042] FIG12 is a schematic diagram of address granularity redistribution in a second scenario provided by an embodiment of the present application;

[0043] FIG13 is a schematic diagram of an application scenario of an image transmission method provided in an embodiment of the present application;

[0044] FIG14 is a flowchart of an image transmission method provided in an embodiment of the present application.

[0045] Icons: image management chip 100; cache 110; address resource pool 120; write cache module 130; information storage 140; read cache module 150; input data shift module 160; output data shift module 170; first device 310; second device 320. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0047] Please refer to FIG1 , which is a schematic diagram of an image management chip provided in accordance with an embodiment of the present application. The image management chip includes a buffer 110 , an address resource pool 120 , a write cache module 130 , and an information memory 140 .

[0048] The cache 110 includes multiple cache units. The cache units may be SRAM (Single Port Random-Access Memory), but this is not a limitation.

[0049] In this embodiment, the storage space of the buffer 110 is the sum of the storage spaces of the multiple cache units. The storage space of the buffer 110 can be divided into multiple cache areas of a first preset size as required, with different cache areas storing different image blocks. The first preset size is the same between the cache areas.

[0050] The cache 110 further includes a cache controller, which is connected to the write cache module 130, the address resource pool 120 and each cache unit respectively to control each part of the image management chip to implement the functions of the image management method provided in this application.

[0051] The address resource pool 120 is connected to the cache 110 , wherein the address resource pool 120 stores a plurality of address granules, and different address granules correspond to different cache areas.

[0052] In this embodiment, the address resource pool 120 may include a memory, the storage space of which may be divided into different areas of the same size. Each area stores the address of a cache area in the cache 110, and the address granule includes the cache area address and the corresponding area in the memory.

[0053] The write cache module 130 is connected to the address resource pool 120 and the cache 110 .

[0054] In this embodiment, the write cache module 130 includes a memory, so that the write cache module 130 can receive and temporarily store written image blocks.

[0055] A plurality of information memories 140 are connected to the write cache module 130. The information memories 140 may be registers, FIFOs (First In First Out), etc., for storing cache area addresses corresponding to address granules.

[0056] The data of the image block includes different types of pixel components. For example, during image transmission, the image is compressed into a YUV (a color encoding method) format. The image block in the YUV format includes a Y component, a U component, and a V component, where Y represents brightness, and U and V represent chroma (or color saturation). In this embodiment, the Y component and UV component of the image block can be stored in different buffers 110, respectively. Accordingly, different information memories 140 can be used to store the cache area addresses of different components, respectively.

[0057] In an embodiment of the present application, after the write cache module 130 receives a written image block, the address resource pool 120 may allocate an address granule to the written image block and send the address granule to the write cache module 130. The write cache module 130 is further configured to store the image block in a cache area corresponding to the address granule.

[0058] In the embodiment of the present application, when the cache area corresponding to an address granule is fully stored with image block data, the address of the cache area corresponding to the address granule can be stored in information memory 140, indicating that the image block can be read. At the same time, if the address of the cache area corresponding to the address granule is stored in information memory 140, the address granule will not be reallocated to prevent newly written image blocks from overwriting unread image blocks, thereby reducing the possibility of data loss.

[0059] Accordingly, the address of the cache area corresponding to the address granule is written into the information memory 140 ; ​​the information memory 140 is configured to provide the address of the cache area corresponding to the address granule to the acquirer of the image block.

[0060] The acquirer may be a receiver in the image transmission process. The acquirer is configured to connect to the information storage 140, the buffer 110, and the address resource pool 120. The acquirer may acquire an image block from the buffer 110 based on the address of the buffer area corresponding to the address granule provided by the information storage 140. After acquiring the image block from the buffer 110, the acquirer may also release the address granule back to the address resource pool 120 so that the address granule can be allocated to a newly written image block and the buffer area corresponding to the address granule can be overwritten by the newly written image block.

[0061] Please refer to FIG. 2 , which is a schematic diagram of an expansion of an image management chip provided in an embodiment of the present application.

[0062] In one embodiment, the image management chip may further include a read cache module 150. The read cache module 150 is configured to be connected to the cache 110, the address resource pool 120, and the information storage device respectively.

[0063] In this embodiment, the read cache module 150 is configured as an acquirer, and the receiver during the image transmission process is connected to the read cache module 150. The receiver during the image transmission process can send instructions to the read cache module 150 to enable the read cache module 150 to obtain the address of the cache area corresponding to the address granule stored in the information memory 140, and enable the read cache module 150 to read the image block in the cache area corresponding to the address granule from the cache 110 based on the address of the cache area corresponding to the address granule and output it.

[0064] Similar to the write cache module 130 , the read cache module 150 may include a memory to temporarily store image blocks read from the cache 110 .

[0065] Accordingly, the read cache module 150 is further configured to release the address granule corresponding to the cache area in response to the image block being read out of the cache area, so that the cache area corresponding to the address granule can store a new image block.

[0066] In one embodiment, the image management chip further includes: an input data shift module 160 configured to be connected to the write cache module 130, for receiving written image blocks, and shifting and splicing the input multiple image blocks into image blocks of a second preset size.

[0067] Please refer to Figures 3 and 4, where P represents a pixel and T represents an image block. As shown in Figure 3, an image block consists of multiple rows, such as L rows. Each row may include multiple pixels, such as K pixels. This results in different image blocks having different lengths and widths. During image transmission, multiple image blocks need to be arranged into a row, as shown in Figure 4. Therefore, the length and width of each image block in a row must match.

[0068] During image transmission, the formats of compressed and converted image blocks may differ. For example, different components may be transmitted, such as the Y component and UV component, where the Y component may be 16×8 and the U component may be 8×4. Images of different frames may also be transmitted, for example, where the image blocks of one frame are 16×8 and those of another frame are 8×4, which may result in different image block formats. Therefore, in this embodiment, an input data shifting module 160 is provided. The input data shifting module 160 can receive image blocks and shift and splice the input multiple image blocks into image blocks of a second predetermined size, thereby ensuring that the image blocks input to the buffer 110 are of uniform size.

[0069] Accordingly, the image management chip further includes an output data shift module 170 connected to the read cache module 150 for shifting the image block output by the read cache module 150 to restore the pixels in the image block to the order of input.

[0070] By shifting and splicing image blocks, the image management chip can temporarily store different types of image blocks to meet the image temporary storage requirements in different image transmission scenarios.

[0071] Based on the same inventive concept, an embodiment of the present application further provides an image management method, which can be applied to the image management chip of any of the above embodiments, wherein the image management chip is respectively connected to the sender and receiver of the image transmission.

[0072] Next, the contents of the above-mentioned image management chip will be expanded in conjunction with the image management method. Please refer to Figure 5, which is a flow chart of an image management method provided by an embodiment of the present application. The image management method includes:

[0073] S110 , in response to writing of an image block, allocating address granules to the image block.

[0074] In this embodiment, after the image data is compressed into an image block by the sender of the image transmission, the image block can be sent to the image management chip. The write cache module 130 in the image management chip can receive the image block, and the address resource pool 120 allocates address particles to the image block in response to the writing of the image block in the write cache module 130.

[0075] In one embodiment, before allocating address granules to the image blocks, the input multiple image blocks may be shifted and spliced ​​into image blocks of a second preset size.

[0076] If the image management chip is required to support the simultaneous writing of multiple image blocks, and the written image blocks can be of different formats, then in this embodiment, the input data shift module 160 of the image management chip can be used to shift and splice the written image blocks, so that the multiple image blocks are shifted and spliced ​​into one or a row of image blocks of a second preset size. Thus, the write cache module 130 and the cache can store and manage image blocks of a unified format, thereby realizing temporary storage management of the simultaneous writing of multiple image blocks.

[0077] In an embodiment of the present application, each address granule corresponds to a different cache area in the cache 110 , and the address granule is data recording the address of the corresponding cache area; the cache 110 includes a plurality of cache areas of a first preset size.

[0078] During the image transmission process, the image block format after image data compression may be different. Accordingly, the first preset size of the cache area may also be different. In addition to storing image blocks, the cache 110 may also store data from other modules. Therefore, when temporarily storing image blocks, a cache 110 should be selected that has a small storage space while realizing the image block temporary storage function.

[0079] In this embodiment, the buffer 110 can be dynamically configured, that is, a larger buffer 110 is provided, which includes multiple buffer units, and the width and depth of the buffer units can be configured as needed. Therefore, when an image is transmitted, the buffer 110 including the buffer units of the required size is used to temporarily store the image block.

[0080] Accordingly, when dynamically configuring the buffer 110, it is necessary to first determine the configuration parameters of the buffer 110. In an embodiment of the present application, before allocating address granules to the image blocks, the cache controller may be configured to determine the configuration parameters of the buffer 110 according to a preset conversion format, so as to configure the buffer 110 based on the configuration parameters.

[0081] In this embodiment, the preset conversion format is a preset compression format of the image block, that is, the format in which the image data is compressed into image blocks during the image transmission process, which can be directly obtained and will not be expanded here.

[0082] The configuration parameters of the cache 110 include the number, width, and depth of cache units in the cache 110. Please refer to FIG6 , which is a schematic diagram of a cache unit according to an embodiment of the present application, wherein Bank Width represents the width of the cache unit, Bank Depth represents the depth of the cache unit, and Granularity 0 to Granularity N represent different address granularities, i.e., one cache unit can correspond to multiple address granularities.

[0083] In this embodiment, one cache unit allows one row of data to be written at the same time. Therefore, multiple cache units can be set in the cache to allow different data to be written at the same time, and each cache unit reads and writes at least one row of image block data at a time, that is, it stores at least the data corresponding to one address particle. The depth of the cache unit can be set according to the size of the data to be stored. In the embodiment of the present application, the number of cache units can be the width of the input image block (that is, the second preset size) divided by the width of the cache unit. The width of a cache unit is equal to the smaller of the size of a row of Y components or the size of a row of UV in the image block. The depth of a cache unit is the storage space size of the cache 110 divided by the width of the cache 110 and then divided by the number of caches 110.

[0084] In addition, if the written image blocks include image blocks of different formats, they can be shifted and spliced ​​into a unified format, and the configuration parameters can be determined in the unified format. That is, the preset conversion format can also be the second preset size of the input shift and splicing module.

[0085] The preset conversion format includes the maximum image width of the image block and the arrangement of the Y component and UV component of the pixels in the image block. For example, the maximum image width of an image block can be 4096 pixels (pixels). Taking NV12 (an image format) as an example, as shown in Figure 7, the Y component is arranged in 16×8, that is, there are 8 rows, 16 Ys in each row, and the size of each Y is 1Bbyte, and each row is 16Bbyte. As shown in Figure 8, the UV component is arranged in 8×4, with a total of 4 rows, 8 UVs in each row, each UV is 2Bbyte, and each row is 16Bbyte. Among them, the Y component and UV component refer to the Y component and UV component of the pixel point. A pixel point includes two parts: the Y component and the UV component. An image block is composed of multiple pixels. The UV component can be a compressed component.

[0086] During image data transmission, image blocks are arranged linearly, with one row of image blocks transmitted at a time. Therefore, buffer 110 stores at least one row of image blocks at a time. For the NV12 format described above, the storage space required to store the Y component is 4096*1*8=32Kbytes, where the maximum image width of the Y component is 4096, 1 ​​represents one Y component, and 8 represents the number of rows of Y components. The space required to store the UV component is 2048*2*4=16Kbytes. Since a single row of UV components contains only 8, the width is half that of the Y component, 2048. Since NV12 uses YUV420 compression, the width of the UV component is half that of the Y component. Since the UV component includes both U and V components, the size of each UV component is 2. Furthermore, the number of UV component rows in a single image block is 4. Therefore, the calculated required size of buffer 110 is 48Kbytes.

[0087] The width of a cache unit is the number of bytes of 1 row of data in the image block (image block width). If multiple image blocks are to be supported, the smallest image block width is selected. For example, in the above example, the width required for a row of Y components or a row of UV components is the same, both 16 bytes, then the width of the cache unit is 16 bytes. If they are different, the smaller one is selected to configure the width of the cache unit. For another example, if the input image block width is required to be 64 bytes, it is necessary to make the width of the multiple image blocks 64 bytes when spliced, and then input the spliced ​​image blocks, and the number of cache units required is 64 / 16=4. Correspondingly, the depth of each cache unit is 48*1024 / 16 / 4=768, that is, the cache 110 includes 4 cache units with a width of 16 bytes and a depth of 768.

[0088] In some scenarios, image blocks are transmitted in rows. As shown in FIG9 , line 0 to line 3 represent different rows of image blocks, each row including N image blocks. Image blocks in different rows need to be transmitted and stored in different cache units. The size of a row of image blocks transmitted in a single transmission may be larger than the first preset size. Therefore, in some embodiments of the present application, a row of image blocks may be assigned to multiple address granules. However, if the data of the image blocks stored in the cache area corresponding to the address granule is small, the storage resources of the cache area will be wasted. For example, if the size of a row of image blocks is 120Kbyte and the size of data that can be stored in each cache area is 50Kbyte, then three address granules and corresponding cache areas need to be allocated to the row of image blocks. The third cache area only stores 20Kbyte, resulting in a waste of 30Kbyte of storage space.

[0089] Based on the above reasons, it is necessary to reasonably set the number of address granules and the first preset size of the corresponding cache area. In some embodiments of the present application, the cache controller can be configured to set the number of address granules and the first preset size based on the configuration parameters of the cache 110 and the preset conversion format.

[0090] For example, the number of address granules and the first preset size can be determined based on the arrangement of the Y component and the UV component in the preset conversion format and the maximum image width. If the maximum image width of the image block is 4096 pixels, taking NV12 as an example, the Y component is 16×8, the UV component is 8×4, and the width of the Y component and UV component is 16Kbyte, then the first preset size can be 1Kbyte. Accordingly, the total storage space of the buffer 110 is 48Kbyte, and 48 cache areas can be divided, setting 48 address granules.

[0091] The maximum image width should be a multiple of the first preset size. For example, if the image width is 768 and the first preset size is set to 1Kbyte, then storing each row of image blocks will result in 1024-768=256 bytes of space being wasted. However, if the first preset size is set to 64bytes, then 768 is a multiple of 64, so there will be no waste.

[0092] Accordingly, the number of information memories 140 can also be determined based on a preset conversion format, where the number of first preset size information memories is equal to the number of rows of each component in the image block. For example, in the NV12 format, there are 8 rows of Y components and 4 rows of NV components. Therefore, 8 information memories 140 are required to store the addresses of the cache areas after the Y components of each row of the image block are stored in the cache area. Therefore, 4 information memories 140 are required to store the addresses of the cache areas after the NV components of each row of the image block are stored in the cache area.

[0093] Next, the storage space size of the information memory 140 can also be configured based on the size of the cache area address corresponding to the address granule and the number of address granules. Since the cache area address corresponding to the address granule may not be read out in a timely manner, the information memory 140 may store multiple addresses. For example, the Y component requires eight information memories 140. The first information memory 140 needs to store the address of the Y component of the 0th row in the image block, as well as the 8th, 16th, 24th, and other rows of the Y component of the image block. The second information memory 140 stores the address of the Y component of the 1st row in the image block, corresponding to the 9th, 17th, 25th, and other rows of the Y component of the image block, and so on. The addresses in the first information memory 140 are read out faster. For example, the first information memory 140 may only need to store four addresses, while the second and third information memories 140 may need to store five addresses, the fourth, sixth, and seventh information memories 140 may need to store six addresses, and the seventh and eighth information memories 140 may need to store seven addresses. If the address size of a cache area is 6 bits, then all memories 140 storing Y component information need to be able to store a size of 6 bits*(4+5*2+6*3+7*2)=276 bits.

[0094] Similarly, four information memories 140 are required to store the UV component. If the first to fourth memories store addresses 4, 5, 6, and 7 respectively, the total storage space of all information memories 140 storing the UV component requires 6*(4+5+6+7)=132 bits.

[0095] S120: Store the image block into the cache area corresponding to the address granule.

[0096] In this embodiment, different address granules correspond to different cache areas. The address granule includes the address of the corresponding cache area. Then, according to the address of the corresponding cache area in the address granule, the image block can be stored in the cache area corresponding to the address of the cache area.

[0097] In an embodiment of the present application, the buffer is configured to allow multiple rows of image blocks to be written.

[0098] For example, FIG10 is a schematic diagram of writing multiple rows of image blocks provided in an embodiment of the present application. The four tables respectively represent records of different address particles stored in image blocks, bank0 to bank3 respectively represent different cache units, T0 to T60 respectively represent image blocks in different rows, and L0 to L3 respectively represent different image blocks in the same row.

[0099] As shown in FIG10 , if a row of image blocks is assigned to multiple address granules, different image blocks in a row of image blocks can be stored in cache units corresponding to different address granules. For example, for the four image blocks L0 to L3 in a row of image blocks T0, the first address granule can be assigned to the first image block in each row of image blocks, the second address granule can be assigned to the second image block in each row of image blocks, and so on. Different images in the same row of image blocks can be stored in different cache units through different address granules, and so on.

[0100] Specifically, for each image block in the first row of image blocks T0, the first image block (T0_L0) is placed at the position of bank0 in the 0th row, the second image block (T0_L1) is placed at the position of bank1 in the 1st row, the third image block (T0_L2) is placed at the position of bank2 in the 2nd row, and the fourth image block (T0_L3) is placed at the position of bank3 in the 3rd row.

[0101] To use all cache units in each row of address granules, that is, to evenly store image blocks in each cache unit and effectively utilize the space in each cache unit, for row T1 of image blocks, the first image block (T1_L0) is written to the location of bank 1 in row 0, the second image block (T1_L1) is written to the location of bank 2 in row 1, the third image block (T1_L2) is written to the location of bank 3 in row 2, and the fourth image block (T1_L3) is written to the location of bank 0 in row 3. This process continues in this order until all 1Kbyte address cache granules are used up.

[0102] S130 , if the cache area corresponding to the address granule is fully stored with the data of the image block, then the address of the cache area corresponding to the address granule is written into the preset information memory 140 .

[0103] In this embodiment, when the cache area is full, the address of the cache area corresponding to the address granule can be written into the information memory 140, so that the address of the cache area can be provided to the acquirer through the information memory 140, and the acquirer can read the image block from the cache 110 according to the address.

[0104] If the image block is allocated to multiple address granules, after the cache area corresponding to the current address granule is full, the address of the cache area corresponding to the address granule is written into the information memory 140, and the cache area corresponding to the next address granule continues to store data of the image block.

[0105] In some embodiments, the image management method may further include S140 , providing the acquirer with an address of a cache area corresponding to the address granule through the information storage 140 .

[0106] In this embodiment, the acquiring party can be the receiving party during the image transmission process, or the read cache module 150. The read cache module 150 can read the image block from the buffer 110 according to the address in the information storage 140, or the receiving party can send an instruction to the read cache module 150 to control the read cache module 150 to read the image block from the buffer 110 according to the address. After obtaining the image block, the read cache module 150 can output the image block.

[0107] Furthermore, if the image blocks are shifted and spliced ​​before being written into the buffer 110, the image blocks in the buffer area corresponding to the address granule are shifted during output to restore the order of the image blocks to the order of input. The output data shift module 170 can be used to shift the output image blocks.

[0108] After the image block is read from the cache area, the read cache module 150 releases the address granule corresponding to the cache area back to the address resource pool 120 in response to the image block being read from the cache area. As a result, the address resource pool 120 can reallocate the address granule to a newly written image block, and the cache area corresponding to the address granule is also allowed to be overwritten. In other words, the release indicates that the cache area corresponding to the address granule allows new image blocks to be written.

[0109] During image transmission, the image will be compressed, which will cause the format of the image block to change. In addition, the image may involve format conversion, converting the image data from one format to another. The format change of the image block is mainly reflected in the change of the UV component. During the transmission process, the UV component can be copied to restore the image or change the image format. For example, the Y component and UV component in YUV420 are 2 to 1 in the vertical direction, while the Y component and UV component in YUV444 are 1 to 1. If the image is converted from YUV420 to YUV444, the UV component in the vertical direction needs to interpolate the UV components of the adjacent upper and lower rows, that is, the UV component needs to be reused once. The detailed principle of format conversion can be referred to the existing technology and will not be expanded here.

[0110] In one embodiment of the present application, before releasing the address granule, the image management method may further include: if it is determined based on the initial format when the image block is written and the target format when it is written out whether the read UV component needs to be reused, then the address of the cache area corresponding to the address granule is rewritten into the next information storage 140.

[0111] In this embodiment, if a UV component needs to be reused, it is stored in the next adjacent information memory 140. Consequently, when the acquiring party obtains the address of the UV component in the buffer 110 from the next information memory 140, it reads the UV component from the cache area and outputs it again. This achieves repeated output of the UV component, equivalent to copying the UV component once before outputting it. Compared to direct copying and storage, writing the address to the information memory 140 only requires the information memory 140 to store the address, eliminating the need for the buffer 110 to store two copies of the same UV component. This reduces the amount of data required to store the UV component, thereby reducing the chip area occupied by the buffer 110.

[0112] For example, please refer to Figure 11, which is a schematic diagram of the address granule reallocation of the first scenario provided by an embodiment of the present application. Among them, G0 to G15 are different address granules, and line0 to line7 are image blocks of different rows. As shown in the first table of Figure 11, line0 to line3 are assigned different address granules, and the address granules used by line0 are G0, G4, G8 and G12 respectively. When the image block of line0 is read out, the address granules need to be reallocated, and the address granules corresponding to line0 can be respectively allocated to line4 to line7 to store the first image block of each row of image blocks. Similarly, the original address granules corresponding to line1 are G1, G5, G9 and G13. When the image block in line1 is read out, the address granules will be reallocated, that is, allocated to line4 to line7 to store the second image block of each row of image blocks, and so on, to achieve the reuse of each address granule.

[0113] Similarly, please refer to Figure 12, which is a schematic diagram of address granule reallocation in the second scenario provided by an embodiment of the present application. G0 to G31 represent different address granules, and line0 represents different rows of image blocks. As shown in the first table of Figure 12, lines 0 to 7 are assigned different address granules, and the address granules used by line 0 are G0, G8, G16, and G24, respectively. As shown in the second table of Figure 12, after the image block of line 0 is read out, the address granules need to be reallocated. The address granules corresponding to line 0 can be respectively assigned to lines 8 to line 11 to store the first image block of each row of image blocks. As shown in the third table of Figure 12, the address granules originally corresponding to line 1 are G1, G9, G17, and G25. After the image blocks in line 1 are read out, the address granules will be reallocated, that is, allocated to line 12 to line 15 to store the first image blocks of each row of image blocks. As shown in the fourth table of Figure 12, the address granules G2, G10, G18, and G26 originally corresponding to line 2 are reallocated to line 8 to line 11, and so on, to achieve the reuse of each address granule.

[0114] In the embodiment of the present application, compared to registers, buffer 110 requires less chip area to store image blocks of the same data volume. Using buffer 110 to store image blocks can reduce the chip area occupied by circuitry that temporarily stores image blocks during image transmission. Registers can be directly controlled by the processor. However, compared to registers, buffer 110 stores larger amounts of data and requires control via read and write instructions. If image blocks stored in buffer 110 are not recorded, issues such as overwriting and duplicate reads may occur. Therefore, in the embodiment of the present application, address granules can be used to record the storage and reading of image blocks. If the address of the cache area corresponding to an address granule is within the preset information memory 140, it indicates that the image block stored in that cache area can be read and that the image block corresponding to the address granule cannot be overwritten by new data. Therefore, when multiple rows of image blocks are written consecutively or simultaneously within a short period of time, address granules can ensure that the image blocks are accurately output, reducing the possibility of data loss. Thus, address granules and buffer 110 can achieve normal storage, management, and output of image blocks while reducing chip area usage.

[0115] Based on the same inventive concept, embodiments of the present application also provide an image transmission method. As shown in Figure 13 , the image transmission method can be applied to a scenario including a first device 310, a second device 320, and the image management chip 100 provided in any of the aforementioned embodiments. The first device 310 and the second device 320 are the sender and receiver of the image transmission, respectively.

[0116] Please refer to FIG14 , which is a flowchart of an image transmission method provided in one embodiment of the present application. The image transmission method includes:

[0117] S210 , after compressing the image data into image blocks, the first device stores the image blocks based on the image management chip.

[0118] In this embodiment, the first device 310 can compress the image data so that the image data is compressed into image blocks for transmission. Since the transmission of image blocks requires converting the image blocks into a linear sequence, the image blocks can be stored based on the image management chip. Since the image management chip uses the buffer 110 to store the image blocks, compared to registers, the buffer 110 requires less chip area to store the same data, which facilitates the back-end design of the circuit.

[0119] S220: The second device sends a read instruction to the image management chip to read the image block from the image management chip.

[0120] In this embodiment, the second device 320 can be the recipient in the image transmission process. The second device 320 can be connected to the information storage 140, the address resource pool 120 and the cache 110 in the image management chip to send a read instruction to obtain the address from the information storage 140, and then read the image block from the cache 110 according to the address, and release the address particles corresponding to the cache area after the image is read back to the address resource pool 120.

[0121] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which may include the image management chip provided in the aforementioned embodiment.

[0122] The technical features of the above embodiments can be freely combined without conflict, and the embodiments obtained by the combination are included in the protection scope of this application.

[0123] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0124] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. An image management method, characterized in that: include: In response to writing of an image block, an address particle is allocated to the image block; each of the address particles corresponds to a different cache area in a cache, and the address particle is data recording an address of a corresponding cache area; the cache includes a plurality of cache areas of a first preset size; Storing the image block in a cache area corresponding to the address granule; If the cache area corresponding to the address granule is fully stored with the data of the image block, the address of the cache area corresponding to the address granule is written into a preset information storage device; the information storage device is configured to provide the address of the cache area corresponding to the address granule to the acquirer of the image block; the acquirer is configured to acquire the image block from the cache device based on the address of the cache area corresponding to the address granule.

2. The method according to claim 1, characterized in that: Before allocating address granules to the image block, the method further includes: Determining configuration parameters of the buffer according to a preset conversion format; the configuration parameters are used to configure the buffer; The preset conversion format is a preset compression format of the image block, and the preset conversion format includes a maximum image width of the image block, and an arrangement of Y components and UV components of pixels in the image block; the Y component is the brightness of the pixel, and the UV component is the chrominance of the pixel; The configuration parameters of the cache include the number, width and depth of cache units in the cache; a plurality of cache units constitute the cache, and the total storage space of the plurality of cache units is divided into a plurality of cache areas.

3. The image management method according to claim 2, characterized in that: After determining the configuration parameters of the buffer according to the preset conversion format, the method further includes: The number of address granules and the first preset size are set based on the configuration parameters of the buffer and the preset conversion format.

4. The image management method according to claim 2, characterized in that: The information storage device includes a plurality of information storage devices corresponding to the Y component and a plurality of information storage devices corresponding to the UV component; The step of writing the address of the cache area corresponding to the address granule into a preset information storage device includes: According to the pixel component type written into the cache area, writing the address corresponding to the cache area into the information storage device corresponding to the component type; The pixel component type includes the Y component and the UV component.

5. The image management method according to any one of claims 1 to 4, characterized in that: After writing the granule information of the address granule into a preset information storage device, the method further includes: Providing the address of the cache area corresponding to the address granule to the acquirer through the information storage device, so that the acquirer reads the image block from the cache area based on the address of the cache area corresponding to the address granule; In response to the image block in the cache area being read out, the address granule corresponding to the cache area is released, and the released address granule indicates that the cache area corresponding to the address granule allows writing of new image blocks.

6. The image management method according to claim 5, characterized in that: The image block includes a UV component, and the UV component is the chromaticity of a pixel point; the information storage includes a plurality of information storage devices; before releasing the address particles, the method further includes: If it is determined whether the read UV component needs to be reused based on the initial format when the image block is written and the target format when it is written, the address of the cache area corresponding to the address granule is rewritten into the next information storage device.

7. The image management method according to claim 5, characterized in that: The image block to be written includes a plurality of image blocks. Before allocating address particles to the image blocks, the method further includes: Shifting and splicing the input multiple image blocks into image blocks of a second preset size; Correspondingly, after providing the acquirer with the address of the cache area corresponding to the address granule through the information storage, the method further includes: The image blocks in the cache area corresponding to the address particle are shifted to restore the arrangement order of the image blocks to the order at the time of input.

8. An image management chip, characterized in that: include: A cache, comprising a plurality of cache areas of a first preset size; An address resource pool storing a plurality of address granules, wherein different address granules correspond to different cache areas; The address granule is data recording the address of the corresponding cache area; A write cache module connected to the address resource pool and the cache; A plurality of information storage devices, each of which is connected to the write cache module; The write cache module is configured to receive written image blocks; The address resource pool is configured to allocate address particles to the image block in response to writing of the image block; The write cache module is further configured to store the image block into a cache area corresponding to the address granule; Furthermore, the write cache module is further configured to write the address of the cache area corresponding to the address granule into the information storage device if the cache area corresponding to the address granule is fully stored with the data of the image block; the information storage device is configured to provide the address of the cache area corresponding to the address granule to the acquirer of the image block; and the acquirer is configured to acquire the image block from the cache device based on the address of the cache area corresponding to the address granule.

9. The image management chip according to claim 8, characterized in that: The buffer is configured to determine configuration parameters of the buffer according to a preset conversion format; the configuration parameters are used to configure the buffer; The preset conversion format is a preset compression format of the image block, and the preset conversion format includes a maximum image width of the image block and an arrangement of Y components and UV components of pixels in the image block; The Y component is the brightness of the pixel, and the UV component is the chromaticity of the pixel; The configuration parameters of the cache include the number, width and depth of cache units in the cache; a plurality of cache units constitute the cache, and the total storage space of the plurality of cache units is divided into a plurality of cache areas.

10. The image management chip according to claim 9, characterized in that: The buffer is further configured to set the number of address granules and the first preset size based on configuration parameters of the buffer and the preset conversion format.

11. The image management chip according to claim 9, characterized in that: The multiple information storage devices include multiple information storage devices corresponding to the Y component and multiple information storage devices corresponding to the UV component; The write cache module is further configured to further include: according to the pixel point component type written into the cache area, writing the address corresponding to the cache area into the information storage device corresponding to the component type; The pixel component type includes the Y component and the UV component.

12. The image management chip according to any one of claims 8 to 11, characterized in that: The image management chip also includes: a read cache module, configured to be connected to the cache, the address resource pool and the information storage device respectively; wherein the read cache module is configured as the acquisition side; The read cache module is further configured to obtain the address of the cache area corresponding to the address granule stored in the information storage device, so as to read the image block in the cache area corresponding to the address granule from the cache device based on the address of the cache area corresponding to the address granule and output it; The read cache module is further configured to release an address granule corresponding to the cache area in response to the image block being read out of the cache area, wherein the released address granule indicates that the cache area corresponding to the address granule allows writing of a new image block.

13. The image management chip according to claim 12, characterized in that: The image block includes a UV component, which is the chromaticity of a pixel point; the buffer is also configured to: if it is determined based on the initial format of the image block when it is written and the target format when it is written, whether the read UV component needs to be reused, then rewrite the address of the cache area corresponding to the address granule into the next information storage device.

14. The image management chip according to claim 12, characterized in that: The image management chip also includes: An input data shift module is configured to be connected to the write cache module, and is used to receive written image blocks, and shift and splice multiple input image blocks into image blocks of a second preset size; The output data shift module is connected to the read cache module and is used to shift the image block output by the read cache module to restore the pixels in the image block to the order of input.

15. An image transmission method, characterized in that: include: After compressing the image data into image blocks, the first device stores the image blocks based on the image management chip according to any one of claims 8 to 14; The second device sends a read instruction to the image management chip to read the image block from the image management chip.

16. An electronic device, characterized in that: include: An image management chip as described in any one of claims 8 to 14.

Images