Memory chip compatible with multiple types of storage media

Abstract

Provided in the present invention is a memory chip compatible with multiple types of storage media. The memory chip comprises: a central control unit, which is the control unit of the entire memory control chip; a universal interface, used for performing data interaction with an external host; a universal interface controller, connected to the central control unit and the universal interface; a buffer, connected to the central control unit and the universal interface; a controller compatible with multiple types of storage media, connected to the central control unit, the universal interface controller, and a port controller; the port controller, which controls interfaces of multiple types of storage media; and the interfaces of the multiple types of storage media, which include two or more different storage media interfaces, the storage media interfaces being connected to the memory chip. In the invention, the connection means of shared interfaces is used to reduce the number of ports and enable the classification of access formats, thus better implementing the sharing of logical resources and solving the problems of resource redundancy and numerous interfaces in controllers for different types of storage media, while further increasing the port bandwidth utilization rate.

Description

Memory chips compatible with multiple types of storage media Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to the field of memory chips. Background Art

[0002] Demand for artificial intelligence systems is growing, and smart consumer products are placing increasingly higher demands on storage. The required storage media types are becoming increasingly diverse, such as SRAM, FLASH, and DRAM, while also placing increasingly stringent demands on speed, power consumption, and area. Currently, different storage media types correspond to a variety of interface types, such as SPI, xSPI, SD, and ONFI. In systems that incorporate multiple storage media, data exchange between storage media and host access to storage media face the challenge of converting between multiple different interfaces. Each type of storage media corresponds to a set of proprietary interfaces, resulting in inadequate resource utilization, larger chip areas, and excessive power consumption due to these redundant controls. Technical issues

[0003] To connect different types of storage media, Chinese patent CN113908500A proposes a device and system that conforms to the Extended Serial Peripheral Interface (xSPI) specification. This device utilizes an extensible xSPI interface to connect different storage media. While this device addresses the need for connecting different types of media to the same system, the single interface type is incompatible with non-xSPI storage media. Chinese patent CN113296701A proposes a solid-state storage method and device that connects DRAM, NAND FLASH, and non-volatile storage media to a host system via a single master control chip. This method is compatible with both DRAM and NAND FLASH storage media, but lacks deep integration of different interface types.

[0004] To address the data transfer issue between volatile and non-volatile storage media, Chinese patent CN103890688A proposes a method for transferring data between any two or more storage modules in a storage subsystem. This method focuses on data movement and access flexibility, but lacks integration of controllers for different types of storage media.

[0005] U.S. Patent No. 9,424,182B2 proposes an adaptive storage system for enhancing the performance of external technology devices. This system utilizes a single controller to access data from FLASH, DRAM, and SRAM, and proposes DMA for data transfer between FLASH, DRAM, and SRAM. While this implementation offers broad data transfer coverage and high flexibility, it lacks unified and coordinated control of multiple storage media types, nor does it propose a feasible and efficient data transmission path architecture. In particular, the direct data paths between these multiple storage media types are not supported by actual storage media. Summary of the Invention

[0006] The purpose of the present invention is to solve the problems in the prior art and provide a storage chip compatible with multiple types of storage media, which can solve the problems of resource redundancy and large number of interfaces of controllers of different types of storage media, and at the same time improve the port bandwidth utilization rate.

[0007] To achieve the above objectives, the present invention provides a storage chip compatible with multiple types of storage media, comprising:

[0008] Central control unit: It is the control unit of the entire storage control chip;

[0009] General interface: used for data exchange with external host;

[0010] Universal interface controller: connected to the central control unit and the universal interface, used to control the universal interface and interpret the host's access instructions;

[0011] Buffer: connected to the central control unit and the general interface to buffer data;

[0012] Compatible with multiple types of storage media controllers: connected to the central control unit, universal interface controller, and port controller to implement read and write control of different types of storage media;

[0013] Port controller: connected to the central control unit, compatible with multiple types of storage media controllers and multiple types of storage media interfaces, and controls multiple types of storage media interfaces;

[0014] Multi-type storage medium interface: includes two or more different storage medium interfaces, and the storage medium interface is connected to the storage chip.

[0015] Preferably, the multi-type storage medium interface is at least two of an ONFI interface, an SD card interface, an SRAM interface, and a DRAM interface.

[0016] Preferably, the interfaces of the different storage medium interfaces are integrated with each other, and some or all of the control lines or data lines are shared.

[0017] Preferably, the control lines or data lines are shared by utilizing the difference in response time or by ensuring that access times to different types of storage media do not overlap.

[0018] Preferably, the difference in response time is utilized by inserting access operations to storage media that can respond quickly into accesses that require a longer response time, thereby improving the bandwidth utilization of the storage medium interface; the access times to different types of storage media do not overlap, and when a non-volatile storage medium needs to be accessed, the storage medium interface is used for data transmission of the non-volatile storage medium; and when a volatile storage medium needs to be accessed, the storage medium interface is used for data transmission of the volatile storage medium.

[0019] Preferably, the controller compatible with multiple types of storage media integrates the control of all storage media into one controller, and adopts an access form classification mechanism to perform logical resource integration.

[0020] Preferably, the access form classification mechanism is based on address and data line characteristics.

[0021] Preferably, the classification according to the characteristics of the address and data lines is as follows: a controller having a shared port for the address and data lines is classified as a serial type, while a controller having independent and parallel access to the address and data lines is classified as a parallel type.

[0022] Preferably, the classification according to address and data line characteristics is classified according to the amount of data accessed each time, into two forms: large-batch data storage and small-batch data real-time access.

[0023] Preferably, the address mapping mechanism of the controller supports mapping the same access instruction to a single, two or more target memories; the port mapping mechanism of the controller supports mapping a single access instruction to a single, two or more target ports. Beneficial effects

[0024] The beneficial effects of the present invention are as follows: The multi-type storage medium controller of the present invention adopts a shared interface multiplexing connection method for the interfaces of multiple types of storage media, thereby saving the number of ports, converting the parsed access information into the access form corresponding to the target memory, and classifying the access format, thereby better realizing the sharing of logical resources, solving the problems of resource redundancy and the large number of interfaces of different types of storage medium controllers, and improving the port bandwidth utilization rate. In addition, because the present invention uniformly coordinates and controls multiple types of storage media, data transmission between multiple types of storage media can be completed within the chip of the present invention without the need for transfer through an external host, which can significantly reduce data transmission time and power consumption as well as the host's operating overhead.

[0025] The features and advantages of the present invention will be described in detail through embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a structural diagram of a storage chip system compatible with multiple types of storage media according to the present invention;

[0027] FIG2 is a schematic diagram of an interface sharing method 1 in a storage chip compatible with multiple types of storage media according to the present invention;

[0028] FIG3 is a schematic diagram of a method 2 for sharing interfaces in a storage chip compatible with multiple types of storage media according to the present invention;

[0029] FIG4 is a schematic diagram of the structure of a controller compatible with multiple types of storage media in a storage chip compatible with multiple types of storage media according to the present invention;

[0030] FIG5 is a schematic diagram of port mapping relationships in a storage chip compatible with multiple types of storage media according to the present invention;

[0031] FIG6 is a schematic diagram of the address mapping relationship in a storage chip compatible with multiple types of storage media according to the present invention;

[0032] 7 is a schematic diagram of a port mapping implementation method in a storage chip compatible with multiple types of storage media according to the present invention;

[0033] 8 is a schematic diagram of an implementation method for classifying address and data lines in a storage chip compatible with multiple types of storage media according to the present invention;

[0034] FIG9 is a schematic diagram of a data volume classification implementation method in a storage chip compatible with multiple types of storage media according to the present invention;

[0035] FIG10 is a schematic diagram of a time division multiplexing scenario under response time differences in a storage chip compatible with multiple types of storage media according to the present invention. DETAILED DESCRIPTION

[0036] Example 1:

[0037] Referring to FIG1 , the present invention provides a memory chip compatible with multiple types of storage media, including:

[0038] The central control unit (CCU) controls the entire memory control chip. It provides global control of the memory chip system, including module configuration, data flow control, sleep mode entry and exit, and interrupt response. This CCU utilizes a low-power, compact, and fast-response microprocessor (MCU) (such as the Hummingbird E203 and T-head E902), helping to reduce chip power consumption and area.

[0039] Universal interface: used for data exchange with an external host. This can be a high-performance xSPI interface, an SD protocol interface, or other universal standard interfaces.

[0040] Universal Interface Controller: Connected to the central control unit and the universal interface, it controls the universal interface and interprets host access commands. The universal interface controller interprets xSPI protocol access commands or SD protocol access commands according to the protocol used by the universal interface.

[0041] Buffer: Connected to the central control unit and the universal interface, it buffers data from each module. The buffer can be implemented using SRAM. On-chip SRAM offers fast access, high integration, and a small footprint, making it an excellent choice for data caching.

[0042] Compatible with multiple types of storage media controller: connected to the central control unit, universal interface controller, and port controller to implement read and write control of different types of storage media. The compatible with multiple types of storage media controller includes control of access to FLASH, DRAM, and SRAM. The compatible with multiple types of storage media controller integrates the control of all storage media into one controller, and adopts an access form classification mechanism to integrate logical resources. The access form classification mechanism is classified according to the characteristics of the address and data lines. The classification method according to the characteristics of the address and data lines is: a type of controller with a shared port for address and data lines is classified as a serial type, and a controller with independent and parallel access to address and data lines is classified as a parallel type. The classification method according to the characteristics of the address and data lines is: classified according to the amount of data accessed each time, divided into two forms: large-scale data storage and small-batch data real-time access. The address mapping mechanism of the controller supports mapping the same access instruction to a single, two or more target memories; the port mapping mechanism of the controller supports mapping a single access instruction to a single, two or more target ports.

[0043] Port controller: connected to the central control unit, compatible with multiple types of storage media controllers and multiple types of storage media interfaces, controls multiple types of storage media interfaces, and adapts to access to different media in different time periods.

[0044] Multi-type storage medium interface: includes two or more different storage medium interfaces, and the storage medium interface is connected to the storage chip. The storage medium interface includes a FLASH interface (such as an ONFI interface or an SPI interface, etc.), a DRAM interface (such as an SDR / DDR DRAM interface or an xSPI interface or others) and an SRAM interface. The interfaces of different storage medium interfaces are integrated with each other, and some or all of the control lines or data lines are shared. The sharing method of the control lines or data lines is to utilize the difference in response time or the non-overlapping access time of different types of storage media. The utilization of the difference in response time is to insert an access operation to a storage medium that can respond quickly into an access that requires a longer response time, thereby improving the bandwidth utilization of the storage medium interface; the non-overlapping access time of different types of storage media is that before the system starts and the system sleeps, the storage medium interface is used to access non-volatile storage media, and at other times the storage medium interface is used to access volatile storage media.

[0045] When the host first accesses a memory chip system in standby mode, the host initiates an access request, wakes up the memory chip system, and initializes the memory chip through a reset instruction. The memory chip enters an active state and can accept read and write access from the host. The host transmits the access instruction to the memory chip system through a universal interface for instruction interpretation. After classification processing, the host notifies the central processing unit to adopt the corresponding access mode. For example, for low-latency access to an SRAM-like interface, the access instruction will directly access the storage medium quickly through the hardware without going through the buffer. For example, for access to NAND FLASH non-volatile storage media, the read batch data will be stored in the buffer first so that the data can be transmitted to the host system in the form of a universal interface, or the buffer can quickly receive large batches of data that the host needs to write, and the central processing unit will allocate time periods for writing based on the current bandwidth utilization of multiple types of storage media interfaces.

[0046] In this embodiment, a central control unit is used to logically control and coordinate multiple interface controllers to read and write data on multiple external storage media, which can effectively improve bandwidth and flexibility in accessing data.

[0047] Multi-Type Media Interfaces Use a Shared Connection Method: In this embodiment, the multi-type media interfaces utilize shared connection method 1, as shown in Figure 2. The xSPI interface and ONFI interfaces NWP_ and NDAT0-NDAT7 are shared. In the ONFI protocol, NDAT0-NDAT7 do not have command characteristics and can be used for other interface functions while waiting for a response. For example, while waiting for an ONFI NRB command, the port controller releases access to ONFI NWP_ and NDAT0-NDAT7. If the host initiates an access or a command is already pending, and the access address range belongs to storage media with an xSPI interface (such as xSPI PSRAM), the system can access the PSRAM through the reused xSPI interface without waiting for NRB to be valid. This significantly improves ONFI interface bandwidth utilization. A timing diagram is shown in Figure 10.

[0048] Compatible Multi-Type Storage Media Controller and Port and Address Mapping: As shown in Figure 4, the implementation of a compatible multi-type storage media controller can consist of a classifier and a mapping controller. The classifier can be composed of multiple sub-classifiers, and the mapping controller can be composed of an address mapping controller and a port mapping controller, as shown in Figures 5 and 6. The address mapper can map to any type of media, or the same access instruction can be mapped to two or more media, as shown in Figure 6. The port mapping controller can map to the interface corresponding to any type of media, or the same access instruction can be mapped to the interfaces corresponding to two or more media, as shown in Figure 7. Address mapping and port mapping are centrally managed by a central control unit, and the mapping table can be cached in a buffer.

[0049] Address data line classification and data volume classification: In this embodiment, different types of access interfaces can be divided into serial classifiers and parallel classifiers based on whether the data lines and address lines are executed in parallel. The implementation of the classifier can be composed of sub-classifier 0-serial classifier and sub-classifier 1-parallel classifier, as shown in Figure 8.

[0050] Example 2:

[0051] The difference between this embodiment and the first embodiment is that the multi-type media interface adopts the shared connection mode 2, as shown in Figure 3. The SD interface and ONFI interfaces NDAT0 to NDAT5 are shared. The operation mode is the same as that described in the shared connection mode 1.

[0052] Example 3:

[0053] The difference between this embodiment and the first embodiment is that this embodiment is divided into large-volume data access instructions and small-volume real-time access instructions based on the size of the accessed data, as shown in FIG9 .

[0054] The above embodiments are intended to illustrate the present invention, not to limit the present invention. Any solution that is a simple transformation of the present invention falls within the protection scope of the present invention.

Claims

1. A storage chip compatible with multiple types of storage media, characterized by: include: Central control unit: It is the control unit of the entire storage control chip; General interface: used for data exchange with external host; Universal interface controller: connected to the central control unit and the universal interface, used to control the universal interface and interpret the access instructions of the host; Buffer: connected to the central control unit and the general interface to buffer data; Compatible with multiple types of storage media controllers: connected to the central control unit, universal interface controller, and port controller to implement read and write control of different types of storage media; Port controller: connected to the central control unit, compatible with multiple types of storage media controllers and multiple types of storage media interfaces, and controls multiple types of storage media interfaces; Multi-type storage medium interface: includes two or more different storage medium interfaces, and the storage medium interface is connected to the storage chip.

2. The storage chip compatible with multiple types of storage media as claimed in claim 1, characterized in that: The multi-type storage medium interfaces are at least two of an ONFI interface, an SD card interface, an SRAM interface, and a DRAM interface.

3. The storage chip compatible with multiple types of storage media as claimed in claim 1, characterized in that: The interfaces of the different storage medium interfaces are integrated with each other, and some or all of the control lines or data lines are shared.

4. The storage chip compatible with multiple types of storage media as claimed in claim 3, characterized in that: The control line or the data line is shared in a manner that utilizes the difference in response time and / or the non-overlapping access time to different types of storage media.

5. The storage chip compatible with multiple types of storage media as claimed in claim 4, characterized in that: The method of utilizing the difference in response time is to insert an access operation to a storage medium that can respond quickly into an access that requires a longer response time, thereby improving the bandwidth utilization of the storage medium interface; the method of utilizing the non-overlapping access time to different types of storage media is to use the storage medium interface for data transmission of the non-volatile storage medium when a non-volatile storage medium needs to be accessed; and to use the storage medium interface for data transmission of the volatile storage medium when a volatile storage medium needs to be accessed.

6. The storage chip compatible with multiple types of storage media as claimed in claim 1, characterized in that: The controller compatible with multiple types of storage media integrates the control of all storage media into one controller, and adopts an access form classification mechanism to perform logical resource integration.

7. The storage chip compatible with multiple types of storage media according to claim 6, characterized in that: The access form classification mechanism is to classify according to address and data line characteristics.

8. The storage chip compatible with multiple types of storage media as claimed in claim 7, characterized in that: The classification method according to the characteristics of the address and data lines is as follows: a type of controller having a common port for the address and data lines is classified as a serial type, and a controller having independent and parallel access to the address and data lines is classified as a parallel type.

9. The storage chip compatible with multiple types of storage media according to claim 7, characterized in that: The classification method according to the address and data line characteristics is: classification according to the amount of data accessed each time, divided into two forms: large batch data storage form and small batch data real-time access form.

10. The storage chip compatible with multiple types of storage media according to any one of claims 6 to 9, characterized in that: The address mapping mechanism of the controller supports mapping the same access instruction to a single, two or more target memories; the port mapping mechanism of the controller supports mapping a single access instruction to a single, two or more target ports.

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