Voltage regulator circuit, electronic device, and voltage regulation method

Abstract

Disclosed in the present application are a voltage regulator circuit, an electronic device, and a voltage regulation method. When a post-stage load of a VRM operates, a logic high level is inputted to an SYNC pin of an SPS / DrMOS, such that the SPS / DrMOS operates normally; and when the post-stage load of the VRM does not operate, the SYNC pin of the SPS / DrMOS is set to be in an intermediate state, such that the SPS / DrMOS enters a standby mode, thereby reducing a quiescent current on a VCC pin, and thus reducing extra power consumption on the VCC pin of the SPS / DrMOS.

Description

Voltage regulation circuit, electronic device and voltage regulation method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 19, 2023, with application number 202311224545.6 and application name “Voltage Regulation Circuit, Electronic Device and Voltage Regulation Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic circuits, and in particular to a voltage regulation circuit, an electronic device, and a voltage regulation method. Background Art

[0003] The load demand voltage and draw current of some modules in electronic devices, such as the central processor unit (CPU), graphics processing unit (GPU), and application specific integrated circuit (ASIC), change dynamically. For example, the CPU's load voltage and current vary greatly when opening a document and when opening a game. Therefore, the core voltage Vcore required by each of the above modules is different and may increase or decrease instantly, while the device power supply that outputs a fixed voltage cannot meet the voltage requirements of the above modules. To this end, a voltage regulator module (VRM) is provided in the electronic device to convert the larger DC voltage (such as 12V) output by the power supply into a stable smaller DC voltage (such as 0.5V-2V), and can adjust the output voltage in real time according to the load demand to meet the operating voltage requirements of the above modules.

[0004] Summary of the Invention

[0005] The present application provides a voltage regulation circuit, an electronic device, and a voltage regulation method, which can reduce the extra power consumption of the electronic device.

[0006] In a first aspect, a voltage regulation circuit is provided, comprising: a pulse width modulation (PWM) controller, N first circuits, where N is a positive integer, wherein the first circuit comprises: a unidirectional conduction device, and a second circuit, wherein the PWM controller is used to output a PWM voltage signal to the second circuit, and the second circuit is used to reduce the voltage received at the high-voltage input end of the voltage regulation circuit according to the PWM voltage signal and then output the reduced voltage; the PWM controller comprises an EN pin, and the EN pin of the PWM controller is connected to the input end of the enable signal of the PWM controller; the second circuit comprises a DrMOS, and the DrMOS comprises a SYNC pin and a VCC pin, the VCC pin is connected to the input end of the driving voltage of the DrMOS, and the SYNC pin is not connected to the input end of the driving voltage of the DrMOS. The first end of the pull-up resistor module is connected to the VCC pin, and the second end is connected to the SYNC pin; the first end of the pull-down resistor module is connected to the SYNC pin, and the second end is grounded; the pull-up resistor module includes a first resistor and / or a third resistor, and the pull-down resistor module includes a second resistor and / or a fourth resistor; the first ends of the first resistor and the third resistor are both connected to the VCC pin, and the second ends are both connected to the SYNC pin; the first ends of the second resistor and the fourth resistor are both connected to the SYNC pin, and the second ends are both grounded; the first resistor and the second resistor belong to the voltage regulation circuit and are located outside the PWM controller and the second circuit; the third resistor and the fourth resistor belong to DrMOS; the first end of the unidirectional conduction device is connected to the EN pin of the PWM controller, and the second end is connected to the SYNC pin.

[0007] In the voltage regulation circuit of the first aspect, the SYNC pin is not connected to the input terminal of the DrMOS driving voltage, but is connected to VCC through a pull-up resistor module and to ground through a pull-down resistor module. In this way, the voltage on the SYNC pin during the working process and the non-working process of the voltage regulation circuit can be adjusted to prevent the SYNC pin from continuously receiving the driving voltage.

[0008] In combination with the first aspect, in some embodiments, the quiescent current on the VCC pin when the SYNC pin is at an intermediate state level is less than the quiescent current on the VCC pin when the SYNC pin is at a logic high level; when the EN pin of the PWM controller receives a logic high level, the unidirectional conduction device is turned on from the first end to the second end, and the SYNC pin receives a high level; when the EN pin of the PWM controller receives a logic low level, the unidirectional conduction device is turned off from the first end to the second end, and the SYNC pin receives an intermediate state level.

[0009] According to the above embodiment, when the PWM controller is working, a logic high level is input to the SYNC pin to enable the DrMOS to work normally; when the PWM controller is not working, the SYNC pin is set to an intermediate state, thereby reducing the quiescent current on the VCC pin, that is, reducing the additional power consumption on the VCC pin.

[0010] In conjunction with the first aspect, in some embodiments, the voltage regulation circuit further includes: a first capacitor, a first end of the first capacitor being connected to the SYNC pin, and a second end of the first capacitor being grounded. The first capacitor can be used to adjust the timing of the SYNC pin transitioning from a logic high level to an intermediate level, causing the SYNC pin to power down later than the EN pin, thereby preventing an undervoltage fault in the PWM controller.

[0011] In combination with the first aspect, in some implementations, the first capacitor is located outside the PWM controller and the second circuit.

[0012] In combination with the first aspect, in some embodiments, when the voltage difference from the first end to the second end of the unidirectional conductive device is greater than the conduction voltage drop of the unidirectional conductive device, the unidirectional conductive device is conducted from the first end to the second end; otherwise, the unidirectional conductive device is cut off.

[0013] In combination with the first aspect, in some embodiments, the unidirectional conducting device is a diode, the anode of the diode is connected to the EN pin of the PWM controller, and the cathode of the diode is connected to the SYNC pin.

[0014] In combination with the first aspect, in some embodiments, the DrMOS includes: a driver, a first switching tube and a second switching tube, wherein, for the first switching tube, the drain is connected to the high-voltage input end of the voltage regulation circuit, the gate is connected to the first output end of the driver, and the source is connected to the output end of the DrMOS; for the second switching tube, the drain is connected to the output end of the DrMOS, the gate is connected to the second output end of the driver, and the source is grounded; the input end of the driver is connected to the output end of the PWM controller.

[0015] In combination with the previous embodiment, the first switch tube may be an N-type field effect transistor, and the second switch tube may be an N-type field effect transistor.

[0016] Combined with the previous embodiment, when the PWM voltage signal is in the positive half cycle, the first output end of the driver outputs the first drive signal, the first switch tube is turned on, and the second switch tube is turned off; when the PWM voltage signal is in the negative half cycle, the second output end of the driver outputs the second drive signal, the first switch tube is turned off, and the second switch tube is turned on.

[0017] In combination with the previous embodiment, the second circuit further includes: a first inductor and a second capacitor, the first end of the first inductor is connected to the output end of the DrMOS, the second end of the first inductor and the first end of the second capacitor are both connected to the high-voltage output end of the voltage regulation circuit, and the second end of the second capacitor is grounded.

[0018] In combination with the first aspect, in some embodiments, the high voltage input terminal of the voltage regulating circuit is connected to the high voltage output terminal of the power supply.

[0019] In combination with the first aspect, in some embodiments, the high voltage output terminal of the voltage regulating circuit is connected to the high voltage input terminal of the load.

[0020] In combination with the previous embodiment, the current outputted from the high-voltage output terminal of the voltage regulating circuit to the load is the sum of the output currents of the activated first circuits among the N first circuits.

[0021] In combination with the first aspect, in some implementations, the voltage regulation circuit is connected to a load, and the load includes any one of the following: a CPU, a GPU, and an ASIC.

[0022] In conjunction with the first aspect, in some embodiments, the input terminal of the enable signal of the PWM controller is a GPIO interface. The GPIO interface can be used to receive a control signal from a control unit (such as a CPU, EC, etc.).

[0023] In combination with the first aspect, in some implementations, the PWM controller is integrated into a first chip, the DrMOS is integrated into a second chip, and the first chip and the second chip are different.

[0024] In a second aspect, an electronic device is provided, which includes the voltage regulating circuit provided in the first aspect or any one embodiment of the first aspect.

[0025] In combination with the second aspect, in some embodiments, the electronic device further includes a power supply, which is used to input voltage to the voltage regulating circuit.

[0026] In combination with the second aspect, in some embodiments, the electronic device further includes a load, and the voltage output by the voltage regulating circuit is provided to the load.

[0027] In a third aspect, a voltage regulation method is provided, applicable to the electronic device provided in the second aspect or any embodiment of the second aspect. The method may include: the electronic device detecting an operation of starting a load; inputting a logic high level to an EN pin of a PWM controller; detecting an operation of shutting down the load; and inputting a logic low level to the EN pin of the PWM controller.

[0028] Through the method of the third invention, the electronic device can use the voltage regulation circuit to reduce the larger voltage and output it to meet the actual needs of the subsequent load, and can also reduce the additional power consumption on the VCC pin in the DrMOS when the subsequent load is not working.

[0029] In combination with the third aspect, in some implementations, the electronic device inputs a logic high level or a logic low level to the EN pin of the PWM controller through the GPIO interface.

[0030] In conjunction with the third aspect, in some embodiments, after the electronic device inputs a logic high level to the EN pin of the PWM controller, it can also obtain the voltage requirement of the load and adjust the duty cycle of the PWM voltage signal output by the PWM controller to the second circuit based on the load voltage requirement. For example, if the load voltage requirement increases, the duty cycle is increased, and vice versa.

[0031] In conjunction with the third aspect, in some embodiments, the electronic device may further obtain a current demand of a load and adjust the number of activated first circuits among the N first circuits of the voltage regulation circuit based on the current demand of the load. For example, if the current demand of the load increases, the number of activated first circuits may be increased, and vice versa.

[0032] In a fourth aspect, a PCB board is provided, comprising the voltage regulating circuit in the first aspect or any one embodiment of the first aspect.

[0033] In a fifth aspect, a chip is provided, comprising the voltage regulating circuit according to the first aspect or any one embodiment of the first aspect.

[0034] In a sixth aspect, a power supply system is provided. The power supply system may include: a power supply, the voltage regulation circuit according to the first aspect or any embodiment of the first aspect, and a load. The power supply is configured to provide an input voltage to the voltage regulation circuit, and the voltage regulation circuit is configured to reduce the input voltage provided by the power supply and output it to the load.

[0035] In a seventh aspect, a power supply circuit is provided. The power supply circuit may include: a power supply; and the voltage regulation circuit according to the first aspect or any embodiment of the first aspect. The power supply is configured to provide an input voltage to the voltage regulation circuit, and the voltage regulation circuit is configured to reduce the input voltage provided by the power supply and output the reduced voltage.

[0036] In an eighth aspect, a power supply system is provided, which may include: the voltage regulating circuit according to the first aspect or any one of the embodiments of the first aspect, and a load. The voltage regulating circuit is configured to reduce a received input voltage and output the reduced voltage to the load.

[0037] In a ninth aspect, a readable storage medium is provided, comprising instructions, which, when executed on a device, cause the device to execute a method as in the third aspect or any one of the implementations of the third aspect.

[0038] In a tenth aspect, a program product is provided. When the program product is run on a device, the device executes the method of the third aspect or any one of the implementation methods of the third aspect.

[0039] In the eleventh aspect, a chip system is provided, which includes at least one processor for implementing the method of the third aspect or any one embodiment of the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a structural diagram of a single-phase VRM provided in an embodiment of the present application;

[0041] FIG2 is a structural diagram of a multi-phase VRM provided in an embodiment of the present application;

[0042] FIG3 is a schematic diagram of some pins of the MP2886, some pins of the MP86941, and some peripheral structures provided in an embodiment of the present application;

[0043] FIG4 is a partial structural diagram of an improved VRM provided in an embodiment of the present application;

[0044] FIG5 is a diagram showing an internal structure of an SPS / DrMOS provided in an embodiment of the present application;

[0045] FIG6 is a partial structural diagram of an improved VRM provided in an embodiment of the present application;

[0046] FIG7 is a partial structural diagram of an improved VRM provided in an embodiment of the present application;

[0047] FIG8 is a partial structural diagram of an improved VRM provided in an embodiment of the present application;

[0048] FIG9 is a partial structural diagram of an improved VRM provided in an embodiment of the present application;

[0049] FIG10 is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described clearly and in detail below with reference to the accompanying drawings.

[0051] First, several concepts involved in this application are introduced.

[0052] VRM

[0053] The VRM is used to convert the larger DC voltage (such as 12V) output by the power supply in electronic devices into a stable smaller DC voltage (such as 0.5V-2V) and output it to modules such as the CPU, GPU, and ASIC to meet the operating voltage requirements of the above modules.

[0054] 1 is a schematic diagram of a single-phase voltage regulator module (single-phase VRM) 10. The single-phase VRM 10 may also be referred to as a single-phase DC-DC Buck type step-down circuit.

[0055] The single-phase VRM 10 may include a pulse-width modulation (PWM) controller 101, a driver 102, a high-side power stage field-effect transistor (HS-FET) M1, a low-side power stage field-effect transistor (LS-FET) M2, an inductor L, and a capacitor C. The single-phase VRM 10 also includes a first input terminal, a second input terminal, and a first output terminal and a second output terminal.

[0056] The first input terminal is also called the high-voltage input terminal, which is connected to the high-voltage output terminal of the device power supply and is used to receive the input voltage Vin; the second input terminal is also called the low-voltage input terminal, which is connected to the low-voltage output terminal of the device power supply. The first output terminal is also called the high-voltage output terminal, which is connected to one input terminal of the subsequent load and is used to output the core voltage Vcore required by the subsequent load; the second output terminal is also called the low-voltage output terminal, which is connected to the other input terminal of the subsequent load. The second input terminal and the second output terminal can both be connected to the ground terminal (GND). The input voltage Vin can be the output voltage of the device power supply, and the device power supply can be a battery. The subsequent load refers to modules such as CPU, GPU, ASIC, etc. with special operating voltage requirements.

[0057] The PWM controller 101 is connected to the driver 102 and is configured to output a PWM voltage signal to the driver 102. This PWM voltage signal can be generated by a comparator CP within the PWM controller 101, which compares a fixed reference voltage Vref with the core voltage Vcore output by the single-phase VRM 10. The PWM controller 101 is configured to control the duty cycle of the PWM waveform based on the real-time load requirements, so that the output voltage stabilizes at the required value of the core voltage Vcore. The PWM voltage signal output by the PWM controller 101 is an analog signal that alternates between high and low levels. When the PWM voltage signal is high, the PWM voltage signal is in the positive half-cycle; when the PWM voltage signal is low, the PWM voltage signal is in the negative half-cycle.

[0058] The driver 102 may include a control logic circuit 1011 and two driver circuits 1012 and 1013 .

[0059] M1 or M2 can be an N-type field effect transistor or a P-type field effect transistor.

[0060] The drain (D) of M1 is connected to the first input terminal, the gate (G) of M1 is connected to the output terminal of the driver circuit 1012, and the source (S) of M1 is connected to the first terminal of L. The drain (D) of M2 is connected to the first terminal of L, the gate (G) of M2 receives the output terminal of the driver circuit 1013, and the source (S) of M2 is connected to the second input terminal. The second terminal of L is connected to the first output terminal, which is used to output the required core voltage Vcore to the downstream load. The first terminal of C is connected to the second terminal of L, and the second terminal of C is connected to the second output terminal.

[0061] When the PWM voltage signal output by PWM controller 101 is in the positive half-cycle, control logic circuit 1011 in driver 102 generates a signal that instructs driver circuit 1012 to output a first drive signal S1 to M1, turning M1 on and M2 off / off. Current flows from VCC through M1 and L, charging C and generating a self-induced electromotive force in L. When the PWM voltage signal output by PWM controller 101 is in the negative half-cycle, control logic circuit 1011 in driver 102 generates a signal that instructs driver circuit 1013 to output a second drive signal S2 to M2, turning M1 off / off and M2 on. The current in L attempts to maintain its existing magnetic field, causing a voltage reversal and accumulation in C. When the electromotive force on L decreases or diminishes, C outputs the supply voltage to the downstream load. In this way, under the influence of the PWM voltage signal, driver 102 controls the frequent switching of M1 and M2 to provide a continuous and stable current and voltage to the downstream load.

[0062] Integrating M1, M2, and driver 102 into a single chip—a device called a smart power stage (SPS), also known as DrMOS—reduces overall size while increasing power density and efficiency. The SPS / DrMOS also incorporates an overcurrent protection circuit to control output current to prevent it from exceeding the rated value, and an error detection circuit to detect faults such as overheating, overvoltage, and short circuits.

[0063] The output terminal of the DrMOS is connected to the source (S) of M1, and the drain (D) of M2 is connected to the first end of L.

[0064] A phase of a VRM refers to a circuit consisting of driver 102, M1, M2, inductor L, and capacitor C. To meet the requirements of different loads and increase output power, a multi-phase voltage regulator module (multi-phase VRM) is introduced.

[0065] 2 is a schematic diagram of a multi-phase VRM 20. The multi-phase VRM 20 may also be referred to as a multi-phase DC-DC Buck type step-down circuit.

[0066] The multi-phase VRM 20 may include a PWM controller 201 and multiple single-phase circuits interleaved in parallel. Each single-phase circuit has the same structure as the single-phase circuit shown in Figure 1 . The first output terminal of each single-phase circuit is connected to an input terminal of a downstream load, outputting the core voltage Vcore required by the downstream load. The PWM controller 201 is configured to provide a PWM voltage signal to some or all of the single-phase circuits in the multi-phase circuit. The current output by the multi-phase VRM 20 to the downstream load is the sum of the output currents of the activated single-phase circuits in the multi-phase circuit.

[0067] The multi-phase VRM 20 requires the use of multiple SPS / DrMOS.

[0068] Additional power consumption from the VRM

[0069] Some possible implementations of the VRM may result in additional power consumption, for example, as follows:

[0070] Certain PWM controller and SPS / DrMOS chip structures can cause excessive power consumption. Typically, a PWM controller is integrated into a power management IC (PMIC), referred to as a PWM controller chip; an SPS / DrMOS chip is integrated into another PMIC, referred to as an SPS / DrMOS chip. The following describes the structures of PWM controller and SPS / DrMOS chips that cause excessive power consumption.

[0071] The PWM control chip includes the structure of the PWM controller 201 described above in FIG. 2 , and also includes an enable pin EN. The EN pin can be connected to a signal interface (e.g., a general-purpose input / output (GPIO) interface) to receive an enable signal, also known as a control signal, from a control unit (e.g., a CPU, an embedded controller (EC)) in an electronic device. When the EN pin receives a logic high level, the PWM control chip operates, implementing the aforementioned PWM controller functionality. When the EN pin receives a logic low level, the PWM control chip does not operate.

[0072] When the VRM's subsequent load (such as a GPU) is working, the EN pin in the PWM control chip is at a logic high level, enabling the PWM control chip to implement the functions of the PWM controller mentioned above; when the VRM's subsequent load (such as a GPU) is not working, the EN pin in the PWM control chip is at a logic low level, and the PWM control chip does not operate.

[0073] Refer to Table 1, which shows the logic level of the EN pin of the PWM control chip.

[0074] Table 1

[0075] As shown in Table 1, the logic high level of the EN pin of the PWM control chip is required to be greater than 0.8V, for example, it can be 3.3V or other values.

[0076] The SPS / DrMOS chip includes the one SPS / DrMOS in FIG. 1 or the multiple SPS / DrMOS in FIG. 2 .

[0077] Referring to Figure 3, Figure 3 exemplifies some pins of the PWM control chip, some pins of the SPS / DrMOS chip, and some peripheral structures. As shown in Figure 3, the PWM control chip may include a PWM pin, an EN pin, etc., and the SPS / DrMOS chip includes an EN pin, a VCC pin, a SYNC pin, a PWM pin, a VIN pin, and some other pins (such as a SW pin for outputting a switching signal, a GND pin, etc.). The EN pin of the PWM control chip can be connected to the GPIO for receiving an enable signal. The PWM pin of the PWM control chip is directly connected to the PWM pin of the SPS / DrMOS chip, and the PWM pin of the PWM control chip is used to output a PWM voltage signal to the PWM pin of the SPS / DrMOS chip. The switch SW pin of the SPS / DrMOS chip is connected to the first end of the inductor L in the VRM, and the L can be the inductor L in Figure 1 or Figure 2.

[0078] In the SPS / DrMOS chip, the VCC pin is used to receive the power supply voltage that drives the SPS / DrMOS chip. The VCC pin is usually directly connected to the public VCC network in the electronic device to receive the driving voltage output by the public VCC network. The driving voltage can be, for example, 3.3V. Typically, as shown in Figure 3, outside the SPS / DrMOS chip, the SYNC pin is also directly connected to the public VCC network to receive the power supply voltage (such as 3.3V) that drives the SPS / DrMOS chip. The PWM pin is used to receive the PWM voltage signal output by the PWM controller of the previous stage. The VIN pin is connected to the high-voltage output terminal of the device power supply and is used to receive the DC voltage output by the device power supply.

[0079] The SYNC pin is a mode switch control pin. When this pin is high, the SPS / DrMOS chip enters active mode. When this pin is at an intermediate level or left floating, the SPS / DrMOS chip enters standby mode. When this pin is low, the SPS / DrMOS chip enters diode emulation mode. In diode emulation mode, when the current of inductor L flows from the second terminal to the first terminal, M2 turns on. When the current of inductor L flows from the first terminal to the second terminal, M2 turns off, preventing current backflow.

[0080] When the SYNC pin is left floating or at an intermediate level, the SPS / DrMOS chip enters standby mode and stops working. Even if the SPS / DrMOS chip receives a PWM voltage signal, it will not output voltage, i.e., it enters standby mode. When the SPS / DrMOS chip enters normal working mode, it will start working as long as the SPS / DrMOS chip receives a PWM signal from the PWM controller.

[0081] The SYNC pin can receive high, low, and intermediate voltage levels. Refer to Table 2, which shows the three-state voltage range of the SYNC pin in the SPS / DrMOS chip.

[0082] Table 2

[0083] As shown in Table 2, the intermediate state level of the SYNC pin is between logic high and logic low. When the SYNC pin is in the intermediate state, the SPS / DrMOS chip and other connected devices are disconnected, entering standby mode.

[0084] Refer to Table 3, which shows the relationship between the SPS / DrMOS mode, SYNC pin status, and the quiescent current on the VCC pin. The quiescent current on the VCC pin refers to the current when there is no signal input to the SPS / DrMOS, that is, the current consumed by the device without being affected by external factors.

[0085] Table 3

[0086] As shown in Table 3, when the SYNC pin is logic high, the VCC pin draws approximately 4mA of quiescent current, resulting in a power consumption of 3.3V*4mA=13.2mW. When the SYNC pin is in an intermediate state, the VCC pin draws approximately 30μA of quiescent current, resulting in a power consumption of only 3.3V*30μA=99μW, significantly lower than when the SYNC pin is logic high.

[0087] When the VRM's downstream load (such as a GPU) is operating, the SYNC pin on the SPS / DrMOS chip is at a logic high level. Directly connecting the SYNC pin to the VCC pin satisfies this requirement. When the SYNC pin is at a logic high level, the SPS / DrMOS chip performs the aforementioned SPS / DrMOS functions.

[0088] However, when the VRM's downstream load (such as a GPU) is not operating, the direct connection between the SYNC pin and the VCC pin results in an additional power consumption of 3.3V*4mA=13.2mW on the VCC pin. If the VRM used in the electronic device is a single-phase VRM, there is an additional power consumption of approximately 13.2mW; if the VRM used in the electronic device is a multi-phase VRM, there is an additional power consumption of approximately 13.2mW*number of phases. If the electronic device is equipped with multiple VRMs, this additional power consumption will be further increased.

[0089] This extra power consumption is not limited to VRMs that use an SPS / DrMOS chip as an SPS / DrMOS. It is also common in VRMs with the following characteristics: the SPS / DrMOS includes a SYNC pin and a VCC pin, a large static current flows on the VCC pin when the SYNC pin is at a logic high level, and the SYNC pin continuously receives a logic high level.

[0090] In order to solve the above problems, the present application provides a power consumption optimization solution, which improves the peripheral connection relationship of the SYNC pin of the SPS / DrMOS in the VRM to achieve the following purposes: when the subsequent load of the VRM is working, a logic high level is input to the SYNC pin to enable the SPS / DrMOS to operate normally; when the subsequent load of the VRM is not working, the SYNC pin is set to an intermediate state to enable the SPS / DrMOS to enter standby mode, thereby reducing the quiescent current on the VCC pin and reducing the additional power consumption on the VCC pin.

[0091] The optimization solution provided in this application can be used to improve the peripheral connection relationship of the SYNC pin in a single-phase VRM, and can also be used to improve the peripheral connection relationship of multiple SYNC pins in a multi-phase VRM.

[0092] The solution provided in this application can be applied to a VRM having the above-mentioned problem, and having a smaller quiescent current on the VCC pin when the SYNC pin of the SPS / DrMOS is in an intermediate state than when it is at a logic high level. For example, it can be applied to a VRM in which a PWM control chip is used as a PWM controller and an SPS / DrMOS chip is used as an SPS / DrMOS. Taking this as an example, when the downstream load of the VRM is not working, there is only 3.3V*30μA=99μW of power consumption on the VCC pin of an SPS / DrMOS, which is significantly reduced compared to the 3.3V*4mA=13.2mW of power consumption on the VCC pin of an SPS / DrMOS in the above problem. When a multi-phase VRM or multiple VRMs are provided in an electronic device, the overall additional power consumption will be further reduced.

[0093] Improved VRM

[0094] The VRM improvements provided in this application primarily involve the following three pins: the PWM controller's EN pin, the SPS / DrMOS's SYNC pin, and the VCC pin. For simplicity, all subsequent references to the EN pin refer to the PWM controller's EN pin, all subsequent references to the SYNC pin refer to the SPS / DrMOS's SYNC pin, and all subsequent references to the VCC pin refer to the SPS / DrMOS's VCC pin.

[0095] (1) The first improved VRM

[0096] Refer to FIG4 , which shows a peripheral connection method of the SYNC pin in an improved VRM provided by an embodiment of the present application.

[0097] As shown in Figure 4, two resistors R1 and R2 and a unidirectional conduction device D1 are added to the periphery of the PWM controller and SPS / DrMOS. That is, the resistors R1, R2, and D1 belong to the peripheral circuit of the PWM controller and SPS / DrMOS, and the peripheral circuit and the PWM controller and SPS / DrMOS are not integrated into the same chip. Among them, the first end of R1 is connected to the VCC pin, and the second end of R1 is connected to the SYNC pin. The first end of R2 is connected to the SYNC pin, and the second end of R2 is grounded. The first end of D1 is connected to the EN pin of the PWM controller, and the second end of D2 is connected to the SYNC pin. When the voltage at the first end of D1 is greater than the voltage at the second end and the difference reaches the conduction voltage drop of D1, D1 conducts unidirectionally from the first end to the second end. D1 can be a unidirectional conduction device or a unidirectional conduction circuit that forms a small conduction voltage drop (less than 1V), for example, a diode.

[0098] Therefore, on the periphery of the SPS / DrMOS, the SYNC pin is no longer directly connected to the VCC pin.

[0099] When the VRM's downstream load is operating, the voltage on the SYNC pin is at a logic high level. This is achieved through the following logic: When the VRM's downstream load is operating, the PWM controller's EN pin is at a logic high level; R1 and R2 divide the voltage between the VCC pin and ground, and the voltage on the SYNC pin is the voltage divided by R2; the voltage difference between the first and second terminals of D1 (i.e., the voltage difference between the EN and SYNC pins) is greater than the conduction voltage drop of D1, causing the first and second terminals of D1 to conduct; then, the voltage on the SYNC pin equals the voltage on the EN pin minus the voltage divided by R2, and the voltage on the SYNC pin is at a logic high level.

[0100] For example, assuming the power supply voltage received by the VCC pin is 3.3V and R1 and R2 have the same resistance value, the voltage divided by R2 on the SYNC pin is 1.65V. Assuming that when the VRM's downstream load is operating, the logic high level of the EN pin is 3.3V and the conduction voltage drop of D1 is 0.3V, D1 will be turned on, and the voltage on the SYNC pin after D1 is turned on will be 3V. If the three-state voltage of the SYNC pin is as shown in Table 2, the voltage on the SYNC pin is a logic high level at this time.

[0101] When the VRM's downstream load is not operating, the voltage on the SYNC pin is at an intermediate level. This is achieved through the following logic: R1 and R2 divide the voltage between the VCC pin and ground, resulting in the voltage on the SYNC pin being the voltage divided by R2. The PWM controller's EN pin is at a logic low level, and the voltage difference between the first and second terminals of D1 (i.e., the voltage difference between the EN pin and the SYNC pin) is less than the conduction voltage drop of D1, resulting in a non-conducting connection between the first and second terminals of D1. The voltage on the SYNC pin remains at the intermediate level, divided by R2.

[0102] For example, assuming the power supply voltage received by the VCC pin is 3.3V and R1 and R2 have the same resistance value, the voltage divided by R2 on the SYNC pin is 1.65V. Assuming that when the downstream load of the VRM is not working, the logic low level of the EN pin is 0.3V, and the conduction voltage drop of D1 is 0.3V, D1 is not conducting, and the voltage on the SYNC pin remains at the voltage divided by R2, 1.65V. If the three-state voltages of the SYNC pin are as shown in Table 2, the voltage on the SYNC pin at this time is at the intermediate state level.

[0103] The R1, R2, voltage on the VCC pin, logic level of the EN pin, on-state voltage drop of D1, etc. provided in this application are used to meet the implementation logic in the above two cases.

[0104] (2) The second improved VRM

[0105] Referring to Figure 5 , which exemplarily illustrates an internal structure of an SPS / DrMOS, within the SPS / DrMOS, a resistor R3 is connected between the SYNC pin and the VCC pin, and a resistor R4 is connected between the SYNC pin and GND.

[0106] Based on the SPS / DrMOS shown in FIG5 , referring to FIG6 , FIG6 shows a peripheral connection method of the SYNC pin in an improved VRM provided by an embodiment of the present application.

[0107] As shown in Figure 6, a unidirectional conduction device D1 is added to the periphery of the PWM controller and the SPS / DrMOS shown in Figure 5. That is, D1 is a peripheral circuit of the PWM controller and SPS / DrMOS, and D1, the PWM controller, and the SPS / DrMOS are not integrated into the same chip. The first end of D1 is connected to the EN pin of the PWM controller, and the second end of D2 is connected to the SYNC pin. When the voltage at the first end of D1 is greater than the voltage at the second end, and the difference reaches the conduction voltage drop of D1, D1 conducts unidirectionally from the first end to the second end. In this way, R3 can perform the function of R1 in Figure 4, and R4 can perform the function of R2 in Figure 4. The VRM based on the structure of Figure 6 can also implement the logic of the VRM based on the structure of Figure 4 described above. For details, please refer to the previous article.

[0108] In some embodiments, R1 in FIG. 4 and R3 and R4 in FIG. 6 may exist simultaneously, so that the parallel resistance of R1 and R3 and R4 divides the voltage between the VCC pin and the ground terminal.

[0109] In some embodiments, R2 in FIG. 4 and R3 and R4 in FIG. 6 may exist simultaneously, so that the parallel resistance of R3, R2, and R4 divides the voltage between the VCC pin and the ground terminal.

[0110] In some embodiments, R1 and R2 in FIG. 4 and R3 and R4 in FIG. 6 may exist simultaneously, so that the parallel resistance of R1 and R3 and the parallel resistance of R2 and R4 divide the voltage between the VCC pin and the ground terminal.

[0111] In the above three embodiments, the voltage division on the SYNC pin can be changed by connecting R1 and R3 in parallel, and / or by connecting R2 and R4 in parallel. By setting R1 and / or R2 according to actual needs, the voltage on the SYNC pin can be at a suitable intermediate state level when the downstream load of the VRM is not working. The suitable intermediate state level can be the middle range of the intermediate state level range of the SYNC pin. For example, when the intermediate state level range of the SYNC pin is 1.3V-1.7V as shown in Table 2, the suitable intermediate state level can be around 1.5V. The suitable intermediate state level can improve the stability of the VRM and ensure that the purpose of this application is achieved.

[0112] In some implementations, the SPS / DrMOS may include only R3 but not R4, and thus must be used in conjunction with R2 in Figure 4. Alternatively, the SPS / DrMOS may include only R4 but not R3, and thus must be used in conjunction with R1 in Figure 4.

[0113] (3) The third improved VRM

[0114] Refer to FIG. 7 , which shows a peripheral connection method of a SYNC pin in an improved VRM provided by an embodiment of the present application. The VRM includes the SPS / DrMOS shown in FIG. 5 .

[0115] As shown in FIG7 , a reserved position L for a unidirectional conduction device D1 is set between the EN pin and the SYNC pin in the periphery of the PWM controller and the SPS / DrMOS shown in FIG5 . D1 , set a resistor R1 between the VCC pin and the SYNC pin to reserve a position L R1 . L D1 When the device is not integrated, the EN pin and the SYNC pin are disconnected; L R1 When the device is not integrated, the VCC pin and the SYNC pin are disconnected at the periphery. D1 , reserved space L R1 The peripheral circuits of the PWM controller and SPS / DrMOS are not integrated into the same chip as the PWM controller and SPS / DrMOS.

[0116] If in L D1 Set D1, L R1 If R1 is not set, the EN pin and the SYNC pin are connected through D1, and the VCC pin and the SYNC pin are disconnected at the periphery. D1, R3, and R4 can be used to achieve the purpose of this application, that is, when the subsequent load of the VRM is working, a logic high level is input to the SYNC pin to enable the SPS / DrMOS to work normally. When the subsequent load of the VRM is not working, the SYNC pin is set to an intermediate state to reduce the additional power consumption on the VCC pin.

[0117] If L D1 If D1 is not set and R1 with 0Ω is set in L2, the EN pin and SYNC pin are disconnected, and the VCC pin and SYNC pin are directly connected at the periphery. This connection method is the VRM with large additional power consumption as shown in Figure 3.

[0118] It can be seen that the VRM shown in Figure 7 can be flexibly adjusted according to actual needs. D1 , L R1 Devices are integrated to achieve different functions.

[0119] (4) The fourth improved VRM

[0120] In normal operation of the PWM controller, when the EN pin of the PWM controller is at a logic high level, the VRM outputs a voltage; when the EN pin of the PWM controller is at a logic low level, the VRM does not output a voltage.

[0121] As described above, the improved VRM's SYNC pin goes high when the EN pin is set to a logic high, and enters an intermediate state when the EN pin is set to a logic low. This indicates that the voltage drops on the SPS / DrMOS's SYNC pin and the PWM controller's EN pin occur simultaneously. However, the SYNC pin's intermediate state voltage range is approximately 1.3V to 1.7V, while the EN pin's low voltage threshold is approximately 0.4V, lower than the SYNC pin's intermediate state voltage. Therefore, when the VRM stops outputting voltage, the SPS / DrMOS may enter standby mode first, followed by a period of time, t, before the PWM controller's EN pin goes low. During this period, the PWM controller's EN pin is enabled, but the SPS / DrMOS enters standby mode. The PWM controller detects that the VRM is not outputting voltage despite its own output being enabled, and reports an output undervoltage fault.

[0122] To avoid the above-mentioned undervoltage fault, the present application also provides an improved VRM, which can make the SYNC pin power off slower than the EN pin, that is, it can ensure that after the EN pin enters the low level, the SYNC pin enters the intermediate state level from the high level, thereby eliminating the output undervoltage fault reported at the moment of power off.

[0123] Refer to FIG8 , which shows a peripheral connection method of the SYNC pin in an improved VRM provided by an embodiment of the present application.

[0124] As shown in Figure 8, based on the structure shown in Figure 4, a capacitor C1 is added to the periphery of the PWM controller and SPS / DrMOS. The first end of C1 is connected to the SYNC pin, and the second end of C1 is grounded. In other words, C1 is located in the peripheral circuit of the PWM controller and SPS / DrMOS, and C1, the PWM controller, and the SPS / DrMOS are not integrated into the same chip.

[0125] When the VRM's downstream load is operating, the PWM controller's EN pin is at a logic high level, D1 is turned on, and the voltage on the SYNC pin is at a logic high level. This charges capacitor C1, with the voltage polarity being positive at the top and negative at the bottom. Soon, the capacitor voltage approaches the logic high level indicated by the EN pin input. When the VRM's downstream load is not operating, the PWM controller's EN pin is at a logic low level, D1 is turned off, and capacitor C1 gradually discharges. The voltage released by C1 is added to the voltage divided by R2 and output to the SYNC pin, gradually decreasing the voltage on the SYNC pin from a logic high level to an intermediate level. Therefore, C1 can be used to adjust the timing of the SYNC pin's transition from a logic high level to an intermediate level, allowing the SYNC pin to power down later than the EN pin.

[0126] The fourth improved VRM can be combined with any of the aforementioned improved VRMs, i.e., C1 can be added not only to FIG4 but also to FIG6 , or to the alternative embodiment of FIG6 , or to FIG7 . The first end of each of the aforementioned C1s is connected to the SYNC pin, and the second end of each is grounded, achieving the same function as C1 in FIG8 .

[0127] For example, referring to FIG9 , FIG9 shows a peripheral connection method of a SYNC pin in an improved VRM provided in an embodiment of the present application. The VRM adds C1 on the basis of the SPS / DrMOS shown in FIG6 .

[0128] C1 may also be referred to as a first capacitor.

[0129] Similarly, the power-on process of the PWM controller presents the same undervoltage risk. After the PWM controller is powered on, the SYNC pin of the SPS / DrMOS may not reach a high level until a period of time t has passed. During this period, the PWM controller's EN pin is enabled, but the SPS / DrMOS is still in standby mode. The PWM controller detects that the VRM is not outputting voltage even though it has enabled its output, and the PWM controller will report an output undervoltage fault. To address this, after the EN pin of the PWM controller reaches a logic high level, the internal components of the PWM controller can delay their operation for a period of time. This prevents the PWM controller from entering the enabled state before the SPS / DrMOS during power-up, thereby eliminating the output undervoltage fault reported at the moment of power-on.

[0130] In the improved VRM of the present application, the circuit including the DrMOS, L, C, and the peripheral structures of the PWM controller and DrMOS shown in Figures 4, 6, and 8 above can be referred to as the first circuit. The circuit including the DrMOS, L, and C can be referred to as the second circuit. L and C can be the same as those in Figures 1 or 2. L can also be referred to as the first inductor, and C can also be referred to as the second capacitor.

[0131] M1 in FIG. 1 or FIG. 2 may also be referred to as a first switching tube, and M2 may also be referred to as a second switching tube.

[0132] The pull-up resistor module may include the aforementioned R1 and / or R3, and the pull-down resistor module may include the aforementioned R2 and / or R4. R1 may be referred to as the first resistor, R2 may be referred to as the second resistor, R3 may be referred to as the third resistor, and R4 may be referred to as the fourth resistor.

[0133] In the improved VRM provided herein, the PWM controller can be integrated into one chip, and the SPS / DrMOS integrated into another, with the two chips being distinct. Alternatively, the PWM controller, SPS / DrMOS, and the aforementioned peripheral circuits (e.g., L, C, C1, R1-R4, etc.) can all be integrated into the same chip.

[0134] In general, the improved VRM provided in this application may include: a PWM controller, one or more SPS / DrMOS transistors, and a peripheral connection relationship between the PWM controller and the one or more SPS / DrMOS transistors. The functions of each module in the VRM can be described above, and the peripheral connection relationship between the PWM controller and the one or more SPS / DrMOS transistors can refer to any of the connection relationships described above in Figures 4, 6-8.

[0135] The improved VRM provided in this application can be a single-phase VRM or a multi-phase VRM.

[0136] The improved VRM provided in this application is used to convert the larger DC voltage (such as 12V) output by the power supply in the electronic device into a stable smaller DC voltage (such as 0.5V-2V), and output it to the subsequent loads such as the CPU, GPU, and ASIC. In addition, the VRM can also reduce the additional power consumption on the VCC pin of the SPS / DrMOS when the subsequent loads of the VRM are not working.

[0137] The present application discloses a printed circuit board (PCB), which may include any of the improved VRMs described above.

[0138] The present application discloses a chip system, which may include any of the improved VRMs introduced above.

[0139] The present application discloses a power supply system, which may include: a power supply, any of the improved VRMs described above, and a load. The power supply is used to provide a DC input voltage to the VRM, and the VRM is used to reduce the DC input voltage provided by the power supply and output it to the load.

[0140] The present application discloses a power supply circuit, which may include: a power supply and any of the improved VRMs described above. The power supply is used to provide a DC input voltage to the VRM, and the VRM is used to reduce the DC input voltage provided by the power supply and output it.

[0141] The present application discloses a power supply circuit, which may include: any of the improved VRMs described above, and a load. The VRM is used to reduce a received DC input voltage and output it to the load.

[0142] The present application discloses an electronic device, which may include any one of the improved VRMs described above.

[0143] The present application discloses an electronic device, which may include the power supply system provided above.

[0144] The present application discloses an electronic device, which may include any one of the power supply circuits provided above.

[0145] In the electronic device provided in the present application, when the post-stage load of the VRM is working, the application processor (AP) (such as a CPU) or controller (such as an embedded controller (EC)) in the electronic device can input a logic high level to the EN pin of the PWM controller through the GPIO; when the post-stage load of the VRM is not working, the AP or controller can input a logic low level to the EN pin of the PWM controller through the GPIO.

[0146] The electronic device disclosed in the present application may be a mobile phone, a tablet computer, a desktop computer, a desktop computer with a touch-sensitive surface or touch panel, a laptop computer, a notebook computer, a smart screen, a wearable device (such as a smart watch, a smart bracelet, etc.), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a car computer, a smart headset, a game console, an Internet of Things (IOT) device or a smart home device, etc.

[0147] Referring to Figure 10, Figure 10 is a schematic diagram of the hardware structure of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 is used in the voltage regulation method provided in an embodiment of the present application.

[0148] As shown in FIG. 10 , the electronic device 100 may include: a power supply 1001 , a power management module 1002 , a processor 1003 , and a memory 1004 .

[0149] The power source 1001 may be a battery, which may be charged in a wired or wireless manner and may also supply power to various modules in the electronic device through the power management module 1002 .

[0150] The power management module 1002 is connected to the power supply 1001 and the processor 1003. The power management module 1002 receives the power supply voltage output by the power supply 1001 and provides power to the processor 1003 and other modules. The power management module 1002 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In other embodiments, the power management module 1002 can also be provided in the processor 1003.

[0151] The processor 1003 may include one or more processing units, for example, the processor 1003 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0152] The memory 1004 can be used to store computer executable program code, which can include instructions. The processor 1003 executes various functional applications and data processing of the electronic device 100 by running the instructions stored in the memory 1004. The memory 1004 can include a program storage area and a data storage area. In a specific implementation, the memory 1004 can include a high-speed random access memory and can also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices.

[0153] The power management module 1002 in this application includes the improved VRM provided above. As shown in Figure 10, the power management module 1002 includes a VRM that powers the GPU in the processor 1003. The high-voltage input of the VRM is connected to the high-voltage output of the power supply 1001, and the low-voltage input of the VRM is connected to the low-voltage output of the power supply 1001 and grounded; the high-voltage output of the VRM is connected to the high-voltage input of the GPU, and the low-voltage output of the VRM is connected to the low-voltage input of the GPU and grounded. The structure of the VRM can refer to the structure of any of the VRMs in Figures 4, 6, and 8, for example.

[0154] Not limited to the GPU, other modules in the electronic device 100, such as AP, ASIC and other load modules, can be configured with corresponding VRMs in the power management module 1002, which are used to reduce the power voltage output by the power supply 1001 to the core voltage required by these load modules and then provide it to the corresponding load modules.

[0155] As shown in FIG10 , electronic device 100 may further include: a wireless communication module 1005, a mobile communication module 1006, an antenna 1005A, an antenna 1006A, a sensor module 1008, a focus motor 1009, a camera 1010, a display screen 1011, etc. Sensor module 1008 may include a gyroscope sensor 1008A, an acceleration sensor 1008B, an ambient light sensor 1008C, an image sensor 1008D, a distance sensor 1008E, etc. Wireless communication module 1005 may include a WLAN communication module, a Bluetooth communication module, etc. The various components of the electronic device may transmit data via a bus.

[0156] The wireless communication function of the electronic device 100 can be implemented through the antenna 1005A, the antenna 1006A, the mobile communication module 1006, the wireless communication module 1005, the modem processor and the baseband processor.

[0157] Antenna 1005A and antenna 1006A can be used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization.

[0158] The mobile communication module 1006 can provide wireless communication solutions, including 2G / 3G / 4G / 5G, for the electronic device 100. The mobile communication module 1006 may include at least one filter, a switch, a power amplifier, a low-noise amplifier (LNA), and the like. The mobile communication module 1006 can receive electromagnetic waves via antenna 1006A, filter and amplify the received electromagnetic waves, and transmit them to the modem processor for demodulation. The mobile communication module 1006 can also amplify the signals modulated by the modem processor and convert them into electromagnetic waves for radiation via antenna 1006A.

[0159] The modem processor may include a modulator and a demodulator. The modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium- or high-frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is passed to the application processor. The application processor outputs audio signals through an audio device or displays images or videos on the display screen 1011.

[0160] The wireless communication module 1005 can provide wireless communication solutions including wireless local area networks (WLAN), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc. applied to the electronic device 100. The wireless communication module 1005 can be one or more devices integrating at least one communication processing module. The wireless communication module 1005 receives electromagnetic waves via the antenna 1005A, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 1003. The wireless communication module 1005 can also receive the signal to be transmitted from the processor 1003, frequency modulate it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 1005A.

[0161] The gyroscope sensor 1008A can be used to determine the motion posture of the electronic device 100. In some embodiments, the angular velocity of the electronic device 100 around three axes (i.e., x, y, and z axes) can be determined by the gyroscope sensor 1008A. The gyroscope sensor 1008A can be used for anti-shake shooting. For example, when the shutter is pressed, the gyroscope sensor 1008A detects the angle of the electronic device 100 shaking, calculates the distance that the lens module needs to compensate based on the angle, and allows the lens to offset the shaking of the electronic device 100 through reverse movement to achieve anti-shake. The gyroscope sensor 1008A can also be used for navigation and somatosensory game scenes.

[0162] Accelerometer 1008B can detect the magnitude of acceleration of electronic device 100 in all directions (generally three axes). When electronic device 100 is stationary, it can detect the magnitude and direction of gravity. It can also be used to identify the electronic device's posture. For example, accelerometer 1008B can be used in applications such as landscape or portrait screen switching and pedometers.

[0163] The ambient light sensor 1008C is used to sense the brightness of the ambient light. The electronic device 100 can adaptively adjust the brightness of the display screen 1011 based on the sensed ambient light brightness. The ambient light sensor 1008C can also be used to automatically adjust the white balance when taking photos.

[0164] Image sensor 1008D, also known as a photosensitive element, utilizes the photoelectric conversion function of a photoelectric device to convert the light image on the photosensitive surface into an electrical signal proportional to the light image. The image sensor can be a charge coupled device (CCD) sensor or a complementary metal oxide semiconductor (CMOS) sensor.

[0165] The distance sensor 1008E can be used to measure distance. The electronic device 100 can measure distance using infrared or laser. In some shooting scenarios, the electronic device 100 can use the distance sensor 1008E to measure distance to achieve fast focusing.

[0166] The focus motor 1009 can be used for fast focusing. The electronic device 100 can control the movement of the lens through the focus motor 1009 to achieve automatic focusing.

[0167] The electronic device 100 can implement a shooting function through an ISP, a camera 1010, a video codec, a GPU, a display screen 1011, and an application processor.

[0168] The ISP processes data fed back by the camera 1010. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, which is then passed to the ISP for processing and transformed into a visible image. The ISP can also perform algorithmic optimization on image noise and brightness. It can also optimize parameters such as exposure and color temperature of the captured scene. In some embodiments, the ISP can be located within the camera 1010.

[0169] The camera 1010 can be used to capture still images or videos. The lens generates an optical image of an object and projects it onto the image sensor. The image sensor converts the optical signal into an electrical signal, which is then transmitted to the ISP for conversion into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard format such as RGB or YUV. In some embodiments, the electronic device 100 may include one or N processors 1010, where N is a positive integer greater than one.

[0170] Video codecs are used to compress or decompress digital images. The electronic device 100 may support one or more video codecs. In this way, the electronic device 100 can open or save pictures or videos in multiple encoding formats.

[0171] Electronic device 100 can implement display functions using a GPU, display screen 1011, and an application processor. A GPU is a microprocessor for image processing that connects display screen 1011 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 1003 may include one or more GPUs that execute program instructions to generate or modify display information.

[0172] Display screen 1011 is used to display images, videos, etc. Display screen 1011 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-oLed, or a quantum dot light-emitting diode (QLED). In some embodiments, electronic device 100 may include one or N display screens 1011, where N is a positive integer greater than 1.

[0173] It should be understood that the structure illustrated in the embodiments of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0174] This application also provides a voltage regulation method, which is applied to the improved VRM provided in this application. In this method, when an operation of starting the VRM's downstream load is detected, a logic high level is input to the EN pin of the PWM controller to enable normal operation of the SPS / DrMOS. When an operation of shutting down the VRM's downstream load is detected, a logic low level is input to the EN pin of the PWM controller to put the SPS / DrMOS into standby mode, thereby reducing the quiescent current on the VCC pin and reducing the excess power consumption on the VCC pin.

[0175] In conjunction with this voltage regulation method, in some embodiments, after the electronic device inputs a logic high level to the EN pin of the PWM controller, it can also obtain the voltage requirement of the load and adjust the duty cycle of the PWM voltage signal output by the PWM controller to the second circuit based on the load voltage requirement. For example, if the load voltage requirement increases, the duty cycle is increased, and vice versa.

[0176] In conjunction with this voltage regulation method, in some embodiments, the electronic device may further obtain the current demand of the load and adjust the number of activated first circuits among the N first circuits of the voltage regulation circuit based on the current demand of the load. For example, if the current demand of the load increases, the number of activated first circuits may be increased, and vice versa.

[0177] The various implementation modes of this application can be combined arbitrarily to achieve different technical effects.

[0178] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described herein are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0179] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0180] The terms "first" and "second" are used for descriptive purposes only and should not be understood to imply or suggest relative importance or implicitly indicate the number of the technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0181] In short, the above description is only an embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made based on the disclosure of this application should be included in the scope of protection of this application.

Claims

1. A voltage regulating circuit, characterized in that: include: A pulse width modulation (PWM) controller, N first circuits, wherein N is a positive integer, wherein: The first circuit includes: a unidirectional conduction device and a second circuit, wherein: The PWM controller is used to output a PWM voltage signal to the second circuit, and the second circuit is used to reduce the voltage received by the high-voltage input terminal of the voltage regulating circuit according to the PWM voltage signal and then output it; The PWM controller includes an EN pin, and the EN pin of the PWM controller is connected to the input end of the enable signal of the PWM controller; the second circuit includes a DrMOS, and the DrMOS includes a SYNC pin and a VCC pin, the VCC pin is connected to the input end of the driving voltage of the DrMOS, and the SYNC pin is not connected to the input end of the driving voltage of the DrMOS; The first end of the pull-up resistor module is connected to the VCC pin, and the second end is connected to the SYNC pin; the first end of the pull-down resistor module is connected to the SYNC pin, and the second end is grounded; the pull-up resistor module includes a first resistor and / or a third resistor, and the pull-down resistor module includes a second resistor and / or a fourth resistor; the first ends of the first resistor and the third resistor are both connected to the VCC pin, and the second ends are both connected to the SYNC pin; the first ends of the second resistor and the fourth resistor are both connected to the SYNC pin, and the second ends are both grounded; the first resistor and the second resistor belong to the voltage regulation circuit and are located at the periphery of the PWM controller and the second circuit; the third resistor and the fourth resistor belong to the DrMOS; The first end of the unidirectional conduction device is connected to the EN pin of the PWM controller, and the second end is connected to the SYNC pin.

2. The voltage regulating circuit according to claim 1, characterized in that: The static current on the VCC pin when the SYNC pin is at an intermediate level is less than the static current on the VCC pin when the SYNC pin is at a logic high level; When the EN pin of the PWM controller receives a logic high level, the unidirectional conductive device is turned on from the first end to the second end, and the SYNC pin receives a high level; When the EN pin of the PWM controller receives a logic low level, the unidirectional conduction device is cut off from the first end to the second end, and the SYNC pin receives an intermediate state level.

3. The voltage regulating circuit according to claim 1 or 2, characterized in that: The voltage regulating circuit further includes: a first capacitor, a first end of the first capacitor is connected to the SYNC pin, and a second end of the first capacitor is grounded.

4. The voltage regulating circuit according to claim 3, characterized in that: The first capacitor is located outside the PWM controller and the second circuit.

5. The voltage regulating circuit according to any one of claims 1 to 4, characterized in that: The unidirectional conducting device is a diode, the anode of the diode is connected to the EN pin of the PWM controller, and the cathode of the diode is connected to the SYNC pin.

6. The voltage regulating circuit according to any one of claims 1 to 5, characterized in that: The DrMOS includes: a driver, a first switch tube and a second switch tube, wherein: For the first switch tube, the drain is connected to the high voltage input terminal of the voltage regulating circuit, the gate is connected to the first output terminal of the driver, and the source is connected to the output terminal of the DrMOS; For the second switch tube, the drain is connected to the output terminal of the DrMOS, the gate is connected to the second output terminal of the driver, and the source is grounded; The input end of the driver is connected to the output end of the PWM controller.

7. The voltage regulating circuit according to claim 6, characterized in that: When the PWM voltage signal is in a positive half cycle, the first output terminal of the driver outputs a first driving signal, the first switch tube is turned on, and the second switch tube is turned off; When the PWM voltage signal is in the negative half cycle, the second output terminal of the driver outputs a second driving signal, the first switch tube is turned off, and the second switch tube is turned on.

8. The voltage regulating circuit according to claim 6 or 7, characterized in that: The second circuit further includes: a first inductor, a second capacitor, The first end of the first inductor is connected to the output end of the DrMOS, the second end of the first inductor and the first end of the second capacitor are both connected to the high voltage output end of the voltage regulating circuit, and the second end of the second capacitor is grounded.

9. The voltage regulating circuit according to any one of claims 1 to 8, characterized in that: The high voltage input end of the voltage regulating circuit is connected to the high voltage output end of the power supply.

10. The voltage regulating circuit according to any one of claims 1 to 9, characterized in that: The high voltage output terminal of the voltage regulating circuit is connected to the high voltage input terminal of the load.

11. The voltage regulating circuit according to claim 10, characterized in that: The current outputted by the high-voltage output terminal of the voltage regulating circuit to the load is the sum of the output currents of the first circuits started among the N first circuits.

12. The voltage regulating circuit according to any one of claims 1 to 11, characterized in that: The voltage regulating circuit is connected to a load, and the load includes any one of the following: a CPU, a GPU, and an ASIC.

13. The voltage regulating circuit according to any one of claims 1 to 12, characterized in that: The input end of the enable signal of the PWM controller is a GPIO interface.

14. The voltage regulating circuit according to any one of claims 1 to 13, characterized in that: The PWM controller is integrated in a first chip, and the DrMOS is integrated in a second chip, and the first chip and the second chip are different.

15. An electronic device, characterized in that: The electronic device comprises the voltage regulating circuit as claimed in any one of claims 1-14.

16. A chip, characterized in that: The chip comprises the voltage regulating circuit as described in any one of claims 1-13.

17. A voltage regulation method, characterized in that: The method is applied to an electronic device, the electronic device is the electronic device according to claim 12, the electronic device includes a load, the load is connected to the voltage regulating circuit, and the method includes: The electronic device detects an operation of starting the load; The electronic device inputs a logic high level to the EN pin of the PWM controller; The electronic device detects an operation of shutting down the load; The electronic device inputs a logic low level to the EN pin of the PWM controller.

18. The method according to claim 17, characterized in that The electronic device inputs a logic high level or a logic low level to the EN pin of the PWM controller through the GPIO interface.

19. The method according to claim 17 or 18, characterized in that After the electronic device inputs a logic high level to the EN pin of the PWM controller, the method further includes: The electronic device obtains a voltage requirement of the load; The electronic device adjusts the duty cycle of the PWM voltage signal output by the PWM controller to the second circuit according to the voltage requirement of the load.

20. The method according to any one of claims 17 to 19, characterized in that: The method further comprises: The electronic device obtains the current demand of the load; The electronic device adjusts the number of activated first circuits among the N first circuits of the voltage regulation circuit according to the current demand of the load.

Images