Drive circuit for semiconductor element and power conversion device

Abstract

In a drive circuit (300) of a semiconductor element (Q), a drive unit (2) supplies a drive voltage to a control terminal (G), thereby transitioning the semiconductor element (Q) between an ON state and an OFF state. A capacitor (4) is connected between the control terminal (G) and a negative terminal (S). A current output unit (5) outputs a pulse current between the control terminal (G) and the negative terminal (S). A timing control unit (6) controls the output timing of the pulse current from the current output unit (5) so that the pulse current is output during an ON period after the semiconductor element (Q) has transitioned to the ON state or during an OFF period after the semiconductor element (Q) has transitioned to the OFF state. A voltage detection unit (7) detects the voltage between a reference potential and the control terminal (G) or the negative electrode terminal (S). A temperature estimation unit (8) estimates the temperature of the semiconductor element (Q) on the basis of the voltage detected by the voltage detection unit (7) during the ON period or the OFF period.

Description

Semiconductor element drive circuit and power conversion device

[0001] The present disclosure relates to a drive circuit for a semiconductor device and a power conversion device including the drive circuit for a semiconductor device.

[0002] BACKGROUND ART In recent years, semiconductor elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) have become widespread. These semiconductor elements are used, for example, as power semiconductor elements in power conversion devices.

[0003] Miniaturization of semiconductor elements requires the application of high-density current to the semiconductor elements. An increase in current density increases the energy loss of the semiconductor elements, which can lead to an increase in temperature of the semiconductor elements. If the temperature of the semiconductor elements rises excessively, the semiconductor elements may be destroyed. From this perspective, temperature management of semiconductor elements is important. Techniques for temperature management of semiconductor elements have been proposed (see, for example, Japanese Patent No. 7042991 (Patent Document 1)).

[0004] Patent No. 7042991

[0005] Julio Brandelero, Jeffrey Ewanchuk and Stefan Mollov, On-line Virtual Junction Temperature Measurement via DC Gate Current Injection, CIPS 2018, 423-429.

[0006] There is always a demand for highly accurate estimation of the temperature of a semiconductor element. The semiconductor device disclosed in Patent Document 1 has room for improvement in the accuracy of estimation of the temperature of the semiconductor element.

[0007] The present disclosure has been made in consideration of the above-mentioned problems, and one of the objects of the present disclosure is to improve the accuracy of estimating the temperature of a semiconductor element.

[0008] In a semiconductor device drive circuit according to one embodiment, the semiconductor device has a positive terminal, a negative terminal, and a control terminal for controlling a current flowing between the positive and negative terminals. The semiconductor device drive circuit includes a drive unit, a capacitor, a pulse current source, a timing control unit, a voltage detection unit, and a temperature estimation unit. The drive unit supplies a drive voltage to the control terminal to transition the semiconductor device between an ON state and an OFF state. The capacitor is connected between the control terminal and the negative terminal. The current output unit outputs a pulse current between the control terminal and the negative terminal. The timing control unit controls the output timing of the pulse current from the current output unit so that the pulse current is output during an ON period after the semiconductor device has transitioned to the ON state or during an OFF period after the semiconductor device has transitioned to the OFF state. The voltage detection unit detects a voltage between the control terminal or the negative terminal and a reference potential. The temperature estimation unit estimates the temperature of the semiconductor device based on the voltage detected by the voltage detection unit during the ON period or the OFF period.

[0009] According to the configuration of the present disclosure, a drive circuit with improved accuracy in estimating the temperature of a semiconductor element is provided.

[0010] 1 is a block diagram showing an example of the configuration of a power conversion system using a power conversion device according to a first embodiment. FIG. 2 is a circuit block diagram showing an example of the configuration of a drive circuit that drives a semiconductor module. FIG. 3 is a circuit block diagram showing an example of the configuration of a current output unit. FIG. 4 is a circuit block diagram showing a first example of the configuration of the drive circuit for the semiconductor module according to the first embodiment. FIG. 5 is a circuit block diagram showing a second example of the configuration of the drive circuit for the semiconductor module according to the first embodiment. FIG. 6 is a circuit block diagram showing a third example of the configuration of the drive circuit for the semiconductor module according to the first embodiment. FIG. 7 is a circuit block diagram showing a fourth example of the configuration of the drive circuit for the semiconductor module according to the first embodiment. FIG. 8 is a time chart for explaining an example of the temperature estimation process of a power semiconductor element Q according to the first embodiment. FIG. 9 is a diagram showing a time change in the voltage detected by the voltage detection unit when a capacitor is not provided. FIG. 10 is a diagram showing a time change in the voltage detected by the voltage detection unit when a capacitor is provided. FIG. 11 is a circuit block diagram showing a first example of the configuration of a drive circuit for a semiconductor module according to a second embodiment. FIG. 12 is a circuit block diagram showing a second example of the configuration of a drive circuit for a semiconductor module according to the second embodiment.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0012] In the following embodiments, a configuration in which a semiconductor device drive circuit according to the present disclosure is applied to a power conversion device will be described as an example. However, the application of the semiconductor device drive circuit according to the present disclosure is not limited to power conversion applications.

[0013] 1 is a block diagram showing an example of the configuration of a power conversion system using a power conversion device according to embodiment 1. The power conversion system 900 includes a power conversion device 100, a power supply 91, and a load 92.

[0014] The power supply 91 is a DC power supply that supplies DC power to the power conversion device 100. The power supply 91 may include, for example, a DC system, a solar cell, or a storage battery. The power supply 91 may also include an AC / DC converter (e.g., a rectifier circuit) connected to an AC system. The power supply 91 may also include a DC / DC converter that increases or decreases the voltage of the DC power output from the DC system.

[0015] The load 92 is, for example, a device driven by AC power supplied from the power conversion device 100. The load 92 is, for example, a three-phase motor for a hybrid vehicle, an electric vehicle, a railcar, an elevator, or an air conditioning device. The load 92 may also be, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system.

[0016] The power conversion device 100 is electrically connected between a power source 91 and a load 92, and performs power conversion operations. The power conversion device 100 is, for example, a three-phase inverter. The power conversion device 100 converts DC power supplied from the power source 91 into AC power and supplies the AC power to the load 92. The power conversion device 100 includes a main conversion circuit 200 and a drive circuit 300.

[0017] The main conversion circuit 200 converts DC power supplied from a power source 91 into AC power and supplies the AC power to a load 92. The main conversion circuit 200 includes a semiconductor module 201. In this example, the semiconductor module 201 is a two-level, three-phase full-bridge circuit that includes six power semiconductor elements Q1 to Q6 and six freewheel diodes DI1 to DI6. The freewheel diodes DI1 to DI6 are connected in anti-parallel to the power semiconductor elements Q1 to Q6, respectively. The power semiconductor elements Q1 and Q2 are connected in series to form a U-phase arm of the full-bridge circuit. The power semiconductor elements Q3 and Q4 are connected in series to form a V-phase arm of the full-bridge circuit. The power semiconductor elements Q5 and Q6 are connected in series to form a W-phase arm of the full-bridge circuit. The output terminals of each phase arm (i.e., the three output terminals of the semiconductor module 201) are electrically connected to the load 92.

[0018] The drive circuit 300 drives the semiconductor module 201 in the main conversion circuit 200 so that the desired power is supplied from the power conversion device 100 to the load 92. That is, the drive circuit 300 controls each of the six power semiconductor elements Q1 to Q6. The configuration of the drive circuit 300 will be described in detail with reference to FIGS. 2 to 7.

[0019] 1 illustrates the power conversion device 100 as a two-level, three-phase inverter, but the present disclosure is not limited to this. The power conversion device 100 may be a multi-level (three or more levels) power conversion device. When supplying power to a single-phase load, the power conversion device 100 may be a single-phase inverter. When supplying power to a DC load, the power conversion device 100 may be a DC / DC converter or an AC / DC converter.

[0020] <Schematic Configuration of Drive Circuit> Fig. 2 is a circuit block diagram showing an example of the configuration of a drive circuit 300 that drives the semiconductor module 201. To avoid cluttering the page, Fig. 2 representatively illustrates only a power semiconductor element Q, which is one of the six power semiconductor elements Q1 to Q6 shown in Fig. 1. The power semiconductor element Q is a MOSFET, an IGBT, a MESFET (Metal-Semiconductor Field-Effect Transistor), a bipolar transistor, or the like. The material of the power semiconductor element Q is typically Si, but other materials (SiC, GaN, GaN, etc.) may also be used. ａ 20 ３ , diamond, etc.

[0021] In the following, an example will be described in which the power semiconductor element Q is a MOSFET. The power semiconductor element Q includes a drain D, a source S, and a gate G. A current flowing between the drain D and the source S is controlled by a drive voltage applied to the gate G. The drain D, the source S, and the gate G correspond to the "positive terminal," the "negative terminal," and the "control terminal," respectively, according to the present disclosure.

[0022] In addition to controlling the power semiconductor element Q, the drive circuit 300 executes a "temperature estimation process" for estimating the temperature of the power semiconductor element Q. The drive circuit 300 includes an integrated control unit 1, a drive unit 2, a resistor 3, a capacitor 4, a current output unit 5, a timing control unit 6, a voltage detection unit 7, and a temperature estimation unit 8.

[0023] The central control unit 1 is realized by an integrated circuit such as a microprocessor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The central control unit 1 controls the power semiconductor elements Q so that a desired amount of power is supplied to the load 92. For example, the central control unit 1 performs pulse width modulation (PWM) control to modulate the time during which the power semiconductor elements Q are in an on state, depending on the power to be supplied (or the voltage to be output) to the load 92. The central control unit 1 then outputs a drive command DR to the drive unit 2 so that, at each point in time, an on signal is output to the power semiconductor elements Q (any of Q1 to Q6) that should be in an on state, and an off signal is output to the power semiconductor elements Q that should be in an off state.

[0024] Furthermore, when the conditions for executing the temperature estimation process are satisfied (for example, when a request to execute the temperature estimation process is generated), the central control unit 1 outputs a command CMD to the timing control unit 6 to execute the temperature estimation process.

[0025] The driver 2 is electrically connected to a power supply voltage VDD and ground GND. The driver 2 generates a drive voltage for driving the power semiconductor element Q in accordance with a drive command DR from the integrated controller 1, and outputs the drive voltage to the gate G of the power semiconductor element Q. Hereinafter, this drive voltage will be referred to as a "gate voltage Vg." By switching the gate voltage Vg between a high level and a low level, the power semiconductor element Q transitions between an ON state and an OFF state. The integrated controller 1 and driver 2 may be configured integrally.

[0026] The resistor 3 is electrically connected, for example, in a wiring portion between the gate G of the power semiconductor element Q and the driver 2. The wiring portion is a loop wiring that electrically connects the gate G of the power semiconductor element Q and the driver 2, and also electrically connects the source S of the power semiconductor element Q and the driver 2. Depending on the application of the driver circuit 300, the resistor 3 may be connected between the gate G of the power semiconductor element Q and the driver 2 (see FIGS. 5 and 7).

[0027] The capacitor 4 is connected, for example, in the wiring portion between the gate G and source S of the power semiconductor element Q. The capacitance of the capacitor 4 is defined as "C ｏｕｔ The capacitor 4 is a parasitic capacitance C ｄｉｅ The role of the capacitor 4 will be explained in detail later.

[0028] Here, it has been described that the resistor 3 and the capacitor 4 are both provided in the wiring portion. However, the resistor 3 may be provided inside the drive portion 2. The capacitor 4 may be provided inside the drive portion 2 or inside the power semiconductor element Q.

[0029] The current output unit 5 outputs a pulse current to the power semiconductor element Q in accordance with a control signal (a switch signal SW described later) from the timing control unit 6 .

[0030] 3 is a circuit diagram showing an example of the configuration of the current output unit 5. The current output unit 5 includes, for example, a current source 51 and a current switch 52.

[0031] The current source 51 may be any known current source. For example, the current source 51 may be a bipolar transistor. The current source 51 may be a current mirror or may be a constant voltage source with a resistor connected to its output. Depending on the circuit configuration, the current source 51 may be configured as a current source that outputs a current or as a current sink that sinks a current.

[0032] The current switch 52 switches between an ON state and an OFF state in response to a switch signal SW from the timing control unit 6. The current switch 52 is a switching element that operates at a relatively high speed, such as a MOSFET. The current switch 52 may also be an ultra-high speed switching element, such as a GaN HEMT (High Electron Mobility Transistor).

[0033] The current source 51 and the current switch 52 are connected in parallel between the gate G (or source S) of the power semiconductor element Q and a reference node ND. The current source 51 and the current switch 52 may be directly connected to the gate G (or source S) of the power semiconductor element Q. The current source 51 and the current switch 52 may be indirectly connected to the gate G (or source S) of the power semiconductor element Q. In other words, the current source 51 and the current switch 52 may be connected to the gate G or source S of the power semiconductor element Q via other electronic components (semiconductor elements, resistors, etc.) mounted in the drive unit 2. The reference node ND is a node that provides a reference potential Vref. The reference potential Vref may be, for example, a power supply voltage VDD connected to the drive unit 2 or the ground GND of the drive unit 2.

[0034] When the current switch 52 is switched from the off state to the on state, the current output unit 5 starts outputting current to the power semiconductor element Q. When the current switch 52 is switched from the on state to the off state, the current output unit 5 stops outputting current to the power semiconductor element Q.

[0035] 2 again, in response to a command CMD from the general control unit 1, the timing control unit 6 outputs a switch signal SW for controlling the current switch 52 in the current output unit 5. In addition, in response to the command CMD from the general control unit 1, the timing control unit 6 outputs a trigger signal TRG indicating the timing at which the temperature estimating unit 8 should estimate the temperature of the power semiconductor element Q.

[0036] The voltage detection unit 7 directly or indirectly detects the voltage between the gate G (or source S) of the power semiconductor element Q and the reference potential Vref. When the voltage is detected indirectly, other electronic components (semiconductor elements, resistors, etc.) mounted on the drive unit 2 may be present between the voltage detection unit 7 and the power semiconductor element Q. Hereinafter, the voltage detected by the voltage detection unit 7 will be referred to as the "detected voltage V Ｉｇ The voltage detection unit 7 detects the voltage V Ｉｇ is output to the temperature estimation unit 8.

[0037] In response to the trigger signal TRG from the timing control unit 6, the temperature estimation unit 8 detects the detected voltage V Ｉｇ Hereinafter, the temperature estimated by the temperature estimator 8 will be referred to as the "element temperature TEMP." More specifically, the temperature estimator 8 estimates the temperature of the power semiconductor element Q based on the detected voltage V from the voltage detector 7. Ｉｇ The temperature estimation unit 8 stores conversion data indicating the correspondence relationship between the detected voltage V obtained from the voltage detection unit 7 and the element temperature TEMP (details will be described later). Ｉｇ is converted into the element temperature TEMP.

[0038] The temperature estimator 8 outputs (feeds back) the estimated result of the element temperature TEMP to the central controller 1. This enables the central controller 1 to execute control according to the element temperature TEMP. For example, if the element temperature TEMP is higher than a specified temperature, the central controller 1 may change the drive pattern of the power semiconductor element Q so as to reduce loss in the power semiconductor element Q. The central controller 1 may output the element temperature TEMP or a warning to a host system (not shown) of the power conversion device 100.

[0039] 2, for ease of understanding, the drive circuit 300 has been described as being divided into a large number of components (functional blocks). However, some of the components may be integrated. Alternatively, any of the components may be further divided. For example, one or both of the current output unit 5 and the voltage detection unit 7 may be integrated into the drive unit 2. The overall control unit 1 may have the functions of one or both of the timing control unit 6 and the temperature estimator 8.

[0040] <Specific Configurations of the Drive Circuit> Four specific configuration examples of the drive circuit 300 of the semiconductor module 201 will be described.

[0041] 4 is a circuit block diagram showing a first example of the configuration of a drive circuit of the semiconductor module 201 according to the first embodiment. The drive circuit 301 includes a current output unit 5 connected to the source S of the power semiconductor element Q. That is, a current source 51 and a current switch 52 are each connected between the source S of the power semiconductor element Q and a reference node ND. A resistor 3 is connected between the gate G of the power semiconductor element Q and the drive unit 2.

[0042] 5 is a circuit block diagram showing a second example of the configuration of the drive circuit of the semiconductor module 201 according to the first embodiment. The drive circuit 302 differs from the drive circuit 301 in that a resistor 3 is electrically connected between the source S of the power semiconductor element Q and the drive unit 2.

[0043] 6 is a circuit block diagram showing a third example of the configuration of the drive circuit of the semiconductor module 201 according to the first embodiment. The drive circuit 303 includes a current output unit 5 connected to the gate G of the power semiconductor element Q. That is, a current source 51 and a current switch 52 are each connected between the gate G of the power semiconductor element Q and a reference node ND. A resistor 3 is connected between the gate G of the power semiconductor element Q and the drive unit 2.

[0044] 7 is a circuit block diagram showing a fourth example of the configuration of the drive circuit of the semiconductor module 201 according to Embodiment 1. The drive circuit 304 differs from the drive circuit 303 in that a resistor 3 is electrically connected between the source S of the power semiconductor element Q and the drive unit 2.

[0045] Other than the above, the configuration of drive circuits 301 to 304 is the same as (common to) the configuration described in Fig. 2, and therefore description thereof will not be repeated. Note that these four circuit configuration examples are merely illustrative, and the circuit configuration of drive circuit 300 is not limited to these.

[0046] <Temperature Estimation Processing> The temperature estimation processing of the power semiconductor element Q in the drive circuit 300 of the semiconductor module 201 will be described using an example circuit configuration in which the current output unit 5 is connected to the source S of the power semiconductor element Q (see FIG. 4 or 5).

[0047] 8 is a time chart for explaining an example of the temperature estimation process for the power semiconductor element Q in the first embodiment. The horizontal axis represents elapsed time. The vertical axis represents, from top to bottom, the drive command DR from the integrated control unit 1 to the drive unit 2, the gate voltage Vg from the drive unit 2 to the gate G of the power semiconductor element Q, the switch signal SW from the timing control unit 6 to the current output unit 5, and the detected voltage V by the voltage detection unit 7. Ｉｇ Represents.

[0048] 4 or 5 and 8, the integrated control unit 1 outputs a drive command DR to the drive unit 2. The drive command DR is a signal that alternates between a high level (indicated by H) that commands the drive of the power semiconductor element Q and a low level (indicated by L) that commands the stop of the drive of the power semiconductor element Q.

[0049] The driver 2 generates a gate voltage Vg in accordance with the drive command DR. More specifically, when the driver 2 receives a high-level drive command DR, it generates a positive voltage Vcc that is higher than the threshold voltage, and when the driver 2 receives a low-level drive command DR, it generates a negative voltage Vee that is equal to or lower than the threshold voltage (which may be zero voltage). The driver 2 applies the generated voltage to the gate G of the power semiconductor element Q as the gate voltage Vg.

[0050] The time chart shown in FIG. 8 includes a temperature estimation period in which the temperature estimation process is executed and a normal operation period in which the temperature estimation process is not executed.

[0051] <Normal Operation> First, the normal operation period will be described. During normal operation, the current switch 52 in the current output unit 5 is always on. If the current switch 52 is an enhancement type element (such as an n-channel MOSFET), the switch signal SW is always at a high level, as shown in Figure 8. Although not shown, if the current switch 52 is a depletion type element (such as a p-channel MOSFET), the switch signal SW is always at a low level.

[0052] During the period from time t1 to time t2, the power semiconductor element Q is turned on. More specifically, at time t1, the drive command DR switches from low level to high level. Then, after a rise period due to a time constant corresponding to the gate resistance and capacitance of the power semiconductor element Q, the gate voltage Vg reaches the positive voltage Vcc at time t2. During this period, the current switch 52 is always in the on state. Therefore, the gate current supplied from the drive unit 2 to the gate G of the power semiconductor element Q flows directly to the reference node ND via the current switch 52. Similarly, the current from the current source 51 also flows to the reference node ND via the current switch 52. Therefore, the detected voltage V by the voltage detection unit 7 Ｉｇ remains unchanged at Vss.

[0053] After the rising period has elapsed, the gate voltage Vg is stabilized at Vcc during the period from time t2 to time t3. Hereinafter, this period will be referred to as the "on period" (indicated by Ton in the drawing).

[0054] During the period from time t3 to time t4, the power semiconductor element Q is turned off. More specifically, at time t3, the drive command DR switches from high level to low level. Then, after a falling period due to the time constant, the gate voltage Vg reaches the negative voltage Vee at time t4. During this time, the current switch 52 is always in the on state. Therefore, the gate current flows to the reference node ND via the current switch 52. The current from the current source 51 also flows to the reference node ND via the current switch 52. Therefore, the detected voltage V by the voltage detection unit 7 Ｉｇ remains unchanged at Vss.

[0055] After the falling period has elapsed, the gate voltage Vg stabilizes at Vee from time t4 onwards. Hereinafter, this period will be referred to as an "off period" (indicated by Toff in the drawing).

[0056] <Temperature Estimation Process> Next, the temperature estimation period will be described. The temperature estimation process is performed during an ON period or an OFF period in which the gate voltage Vg is stable.

[0057] First, the temperature estimation process during the on-period will be described. At time t5, the drive command DR is switched from low to high. At time t6, when a predetermined delay time d1 has elapsed since time t5, the timing control unit 6 switches the switch signal SW from high to low. The delay time d1 is preferably set to a length equal to or longer than the time constant of the power semiconductor element Q.

[0058] When the switch signal SW goes low at time t6, the current switch 52 is turned off. As a result, the current from the current source 51 flows to the source S of the power semiconductor element Q instead of the reference node ND. In other words, current injection from the current source 51 to the power semiconductor element Q begins. As a result, the voltage V detected by the voltage detection unit 7 Ｉｇ rises.

[0059] At time t6, the current switch 52 is turned off and current injection into the power semiconductor element Q is started. Then, the detected voltage V Ｉｇ (t-t6) is expressed as the following formula (1).

[0060] In formula (1), R ｇ is the resistance of the peripheral circuit of the power semiconductor element Q that contributes to the gate resistance of the power semiconductor element Q (excluding the gate resistance of the power semiconductor element Q itself). ｇ is referred to as the "peripheral gate resistance". ｇ includes the resistance of the driving unit 2, the resistance 3 (resistance of the wiring unit), etc. ｇｉｎｔ is the gate resistance of the power semiconductor element Q itself. ｇｉｎｔis called the "internal gate resistor." The internal gate resistor R ｇｉｎｔ is fabricated on the power semiconductor element Q using a material such as polysilicon. ｇｉｎｔ includes the parasitic resistance due to the gate wiring pattern on the power semiconductor element Q. ｇ is the current supplied from the current output unit 5 to the power semiconductor element Q (between the gate G and the source S). ｇ is referred to as the "supply current". ｄｉｅ is the parasitic capacitance of the power semiconductor element Q (the capacitance of the power semiconductor element Q as seen from the gate G of the power semiconductor element Q).

[0061] When current injection into the power semiconductor element Q starts at time t6, the sum of the peripheral gate resistance and the internal gate resistance (R ｇ +R ｇｉｎｔ ) is supplied with a current I ｇ Base voltage V0 multiplied by (R ｇ +R ｇｉｎｔ ) I ｇ occurs steadily (see the first term on the right side of equation (1)).

[0062] In addition, the parasitic capacitance C of the power semiconductor element Q ｄｉｅ A charging voltage Vchg occurs due to the charging of the parasitic capacitance C (see the second term on the right side of equation (1)). The charging voltage Vchg increases as time (t-t6) passes after the current switch 52 is turned off. ｄｉｅ can be considered to be basically constant. In addition, the supply current I from the current source 51 to the power semiconductor element Q ｇ Under such conditions, the detected voltage V Ｉｇ increases linearly.

[0063] At time t7, the timing control unit 6 changes the switch signal SW from low level back to high level. This turns on the current switch 52. Then, the current from the current source 51 starts to flow to the reference node ND, and the charge stored in the parasitic capacitance of the power semiconductor element Q is discharged to the reference node ND. Therefore, the detection voltage V Ｉｇ drops to Vss.

[0064] The period during which the switch signal SW is set to a low level and the current switch 52 is controlled to be in an off state is referred to as "toff1." In this example, the trigger signal TRG is output from the timing control unit 6 to the temperature estimation unit 8 at time t7, so toff1=t7-t6. In equation (1), if the time difference toff1 from time t6 to time t7 is constant, the detected voltage V detected by the voltage detection unit 7 is Ｉｇ The value obtained by subtracting the charging voltage Vchg of the parasitic capacitance of the power semiconductor element Q from the supply current I is expressed by the following equation (2). ｇ can be controlled to a constant value. Therefore, the second term on the left side of equation (2) is a constant value. Therefore, equation (2) expresses the voltage V detected by the voltage detection unit 7 as Ｉｇ (toff1) is the sum of the peripheral gate resistance and the internal gate resistance (R ｇ +R ｉｎｔ )

[0065] Peripheral gate resistance R ｇ and the internal gate resistor R ｇｉｎｔ Each of these gate resistances has a temperature dependency. If each of these gate resistances changes linearly with respect to temperature T, the peripheral gate resistance R ｇ and the internal gate resistor R ｇｉｎｔ are expressed as the following formulas (3) and (4), respectively (K １ , K ２ is a constant).

[0066] Peripheral gate resistance R ｇ The temperature dependence of the internal gate resistance R ｇｉｎｔ In other words, when the change in gate resistance due to the change in temperature T is sufficiently smaller than the temperature dependence of ΔR ｇ <ΔR ｇｉｎｔ When the sum of the peripheral gate resistance and the internal gate resistance (R ｇ +R ｇｉｎｔ ) can be considered to be determined according to the amount of change in the temperature of the power semiconductor element Q. Therefore, the detected voltage V Ｉｇ If (toff1) is obtained, the sum of the peripheral gate resistance and the internal gate resistance (R ｇ +R ｇｉｎｔ) is obtained, and thereby the temperature change amount of the power semiconductor element Q is obtained. This means that the detected voltage V Ｉｇ This means that conversion data that defines the correspondence between (toff1) and the temperature of the power semiconductor element Q can be prepared in advance.

[0067] The conversion data is prepared, for example, as follows: The drive circuit 300 and the power semiconductor element Q are placed in a thermostatic chamber. The element temperature TEMP is changed to various temperatures. Then, at each temperature, the element temperature TEMP and the voltage V detected by the voltage detection unit 7 are calculated. Ｉｇ The correspondence with (toff1) is recorded.

[0068] The temperature estimating unit 8 stores the conversion data thus prepared in advance. Ｉｇ When (toff1) is received, the detection voltage V Ｉｇ The temperature estimating unit 8 converts the temperature (toff1) into the element temperature TEMP. The temperature estimating unit 8 outputs the element temperature TEMP to the general control unit 1.

[0069] Next, the temperature estimation process during the off period will be described. At time t8, the drive command DR switches from high to low. At time t9, when a predetermined delay time d2 has elapsed since time t8, the switch signal SW switches from high to low. Like the delay time d1, the delay time d2 can be set to a time length equal to or longer than the time constant of the power semiconductor element Q. When the switch signal SW switches to low, the current switch 52 is turned off, and the current from the current source 51 flows to the power semiconductor element Q instead of the reference node ND.

[0070] When current injection into the power semiconductor element Q starts at time t9, the sum of the peripheral gate resistance and the internal gate resistance (R ｇ +R ｇｉｎｔ ) is supplied with a current I ｇ Base voltage V0 multiplied by (R ｇ +R ｇｉｎｔ) Ig is generated steadily (see the first term on the right side of the following equation (5)). In addition, a charging voltage Vchg is generated due to charging of the parasitic capacitance of the power semiconductor element Q. The charging voltage Vchg increases as time passes (t-t9) after the current switch 52 is turned off at time t8 (see the second term on the right side of the equation (5)). The parasitic capacitance C ｄｉｅ can be regarded as a constant value. In addition, the supply current I from the current source 51 to the power semiconductor element Q ｇ In this case, the detected voltage V Ｉｇ increases linearly.

[0071] At time t10, when the switch signal SW is returned from low level to high level, the current switch 52 is turned on. Then, the current from the current source 51 starts to flow to the reference node ND, and the charge stored in the parasitic capacitance of the power semiconductor element Q is discharged to the reference node ND. Therefore, the detection voltage V Ｉｇ drops to Vss.

[0072] The period during which the current switch 52 is controlled to the off state is denoted as "toff2" (=t10-t9). During the off period, as well as during the on period, the detected voltage V Ｉｇ (toff2) is the sum of the peripheral gate resistance and the internal gate resistance (R ｇ +R ｇｉｎｔ ) Therefore, the following equation (6) holds true.

[0073] Although detailed description will not be repeated, the detected voltage V Ｉｇ By preparing conversion data in advance that defines the correspondence between (toff2) and the element temperature TEMP, the detection voltage V Ｉｇ The element temperature TEMP can be calculated from (toff2).

[0074] <Role of the capacitor> The capacitor 4 detects the detected voltage V Ｉｇ The following will explain the influence of the ON period as a representative example, but the same applies to the OFF period.

[0075] FIG. 9 shows the voltage V detected by the voltage detector 7 when the capacitor 4 is not provided. Ｉｇ The horizontal axis represents the elapsed time, and the vertical axis represents the detected voltage V Ｉｇ The same applies to FIG. 10 described later.

[0076] A time t6 at which the switch signal SW is switched from high to low may be delayed by a time t6', which is Δt before the actual time t6. The time t6 may be delayed or accelerated by the time t6'. Figure 9 shows an example in which the switch signal SW is switched from high to low at a time t6', which is Δt before the actual time t6.

[0077] Detection voltage V for calculating element temperature TEMP Ｉｇ is acquired multiple times during the period from time t6′ to time t7. For simplicity, the detected voltage V Ｉｇ The situation where one of the acquisition times is time t6′ (i.e., the detection voltage V Ｉｇ is equal to the base voltage V0) will be explained as an example.

[0078] 9, the base voltage when the switching time of the switch signal SW is t6 is written as V0, while the base voltage when the switching time of the switch signal SW is t6' is written as V0'. A deviation of Δt in the switching time of the switch signal SW causes an error of ΔV0 in the base voltage (in this example, V0 > V0', so ΔV0 = V0 - V0'). This error ΔV0 is expressed by the following equation (7):

[0079] In addition, the parasitic capacitance C of the power semiconductor element Q ｄｉｅ may vary due to voltage fluctuations and / or temperature fluctuations of the power semiconductor element Q. ｄｉｅ The amount of change in ｄｉｅ ". The lower diagram of FIG. 9 shows the parasitic capacitance C ｄｉｅ When the detected voltage V Ｉｇ In comparison with the time variation of the parasitic capacitance C ｄｉｅ When the detected voltage V changesＩｇ The time variation of the parasitic capacitance C ｄｉｅ When changes, the error ΔV0 of the base voltage is expressed as C in equation (7). ｄｉｅ (C ｄｉｅ +ΔC ｄｉｅ ) is replaced with the following equation (8).

[0080] Parasitic capacitance C ｄｉｅ The change in ΔC ｄｉｅ can take on either a positive or negative value depending on voltage and / or temperature fluctuations. ｄｉｅ 1. In this case, the detected voltage V Ｉｇ The slope of I ｇ / (C ｄｉｅ +ΔC ｄｉｅ ) is the parasitic capacitance C ｄｉｅ When there is no change in the detected voltage V Ｉｇ The slope of I ｇ / C ｄｉｅ However, on the other hand, ΔC ｄｉｅ If <0, the parasitic capacitance C ｄｉｅ When the detected voltage V changes Ｉｇ The slope of I ｇ / (C ｄｉｅ +ΔC ｄｉｅ ) has a parasitic capacitance C ｄｉｅ When there is no change in the detected voltage V Ｉｇ The slope of I ｇ / C ｄｉｅ It will be steeper than

[0081] FIG. 10 shows the detected voltage V detected by the voltage detector 7 when the capacitor 4 is provided. Ｉｇ The capacitor 4 has a capacitance C ｏｕｔ It has.

[0082] Since the explanation is the same as that in FIG. 9, it will not be repeated. ｏｕｔ The capacitor 4 is provided with a parasitic capacitance C ｄｉｅ If does not change, then in equation (7), C ｄｉｅ (C ｏｕｔ +C ｄｉｅ ), the base voltage error ΔV0 is expressed as in the following equation (9).

[0083] Capacity C ｏｕｔ The capacitor 4 is provided with a parasitic capacitance C ｄｉｅ When C changes in equation (7), ｄｉｅ (C ｏｕｔ +C ｄｉｅ +ΔC ｄｉｅ ), the base voltage error ΔV0 is expressed as in the following equation (10).

[0084] Parasitic capacitance C ｄｉｅ When comparing the case where the coefficient of Δt does not change, the coefficient of Δt when the capacitor 4 is not provided is Ig / C ｄｉｅ (see equation (7)), whereas the coefficient of Δt when the capacitor 4 is provided is Ig / (C ｏｕｔ +C ｄｉｅ ) (see equation (9)). Parasitic capacitance C ｄｉｅ When the capacitor 4 is not provided, the coefficient of Δt is Ig / (C ｄｉｅ +ΔC ｄｉｅ ) (see equation (8)), whereas the coefficient of Δt when the capacitor 4 is provided is Ig / (C ｏｕｔ +C ｄｉｅ +ΔC ｄｉｅ ) (see equation (10)). In other words, when the capacitor 4 is provided, the capacitance C of the capacitor 4 is included in the denominator of the coefficient of Δt, compared to when the capacitor 4 is not provided. ｏｕｔ This coefficient is reduced by the amount of the parasitic capacitance C ｄｉｅ Even when the parasitic capacitance C ｄｉｅ This also applies if does not change.

[0085] In this way, by providing the capacitor 4, the difference Δt in the switching time of the switch signal SW is smaller than the detected voltage V detected by the voltage detection unit 7, compared to when the capacitor 4 is not provided. Ｉｇ As a result, the temperature estimation error of the power semiconductor element Q can be reduced.

[0086] In particular, the capacitance C of the capacitor 4ｏｕｔ is the parasitic capacitance C of the power semiconductor element Q ｄｉｅ It is preferable that the ratio is at least half of the value of C ｏｕｔ ≧C ｄｉｅ / 2) As a result, the temperature estimation error of the power semiconductor element Q can be reduced to 70% or less compared to when the capacitor 4 is not provided.

[0087] Capacitance C of capacitor 4 ｏｕｔ The capacitance C of the capacitor 4 can change with the change in the gate voltage Vg (Vcc or Vee). ｏｕｔ When the voltage dependency of is large, the capacitance change amount ΔC of the capacitor 4 due to the change in the gate voltage Vg ｏｕｔ When the gate voltage Vg repeatedly switches between Vcc and Vee, the capacitance C of the capacitor 4 remains constant even if Vcc and / or Vee fluctuates. ｏｕｔ The capacitance C of the capacitor 4 is set to ｏｕｔ It is preferable that the voltage dependency of is small.

[0088] In particular, the capacitance C of the capacitor 4 ｏｕｔ Reference standard (for example, capacitance C when no gate voltage Vg is applied to the gate G of the power semiconductor element Q) ｏｕｔ ) with respect to the capacitance change ΔC of the capacitor 4 per unit voltage change (1 V) of the gate voltage Vg ｏｕｔ It is preferable that the error ratio is 0.2% or less. This makes it possible to suitably reduce errors in estimating the temperature of the power semiconductor element Q due to fluctuations in the gate voltage Vg.

[0089] As described above, in the first embodiment, the capacitor 4 is connected between the gate G and source S of the power semiconductor element Q. This reduces an estimation error in the element temperature TEMP that may occur when a time lag Δt occurs in the switching of the switch signal SW. Therefore, according to the first embodiment, the temperature of the power semiconductor element Q can be estimated with higher accuracy than when the capacitor 4 is not provided.

[0090] Second Embodiment In a second embodiment, a configuration will be described in which a resistor element is used in addition to the capacitor 4, thereby enabling further improvement in the accuracy of estimating the element temperature TEMP.

[0091] <Specific Configuration of Drive Circuit> Fig. 11 is a circuit block diagram showing a first example of the configuration of the drive circuit of the semiconductor module 201 in the second embodiment. The drive circuit 305 differs from the drive circuit 301 in the first embodiment (see Fig. 4) in that it further includes a resistive element 9 connected to the gate G of the power semiconductor element Q. The resistance value of the resistive element 9 is set to "R ｃｏｎｔ " should be written.

[0092] 12 is a circuit block diagram showing a second example of the configuration of the drive circuit of the semiconductor module 201 according to the second embodiment. The drive circuit 306 differs from the drive circuit 301 according to the first embodiment in that it further includes a resistive element 9 connected to the source S of the power semiconductor element Q.

[0093] Other configurations of drive circuits 305 and 306 are similar to the corresponding configurations of drive circuit 301. The temperature estimation process is also similar to the process described in embodiment 1 (see FIG. 8 ), so detailed description will not be repeated.

[0094] <Specific Configuration of Semiconductor Element> The location where the resistance element 9 is provided is not limited to within the drive circuit 300 of the power semiconductor element Q. The resistance element 9 may be provided within the power semiconductor element Q.

[0095] Fig. 13 is a diagram showing a first example of the circuit configuration of the power semiconductor element Q in the second embodiment. Fig. 14 is a diagram showing a second example of the circuit configuration of the power semiconductor element Q in the second embodiment. As shown in Figs. 13 and 14, the power semiconductor element Qa may include a resistive element 9 connected to the gate G, for example. As in the power semiconductor element Qb, the resistive element 9 may be connected to the source S. In these cases, the configuration of the drive circuit 300 for the power semiconductor element Q is the same as the configuration described in the first embodiment (see Figs. 2 to 7).

[0096] <Role of Resistance Element> The higher the ratio of the base voltage V0 to the total voltage of the base voltage V0 and the charging voltage Vchg (in other words, the larger the value obtained by dividing the base voltage V0 by the charging voltage Vchg), the smaller the temperature estimation error ΔV of the power semiconductor element Q.

[0097] When the resistor element 9 is not connected to the power semiconductor element Q, the base voltage V0 is (R ｇ +R ｇｉｎｔ ) I ｇ Whereas the resistance value R ｃｏｎｔ When the resistor element 9 is connected to the power semiconductor element Q, the base voltage V0 is (R ｇ +R ｇｉｎｔ +R ｃｏｎｔ ) I ｇ In this way, the resistance value R ｃｏｎｔ By adding ｃｈｇ The value obtained by dividing by is increased, thereby reducing the temperature estimation error ΔV of the power semiconductor element Q.

[0098] In particular, the resistance value R of the resistor element 9 connected to the power semiconductor element Q ｃｏｎｔ is preferably 2Ω or more (R ｃｏｎｔ ≧2Ω). This allows the temperature estimation error of the power semiconductor element Q to be reduced to about 30% compared to when the resistance element 9 is not provided.

[0099] Parasitic capacitance C of power semiconductor element Q ｄｉｅ Capacity C is more than half of ｏｕｔ and a capacitor 4 having a resistance value R of 2 Ω or more. ｃｏｎｔ By combining the resistor element 9 having the above-mentioned resistance value with the resistor element 9 having the above-mentioned resistance value, the temperature estimation error of the power semiconductor element Q can be reduced to 20% or less.

[0100] As described above, in the second embodiment, similarly to the first embodiment, the capacitor 4 is connected between the gate G and source S of the power semiconductor element Q. This reduces an estimation error in the element temperature TEMP that may occur when a time lag Δt occurs in switching the switch signal SW. Therefore, according to the second embodiment, the temperature of the power semiconductor element Q can be estimated with higher accuracy than when the capacitor 4 is not provided.

[0101] In addition, in the second embodiment, a resistance element 9 is connected to the gate G or source S of the power semiconductor element Q. As a result, the resistance associated with the gate of the power semiconductor element Q and the supply current I from the current source 51 ｇThe base voltage V0 steadily generated in response to the parasitic capacitance C of the power semiconductor element Q is ｄｉｅ Therefore, the parasitic capacitance C of the power semiconductor element Q becomes dominant over the charging voltage Vchg accompanying the charging of the ｄｉｅ Therefore, according to the second embodiment, the temperature of the power semiconductor element Q can be estimated with higher accuracy than when neither the capacitor 4 nor the resistance element 9 is provided.

[0102] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not by the description of the embodiments above, and it is intended to include all modifications within the meaning and scope of the claims.

[0103] 100 Power conversion device, 200 Main conversion circuit, 201 Semiconductor module, 300 to 306 Drive circuit, 900 Power conversion system, 1 General control unit, 2 Drive unit, 3 Resistor, 4 Capacitor, 5 Current output unit, 51 Current source, 52 Current switch, 6 Timing control unit, 7 Voltage detection unit, 8 Temperature estimation unit, 9 Resistance element, 91 Power supply, 92 Load, DI1 to DI6 Freewheeling diodes, Q, Q1 to Q6 Power semiconductor elements, D Drain, S Source, G Gate, ND Reference node.

Claims

1. A drive circuit for driving a semiconductor element, wherein the semiconductor element has a positive terminal, a negative terminal, and a control terminal for controlling a current flowing between the positive terminal and the negative terminal, the drive circuit comprising: a drive unit that transitions the semiconductor element between an on state and an off state by supplying a drive voltage to the control terminal; a capacitor connected between the control terminal and the negative terminal; a current output unit that outputs a pulse current between the control terminal and the negative terminal; a timing control unit that controls an output timing of the pulse current from the current output unit so that the pulse current is output during an on period after the semiconductor element transitions to the on state or during an off period after the semiconductor element transitions to the off state; a voltage detection unit that detects a voltage between the control terminal or the negative terminal and a reference potential; and a temperature estimation unit that estimates a temperature of the semiconductor element based on a voltage detected by the voltage detection unit during the on period or the off period.

2. A driving circuit for a semiconductor element as described in claim 1, wherein the temperature estimation unit estimates the temperature of the semiconductor element from the detected voltage by referring to conversion data that specifies the correspondence between the detected voltage and the temperature of the semiconductor element when the period from the start of output of the pulse current to voltage detection by the voltage detection unit is set to a predetermined length of time.

3. The semiconductor element drive circuit according to claim 1 or 2, wherein the capacitance of the capacitor is equal to or greater than half the parasitic capacitance of the semiconductor element.

4. A semiconductor element drive circuit according to any one of claims 1 to 3, wherein the amount of change in capacitance of the capacitor per unit voltage change in the drive voltage is 0.2% or less with respect to the reference capacitance of the capacitor.

5. A power conversion device comprising: a drive circuit according to any one of claims 1 to 4; and a main conversion circuit including the semiconductor element and performing power conversion operations.

6. The power conversion device according to claim 5, wherein the semiconductor element further includes a resistive element connected to at least one of the control terminal and the negative terminal.

7. The power conversion device according to claim 6, wherein the resistance of the resistive element is 2 ohms or more.

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