Semiconductor wafer and method for manufacturing semiconductor wafer

Abstract

This semiconductor wafer containing SiC as a main component comprises: a first main surface; a second main surface that is opposite to the first main surface; and a release-promoting layer that is formed between the first main surface and the second main surface within a range of 10 μm or less in the thickness direction perpendicular to the first main surface and the second main surface. The release-promoting layer is a region in which voids or a release-promoting substance is distributed over a range of 500 μm or more at an interval of 200 μm or less in a plane direction parallel to the first main surface and the second main surface.

Description

Semiconductor wafer and semiconductor wafer manufacturing method

[0001] The present invention relates to a semiconductor wafer and a method for manufacturing the same.

[0002] Conventionally, a technique has been known in which, after forming devices (e.g., electrodes or wiring patterns) on the surface of a semiconductor wafer, a modified layer is formed in the surface direction of the semiconductor wafer by irradiating the semiconductor wafer with laser light focused at a predetermined depth in the thickness direction at regular intervals, and the semiconductor wafer is then divided into a device-formed portion and a device-unformed portion starting from this modified layer (e.g., Patent Document 1).

[0003] Japanese Patent Application Publication No. 2023-73458

[0004] In the method of Patent Document 1, when the modified layer in the semiconductor wafer is not sufficiently formed, a strong force is required to peel off the crystalline structure when dividing the semiconductor wafer into a device-formed portion and a device-unformed portion, which may result in distortion in the device-formed portion, causing breakage or cracks.

[0005] The present invention has been made in view of the above, and a main object of the present invention is to provide a semiconductor wafer that can be easily separated.

[0006] The semiconductor wafer according to the present invention is a disk-shaped semiconductor wafer mainly composed of SiC, and includes a first crystal layer made of a single crystal material of SiC, and a second crystal layer made of the SiC crystal layer formed on the first crystal layer, the disk shape having a diameter of 145 mm or more, a peeling-promoting layer formed on at least one of the first crystal layer and the second crystal layer, the peeling-promoting layer containing voids or a peeling-promoting substance, and the second crystal layer having a diameter of 1×10 １８ atoms / cm ３A method for producing a semiconductor wafer according to the present invention is a method for producing a disk-shaped semiconductor wafer whose main component is SiC, and includes a first step of forming an inhibiting region that partially disrupts or inhibits the SiC crystal structure on or near the surface of a SiC single crystal material, and a second step of growing a SiC crystal to a thickness of 50 μm or more on the surface of the SiC single crystal material on which the first step has been carried out in an atmosphere of a mixed gas of argon and nitrogen.

[0007] According to the present invention, it is possible to provide a semiconductor wafer that can be easily separated.

[0008] FIG. 1 is a diagram showing an example of the overall configuration of a system according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram of a pretreatment for forming a layer containing microvoids. FIG. 3 is an explanatory diagram of a pretreatment for forming a layer containing a delamination-promoting substance. FIG. 4 is an explanatory diagram of a pretreatment for forming a layer containing another delamination-promoting substance. FIG. 5 is a diagram showing an example of the appearance of a cut surface when a SiC wafer is cut along a plane passing through a delamination-promoting layer. FIG. 6 is a diagram showing a schematic view of a thermal etching process in a first example of a processing step according to a second embodiment of the present invention. FIG. 7 is a diagram showing a schematic view of a surface oxidation process in a second example of a processing step according to a second embodiment of the present invention. FIG. 8 is a diagram showing a schematic view of a plasma etching process in a third example of a processing step according to a second embodiment of the present invention. FIG. 9 is a table summarizing the setting conditions, impurity concentrations, and non-defective yield rates after delamination in each example.

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to these embodiments. In addition, in order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part more schematically than in the embodiments, but these are merely examples and do not limit the interpretation of the present invention.

[0010] Hereinafter, several embodiments of the present invention will be described with reference to the drawings. In the following description, the semiconductor wafer is a SiC (silicon carbide) wafer, but the present invention can also be applied to semiconductor wafers other than SiC wafers. Examples of semiconductor wafers other than SiC wafers include GaN (gallium nitride), AlN (aluminum nitride), and diamond wafers.

[0011] First Embodiment FIG. 1 shows an example of the overall configuration of a system according to a first embodiment of the present invention.

[0012] The surface device step and wafer division step are performed in a second entity. The second entity may be a device manufacturer that extracts SiC chips from the SiC wafer 40 and provides SiC chips or devices having SiC chips. The SiC wafer 40 is roughly divided into a layer serving as a base SiC crystal and a layer serving as a grown SiC crystal (oriented SiC crystal).

[0013] In the surface device step, devices are formed on the first main surface (front surface) of the SiC wafer 40. The devices may include electrodes and wiring patterns.

[0014] In the wafer dividing step, the SiC wafer 40 having the device is divided along a surface direction (a direction perpendicular to the thickness direction, in other words, a direction parallel to the first main surface). In this wafer dividing step, the SiC wafer 40 is divided along the surface direction by, for example, a technique called laser slicing using a laser device. Specifically, for example, a laser device irradiates a peeling promoting layer 116 formed in advance inside the SiC wafer 40 with laser light (e.g., a pulsed laser) from the second main surface (rear surface) side of the SiC wafer 40. As a result, a modified layer is formed in the peeling promoting layer 116, and the SiC wafer 40 is divided, starting from this modified layer, into a main wafer 111 which is the SiC wafer portion having the first main surface and a remaining wafer 112 which is the SiC wafer portion having the second main surface.

[0015] The delamination promoter layer 116 in the SiC wafer 40, which is irradiated with laser light during laser slicing, is a layer that is more easily delaminateable due to an incomplete SiC crystal structure or other reasons than the other portions. By irradiating the delamination promoter layer 116 with laser light to form a modified layer, and then dividing the SiC wafer 40 along the delamination promoter layer 116 into the main wafer 111 and the remaining wafer 112 starting from the modified layer, the division (delamination) can be performed more easily than when other portions are modified layers. One possible reason for this is that the delamination promoter layer 116 has an incomplete crystal structure compared to the other portions, resulting in weaker interatomic bonding. Another possible reason is that the delamination promoter layer 116 easily absorbs laser light, which makes it easier to form a modified layer. Various other factors are also considered, but regardless of the reason, by peeling the portion including the first main surface from the SiC wafer 40 starting from the delamination promoter layer 116, the SiC wafer 40 can be divided into the main wafer 111 and the remaining wafer 112 with less force. This makes it possible to suppress the occurrence of distortion in the device formation portion of the main wafer 111 when peeled off, thereby preventing the occurrence of breakage or cracks.

[0016] The delamination promoting layer 116 is formed in the SiC wafer 40 when the SiC wafer 40 is manufactured by a first entity different from the second entity, as will be described later.

[0017] In the wafer dividing step, the SiC wafer 40 may be divided into the main wafer 111 and the remaining wafer 112 by a method other than the laser slicing described above. For example, the SiC wafer 40 can be divided into the main wafer 111 and the remaining wafer 112 by removing the peeling-promoting layer 116 in the SiC wafer 40 by etching. In this case, the etching can be, for example, electrolytic etching, chemical etching, thermal etching, or the like. By performing the wafer dividing step by etching in this way, the SiC wafer 40 can be divided into the main wafer 111 and the remaining wafer 112 without using a laser device. In addition, the SiC wafer 40 can be divided into the main wafer 111 and the remaining wafer 112 by processing the peeling-promoting layer 116 formed in the SiC wafer 40 by any method.

[0018] The first entity performs the acquisition step, processing step, pre-processing step, growth step, and wafer providing step (also, in this embodiment, an inspection step is performed between the acquisition step and the processing step, as will be described later). The first entity is a company that provides a new service, that is, a company that performs a service of acquiring (recovering) a remaining wafer 112 of a SiC wafer 40 from a second entity, growing a grown SiC crystal on the remaining wafer 112 to reclaim the SiC wafer 40, and providing the reclaimed SiC wafer 40 to the same or a different second entity. One or more second entities exist for the first entity. Note that the wafer division step described above may be performed in the first entity rather than the second entity.

[0019] In the obtaining step, the remaining wafer 112 is obtained from the second entity. In the processing step, the sliced ​​surface of the remaining wafer 112 is processed to obtain a seed crystal 113a made of a SiC single crystal material.

[0020] In the pretreatment step, an inhibiting region that partially disrupts or inhibits the SiC crystal structure is formed on or near the surface of seed crystal 113a obtained in the processing step or seed crystal 113b made of a newly prepared SiC single crystal material. This pretreatment for forming the aforementioned peel-promoting layer 116 is performed on seed crystals 113a and 113b, and pretreated seed crystal 114 is obtained. Details of the pretreatment step will be described later.

[0021] In the growth step, a grown SiC crystal (an example of a semiconductor crystal layer) 115 is grown on the surface of the seed crystal 114 obtained in the pretreatment step, thereby manufacturing a new SiC wafer 40. Inside the SiC wafer 40 manufactured here, a peeling-promoting layer 116 is formed by the inhibition region formed in the seed crystal 114 in the pretreatment step.

[0022] In the wafer providing step, the SiC wafer 40 obtained in the growing step is provided to a second entity that may be the same as or different from the source from which the remaining wafer 112 was obtained.

[0023] In a conventional process not employing the present invention, the portion of the SiC wafer 40 corresponding to the remaining wafer 112 is ground without being separated from the main wafer 111, and the resulting grinding waste is discarded. In contrast, in this embodiment, the remaining wafer 112 is separated from the main wafer 111 and recovered rather than discarded as grinding waste. This is then reclaimed as a new semiconductor wafer by a first entity and provided to a second entity. In the second entity, devices are formed on the semiconductor wafer provided by the first entity (the SiC wafer 40 reclaimed from the remaining wafer 112), and the semiconductor wafer is then separated into the main wafer 111 and the remaining wafer 112. The remaining wafer 112 is recovered by the first entity and used as a seed crystal 114 to form a grown SiC crystal together with the peeling-promoting layer 116, thereby being reused as the SiC wafer 40. By repeating this process, the remaining wafer 112 portion of the SiC wafer 40, which would have been ground and discarded in the past, can be reused. This process according to the present invention enables the reuse of expensive SiC wafers, thereby reducing device manufacturing costs. Furthermore, waste generated in the entire SiC wafer manufacturing process, including high-temperature processes, can be significantly reduced, thereby reducing the environmental impact.

[0024] The processing step may be performed by processing device 172, the pre-processing step may be performed by pre-processing device 173, and the growth step may be performed by growth device 174 (the inspection step described below may be performed by inspection device 171).

[0025] Among the steps in the first entity, the acquisition step, processing step, pre-processing step, growth step, and wafer provision step will be described first, followed by the inspection step.

[0026] <Acquisition Step> In the acquisition step, remaining wafers 112 are acquired from one or more second entities. An arbitrary number of remaining wafers 112 may be sent to the first entity at an arbitrary timing from the second entity, or an acquisition schedule including the number and acquisition timing of remaining wafers 112 to be acquired from each of one or more second entities may be shared between the second entity and the first entity, and the remaining wafers 112 may be acquired from the second entity according to the acquisition schedule. Note that if the wafer division step is performed by the first entity, the acquisition step is not necessary.

[0027] <Processing Step> The processing in the processing step includes grinding (typically grinding and / or polishing) the sliced ​​surfaces and removing the process-affected layer including the cut sliced ​​surfaces. The processing device 172 may include, for example, a device (e.g., a grinder) that grinds and / or polishes the sliced ​​surfaces and a device that removes the process-affected layer, or these devices may be integrated (i.e., grinding and removal may be performed by a single device). For example, the processing device 172 may be a device that performs grinding and polishing using a CMP (Chemical Mechanical Polishing) method or the like.

[0028] In the processing step, the remaining wafer 112 is processed to obtain a seed crystal 113a. The seed crystal 113a may be composed mainly of the base SiC crystal, or may be composed of the base SiC crystal and some oriented SiC crystal. Alternatively, a new SiC single crystal material may be prepared and used as the seed crystal 113b instead of the seed crystal 113a.

[0029] <Pretreatment Step> In pretreatment device 173, an inhibiting region is formed on or near seed crystals 113a and 113b, which partially disrupts or inhibits the formation of a crystalline structure when growing SiC crystals in the subsequent growth step. The presence of this inhibiting region causes a peeling-promoting layer 116, which is easier to peel than other portions, to be formed inside SiC wafer 40 manufactured from seed crystals 113a and 113b in the growth step. Specifically, pretreatment device 173 performs, as pretreatment, one of the processing steps described below with reference to FIGS. 2 to 4, thereby forming the inhibiting region on seed crystals 113a and 113b.

[0030] 2 is an explanatory diagram of a pretreatment for forming a layer containing microvoids as the peeling-promoting layer 116. In Fig. 2, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the state of processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper part shows a perspective view, and the lower part shows an enlarged cross-sectional view.

[0031] In the pretreatment step, as shown in FIG. 2( b), for example, pulsed laser light is irradiated from a laser 201, which is a pretreatment device 173, onto the surface of the seed crystal 113 a in a grid pattern at regular intervals, thereby forming laser-machined grooves 202 on the surface of the seed crystal 113 a. In the subsequent growth step, the seed crystal 113 a with the grooves 202 formed thereon is used as a pretreated seed crystal 114, and a SiC crystal is grown on the surface to a thickness of 50 μm or more, thereby forming a grown SiC crystal 115. As a result, as shown in FIG. 2( c), for example, voids due to the grooves 202 are generated at regular intervals between the seed crystal 114 and the grown SiC crystal 115. These voids partially disrupt the crystal structure, forming layers 116 that are easy to peel along the voids. In this manner, a SiC wafer 40 is manufactured, having a peel-promoting layer 116 between a first main surface 40 a on the front side (the grown SiC crystal 115 side) and a second main surface 40 b on the back side (the seed crystal 114 side).

[0032] It is preferable that grooves 202 formed in the surface of seed crystal 113a in the pretreatment step have a maximum depth of 1 μm or more, which makes it possible to form peeling promoting layer 116 in the region including grooves 202 while allowing the SiC crystal to grow sufficiently in the growth step.

[0033] 3 is an explanatory diagram of a pretreatment for forming a layer containing a substance for promoting delamination (hereinafter referred to as a "peeling-promoting substance") as the delamination-promoting layer 116. In FIG. 3, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the state of processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper part shows a perspective view, and the lower part shows an enlarged cross-sectional view.

[0034] In the pretreatment step, as shown in FIG. 3( b), for example, fine particles 211 composed primarily of carbon are dispersed and arranged on the surface of a seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the fine particles 211 dispersed and arranged on its surface is used as a pretreated seed crystal 114, and a SiC crystal is grown on its surface to a thickness of 50 μm or more, thereby forming a grown SiC crystal 115. As a result, as shown in FIG. 3( c), for example, fine particles 211 are sandwiched in places between the seed crystal 114 and the grown SiC crystal 115, and the formation of the crystal structure is inhibited by these fine particles 211, resulting in the formation of a layer 116 having an incomplete crystal structure. In this manner, a SiC wafer 40 is manufactured, having a delamination promoting layer 116 between a first main surface 40a on the front side (the grown SiC crystal 115 side) and a second main surface 40b on the back side (the seed crystal 114 side).

[0035] It is preferable that the carbon-based particles 211 dispersed on the surface of seed crystal 113a in the pretreatment step are graphite or diamond particles with a particle diameter of 10 μm or less. In this way, it becomes possible to form peeling promoting layer 116 in the region containing particles 211 while sufficiently growing the SiC crystal in the growth step.

[0036] 4 is an explanatory diagram of a pretreatment for forming a layer containing a delamination-promoting substance different from that shown in FIG. 3 as the delamination-promoting layer 116. In FIG. 4, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the state of processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper part shows a perspective view, and the lower part shows an enlarged cross-sectional view.

[0037] In the pretreatment step, ions 221 are implanted from the surface of the seed crystal 113a into its interior, as shown in FIG. 4B . Specifically, ions 221 generated, for example, by an ion source are accelerated and externally bombarded toward the surface of the seed crystal 113a, thereby implanting and dispersing the ions 221 near the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the ions 221 dispersed therein is used as the pretreated seed crystal 114, and a SiC crystal is grown on the surface to a thickness of 50 μm or more, thereby forming a grown SiC crystal 115. As a result, as shown in FIG. 4C , ions 221 are disposed in places near the boundary between the seed crystal 114 and the grown SiC crystal 115, and the formation of the crystal structure is hindered by the ions 221, resulting in the formation of a layer 116 having an incomplete crystal structure. In this manner, SiC wafers 40 are manufactured, each having delamination promoting layer 116 between first main surface 40a on the front side (side of grown SiC crystal 115) and second main surface 40b on the back side (side of seed crystal 114). If delamination promoting layer 116 in SiC wafers 40 is to be removed by etching in the subsequent wafer dividing step as described above, it is preferable to form delamination promoting layer 116 by the method described in FIG.

[0038] It is preferable to use ions of one or more of Si, C, Al, B, P, N, O, H, a rare gas element, and a rare earth element as the ions 221 implanted into seed crystal 113a in the pretreatment step. In this way, it becomes possible to form separation promoting layer 116 in the region containing ions 221 while sufficiently growing the SiC crystal in the growth step.

[0039] In the pretreatment step, the seed crystals 113a and 113b are subjected to any of the pretreatments described above by the pretreatment device 173, thereby obtaining the seed crystal 114. Note that, although an example in which the pretreatment is performed on the seed crystal 113a obtained in the processing step has been described in Figures 2 to 4, the same pretreatment can also be performed on a newly prepared seed crystal 113b to obtain the seed crystal 114.

[0040] <Growth Step> In the growth apparatus 174, a grown SiC crystal (oriented SiC crystal) 115 is grown on the seed crystal 114 to a thickness of 50 μm or more. This crystal growth may be performed by sublimation, CVD (Chemical Vapor Deposition), or another method. As a result, as described with reference to FIGS. 2 to 4 , a new SiC wafer 40 is obtained, which is composed of the seed crystal 114, which is a crystal layer made of a single-crystal SiC material, and the grown SiC crystal 115, which is a crystal layer of SiC formed on the seed crystal 114, and has a delamination promoting layer 116 between the first main surface 40a facing the grown SiC crystal 115 and the second main surface 40b facing the seed crystal 114. In this SiC wafer 40, voids due to grooves 202 or an incomplete crystal structure due to particles 211 or ions 221 are formed as the delamination promoting layer 116 in at least one of the seed crystal 114 and the grown SiC crystal 115.

[0041] As illustrated in FIG. 3( c), the delamination promoting layer 116 is preferably formed to a thickness of 10 μm or less in the thickness direction (the vertical direction in the figure) perpendicular to the first and second main surfaces 40 a and 40 b. Specifically, when a cross section of the SiC wafer 40 in the thickness direction is observed at any position including the delamination promoting layer 116, the thickness of the delamination promoting layer 116 at that cross section is preferably 10 μm or less. This allows the thickness of the delamination promoting layer 116 to be thinner than the height of the unevenness (typically about 20 to 50 μm) on the sliced ​​surface that occurs when a conventional SiC wafer without the delamination promoting layer 116 is divided by laser slicing. This reduces the amount of grinding debris generated in the processing step and the amount of SiC waste. As shown in FIGS. 2 to 4, the delamination promoting layer 116 is part of the seed crystal 114 or the grown SiC crystal 115.

[0042] 3(c), in the delamination promoting layer 116, it is preferable that voids due to the grooves 202 and delamination promoting substances consisting of particles 211 or ions 221 are distributed over a range of at least 500 μm or more at intervals of 200 μm or less in a plane direction parallel to the first main surface 40 a and the second main surface 40 b (the left-right direction in the figure), as shown in FIG. 3(c). In this way, it is possible to form the delamination promoting layer 116 that can be easily delaminate with little force when the first entity divides the SiC wafer 40 into the main wafer 111 and the remaining wafer 112 in the wafer dividing step.

[0043] 5A and 5B are diagrams showing examples of the appearance of a cut surface when the SiC wafer 40 shown in FIG. 2C is cut along a plane parallel to the first main surface 40a and passing through at least a portion of the delamination promoting layer 116. FIG. 5A shows an example of a cut surface when the delamination promoting layer 116 is formed over the entire surface in the planar direction at a predetermined depth within the SiC wafer 40. FIG. 5B shows an example of a cut surface when the delamination promoting layer 116 is formed over the entire periphery of the SiC wafer 40. FIG. 5C shows an example of a cut surface when the delamination promoting layer 116 is formed only partially in the region near the periphery of the SiC wafer 40. The delamination promoting layer 116 may be formed in other arrangements.

[0044] As shown in the above examples, the delamination promoting layer 116 may be formed over the entire surface or only in a partial region when viewed from the first main surface 40a of the SiC wafer 40. As long as the delamination promoting layer 116 is distributed over a certain range in the surface direction, for example, a range of 500 μm or more, the delamination promoting layer 116 can be formed in any region within the SiC wafer 40.

[0045] <Wafer Providing Step> A new SiC wafer 40 composed of a seed crystal 114 and a grown SiC crystal 115 is provided to a second entity that may be the same as or different from the source of the remainder wafer on which the SiC wafer is based. In this way, the acquired remainder wafer 112 is regenerated into such a new SiC wafer 40 and provided to the second entity, so that the second entity can obtain a main wafer from the SiC wafer 40.

[0046] The above is a description of the obtaining step, processing step, pre-treatment step, growth step, and wafer providing step.

[0047] In this embodiment, between the obtaining step and the processing step, there is an inspection step for inspecting the sliced ​​surface of the obtained remaining wafer 112. The inspection step is, for example, as follows.

[0048] <Inspection Step> The inspection in the inspection step includes measuring at least one of the height difference of the sliced ​​surfaces and the thickness of the process-affected layer having the sliced ​​surfaces. In this embodiment, both are measured. The height difference of the sliced ​​surfaces is the height difference caused by the uneven shape of the surface resulting from the laser irradiation or the division into the main wafer 111 and the remaining wafer 112 in the wafer division step.

[0049] The inspection step is performed by an inspection device 171. The inspection device 171 may include a laser microscope and a Raman spectrometer. The laser microscope may be used to measure the height difference of the sliced ​​surface. The Raman spectrometer may be used to measure the thickness of the processing-affected layer. The measurement methods for both the height difference of the sliced ​​surface and the thickness of the processing-affected layer are not limited to this example. For example, the height difference of the sliced ​​surface may be measured by a white light interferometer or a contact-type shape measuring machine.

[0050] At least one of the following (x) and (y) may be performed. The processing in the (x) processing step includes determining the amount of removal of the sliced ​​surface based on at least one of the measured height difference of the sliced ​​surface of the remaining wafer 112 and the measured thickness of the process-affected layer, and removing the sliced ​​surface according to the determined amount of removal. This allows appropriate (neither excessive nor insufficient) sliced ​​surface processing to be performed according to the acquired quality (state) of the remaining wafer 112. For example, if the PV value (maximum valley depth) is measured as an example of the height difference of the sliced ​​surface and the process-affected layer depth is measured as an example of the thickness of the process-affected layer, the removal amount may be calculated as PV value + (process-affected layer depth × N), where N may be any value greater than 0 (e.g., any natural number). A processing command associated with information indicating the removal amount may be input to the processing device 172 (or a control device of the processing device 172), and the processing device 172 may then process the sliced ​​surface according to the removal amount. The "cutting amount" may be defined by a parameter value for each of one or more parameter items. For example, the parameter items may include the duration of processing by the processing device 172 and the processing power (e.g., temperature, pressure, etc.). (y) In the growth step, the thickness of the grown SiC crystal to be grown is determined based on at least one of the measured height difference of the sliced ​​surface of the remaining wafer 112 and the measured thickness of the processing-affected layer, and the grown SiC crystal is grown to the determined thickness. This allows appropriate (neither excessive nor insufficient) crystal growth to be performed depending on the quality (condition) of the obtained remaining wafer 112. For example, the grown thickness may be determined based on at least one of X, Y, Z, and α. Specifically, the grown thickness may be X-Y+Z+α. X may be the thickness required at the start of the surface device step or the wafer division step in the second entity (the thickness required by the second entity). Y may be the thickness of the grown SiC crystal at the time of receipt by the first entity. Z may be the amount of removal determined in (x) above, and α may be any value (for example, about 50 μm) determined as a processing allowance (processing margin) for removing irregularities after growth and flattening the surface.A crystal growth command associated with information representing the thickness to be grown may be input to the growth apparatus 174 (or a control device for the growth apparatus 174), causing the growth apparatus 174 to grow a SiC crystal of that thickness on the seed crystal.

[0051] Next, an example for verifying the effect of the peeling-promoting layer 116 on the SiC wafer 40 formed by growing the grown SiC crystal 115 on the seed crystal 114 will be specifically described.

[0052] In the pretreatment step, a disk-shaped SiC substrate (diameter 150 mm) was obtained and used as the seed crystal 113a. As described with reference to FIG. 4B, hydrogen ions were implanted as ions 221 for forming the peeling-promoting layer 116. The hydrogen ion implantation conditions were an acceleration voltage of 170 keV and a dose of 8×10. １５ ions / cm ２ The temperature was 500°C.

[0053] In the subsequent growth step, the SiC substrate into which hydrogen ions had been implanted in the pretreatment step was placed in a container filled with raw material powder. In Example 1, a first raw material composed of SiC mixed with a second raw material containing the rare earth element yttrium (Y) was used as the raw material powder. In Example 1, the mixing ratio of the first raw material and the second raw material in the raw material powder was adjusted so that the weight ratio of yttrium to the weight of the first raw material, SiC, was 6.4%. The container was then placed in a resistance furnace (sintering furnace) in a location where the temperature range was within ±50°C of the set temperature, and heat-treated in an argon and nitrogen mixed gas atmosphere at a set temperature of 2450°C for 20 hours. A SiC single crystal was grown on the SiC substrate as a seed crystal 114 to a thickness of approximately 200 μm, forming a grown SiC crystal 115. The nitrogen gas flow rate was adjusted so that the calculated nitrogen gas partial pressure in the furnace was 0.0025 atm. As a result, as described in FIG. 4 , a SiC wafer 40 was obtained, which had a seed crystal 114 and a grown SiC crystal 115, and in which an incomplete crystal structure due to the hydrogen ions implanted into the seed crystal 114 was formed as a peeling-promoting layer 116 between the first main surface 40 a and the second main surface 40 b.

[0054] Furthermore, the SiC wafer 40 obtained above was subjected to mechanical polishing so that both surfaces thereof were flat. The polishing amounts of the surface on the side of grown SiC crystal 115 (first main surface 40a) and the opposite surface (second main surface 40b) were adjusted so that the amount of polishing removed on the side of grown SiC crystal 115 was 50 μm and the thickness of SiC wafer 40 after polishing was 350 μm.

[0055] A surface device step was performed on the polished SiC wafer 40 thus obtained, thereby forming a SiC-MOSFET device. Thereafter, a pulsed laser having a wavelength of 1064 nm was irradiated onto the peeling promoting layer 116 from the back surface (second main surface 40b) side of the SiC wafer 40, and the laser light was scanned in the surface direction to perform a wafer dividing step, thereby peeling off the SiC wafer 40 at the peeling promoting layer 116. The irradiation conditions of the laser light at this time were an irradiation fluence of 100 J / cm ２ The pulse width was set to 10 ns, and the laser focusing position was set to a position 200 μm from the back surface (second main surface 40 b) of the SiC wafer 40. In this way, the SiC wafer 40 on which the SiC-MOSFET devices were formed was divided into a main wafer 111 and a remaining wafer 112.

[0056] In Example 2, a SiC substrate (diameter 200 mm) having a larger disk diameter than that of Example 1 was used as seed crystal 113a. Then, each step was carried out under the same conditions as in Example 1, and SiC wafer 40 on which SiC-MOSFET devices were formed was divided into main wafer 111 and remaining wafer 112.

[0057] Example 3 In Example 3, a SiC substrate (diameter 150 mm) having the same shape as in Example 1 was used as seed crystal 113a, and the pretreatment step was carried out under the same conditions as in Examples 1 and 2. Then, the mixing ratio of the first raw material and the second raw material in the raw material powder was adjusted so that the weight ratio of yttrium to the weight of SiC was 0.3%, and the growth step was carried out under the same conditions as in Examples 1 and 2, thereby obtaining SiC wafer 40 having seed crystal 114 and grown SiC crystal 115, and in which an incomplete crystal structure due to hydrogen ions implanted into seed crystal 114 was formed as peeling-promoting layer 116 between first main surface 40a and second main surface 40b. This SiC wafer 40 was subjected to a surface device step and a wafer division step under the same conditions as in Example 1, and SiC wafer 40 on which SiC-MOSFET devices were formed was divided into main wafer 111 and remaining wafer 112.

[0058] Example 4 In Example 4, a SiC substrate (diameter 150 mm) having the same shape as in Examples 1 and 3 was used as seed crystal 113a, and the pretreatment step was carried out under the same conditions as in Examples 1 to 3. Then, a growth step was carried out using only a first raw material made of SiC as the raw material powder, with the other conditions being set the same as in Examples 1 to 3, thereby obtaining a SiC wafer 40 having seed crystal 114 and grown SiC crystal 115, in which an incomplete crystal structure due to hydrogen ions implanted into seed crystal 114 was formed as peeling-promoting layer 116 between first main surface 40a and second main surface 40b. A surface device step and a wafer division step were carried out on this SiC wafer 40 under the same conditions as in Examples 1 to 3, and SiC wafer 40 on which SiC-MOSFET devices were formed was divided into main wafer 111 and remaining wafer 112.

[0059] Example 5 In Example 5, a SiC substrate (diameter 150 mm) having the same shape as in Examples 1, 3, and 4 was used as seed crystal 113a, and the pretreatment step was carried out under the same conditions as in Examples 1 to 4. Then, as in Example 4, only a first raw material made of SiC was used as the raw material powder, and the nitrogen gas flow rate was adjusted so that the nitrogen gas partial pressure in the furnace was calculated to be 0.0000003 atm. The growth step was carried out under the same conditions as in Examples 1 to 4, thereby obtaining a SiC wafer 40 having a seed crystal 114 and a grown SiC crystal 115, in which an incomplete crystal structure due to hydrogen ions implanted into seed crystal 114 was formed as peeling-promoting layer 116 between first main surface 40a and second main surface 40b. A surface device step and a wafer division step were carried out on this SiC wafer 40 under the same conditions as in Examples 1 to 4, and SiC wafer 40 on which SiC-MOSFET devices were formed was divided into a main wafer 111 and a remaining wafer 112.

[0060] Example 6 In Example 6, a SiC substrate (diameter 150 mm) having the same shape as in Examples 1 and 3 to 5 was used as seed crystal 113a, and the pretreatment step was carried out under the same conditions as in Examples 1 to 5. Then, as in Examples 4 and 5, only a first raw material made of SiC was used as raw material powder, and the growth step was carried out in an argon gas atmosphere without introducing nitrogen gas, with the other conditions being the same as in Examples 1 to 5. This resulted in a SiC wafer 40 having seed crystal 114 and grown SiC crystal 115, and in which an incomplete crystal structure due to hydrogen ions implanted into seed crystal 114 was formed as peeling-promoting layer 116 between first main surface 40a and second main surface 40b. A surface device step and a wafer division step were carried out on this SiC wafer 40 under the same conditions as in Examples 1 to 5, and SiC wafer 40 on which SiC-MOSFET devices were formed was divided into main wafer 111 and remaining wafer 112.

[0061] Example 7 In Example 7, a SiC substrate (diameter 100 mm) having a smaller disc diameter than those in the other examples was used as the seed crystal 113a, and the pretreatment step was carried out under the same conditions as in Examples 1 to 6. Then, as in Examples 4 to 6, only a first raw material made of SiC was used as the raw material powder, and as in Example 6, a growth step was carried out in an argon gas atmosphere without introducing nitrogen gas, with the other conditions being the same as in Examples 1 to 6. This resulted in a SiC wafer 40 having a seed crystal 114 and a grown SiC crystal 115, and in which an incomplete crystal structure due to hydrogen ions implanted into the seed crystal 114 was formed as a peeling-promoting layer 116 between the first main surface 40a and the second main surface 40b. A surface device step and a wafer division step were carried out on this SiC wafer 40 under the same conditions as in Examples 1 to 6, and the SiC wafer 40 on which the SiC-MOSFET devices were formed was divided into a main wafer 111 and a remaining wafer 112.

[0062] Example 8 In Example 8, a SiC substrate (diameter 150 mm) having the same shape as in Examples 1 and 3 to 6 was used as the seed crystal 113a, and the pretreatment step was carried out under the same conditions as in Examples 1 to 7. In the subsequent growth step, a raw material powder was prepared by mixing a first raw material made of SiC with a second raw material containing cerium (Ce), a rare earth element different from that used in Examples 1 to 3. The mixing ratio of the first raw material to the second raw material in the raw material powder was adjusted so that the weight ratio of cerium relative to the weight of the first raw material, SiC, was 10.2%. The growth step was carried out under the same other conditions as in Examples 1 to 7, thereby obtaining a SiC wafer 40 having a seed crystal 114 and a grown SiC crystal 115, and in which an incomplete crystal structure due to hydrogen ions implanted into the seed crystal 114 was formed as a peeling-promoting layer 116 between the first main surface 40a and the second main surface 40b. This SiC wafer 40 was subjected to the surface device step and wafer division step under the same conditions as in Examples 1 to 7, and the SiC wafer 40 on which the SiC-MOSFET device was formed was divided into a main wafer 111 and a remaining wafer 112.

[0063] In Example 9, a SiC substrate (diameter 150 mm) having the same shape as in Examples 1, 3 to 6, and 8 was used as seed crystal 113a, and the pretreatment step was carried out under the same conditions as in Examples 1 to 8. In the subsequent growth step, similarly to Examples 1 and 2, a raw material powder was used in which a first raw material made of SiC was mixed with a second raw material containing yttrium so that the weight ratio of yttrium to the weight of SiC was 6.4%. Then, a growth step was carried out in an argon gas atmosphere without introducing nitrogen gas until 12 hours had elapsed since the set temperature in the furnace was maintained at 2450°C, and then in an argon and nitrogen mixed gas atmosphere in which the nitrogen gas flow rate was adjusted so that the nitrogen gas partial pressure in the furnace was calculated to be 0.0025 atm, with the other conditions being set the same as in Examples 1 to 8, thereby obtaining a SiC wafer 40 having a seed crystal 114 and a grown SiC crystal 115, in which an incomplete crystal structure due to hydrogen ions implanted into the seed crystal 114 was formed as a peeling-promoting layer 116 between the first main surface 40a and the second main surface 40b. A surface device step and a wafer division step were carried out on this SiC wafer 40 under the same conditions as in Examples 1 to 8, and the SiC wafer 40 on which the SiC-MOSFET devices were formed was divided into a main wafer 111 and a remaining wafer 112.

[0064] In Example 10, a SiC substrate (diameter 150 mm) having the same shape as in Examples 1, 3 to 6, 8, and 9 was used as seed crystal 113a, and the pretreatment step was carried out under the same conditions as in Examples 1 to 9. In the subsequent growth step, similarly to Examples 1, 2, and 9, a raw material powder was used in which a first raw material made of SiC was mixed with a second raw material containing yttrium so that the weight ratio of yttrium to the weight of SiC was 6.4%. The growth step was carried out in an argon gas atmosphere without introducing nitrogen gas until 9 hours had elapsed since the set temperature in the furnace was maintained at 2450°C, and then in an argon and nitrogen mixed gas atmosphere in which the nitrogen gas flow rate was adjusted so that the nitrogen gas partial pressure in the furnace was calculated to be 0.0025 atm, with the other conditions being the same as in Examples 1 to 9. This resulted in a SiC wafer 40 having a seed crystal 114 and a grown SiC crystal 115, and in which an incomplete crystal structure due to hydrogen ions implanted into the seed crystal 114 was formed as a peeling-promoting layer 116 between the first main surface 40a and the second main surface 40b. The surface device step and wafer division step were carried out on this SiC wafer 40 under the same conditions as in Examples 1 to 9, and the SiC wafer 40 on which the SiC-MOSFET devices were formed was divided into a main wafer 111 and a remaining wafer 112.

[0065] (Confirmation of peeling performance) For each of Examples 1 to 10 described above, 100 samples of SiC wafer 40 were prepared for each Example, and a halogen lamp was irradiated onto the peeled surface of each of main wafer 111 and remaining wafer 112 obtained after the wafer dividing step, and the state of these peeled surfaces was visually inspected. As a result, if any of the peeled surfaces had breaks or cracks of 1 mm or more, it was deemed to be defective, and the yield rate after peeling was evaluated for each Example to confirm the peeling performance of each Example.

[0066] (Confirmation of Impurity Concentration) For each of Examples 1 to 10 described above, the SiC-MOSFET device layer formed in the surface device step was removed from the surface (first main surface 40a) of the SiC wafer 40 facing the grown SiC crystal 115 before the wafer division step, and the SiC wafer 40 was then polished a predetermined thickness to expose the grown SiC crystal 115 at a depth corresponding to that thickness. The impurity (nitrogen, rare earth element) concentrations on this exposed surface were then measured. This measurement was performed at depths of 5 μm, 10 μm, 25 μm, and 55 μm from the first main surface 40a after device layer removal, thereby confirming the concentrations of nitrogen and rare earth elements in the grown SiC crystal 115 at these depths from the first main surface 40a in the thickness direction perpendicular to the first main surface 40a. Dynamic secondary ion mass spectrometry (D-SIMS) was used to measure the impurity concentrations.

[0067] (Analysis of Each Example) FIG. 9 is a table summarizing the set conditions (wafer diameter, type of rare earth element and its weight ratio to SiC in the growth step, and nitrogen gas partial pressure in the furnace) for each of Examples 1 to 10, the impurity (nitrogen, rare earth element) concentrations at various depths (5 μm, 10 μm, 25 μm, and 55 μm) from first main surface 40 a in grown SiC crystal 115, and the yield rate after peeling.

[0068] From the relationship between the set conditions and the yield rate for each example shown in the table of FIG. 9 , it can be seen that in the growth step in which the grown SiC crystal 115 is grown on the seed crystal 114 to restore the thickness of the SiC wafer 40, the delamination performance of the delamination-promoting layer 116 can be improved and the occurrence of breakage or cracking during the wafer division step can be suppressed by appropriately controlling the nitrogen ratio contained in the mixed gas to a specific nitrogen concentration or by incorporating a trace amount of a rare earth element into the grown SiC crystal 115. It can also be seen that the effect obtained by these measures increases as the size (diameter of the disc shape) of the SiC wafer 40 increases. Specifically, when the diameter of the disc shape of the SiC wafer 40 is 145 mm or more, the concentration of nitrogen atoms in the grown SiC crystal 115 at a depth of 25 to 55 μm from the first main surface 40 a in the thickness direction perpendicular to the first main surface 40 a becomes 1×10 １８atoms / cm ３ or more (Examples 1 to 5, 8), and / or the grown SiC crystal 115 is 5×10 １３ atoms / cm ３ When the rare earth element is contained at a concentration equal to or greater than this (Examples 1 to 4, 8 to 10), the delamination performance of delamination promoting layer 116 is sufficiently improved, and it is possible to achieve a high yield rate after delamination. More specifically, in Examples 1 to 5 and 8, when grown SiC crystal 115 has a thickness of 55 μm or greater, the concentration of nitrogen atoms in grown SiC crystal 115 at a depth of 55 μm from first main surface 40 a in the thickness direction perpendicular to first main surface 40 a is 1×10 １８ atoms / cm ３ That is, in the reuse of SiC wafers to which the present invention is applied, by carrying out the above-described treatment in the growth step, it is possible to improve the yield when the wafers are reused.

[0069] The reason why the above-described treatment can improve the peeling performance of the peeling-promoting layer 116 is thought to be, for example, that by setting the concentration of impurities (nitrogen and rare earth elements) in the grown SiC crystal 115 within an appropriate range, stress and warpage that occur when laser light is irradiated in the wafer division step are reduced. It is also speculated that the presence of rare earth elements as impurities in the grown SiC crystal 115 increases the concentration of atomic vacancies in the SiC lattice in the region in the peeling-promoting layer 116 where the laser light is focused, thereby making it easier to break Si—C bonds in that region. In any event, the relationship between the set conditions in each of Examples 1 to 10, the impurity concentration at each depth from the first main surface 40 a in the grown SiC crystal 115, and the yield rate after peeling indicates that the above-described treatment can improve the peeling performance of the peeling-promoting layer 116.

[0070] Although Examples 1 to 10 have described examples in which the wafer dividing step is performed by laser slicing using a pulsed laser, it is believed that the peeling performance of the peeling promoter layer 116 can be improved by similar measures even when the wafer dividing step is performed by other methods. Furthermore, Examples 1 to 10 have described examples in which the peeling promoter layer 116 is formed in the SiC wafer 40 by implanting hydrogen ions into the seed crystal 114. However, it is believed that the peeling performance of the peeling promoter layer 116 can be improved by similar measures even when the peeling promoter layer 116 is formed by implanting other ions or by other methods (e.g., voids due to the grooves 202 described in FIG. 2 or an incomplete crystal structure due to the particles 211 described in FIG. 3 ). In addition, if a circular semiconductor wafer primarily made of SiC has a peeling promoter layer 116 formed therein, the peeling performance of the peeling promoter layer 116 can be improved by performing the above-described measures in the growth step.

[0071] Second Embodiment A second embodiment will be described, focusing mainly on the differences from the first embodiment, and explanations of the commonalities with the first embodiment will be omitted or simplified.

[0072] In the second embodiment, crystal growth in the growth step is performed using a method disclosed in a prior application WO 2023 / 067736 filed by the same applicant as the present application (hereinafter, for convenience, this method will be referred to as the "NGK method" based on the applicant's notation). That is, in the growth step, a SiC single crystal serving as a seed crystal and a SiC powder layer are placed in a container while in contact with each other, and the container is placed in a firing furnace and heat-treated, thereby growing a SiC single crystal on the seed crystal. The NGK method can produce a SiC single crystal (grown SiC crystal) with a lower BPD density than that obtained by sublimation deposition and a similar BPD density to that obtained by CVD. The second embodiment can incorporate all or part of the technology disclosed in WO 2023 / 067736.

[0073] When crystal growth is performed by the NGK method, the surface after processing may have a lower flatness than when crystal growth is performed by sublimation or CVD, and the surface after processing does not need to be completely flat.

[0074] When homoepitaxial growth is performed on a seed crystal by sublimation or CVD, it is usually essential that the growth surface be atomically flat and that there be no process-affected layer, because this can cause unevenness on the epitaxial growth surface and defects such as dislocations to appear in the crystal.

[0075] On the other hand, SiC wafers are hard and stable against heat and chemicals, so planarizing the surface or removing processing damage by CMP after slicing or grinding takes a very long time and also results in significant consumption of polishing slurry, polishing pads, etc.

[0076] Therefore, in this embodiment, the removal of the damaged layer in the processing step is performed by a thermal etching process, a surface oxidation process, or a plasma etching process (i.e., any process that results in lower flatness after etching than etching by CMP). Examples of each process related to the removal of the damaged layer in the processing step according to the second embodiment will be described below. Note that in this embodiment, etching other than the thermal etching process, surface oxidation process, and plasma etching process, such as etching by CMP, or other etching processes (e.g., hydrogen etching) may also be performed.

[0077] FIG. 6 shows a schematic diagram of the thermal etching process.

[0078] The processing device 172 may include a device that removes the damaged layer by a thermal etching process. Such a device is illustrated in Fig. 6. In the thermal etching process, the surface of the remaining wafer (including the damaged layer) that has been heated and processed in the electric furnace 302 is sublimated to a thickness of about several micrometers.

[0079] For example, a gas (e.g., an inert gas such as nitrogen or argon) is introduced through a gas pipe 305 into an electric furnace 302 made of a heat insulating material and provided with a heater 301, creating an inert gas atmosphere inside the electric furnace 302. The inside of the electric furnace 302 may also be a vacuum atmosphere.

[0080] Heating is performed by heater 301, and the maximum heat treatment temperature is within a certain temperature range (for example, 1000 to 2000°C), and may be set taking into account the required etching amount (for example, 1800°C). The maximum temperature is maintained for a certain time range (for example, 1 minute to 5 hours), and may be set taking into account the required etching amount (for example, 1 hour). The "required etching amount," "maximum heat treatment temperature," and "maximum temperature maintenance time" may each be an example of at least one element of the removal amount, and may be determined based on the measured thickness of the work-affected layer.

[0081] The remaining wafer 112 (e.g., the remaining wafer 112 whose surface has been ground) may be placed on a setter 303 (e.g., graphite) on a spacer 304 (e.g., graphite), or may be placed using a sheath or the like made of a heat-resistant material.

[0082] If the surface of the remaining wafer 112 is carbonized after this thermal etching process, the carbonized layer on the surface may be removed by separate annealing in an atmospheric furnace or the like, or by processing such as polishing. To prevent carbonization of the surface, a carbon getter material such as Ta may be placed in the electric furnace 302.

[0083] FIG. 7 shows a schematic diagram of the surface oxidation process.

[0084] The processing device 172 may include a device that removes a process-affected layer by a surface oxidation process. An example of such a device is shown in FIG. 7 . In the surface oxidation process, the surface (including the process-affected layer) of the remaining wafer that has been heated and processed in an oxidizing atmosphere (including the air atmosphere) in the electric furnace 402 is oxidized to a thickness of about several μm. The oxide film may be removed by processing such as polishing, or may be volatilized or melted (by reaction with the raw material powder) during crystal growth.

[0085] For example, in an electric furnace 402 made of insulating material and equipped with a heater 401, the maximum heat treatment temperature may be set within a certain temperature range (e.g., 800 to 2000°C) taking into account the required amount of etching (e.g., 1400°C). The maximum temperature holding time may be set within a certain time range (e.g., 5 minutes to 50 hours) taking into account the required amount of etching (e.g., 1 hour). The "required amount of etching," "maximum heat treatment temperature," and "maximum temperature holding time" may each be an example of at least one element of the amount of removal, and may be determined based on the measured thickness of the work-affected layer.

[0086] The remaining wafer 112 (for example, the remaining wafer 112 with its surface ground) may be placed on a setter 403 (for example, alumina) on a spacer 404 (for example, alumina).

[0087] FIG. 8 shows a schematic diagram of the plasma etching process.

[0088] The processing device 172 may include a device that removes the damaged layer by a plasma etching process. An example of such a device is shown in Fig. 8. In the plasma etching process, the surface of the processed remaining wafer (including the damaged layer) is etched to a depth of several micrometers.

[0089] Plasma etching includes reactive ion etching (RIE), electron cyclotron resonance (ECR), inductively coupled plasma (ICP), capacitively coupled plasma (CCP), etc., but is not particularly limited, and for example, RIE can be applied.

[0090] The substrate temperature, gas type, processing time, and apparatus configuration may be appropriately set depending on the desired etching rate and surface condition. The remaining wafer surface may be previously cleaned of surface deposits by ashing or the like.

[0091] An upper electrode 501 and a lower electrode 503 are disposed in a chamber 502, gas is introduced through a gas inlet pipe 505 and exhausted through a gas exhaust pipe 504, and plasma is generated between the electrodes 501 and 503 by a high frequency power supply 509s.

[0092] The above is a description of examples of each process related to removal of the damaged layer in the processing step according to the second embodiment. Note that there are also differences regarding crystal growth between the sublimation method, the CVD method, and the NGK method, for example, as follows.

[0093] That is, while the sublimation method and the CVD method require precision cleaning after CMP polishing and before forming the epitaxial layer, the NGK method does not require such cleaning.

[0094] Furthermore, in the sublimation and CVD methods, the temperature rise rate is fast, so warping of the seed crystal increases the possibility of seed crystal breakage. Furthermore, in the sublimation and CVD methods, multiple seed crystals can be placed in the chamber of the growth device, but even if one seed crystal breaks, it will affect the other seed crystals. On the other hand, in the NGK method, the temperature rise rate is slower than in the sublimation and CVD methods, so even if the seed crystal is slightly warped, the possibility of breakage due to the warping is low. Furthermore, in the NGK method, one seed crystal is stored in one container, so even if one seed crystal breaks, it will not affect the other seed crystals.

[0095] In both the second and first embodiments, the diameter of the remaining wafer 112 obtained by the obtaining step may be 6 inches or more, for example, the diameter of the remaining wafer may be 8 inches or more (e.g., the second embodiment). For example, whether the diameter is 6 inches or 8 inches, the thickness of the main wafer 111 may be approximately 100 μm, but when the diameter is 6 inches, the thickness of the remaining wafer 112 may be approximately 250 μm, and when the diameter is 8 inches, the thickness of the remaining wafer 112 may be approximately 400 μm.

[0096] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0097] (1) The SiC wafer 40 is a disk-shaped semiconductor wafer primarily composed of SiC. It has a seed crystal 114 (first crystal layer) made of a single-crystal SiC material and a grown SiC crystal 115 (second crystal layer) made of a SiC crystal layer formed on the seed crystal 114, and the diameter of the disk is 145 mm or more. A delamination-promoting layer 116 is formed on at least one of the seed crystal 114 and the grown SiC crystal 115. The delamination-promoting layer 116 contains voids due to the grooves 202 or delamination-promoting substances such as particles 211 and ions 221. The grown SiC crystal 115 has a density of 1×10 １８ atoms / cm ３ The portion containing nitrogen atoms has a concentration of 116 or more. In this way, it is possible to provide a SiC wafer 40 that can be easily separated at the separation promoting layer 116.

[0098] (2) The grown SiC crystal 115 has a nitrogen atom concentration of 1×10 at a depth of 25 μm from the first main surface 40 a in the thickness direction perpendicular to the first main surface 40 a. １８ atoms / cm ３ More specifically, grown SiC crystal 115 has a thickness of at least 55 μm or more, and the concentration of nitrogen atoms at a depth of 55 μm from first main surface 40 a in the thickness direction perpendicular to first main surface 40 a is preferably 1×10 １８ atoms / cm ３ The grown SiC crystal 115 is preferably 5×10 １３ atoms / cm ３ It is preferable to have a portion containing a rare earth element at a concentration equal to or higher than this (Examples 1 to 4 and 8 to 10). In this way, the peeling performance of the peeling promoting layer 116 can be improved, and the occurrence of breakage or cracks during the wafer dividing step can be suppressed.

[0099] (3) The SiC wafer 40 has a first main surface 40a and a second main surface 40b opposite the first main surface 40a. The delamination promoting layer 116 is formed between the first main surface 40a and the second main surface 40b, within a range of 10 μm or less in the thickness direction perpendicular to the first main surface 40a and the second main surface 40b. The delamination promoting layer 116 is a region in which delamination promoting substances, such as voids due to the grooves 202, particles 211, or ions 221, are distributed over a range of 500 μm or more at intervals of 200 μm or less in the planar direction parallel to the first main surface 40a and the second main surface 40b. This configuration makes it possible to provide a SiC wafer 40 that can be easily separated at the delamination promoting layer 116.

[0100] (4) A method for manufacturing SiC wafer 40, which is a disk-shaped semiconductor wafer primarily made of SiC, includes a step (pretreatment step) of forming an inhibiting region that inhibits SiC crystal structure on or near the surface of seed crystals 113 a, 113 b made of SiC single crystal material, and a step (growth step) of growing SiC crystal to a thickness of 50 μm or more on the surface of pretreated seed crystal 114, which is a SiC single crystal material that has been subjected to the pretreatment step, in an argon and nitrogen mixed gas atmosphere. This allows for the manufacture of SiC wafer 40, which has internal delamination promoting layer 116 and can be easily separated at this delamination promoting layer 116.

[0101] In the embodiment described above, an example has been described in which the first entity recovers the remaining wafers 112 produced in the second entity and uses these remaining wafers 112 to reclaim the SiC wafers 40, but the present invention can also be applied to other configurations. That is, even in a case in which the first entity does not recover the remaining wafers 112 but instead manufactures the SiC wafers 40 using only the seed crystals 113b made of a newly prepared SiC single crystal material, the present invention can be applied using a method similar to that of the above embodiment.

[0102] Although one embodiment has been described above, this is merely an example for explaining the present invention, and the scope of the present invention is not limited to this embodiment. The present invention can be implemented in various other forms. For example, any two or more of the above-described embodiments may be combined.

[0103] 40...SiC wafer, 111...main wafer, 112...remaining wafer, 113a, 113b...seed crystal, 114...pretreated seed crystal, 115...grown SiC crystal, 116...peeling promoting layer, 171...inspection device, 172...processing device, 173...pretreatment device, 174...growth device

Claims

1. A disk-shaped semiconductor wafer mainly composed of SiC, comprising: a first crystal layer made of a single crystal material of SiC; and a second crystal layer made of the SiC crystal layer formed on the first crystal layer, the disk shape having a diameter of 145 mm or more; a peeling-promoting layer is formed on at least one of the first crystal layer and the second crystal layer; the peeling-promoting layer contains voids or a peeling-promoting substance; and the second crystal layer has a diameter of 1×10 １８ atoms / cm ３ A semiconductor wafer having a portion containing nitrogen atoms at a concentration of at least one of the nitrogen atoms.

2. The semiconductor wafer according to claim 1, wherein the second crystal layer has a nitrogen atom concentration of 1×10 at a depth of 25 μm from the main surface in a thickness direction perpendicular to the main surface. １８ atoms / cm ３ That's it, a semiconductor wafer.

3. A semiconductor wafer according to claim 1, wherein the second crystal layer has a thickness of at least 55 μm or more, and the concentration of the nitrogen atoms at a depth of 55 μm from the main surface in a thickness direction perpendicular to the main surface is greater than or equal to 1×10 １８ atoms / cm ３ That's it, a semiconductor wafer.

4. The semiconductor wafer according to claim 1, wherein the second crystal layer is 5×10 １３ atoms / cm ３ A semiconductor wafer having a portion containing a rare earth element at a concentration of at least one of the above.

5. A semiconductor wafer as described in claim 1, comprising: a first main surface; and a second main surface opposite to the first main surface; the peeling-promoting layer is formed between the first and second main surfaces within a range of 10 μm or less in a thickness direction perpendicular to the first and second main surfaces; and the peeling-promoting layer is a region in which the voids or the peeling-promoting substance are distributed over a range of 500 μm or more at intervals of 200 μm or less in a plane direction parallel to the first and second main surfaces.

6. A semiconductor wafer according to claim 1, wherein the peeling promoting substance is fine particles mainly composed of carbon.

7. A semiconductor wafer according to claim 1, wherein the peeling promoting substance is ions of one or more of the following elements: Si, C, Al, B, P, N, O, H, a rare gas element, and a rare earth element.

8. A method for manufacturing a disk-shaped semiconductor wafer whose main component is SiC, comprising: a first step of forming an inhibition region that partially divides or inhibits the SiC crystal structure on or near the surface of a SiC single crystal material; and a second step of growing a SiC crystal to a thickness of 50 μm or more on the surface of the SiC single crystal material on which the first step has been carried out in an atmosphere of a mixed gas of argon and nitrogen.

9. A method for manufacturing a semiconductor wafer as defined in claim 8, wherein in the first step, a plurality of grooves each having a maximum depth of 1 μm or more are formed as the inhibition region in the surface of the SiC single crystal material.

10. A semiconductor wafer manufacturing method as defined in claim 8, wherein in the first step, a region in which fine particles of graphite or diamond having a particle diameter of 10 μm or less are dispersed is formed as the inhibition region on the surface of the SiC single crystal material.

11. A semiconductor wafer manufacturing method as defined in claim 8, wherein in the first step, the inhibition region is formed by implanting ions of one or more of Si, C, Al, B, P, N, O, H, rare gas elements and rare earth elements from the surface of the SiC single crystal material to the inside.

12. A semiconductor wafer manufacturing method as defined in claim 8, comprising a third step of dividing the SiC single crystal material on which the grown SiC crystal has been formed in the second step into a main wafer including the surface of the grown SiC crystal and a remaining wafer excluding the main wafer.

13. A semiconductor wafer manufacturing method as described in claim 12, wherein a peeling-promoting layer is formed inside the SiC single crystal material in which the grown SiC crystal is formed, and in the third step, a modified layer is formed by irradiating the peeling-promoting layer with laser light, and the SiC single crystal material is divided into the main wafer and the remaining wafer using the modified layer as a starting point.

14. A semiconductor wafer manufacturing method as defined in claim 12, wherein a peeling-promoting layer is formed inside the SiC single crystal material in which the grown SiC crystal is formed, and in the third step, the peeling-promoting layer is removed by etching to divide the SiC single crystal material into the main wafer and the remaining wafer.

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