Information processing device and display device

Abstract

This information processing device is capable of generating sub-images to be sequentially displayed, and comprises: a first processing unit that is capable of, on the basis of a frame image, generating two or more sub-images among a plurality of sub-images respectively having a plurality of pixel values and arranged in a predetermined arrangement pattern in the frame image; a detection unit that detects a detection pixel to be processed on the basis of the display order of corresponding pixels of the two or more sub-images and the pixel value difference between the pixels in the display order, on the basis of the coordinates of the frame image; and a second processing unit that executes processing for reducing the pixel value difference between corresponding pixels in the detection pixel.

Description

Information processing device and display device

[0001] The present disclosure relates to an information processing device and a display device.

[0002] Display devices are known that display images by projecting image light generated using a liquid crystal light valve onto a screen. Some such display devices use a shift device that can shift the image light in an in-plane direction of the image to improve the display resolution so that the display resolution is higher than the resolution of the liquid crystal light valve (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-086071

[0004] In display devices using such shift devices, pixels are thinned out and displayed in a time-division manner in response to input at the desired resolution. As a result, depending on the input pattern, images with large differences in brightness may be displayed alternately, which may be perceived as flicker.

[0005] Therefore, the present disclosure provides an information processing device and a display device that can suppress flicker.

[0006] In order to solve the above problem, according to the present disclosure, there is provided an information processing device capable of generating sub-images to be displayed in sequence, comprising: a first processing unit capable of generating, based on a frame image, two or more sub-images out of a plurality of sub-images each having a plurality of pixel values ​​arranged in a predetermined arrangement pattern in the frame image; a detection unit that detects a detection pixel to be processed based on the coordinates of the frame image, based on the display order of corresponding pixels in the two or more sub-images and the pixel value difference between pixels in the display order; and a second processing unit that performs processing to reduce the pixel value difference between corresponding pixels in the detection pixel.

[0007] The detection unit may detect a processing pixel from detection pixels in a detection area based on a detection area having a predetermined number or more of adjacent detection pixels, and the second processing unit may reduce a pixel value difference between corresponding pixels in the processing pixels.

[0008] The detection section may detect a pixel to be processed based on a detection region having a predetermined number or more of adjacent detection pixels within a predetermined range of the frame image.

[0009] The detection section may thin out the detection pixels from within the detection region and detect them as the processing pixels.

[0010] The detection unit may detect each of the corresponding pixels in the detection pixel as a detection pixel if one of the corresponding pixels has a pixel value greater than or equal to a first upper limit value and the next pixel to be displayed has a pixel value less than or equal to a second lower limit value.

[0011] The second processing unit may reduce a pixel value difference between corresponding pixels of the detection pixel within a predetermined region in the sub-image.

[0012] The predetermined area may be changed depending on the input frame image.

[0013] The first processing unit may further generate two or more second sub-images from a plurality of sub-images each having a plurality of pixel values ​​arranged in the predetermined arrangement pattern in the second frame image based on a second frame image different from the frame image, and the second processing unit may reduce the pixel value difference between pixels in the display order of corresponding pixels of the two or more sub-images and the two or more second sub-images.

[0014] The second processing unit may change the display order of the pixels so as to reduce the number of the detected pixels in the frame image.

[0015] In order to solve the above problem, according to the present disclosure, there is provided a display device comprising: an information processing device capable of generating sub-images to be displayed in sequence; and a projection device, wherein the information processing device comprises: a first processing unit capable of generating, based on a frame image, two or more sub-images out of a plurality of sub-images, each sub-image having a plurality of pixel values ​​arranged in a predetermined arrangement pattern in the frame image; a detection unit that detects a detection pixel to be processed in the frame image based on the display order of corresponding pixels of the two or more sub-images and the pixel value difference between pixels in the display order; and a second processing unit that executes processing to reduce the pixel value difference between corresponding pixels in the detection pixel, wherein the projection device comprises: a first optical system including a light source capable of emitting light; a liquid crystal light valve having a plurality of pixels and capable of generating image light by modulating light from the first optical system based on each of the two or more sub-images; a light shifting device capable of shifting the image light in an in-plane direction of the image depending on which of the plurality of sub-images the image light belongs to; and a second optical system that is capable of projecting the image light processed by the light shifting device.

[0016] In order to solve the above problem, according to the present disclosure, an information processing device is provided that generates a plurality of sub-images that are displayed in a predetermined order while their display positions are changed based on a frame image in which divisional units having a plurality of pixels are arranged in a matrix, the information processing device comprising: a first processing unit that generates the plurality of sub-images arranged according to the matrix arrangement order for each pixel selected from the divisional unit according to a predetermined rule; a detection unit that detects the divisional unit to be processed; and a second processing unit that changes the pixel values ​​of pixels corresponding to the divisional unit to be processed based on the predetermined order so as to reduce flicker, which is a repetition of high brightness and low brightness.

[0017] The detection section may detect the division unit to be processed based on a display order of corresponding pixels of the plurality of sub-images and a pixel value difference between pixels in the display order.

[0018] The detection section may detect a division unit to be processed based on an area having a predetermined display form in the frame image.

[0019] The second processing unit may change the pixel values ​​of the pixels corresponding to the divisional unit to be processed so that pixel value differences between the plurality of sub-images decrease.

[0020] Four adjacent pixels may be arranged in the division unit, and the first processing unit may generate four sub-images by allocating the four adjacent pixels in a predetermined order.

[0021] Four adjacent pixels may be arranged in the division unit, and the first processing unit may generate two sub-images by allocating two of the four adjacent pixels in a predetermined order.

[0022] In order to solve the above problem, according to the present disclosure, there is provided a display device comprising: an information processing device that generates a plurality of sub-images that are displayed in a predetermined order while their display positions are changed, based on a frame image in which divisional units each having a plurality of pixels are arranged in a matrix; and a projection device, wherein the information processing device comprises: a first processing unit that generates the plurality of sub-images arranged for each pixel selected from each divisional unit of the frame image according to a predetermined rule, according to the matrix arrangement order of the divisional units; and a second processing unit that generates a display period control signal that indicates a display period corresponding to the plurality of sub-images, and the projection device comprises: a first optical system that includes a light source that can emit light; a liquid crystal light valve that has a plurality of pixels and is capable of generating image light during the display period by modulating light from the first optical system based on each of the plurality of sub-images and the display period control signal; a light shifting device that can shift the image light in an in-plane direction of the image depending on which of the plurality of sub-images the image light belongs to; and a second optical system that can project the image light processed by the light shifting device.

[0023] The information processing device may further have a detection unit that detects a divisional unit to be processed, and the second processing unit may change the pixel values ​​of pixels corresponding to the divisional unit to be processed so as to reduce flicker, which is a repetition of high brightness and low brightness.

[0024] The frame images may be supplied to the information processing device in accordance with a display order, and the second processing unit may change processing details of the second processing unit based on the display order.

[0025] The display order of the plurality of sub-images may be changed depending on the frame image.

[0026] 8 is a diagram showing an example of the configuration of a display device according to the first embodiment. FIG. 8 is a diagram showing an example of the configuration of a liquid crystal light valve. FIG. 8 is a diagram showing an example of the configuration of a pixel. A perspective view showing an example of the chip configuration of a distance measuring device. A diagram showing an example of an operation for generating a sub-image. A diagram showing an example of the operation of a light shift device. A diagram showing an example of the operation of a light shift device. A diagram depicting four pixels shown in FIG. 7 superimposed. A diagram summarizing the overall processing. A diagram showing an example of an operation in which still image flicker occurs in a display device. A diagram showing an example of an operation in which moving image flicker occurs in a display device. A block diagram showing an example of the configuration of a flicker processing unit according to the present embodiment. A block diagram showing an example of the configuration of a pattern detection unit according to the present embodiment. A conceptual diagram showing an example of a four-phase display. A conceptual diagram showing an example of a two-phase display. An image showing the display order of sub-images. A diagram showing an example of no detected pixel in the first detection mode. A diagram showing an example of a detected pixel in the first detection mode. A diagram showing an example of processing when pixel continuity over multiple frames of a moving image is not taken into consideration. A diagram showing an example of processing when pixel continuity over multiple frames is taken into consideration. A diagram showing an example of detection in the first mode. A diagram showing an example of detection in the second mode. A diagram showing an example of a first thinning mode. 11. A diagram showing an example of a second thinning mode. A diagram showing the processing concept of a display device according to a second embodiment. A diagram showing processing by a flicker countermeasure processing unit for a correction frame. A diagram showing the processing concept of a display device according to a third embodiment. A diagram showing the processing concept of a display device according to a fourth embodiment. A diagram showing the processing concept of a display device according to a fifth embodiment. A diagram showing an example in which a selected image area changes for each frame. A diagram showing an operation example of a display device according to a sixth embodiment. A diagram showing an operation example of a display device according to a seventh embodiment. A diagram showing an operation example of a display device according to an eighth embodiment. A diagram showing an operation example of a display device according to a ninth embodiment. A diagram showing an example of changing the shift direction of a shift device in an entire image. A diagram showing an operation example of a display device with a one-dot stripe pattern and a one-dot checkerboard pattern. A diagram showing an example of changing the shift direction of a shift device in a central image area where the line of sight is focused. A diagram showing an example of dynamically changing the shift direction of a shift device in an image area. A diagram showing an operation example of a display device according to an eleventh embodiment. A diagram showing an example of shifting the display order of each layer in a detection area. A diagram showing an operation example of a display device when the detection area is a one-dot stripe pattern. A diagram showing an example of detecting a suppression area from within an image. A diagram showing an operation example of a display device in a suppression area.16. A diagram showing an example of generating different control signals for even and odd frames. A diagram showing an example of generating different control signals for two-phase display for even and odd frames. A diagram showing an example of generating a control signal in which one frame out of every ten frames is not shifted. A diagram showing an example of light-emitting operation of a display device when the detection area is a one-dot stripe pattern. A diagram showing the processing concept of a display device according to a sixteenth embodiment.

[0027] Hereinafter, embodiments of an information processing device and a display device will be described with reference to the drawings. The following description will focus on the main components of the display device, but the display device may have components or functions that are not shown or described. The following description does not exclude components or functions that are not shown or described.

[0028] First Embodiment FIG. 1 is a diagram showing an example of the configuration of a display device 1 according to a first embodiment. The display device 1 is a display device capable of suppressing flicker. The display device 1 includes an information processing device 2 and a projection device 3. That is, the display device 1 is a display device that projects an image onto a screen 100, and is a transmissive liquid crystal projector that uses a transmissive liquid crystal panel as a light valve. In this example, an image signal Spic of a frame image including image data having a so-called 4K2K resolution is supplied to the display device 1. The frame images are supplied to the display device 1 continuously in time series.

[0029] The information processing device 2 includes a display control unit 380, an image processing unit 390, and a flicker processing unit 400. The projection device 3 includes a light source 11, a condenser lens 12, a dichroic mirror 13, a total reflection mirror 14, a field lens 18B, a dichroic mirror 15, a field lens 18G, total reflection mirrors 16 and 17, a field lens 18R, three liquid crystal light valves 20R, 20G, and 20B, a cross prism 31, a light shift device 32, and a projection lens 33. While this embodiment uses a liquid crystal projector as an example, the present invention is not limited thereto. That is, the information processing device 2 can be used in display devices that may generate flicker. Furthermore, while the present embodiment uses image data with a 4K2K resolution as an example, the present invention is not limited thereto. For example, the display device 1 can support image data with any resolution.

[0030] The light source 11 is configured to emit white light along an optical path AX and is configured using, for example, various lamps such as a halogen lamp, a metal halide lamp, or a xenon lamp, a light-emitting diode, or a laser light source. The condenser lens 12 is provided on the optical path AX and configured to collect the light emitted from the light source 11. The dichroic mirror 13 is provided downstream of the condenser lens 12 on the optical path AX and configured to reflect blue light LB contained in the white light emitted from the light source 11 and transmit red light LR and green light LG contained in the white light. The total reflection mirror 14 is provided on the optical path of the light reflected by the dichroic mirror 13 and configured to reflect the blue light LB reflected by the dichroic mirror 13. The field lens 18B is provided on the optical path of the light reflected by the total reflection mirror 14 and configured to guide the blue light LB reflected by the total reflection mirror 14 to the liquid crystal light valve 20B. The dichroic mirror 15 is provided downstream of the dichroic mirror 13 on the optical path AX and is configured to reflect the green light LG contained in the light transmitted through the dichroic mirror 13 and transmit the red light LR contained in the light transmitted through the dichroic mirror 13. The field lens 18G is configured to guide the green light LG reflected by the dichroic mirror 15 to the liquid crystal light valve 20G. The total reflection mirror 16 is provided downstream of the dichroic mirror 15 on the optical path AX and is configured to reflect the red light LR contained in the light transmitted through the dichroic mirror 15. The total reflection mirror 17 is provided in the optical path of the light reflected by the total reflection mirror 16 and is configured to reflect the red light LR reflected by the total reflection mirror 16. The field lens 18R is provided in the optical path of the light reflected by the total reflection mirror 17 and is configured to guide the red light LR reflected by the total reflection mirror 17 to the liquid crystal light valve 20R.

[0031] Each of the three liquid crystal light valves 20R, 20G, and 20B includes a transmissive liquid crystal panel and is configured to modulate incident light based on image signals SpicR, SpicG, and SpicB, respectively, to generate image light corresponding to the image signals. In this example, the resolution of each of the liquid crystal light valves 20R, 20G, and 20B is so-called 2K1K. That is, for example, the number of horizontal pixels is approximately 2,000 and the number of vertical pixels is approximately 1,000. The liquid crystal light valve 20R is disposed downstream of the field lens 18R in the optical path of the light reflected by the total reflection mirror 17, and generates red image light by modulating the red light LR incident via the field lens 18R based on the image signal SpicR representing a red image. Liquid crystal light valve 20G is provided downstream of field lens 18G in the optical path of the light reflected by dichroic mirror 15, and generates green image light by modulating green light LG incident via field lens 18G based on an image signal SpicG indicating a green image. Liquid crystal light valve 20B is provided downstream of field lens 18B in the optical path of the light reflected by total reflection mirror 14, and generates blue image light by modulating blue light LB incident from field lens 18B based on an image signal SpicB indicating a blue image.

[0032] 2 is a diagram showing an example of the configuration of the liquid crystal light valve 20R. The same applies to the liquid crystal light valves 20G and 20B. The liquid crystal light valve 20R has a pixel array 21, a signal line drive circuit 22, a gate line drive circuit 23, a common electrode drive circuit 24, and a control circuit 25.

[0033] The pixel array 21 has a plurality of signal lines SGL, a plurality of gate lines WSL, and a plurality of pixels P arranged in a matrix.

[0034] The plurality of signal lines SGL extend in the vertical direction and are arranged side by side in the horizontal direction. A pixel signal SIG including a pixel voltage Vpix is ​​applied to each of the plurality of signal lines SGL. The plurality of gate lines WSL extend in the horizontal direction and are arranged side by side in the vertical direction. A gate signal SWSL is applied to each of the plurality of gate lines WSL.

[0035] 3 is a diagram showing an example of the configuration of a pixel P. The pixel P includes a transistor MN1, a liquid crystal display element 40, and a capacitor CAP.

[0036] The transistor MN1 is a thin-film transistor and an N-type FET (Field Effect Transistor). The gate of the transistor MN1 is connected to the gate line WSL, the source is connected to the signal line SGL, and the drain is connected to the liquid crystal display element 40 and the capacitor CAP.

[0037] The liquid crystal display element 40 has a pixel electrode 41, a liquid crystal layer 42, and a common electrode 43. The pixel electrode 41, the liquid crystal layer 42, and the common electrode 43 are arranged in this order. The pixel electrode 41 is provided individually for each of the plurality of pixels P. The pixel electrode 41 is connected to the drain of the transistor MN1 and one end of the capacitor CAP. When the transistor MN1 is turned on, a pixel voltage Vpix is ​​applied to the pixel electrode 41. The common electrode 43 is provided in common to the plurality of pixels P. A common voltage Vcom is applied to the common electrode 43. In this example, the common voltage Vcom is an AC voltage. The liquid crystal layer 42 is configured to change its light transmittance based on the voltage difference between the pixel electrode 41 and the common electrode 43.

[0038] One end of the capacitor CAP is connected to the drain of the transistor MN1 and the pixel electrode 41 of the liquid crystal display element 40. A common voltage Vcom is applied to the other end of the capacitor CAP. The capacitor CAP maintains the voltage difference between the pixel electrode 41 and the common electrode 43 when the transistor MN1 is in the off state.

[0039] The signal line driving circuit 22 (FIG. 2) is configured to generate a pixel signal SIG including a pixel voltage Vpix based on instructions from the control circuit 25, and drive the pixel array 21 by applying the pixel signals SIG to the signal lines SGL in the pixel array 21, respectively.

[0040] The gate line driving circuit 23 is configured to generate gate signals SWSL based on instructions from the control circuit 25 and drive the pixel array 21 by applying the gate signals SWSL to the gate lines WSL in the pixel array 21, respectively.

[0041] The common electrode driving circuit 24 is configured to drive the common electrode 43 in the pixel array 21 based on instructions from the control circuit 25. The common electrode driving circuit 24 is configured to apply a common voltage Vcom, which is an AC voltage, to the common electrode 43 of the pixel array 21.

[0042] 4 shows an example of the operation of pixel P. In this example, the common voltage Vcom is an AC voltage that transitions between voltage VH and voltage VL each time a sub-frame period SF (described later) elapses. Voltage VH is a voltage higher than voltage VL. For example, the common voltage Vcom is voltage VL during the period from timing t1 to t2, and is voltage VH during the period from timing t2 to t3.

[0043] The signal line drive circuit 22 sequentially writes to the pixel P a pixel voltage Vpix of positive polarity and a pixel voltage Vpix of negative polarity corresponding to the pixel value, for example, based on the pixel value included in the frame image. Specifically, the signal line drive circuit 22 applies a pixel voltage Vpix higher than the common voltage Vcom (voltage VL) to the pixel electrode 41 of the pixel P during the period from timing t1 to t2. That is, the pixel voltage Vpix is ​​a positive voltage with respect to the common voltage Vcom (voltage VL). Furthermore, the signal line drive circuit 22 applies a pixel voltage Vpix lower than the common voltage Vcom (voltage VH) to the pixel electrode 41 of the pixel P during the period from timing t2 to t3. That is, the pixel voltage Vpix is ​​a negative voltage with respect to the common voltage Vcom (voltage VH). The voltage difference ΔV between the pixel voltage Vpix and the common voltage Vcom from timing t1 to t2 and the voltage difference ΔV between the pixel voltage Vpix and the common voltage Vcom from timing t2 to t3 are both voltage differences corresponding to the pixel values ​​and are equal to each other. The light transmittance of the liquid crystal layer 42 is determined by the voltage difference ΔV (absolute value) between the pixel voltage Vpix on the pixel electrode 41 and the common voltage Vcom on the common electrode 43, so the light transmittance from timing t1 to t2 is the same as the light transmittance from timing t2 to t3.

[0044] In this way, the signal line driving circuit 22 writes pixel voltages Vpix of opposite polarities to the pixels P during the period from timing t1 to t2 and the period from timing t2 to t3. As a result, for example, if impurity ions are present in the liquid crystal layer 42, the impurity ions do not move significantly during the period from timing t1 to t3. That is, for example, if the impurity ions are cations, the impurity ions move toward the common electrode 43 during the period from timing t1 to t2 and toward the pixel electrode 41 during the period from timing t2 to t3, resulting in almost no net movement during the period from timing t1 to t3. For example, if the impurity ions are anions, the impurity ions move toward the pixel electrode 41 during the period from timing t1 to t2 and toward the common electrode 43 during the period from timing t2 to t3, resulting in almost no net movement during the period from timing t1 to t3. As a result, burn-in can be suppressed in each of the multiple pixels P in the pixel array 21.

[0045] The control circuit 25 is configured to control the operation of the liquid crystal light valve 20R based on the image signal SpicR. The control circuit 25 performs predetermined processing based on the image signal SpicR and controls the operations of the signal line drive circuit 22, the gate line drive circuit 23, and the common electrode drive circuit 24. In this way, the control circuit 25 controls the operation of the liquid crystal light valve 20R so that the liquid crystal light valve 20R generates image light according to the image signal SpicR. Although the above description has been given using the liquid crystal light valve 20R as an example, the same applies to the liquid crystal light valves 20G and 20B.

[0046] The cross prism 31 (FIG. 1) is configured to generate composite image light by combining the red image light generated by the liquid crystal light valve 20R, the green image light generated by the liquid crystal light valve 20G, and the blue image light generated by the liquid crystal light valve 20B, and to emit this composite image light toward the light shift device 32. The cross prism 31 is provided at a position where the optical paths of the light reflected by the total reflection mirror 17, the dichroic mirror 15, and the light paths of the light reflected by the total reflection mirror 14 intersect with each other.

[0047] The light shift device 32 is provided in the optical path of the composite image light emitted from the cross prism 31 and is configured to shift the composite image light emitted from the cross prism 31 in an in-plane direction of the image based on a control signal CTL. The light shift device 32 includes, for example, a quartz plate. The light shift device 32 is configured to shift the composite image light in the in-plane direction of the image by moving the quartz plate based on the control signal CTL. However, the light shift device 32 is not limited to this, and may also shift the composite image light in the in-plane direction of the image using, for example, a liquid crystal device.

[0048] The projection lens 33 is arranged downstream of the light shift device 32 in the optical path of the composite image light emitted from the cross prism 31, and is configured to project the composite image light emitted from the cross prism 31 and shifted by the light shift device 32 onto the screen 100.

[0049] The display control unit 380 is configured to control the operations of the liquid crystal light valves 20R, 20G, and 20B and the light shift device 32 based on the image signal Spic, thereby controlling the display operation of the display device 1. Specifically, the display control unit 380 supplies image signals SpicR, SpicG, and SpicB generated by the flicker processing unit 400 to the liquid crystal light valves 20R, 20G, and 20B, respectively, based on the image signal Spic, and supplies a control signal CTL generated by the flicker processing unit 400 to the light shift device 32, thereby controlling the display operation of the display device 1.

[0050] The image processing unit 390 is configured to generate four sub-images PAr, PBr, PCr, and PDr for red based on image data of a frame image for red included in the image signal Spic, generate four sub-images PAg, PBg, PCg, and PDg for green based on image data of a frame image for green included in the image signal Spic, and generate four sub-images PAb, PBb, PCb, and PDb for blue based on image data of a frame image for blue included in the image signal Spic. Note that the image processing unit 390 according to this embodiment corresponds to a first processing unit. Also, in this embodiment, array elements having pixel values ​​in image data may be referred to as pixels.

[0051] The flicker processor 400 generates image signals SpicR, SpicG, and SpicB that suppress flicker using these sub-images PAr, PBr, PCr, PDr, PAg, PBg, PCg, PDg, PAb, PBb, PCb, and PDb. Details of the flicker processor 400 will be described later.

[0052] 5 is a diagram showing an example of the operation of the image processing unit 390 to generate four red sub-images PAr, PBr, PCr, and PDr based on a red frame image PFr. The resolution of the frame image PFr is 4K2K, and the resolution of the sub-images PAr, PBr, PCr, and PDr is 2K1K. Note that in FIG. 5, for ease of explanation, the frame image PFr and the sub-images PAr, PBr, PCr, and PDr are each depicted with a reduced number of pixels. The green sub-images PAg, PBg, PCg, and PDg and the blue sub-images PAb, PBb, PCb, and PDb are similarly generated based on the green frame image PFr and the blue frame image PFb.

[0053] The frame image PFr is divided into units (division units U) of four pixels A, B, C, and D arranged in two rows and two columns. Pixel A is the pixel arranged in the lower right of the division unit U, pixel B is the pixel arranged in the lower left of the division unit U, pixel C is the pixel arranged in the upper left of the division unit U, and pixel D is the pixel arranged in the upper right of the division unit U. In the frame image PFr, the arrangement pattern of the plurality of pixels A and the arrangement pattern of the plurality of pixels B are offset from each other in the horizontal direction, and the arrangement pattern of the plurality of pixels C and the arrangement pattern of the plurality of pixels D are offset from each other in the horizontal direction. In the frame image PF, the arrangement pattern of the plurality of pixels A and the arrangement pattern of the plurality of pixels D are offset from each other in the vertical direction, and the arrangement pattern of the plurality of pixels B and the arrangement pattern of the plurality of pixels C are offset from each other in the vertical direction.

[0054] In this example, the image processing unit 390 generates a sub-image P1 including pixel values ​​for a plurality of pixels B and a plurality of pixels C based on the pixels in the odd-numbered columns in this frame image PFr, and generates a sub-image P2 including pixel values ​​for a plurality of pixels A and a plurality of pixels D based on the pixels in the even-numbered columns in this frame image PFr. The image processing unit 390 then generates a sub-image PAr including pixel values ​​for a plurality of pixels A based on the pixels in the even-numbered rows in sub-image P2, generates a sub-image PBr including pixel values ​​for a plurality of pixels B based on the pixels in the even-numbered rows in sub-image P1, generates a sub-image PCr including pixel values ​​for a plurality of pixels C based on the pixels in the odd-numbered rows in sub-image P1, and generates a sub-image PDr including pixel values ​​for a plurality of pixels D based on the pixels in the odd-numbered rows in sub-image P2. Each of the sub-images PAr to PDr has a plurality of pixel values ​​arranged in a predetermined arrangement pattern in the frame image PF. Specifically, sub-image PAr has multiple pixel values ​​for multiple pixels A arranged at the bottom right of each of the divisional units U in frame image PFr, sub-image PBr has multiple pixel values ​​for multiple pixels B arranged at the bottom left of each of the divisional units U in frame image PFr, sub-image PCr has multiple pixel values ​​for multiple pixels C arranged at the top left of each of the divisional units U in frame image PFr, and sub-image PDr has multiple pixel values ​​for multiple pixels D arranged at the top right of each of the divisional units U in frame image PFr. Note that the method for generating sub-images PAr to PDr is not limited to the processing method described above, and other processing methods for generating sub-images PAr to PDr may also be used.

[0055] In this way, the image processing unit 390 generates four sub-images PAr, PBr, PCr, and PDr for red based on the frame image PFr for red, generates four sub-images PAg, PBg, PCg, and PDg for green based on the frame image PFg for green, and generates four sub-images PAb, PBb, PCb, and PDb for blue based on the frame image PFb for blue. Note that sub-images PA, PB, PC, and PD may be generated using pixels having red, green, and blue as a single frame image PF, and sub-images PAr, PBr, PCr, PDr, PAg, PBg, PCg, PDg, PAb, PBb, PCb, and PDb may be generated based on the sub-images PA, PB, PC, and PD.

[0056] The display control unit 380 displays the four sub-images PA, PB, PC, and PD generated by the image processing unit 390 in the order of time t. More specifically, the display control unit 380 sequentially supplies an image signal SpicR containing image data of a sub-image to be displayed among the four red sub-images PAr, PBr, PCr, and PDr generated by the image processing unit 390 to the liquid crystal light valve 20R, supplies an image signal SpicG containing image data of a sub-image to be displayed among the green sub-images PAg, PBg, PCg, and PDg generated by the image processing unit 390 to the liquid crystal light valve 20G, and supplies an image signal SpicB containing image data of a sub-image to be displayed among the four blue sub-images PAb, PBb, PCb, and PDb generated by the image processing unit 390 to the liquid crystal light valve 20B.

[0057] The display control unit 380 controls the operations of the liquid crystal light valves 20R, 20G, and 20B so that the liquid crystal light valves 20R, 20G, and 20B respectively display the sub-image PAr corresponding to red, the sub-image PAg corresponding to green, and the sub-image PAb corresponding to blue during the same period. As a result, the cross prism 31 combines the image light of the sub-image PAr corresponding to red, the image light of the sub-image PAg corresponding to green, and the image light of the sub-image PAb corresponding to blue, and emits the combined image light of the sub-image PA toward the light shift device 32.

[0058] Similarly, the display control unit 380 controls the operation of the liquid crystal light valves 20R, 20G, and 20B so that the liquid crystal light valves 20R, 20G, and 20B respectively display a sub-image PBr corresponding to red, a sub-image PBg corresponding to green, and a sub-image PBb corresponding to blue during the same period. As a result, the cross prism 31 combines the image light of the sub-image PBr corresponding to red, the image light of the sub-image PBg corresponding to green, and the image light of the sub-image PBb corresponding to blue, and emits combined image light for the sub-image PB toward the light shift device 32. Similarly, the display control unit 380 controls the operation of the liquid crystal light valves 20R, 20G, and 20B so that the liquid crystal light valves 20R, 20G, and 20B respectively display a sub-image PCr corresponding to red, a sub-image PCg corresponding to green, and a sub-image PCb corresponding to blue during the same period. As a result, the cross prism 31 combines the image light of the sub-image PCr corresponding to red, the image light of the sub-image PCg corresponding to green, and the image light of the sub-image PCb corresponding to blue, and emits the combined image light for the sub-image PC toward the light shift device 32. Similarly, the display control unit 380 controls the operations of the liquid crystal light valves 20R, 20G, and 20B so that the liquid crystal light valves 20R, 20G, and 20B respectively display the sub-image PDr corresponding to red, the sub-image PDg corresponding to green, and the sub-image PDb corresponding to blue during the same period. As a result, the cross prism 31 combines the image light of the sub-image PDr corresponding to red, the image light of the sub-image PDg corresponding to green, and the image light of the sub-image PDb corresponding to blue, and emits the combined image light for the sub-image PD toward the light shift device 32.

[0059] The display control unit 380 controls the shifting operation of the image light in the light shift device 32 in accordance with the composite image light incident on the light shift device 32 .

[0060] 6A and 6B are diagrams showing an example of the operation of the light shift device 32, in which (A) shows an operating state SA when composite image light for the sub-image PA is incident, (B) shows an operating state SB when composite image light for the sub-image PB is incident, (C) shows an operating state SC when composite image light for the sub-image PC is incident, and (D) shows an operating state SD when composite image light for the sub-image PD is incident. In Fig. 6, the thin grid lines indicate the position of the composite image light in the operating state SA.

[0061] 7A and 7B are diagrams showing an example of the operation of the light shift device 32, in which (A) shows the operating state SA when composite image light for the sub-image PA is incident, (B) shows the operating state SB when composite image light for the sub-image PB is incident, (C) shows the operating state SC when composite image light for the sub-image PC is incident, and (D) shows the operating state SD when composite image light for the sub-image PD is incident. In Fig. 6, the thin-line grid indicates the position of the composite image light in the operating state SA. Fig. 7, like Fig. 6, shows the shift operation of the light shift device 32, and Fig. 7 focuses on one pixel and shows the operating states SA to SD.

[0062] During the period when the composite image light for the sub-image PA is incident from the cross prism 31, the light shift device 32 is in the operating state SA as shown in Fig. 6A and Fig. 7A. In this operating state SA, the light shift device 32 shifts the composite image light for the sub-image PA downward by 0.5 pixels compared to the operating state SD (Fig. 6D and Fig. 7D).

[0063] During the period when the composite image light for the sub-image PB is incident from the cross prism 31, the light shift device 32 is in the operating state SB as shown in Fig. 6(B) and Fig. 7(B) . In this operating state SB, the light shift device 32 shifts the composite image light for the sub-image PB by 0.5 pixels to the left compared to the operating state SA (Figs. 6(A) and 7(A)).

[0064] During the period when the composite image light for the sub-image PC is incident from the cross prism 31, the light shift device 32 is in the operating state SC as shown in Fig. 6(C) and Fig. 7(C). In this operating state SC, the light shift device 32 shifts the composite image light for the sub-image PC upward by 0.5 pixels compared to the operating state SB (Figs. 6(B) and 7(B)).

[0065] During the period when the composite image light for the sub-image PD is incident from the cross prism 31, the light shift device 32 is in the operating state SD as shown in Fig. 6(D) and Fig. 7(D) . In this operating state SD, the light shift device 32 shifts the composite image light for the sub-image PD by 0.5 pixels to the right compared to the operating state SC (Figs. 6(C) and 7(C)).

[0066] Fig. 8 is a diagram illustrating the four pixels shown in Fig. 7 superimposed on each other. As shown in Fig. 7, the light shift device 32 shifts the composite image light according to the composite image light incident on the light shift device 32, so that the center positions of the pixels are shifted from each other as shown in Fig. 8. As a result, the display device 1 can display an image having a pseudo 4K2K resolution using the liquid crystal light valves 20R, 20G, and 20B having a 2K1K resolution.

[0067] (Overall Operation Overview) Fig. 9 is a diagram summarizing the overall processing. As shown in Fig. 9(a), the image processing unit 390 divides the image signal Spic into four sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b. The display control unit 380 then composites and displays the four sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b generated by the image processing unit 390 in order of time t. The sub-images PA, PB, PC, and PD correspond to the composite image light emitted from the cross prism 31.

[0068] More specifically, sub-image PA represents a composite of sub-images PAr, PAg, and PAb; sub-image PB represents a composite value of sub-images PBr, PBg, and PBb; sub-image PC represents a composite value of sub-images PCr, PCg, and PCb; and sub-image PD represents a composite value of sub-images PDr, PDg, and PDb. As can be seen from this, the luminance value of the display image of sub-image PA can be calculated based on the pixel values ​​of sub-images PAr, PAg, and PAb. Similarly, the luminance value of the display image of sub-image PB can be calculated based on the pixel values ​​of sub-images PBr, PBg, and PBb. Similarly, the luminance value of the display image of sub-image PC can be calculated based on the pixel values ​​of sub-images PCr, PCg, and PCb. Similarly, the luminance value of the display image of sub-image PD can be calculated based on the pixel values ​​of sub-images PDr, PDg, and PDb.

[0069] 9(b), when such sub-images PA, PB, PC, and PD are compositely displayed, the display control unit 380 supplies the image signals SpicR, SpicG, and SpicB, and the control signal CTL to the light shift device 32, thereby changing the display positions of the sub-images PA, PB, PC, and PD by mechanical shifting, and controlling the display operation of the display device 1. This makes it possible to increase the original display resolution to a resolution with a pixel size that is one-fourth that of the original, as shown in FIG.

[0070] 1 , the image processing unit 390 generates sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b based on the image signal Spic. The flicker processing unit 400 generates image signals SpicR, SpicG, and SpicB that have been subjected to flicker suppression processing based on the sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b, and generates control signals CTL corresponding to the image signals SpicR, SpicG, and SpicB. The display control unit 380 controls the display operation of the display device 1 by supplying the control signals CTL corresponding to the image signals SpicR, SpicG, and SpicB to the light shift device 32.

[0071] Light source 11 emits white light. Condenser lens 12 collects the light emitted from light source 11. Dichroic mirror 13 reflects blue light LB contained in the white light emitted from light source 11 and transmits red light LR and green light LG contained in the white light. Total reflection mirror 14 reflects the blue light LB reflected by dichroic mirror 13. Field lens 18B guides the blue light LB reflected by total reflection mirror 14 to liquid crystal light valve 20B. Liquid crystal light valve 20B generates blue image light by modulating the blue light LB incident from field lens 18B based on an image signal SpicB indicating a blue image.

[0072] Dichroic mirror 15 reflects green light LG contained in the light transmitted through dichroic mirror 13 and transmits red light LR contained in the light transmitted through dichroic mirror 13. Field lens 18G guides the green light LG reflected by dichroic mirror 15 to liquid crystal light valve 20G. Liquid crystal light valve 20G generates green image light by modulating the green light LG incident via field lens 18G based on an image signal SpicG indicating a green image.

[0073] Total reflection mirror 16 reflects red light LR included in the light transmitted through dichroic mirror 15. Total reflection mirror 17 reflects the red light LR reflected by total reflection mirror 16. Field lens 18R guides the red light LR reflected by total reflection mirror 17 to liquid crystal light valve 20R. Liquid crystal light valve 20R generates red image light by modulating the red light LR incident via field lens 18R based on an image signal SpicR indicating a red image.

[0074] The cross prism 31 generates composite image light by combining the red image light generated by the liquid crystal light valve 20R, the green image light generated by the liquid crystal light valve 20G, and the blue image light generated by the liquid crystal light valve 20B, and emits this composite image light toward the light shift device 32. The light shift device 32 shifts the composite image light emitted from the cross prism 31 in an in-plane direction of the image based on a control signal CTL. The projection lens 33 projects the composite image light emitted from the cross prism 31 and shifted by the light shift device 32 onto the screen 100.

[0075] (Example of Flicker Occurrence) FIG. 10 is a diagram showing an example of operation in which still image flicker occurs in the display device 1. FIG. 10 illustrates an example of operation of the display device 1. Also shown is an example of still image flicker occurring when image signals Spic of a one-dot pattern P10, a one-dot stripe pattern P12, and a one-dot checkerboard pattern P14 are input. Here, an example is described in which the sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b generated by the image processing unit 390 are output as image signals SpicR, SpicG, and SpicB without undergoing flicker suppression processing. In other words, this is an example in which the flicker processing unit 400 is not operating. Note that in this embodiment, the term "flicker" refers to phenomena such as a part of the screen flashing, a part of the screen changing in color, or a horizontal stripe appearing on the screen.

[0076] (A) shows the frame period F. For example, at 60 Hz, it is 16.7 msec. (B) shows the subframe period SF. For example, at 60 Hz, the subframe period is 4.2 msec. (C) shows the potential and the display period. A "+" indicates that a positive pixel voltage Vpix is ​​written to a pixel P, and a "-" indicates that a negative pixel voltage Vpix is ​​written to a pixel P. Also, in (C), the display period is depicted by a rectangular frame. In this example, the light source 11 continues to emit white light by repeating A to D. (D) shows the first four subimages to be displayed. (E) shows an example of a subimage with a 1-dot pattern P10, (F) shows an example of a subimage with a 1-dot stripe pattern P12, and (G) shows an example of a subimage with a 1-dot pattern scroll P16.

[0077] The first frame image PF (frame image PF1) is supplied using the image signal Spic to the display device 1. The image processing unit 390 generates four sub-images PA to PD based on this frame image PF1, and the display control unit 380 supplies these four sub-images PA to PD as image signals SpicR, SpicG, and SpicB to the liquid crystal light valves 20R, 20G, and 20B.

[0078] More specifically, the image processing unit 390 generates four red sub-images PAr-PDr based on the red frame image PF1, generates four green sub-images PAg-PDg based on the green frame image PF1, and generates four blue sub-images PAb-PDb based on the blue frame image PF1. The display control unit 380 then supplies the red sub-images PAr-PDr to the liquid crystal light valve 20R using the image signal SpicR, supplies the green sub-images PAg-PDg to the liquid crystal light valve 20G using the image signal SpicG, and supplies the blue sub-images PAb-PDb to the liquid crystal light valve 20B using the image signal SpicB. As a result, the sub-images PA, PB, PC, and PD are combined in this order by the cross prism 31 and projected onto the screen 100 via the light shift device 32. For example, in sub-images PA, PB, PC, and PD, pixels below the lower threshold of 7 are perceived as black, and pixels above 248 are perceived as white, for example.

[0079] 10(E), when the frame image PF1 is, for example, a one-dot pattern P10, the pixel at pixel position D in the division unit U (see FIG. 5) has a high pixel value, and the pixels at pixel positions A, B, and C have low pixel values ​​(visually perceived as black). That is, when the one-dot pattern P10 is used, the sub-images PA to PC have low pixel values, and the sub-image PD has a high pixel value (visually perceived as white). This causes a 60-Hz flicker to occur in the displayed image.

[0080] 10(F), when the frame image PF1 is, for example, a one-dot stripe pattern P12, the pixels at pixel positions C and D in the division unit U have high pixel values, and the pixels at pixel positions A and B have low pixel values. That is, when the one-dot stripe pattern P12 is used, the sub-images PA and PB have low pixel values, and the sub-images PC and PD have high pixel values. This causes flicker with a 120-hertz cycle to occur in the displayed image.

[0081] 10(G), when the frame image PF1 is, for example, a one-dot checkerboard pattern P14, the pixels at pixel positions A and C in the division unit U have high pixel values, and the pixels at pixel positions B and D have low pixel values. That is, in the case of the one-dot checkerboard pattern P14, the sub-images PB and PD have low pixel values, and the sub-images PA and PC have high pixel values. This causes flicker with a 240-Hz cycle in the displayed image.

[0082] FIG. 11 is a diagram showing an example of an operation in which moving image flicker occurs in the display device 1. As shown in FIG. 11, an example of an operation of the display device 1 is shown. (A) shows the frame period F. For example, at 60 Hz, this is 16.7 msec. (B) shows the subframe period SF. For example, at 60 Hz, the subframe period is 4.2 msec. (C) shows the potential and the display period. A "+" indicates that a positive pixel voltage Vpix is ​​written to a pixel P, and a "-" indicates that a negative pixel voltage Vpix is ​​written to a pixel P. In addition, in (C), the display period is depicted by a rectangular frame. In this example, the light source 11 continues to emit white light. (D) shows the displayed subimage. (E) shows an example of a subimage of a one-dot pattern scroll P16, and (F) shows an example of a subimage of a one-dot pattern scroll P16.

[0083] As shown in FIG. 11E , for example, in the case of the 1-dot pattern scroll P16, in the frame image PF1, the pixel at pixel position D in the division unit U has a high pixel value, and the pixels at pixel positions A, B, and C have low pixel values. That is, in the frame image PF1 of the 1-dot pattern scroll P16, the sub-images PA to PC have low pixel values, and the sub-image PD has a high pixel value. In the frame image PF2, the pixel at pixel position A in the division unit U has a high pixel value, and the pixels at pixel positions B, C, and D have low pixel values. That is, in the frame image PF2 of the 1-dot pattern scroll P16, the sub-images PA and PB have high pixel values, and the sub-images PC and PD have high pixel values. This causes flicker with a 30-hertz period to occur in the moving image display image.

[0084] 11(F), in the case of the 1-dot stripe pattern P18, in the frame image PF1, the pixels at pixel positions C and D of the divisional unit U have high pixel values, and the pixels at pixel positions A and B have low pixel values. That is, in the frame image PF1 of the 1-dot stripe pattern P18, the sub-images PA and PB have low pixel values, and the sub-images PC and PD have high pixel values. In the frame image PF2, the pixels at pixel positions A and B of the divisional unit U have high pixel values, and the pixels at pixel positions C and D have low pixel values. That is, in the frame image PF2 of the 1-dot stripe pattern P18, the sub-images PA and PB have high pixel values, and the sub-images PC and PD have low pixel values. This causes flicker with a 60-hertz period to occur in the moving image display image.

[0085] Here, we will explain the flicker processing unit 400 that suppresses such flicker. Fig. 12 is a block diagram showing an example of the configuration of the flicker processing unit 400 according to this embodiment. As shown in Fig. 12, the flicker processing unit 400 has a pattern detection unit 402, a flicker countermeasure processing unit 404, and a memory 406.

[0086] The pattern detection unit 402 detects pixel regions of the sub-images PA to PD where flicker occurs, based on the sub-images PA to PD generated by the image processing unit 390. For example, the pattern detection unit 402 detects a detection pixel to be processed based on the coordinates of the frame image PF, based on the display order of corresponding pixels in two or more sub-images PA to PD and the pixel value difference between pixels in the display order, based on the sub-images PA to PD generated by the image processing unit 390. Note that the pattern detection unit 402 according to this embodiment corresponds to the detection unit.

[0087] The flicker countermeasure processor 404 executes processing to reduce the pixel value difference between corresponding pixels in the detected pixels detected by the pattern detector 402. As a result, the flicker countermeasure processor 404 generates image signals SpicR, G, B that suppress the occurrence of flicker based on the sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b in which the pixel values ​​of the pixel region in which flicker occurs have been changed. In this case, it is also possible to generate the image signals SpicR, G, B that suppress the occurrence of flicker based on the sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b of a plurality of consecutive frame images PF1.

[0088] Alternatively, the flicker countermeasure processor 404 can change the display order of the sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b based on the information about the detected pixels detected by the pattern detector 402, and can also generate a signal to change the order of mechanical drive of the control signal CTL. In this way, the flicker countermeasure processor 404 according to this embodiment can also execute a process to reduce the pixel value difference between corresponding pixels in the detected pixels by changing the display order of the sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b. In this case, it can also execute a process to change the display order of the sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b based on the sub-images PAr, g, b, PBr, g, b, PCr, g, b, and PDr, g, b of multiple consecutive frame images PF1. The flicker countermeasure processor 404 according to this embodiment corresponds to the second processor.

[0089] 13 is a block diagram showing an example of the configuration of the pattern detection unit 402 according to this embodiment. As shown in FIG. 13, the pattern detection unit 402 includes a detection phase / phase order selection unit 408, a gray level difference detection unit 410, and a processing range detection unit 412.

[0090] The detection phase / phase order selection unit 408 selects the number of phases and the display order of the display image. FIG. 14 is a conceptual diagram showing an example of a four-phase display. As shown in FIG. 14, when the detection phase is four, the sub-images PA, PB, PC, and PD are time-divided and phase-expanded and displayed based on the image signal Spic. FIG. 15 is a conceptual diagram showing an example of a two-phase display. As shown in FIG. 15, when the detection phase is two, the sub-images PA, PB, PC, and PD are time-divided and phase-expanded and displayed based on the image signal Spic. FIG. 15 schematically shows examples of the sub-images PA and PC. The detection phase / phase order selection unit 408 selects the number of phases of the display image. For example, the detection phase / phase order selection unit 408 selects four phases (see FIG. 14), two phases (see FIG. 15), etc. In this way, the information processing device 2 according to this embodiment can generate two or more sub-images from among multiple sub-images.

[0091] 16 is an image showing the display order of the sub-images PA, PB, PC, and PD. As shown in FIG. 16, the detection phase / phase order selection unit 408 selects the order of shifting by the light shift device 32 and the display order of the sub-images PA, PB, PC, and PD. For example, FIG. 16 shows the display order of the sub-images PA, PC, PB, and PD. The detection phase / phase order selection unit 408 selects the display order of the sub-images PA to PD. The detection phase / phase order selection unit 408 can also generate a control signal CTL according to the selected display order.

[0092] The processing range detection unit 412 detects a pixel region where flicker processing is performed. The processing range detection unit 412 has a first detection mode and a second detection mode for moving images. In the first detection mode, detected pixels are detected based on the image signal of a single frame. That is, the first detection mode is a mode in which detected pixels are detected only in the current frame. The second detection mode is a mode in which detected pixels are detected while taking into account continuity with at least one of the previous and next frames. That is, the second detection mode is a mode in which detected pixels are detected by comparing them with pixels in at least one of the previous and next frames. Furthermore, the processing range detection unit 412 can further detect detected pixels that are to undergo flicker processing from among the detected pixels as processed pixels.

[0093] On the other hand, in the second detection mode, the processing range detection unit 412 detects detection pixels based on multiple consecutive frames in addition to the detection units detected in the first detection mode. Also in the second detection mode, the processing range detection unit 412 can further detect detection pixels for which flicker processing is to be performed from among the detection pixels as processing pixels.

[0094] FIG. 17 is a diagram showing an example in which there are no detected pixels in the first detection mode. FIG. 18 is a diagram showing an example in which there are detected pixels in the first detection mode. As shown in FIGS. 17 and 18 , the processing range detection unit 412 detects detected pixels based on the values ​​and display order of pixels A, B, C, and D of the division unit U (see FIG. 5 ). For example, as described above, flicker occurs when a luminance difference occurs in the displayed image (see FIGS. 11 and 12 ). Therefore, the processing range detection unit 412 sets thresholds for pixels A, B, C, and D of the division unit U (see FIG. 5 ) and identifies a division unit U in which two or more consecutive detected pixels are present as a detection unit. In other words, the detection unit includes the detected pixel.

[0095] The processing range detection unit 412 sets the lower threshold to 7 or less and the upper threshold to 248 or more, for example. Pixels equal to or less than the lower threshold of 7 are visually recognized as, for example, black, and pixels equal to or greater than the upper threshold of 248 are visually recognized as, for example, white. Then, when the processing range detection unit 412 detects a pixel equal to or greater than the upper threshold of 248 and then finds two consecutive pixels equal to or less than the lower threshold of 7, the processing range detection unit 412 determines this to be a detection unit. In other words, the pixel equal to or greater than the upper threshold of 248 and two consecutive pixels equal to or less than the lower threshold of 7 are determined to be detected pixels.

[0096] In Figure 17, when the pixels of segmental unit U1 have four phases and the display order is A, B, C, D, the pixel value order is, for example, 49 → 71 → 190 → 112. Among 49 → 71 → 190 → 112, there are no pixels that exceed the upper threshold value of 248, so segmental unit U1 is not detected. Similarly, the pixel value order of segmental unit U2 is 121 → 241 → 16 → 22. Among 121 → 241 → 16 → 22, there are no pixels that exceed the upper threshold value of 248, so segmental unit U2 is not detected. Thus, in the example of Figure 17, there is no segmental unit U that can be used as a detection unit.

[0097] In FIG. 18 , pixel values ​​are underlined in the order that they match the detection pattern. For example, if the pixels of the division unit U1 have four phases and the display order is A, B, C, and D, the pixel value order is 255 → 0 → 0 → 128. Among the 255 → 0 → 0 → 12, there is a pixel with a pixel value of 255, which exceeds the upper threshold value of 248, followed by a series of pixel values ​​of 0, 0, which are equal to or less than the lower threshold value of 7. Therefore, the division unit U1 is detected as a detection unit. That is, pixels A, B, and C of the division unit U1 are detected as detection pixels. Note that, in this embodiment, the detection rule for detection pixels is that after detecting a pixel with the upper threshold value of 248, there are two consecutive pixels equal to or less than the lower threshold value of 7, but this is not limiting. For example, a detection pixel may be detected when the absolute value of the pixel value difference between consecutive pixels in the display order exceeds a predetermined value.

[0098] Similarly, for the pixels of the segmental unit U2, if the display order is A, B, C, and D, and there are four phases, the pixel value order is, for example, 128 → 255 → 1 → 3. Among the phases 128 → 255 → 1 → 3, there is a pixel with a pixel value of 255, which exceeds the upper threshold value of 248, followed by consecutive pixels with pixel values ​​of 1 and 3, which are equal to or less than the lower threshold value of 7. Therefore, the segmental unit U1 is detected as a detection unit. That is, the pixels B, C, and D of the segmental unit U2 are detected pixels. Similarly, for the pixels of the segmental unit U6, if there are four phases and the display order is A, B, C, and D, the pixel value order is, for example, 75 → 250 → 5 → 0. Among the phases 75 → 250 → 5 → 0, there is a pixel with a pixel value of 250, which exceeds the upper threshold value of 248, followed by consecutive pixels with pixel values ​​of 5 and 0, which are equal to or less than the lower threshold value of 7. Therefore, the segmental unit U6 is detected as a detection unit. That is, the pixels B, C, and D of the segmental unit U6 are detected pixels.

[0099] 19 is a diagram showing an example of processing in the second detection mode when pixel continuity across multiple frames is not taken into consideration. The image signal for frame N-1 and the image signal for frame N are shown. For example, when pixel continuity across multiple frames is not taken into consideration, segment units U1a, U2a, U3b, and U8b are not detected.

[0100] 20 is a diagram showing an example of processing when pixel continuity across multiple frames is considered in the second detection mode. The image signal of frame N-1 and the image signal of frame N are shown. For example, when pixel continuity across multiple frames is considered, segment units U1a, U3b, and U8b show an example of detection. Pixel values ​​that match the detection pattern are underlined in order.

[0101] 20, when continuity is taken into consideration, the pixel value order of the pixels in the segmental unit U1a is 4 → 18 → 167 → 38 → 19 → 255 → 0 → 0. Among the order 4 → 18 → 167 → 38 → 19 → 255 → 0 → 0, there is a pixel with a pixel value of 255, which exceeds the upper threshold of 248, followed by a series of pixels with pixel values ​​of 0, 0, which are equal to or less than the lower threshold of 7, so the segmental unit U1a is detected as a detection unit. In other words, pixels B, C, and D of the segmental unit U1b are detected pixels.

[0102] Similarly, when continuity is taken into consideration, the pixel value order of the pixels in segmental unit U3b is 201 → 146 → 72 → 255 → 6 → 2 → 175 → 254. Among 201 → 146 → 72 → 255 → 6 → 2 → 175 → 25, there is a pixel with a pixel value of 255, which exceeds the upper threshold of 248, followed by successive pixels with pixel values ​​of 6 and 2, which are equal to or less than the lower threshold of 7, so segmental unit U3b is detected as a detection unit. In other words, pixel B of segmental unit U3a and pixels A and B of segmental unit U3b are detected pixels.

[0103] Similarly, when continuity is taken into consideration, the pixel value order of the pixels in segmental unit U8b is, for example, 253 → 219 → 253 → 2 → 1 → 149 → 87 → 186. Among 253 → 219 → 253 → 2 → 1 → 149 → 87 → 186, there is a pixel with a pixel value of 253, which exceeds the upper threshold of 248, followed by successive pixels with pixel values ​​of 2 and 1, which are equal to or less than the lower threshold of 7, so segmental unit U3b is detected as a detection unit. In other words, pixels C and D of segmental unit U8a and pixel A of segmental unit U8b are detected as detection pixels.

[0104] Note that the detection units in the first detection mode in each frame N and N-1 also become detection units in the second detection mode. For example, the detection units in frame N-1 are added to the detection units in the first detection mode in frame N-1 with a detection unit in the second detection mode. Similarly, the detection units in frame N are added to the detection units in the first detection mode in frame N with a detection unit in the second detection mode.

[0105] Here, an example of detecting processing pixels will be described using FIGS. 21 to 24 . The processing range detection unit 412 has multiple modes for detecting processing pixels. FIG. 21 illustrates an example of detection in the first mode. In the first mode, the processing range detection unit 412 detects, as detection areas Du1 and Du2, areas where a number of detection units equal to or greater than a threshold value are consecutive from among adjacent detection units. For example, the threshold value is 3 or greater. The detection units within the detection areas Du1 and Du2 are detection processing units. That is, the detection pixels included in the detection processing units are selected as processing pixels. In this manner, areas where detection units are consecutive are areas where flicker is easily visible, and are therefore detected. Flicker suppression processing is performed on the detection processing units in such areas, suppressing the visibility of flicker while suppressing a decrease in contrast throughout the image. Note that the detection pixels in this embodiment correspond to pixels in any of the sub-images PA, PC, PB, and PD. Furthermore, the selected pixels from the detection pixels may also be referred to as processing pixels. That is, the flicker countermeasure processing unit 404 (see FIG. 12) changes the pixel value of the detected pixel or the pixel to be processed so as to reduce flicker.

[0106] FIG. 22 is a diagram showing an example of detection in the second mode. In the second mode, the processing range detection unit 412 detects, as a detection area Du3, an area in an area Ad within a predetermined range where a number of detection units equal to or greater than a threshold value are consecutive. For example, the area Ad is a 3x3 divisional range centered on the area itself. The threshold value within the area Ad is 5 or greater. The detection units within the detection area Du3 are detection processing units. That is, the detection pixels included in the detection processing units are selected as processing pixels. In this way, areas with consecutive detection units are detected because they are areas where flicker is easily visible. Flicker suppression processing is performed on the detection processing units in such areas, suppressing the visibility of flicker while suppressing a decrease in contrast throughout the image.

[0107] Furthermore, the processing range detection unit 412 has a plurality of thinning modes, which thin out areas within the detection area where flicker processing is not performed, thereby suppressing a decrease in overall contrast.

[0108] 23 is a diagram showing an example of the first thinning mode. In the first thinning mode, the processing range detection unit 412 selects every other column Lu1, Lu2, and Lu3 of the division unit in the detection area A23 that is not to be processed. This makes it possible to further suppress the reduction in overall contrast while suppressing flicker.

[0109] 24 is a diagram showing an example of the second thinning mode. In the second thinning mode, the processing range detection unit 412 selects unprocessed division units in a checkerboard pattern within the detection area A24. This makes it possible to further suppress the reduction in overall contrast while suppressing flicker.

[0110] 12 , the flicker countermeasure processing unit 404 executes processing to reduce the pixel value difference between pixels in the processing pixel detected by the processing range detection unit 412. For example, the flicker countermeasure processing unit 404 changes the value of the processing pixel to such an extent that the processing pixel does not fall within the detection rule of the processing range detection unit 412. For example, if the detection rule is that after detecting a pixel equal to or greater than the upper threshold of 248, there are two consecutive pixels equal to or less than the lower threshold of 7, the value of the pixel equal to or greater than the upper threshold of 248 is set to 247 or less, and the value of the two consecutive pixels equal to or less than the lower threshold of 7 is set to 8 or more. For example, the value of the pixel equal to or greater than the upper threshold of 248 is set to 223, and the value of the two consecutive pixels equal to or less than the lower threshold of 7 is set to 32. This suppresses visible flicker.

[0111] As described above, according to this embodiment, the processing range detection unit 412 detects detection pixels to be processed based on the display order of corresponding pixels in two or more sub-images PA, PC, PB, and PD and the pixel value differences between pixels in this display order, and the flicker countermeasure processing unit 404 executes processing to reduce the pixel value differences between corresponding pixels in the detection pixels. This makes it possible to suppress flicker based on the detection pixels. Furthermore, because the pixel value differences across the entire frame image PF are not reduced, it is possible to suppress a decrease in contrast across the entire displayed image. In this way, the visibility of flicker is suppressed while suppressing a decrease in contrast across the entire image.

[0112] Second Embodiment The display device 1 according to the first embodiment selects an area for performing flicker suppression processing for each frame, but the display device 1 according to the second embodiment differs from the display device 1 according to the first embodiment in that it selects frames for performing flicker suppression processing. The differences from the display device 1 according to the first embodiment will be described below.

[0113] Fig. 25 is a diagram showing the processing concept of the display device 1 according to the second embodiment. As shown in Fig. 25, the display device 1 according to the second embodiment performs flicker suppression processing on, for example, odd-numbered frame images PFn-1 and PFn+1 among frame images PFn (n is a natural number). Frame suppression processing is performed. In other words, the flicker countermeasure processing unit 404 does not perform flicker suppression processing on consecutive frame images PFn (n is a natural number) that fall in a predetermined order (in this example, odd-numbered frames).

[0114] FIG. 26 illustrates the processing performed by the flicker countermeasure processor 404 for the correction frame. (A) illustrates a case in which flicker suppression processing is not performed on the one-dot stripe pattern P12, and (B) illustrates a case in which flicker suppression processing is performed on odd-numbered frame images PFn-1 and PFn+1 of the one-dot stripe pattern P12. The flicker countermeasure processor 404 changes the pixel values ​​within the detection unit of the correction frame for which flicker suppression processing is performed. For example, pixel values ​​equal to or greater than the upper threshold value of 248 within the detection unit are set to 223, and pixel values ​​equal to or less than two consecutive lower threshold values ​​of 7 are set to 32. Note that the frame cycle, regularity, and processing frequency for performing flicker suppression processing are not limited to this example. In this way, the display device 1 according to the second embodiment is able to adjust the rate at which flicker suppression processing is performed over time.

[0115] (Third embodiment) The display device 1 according to the first embodiment performs flicker suppression processing on all of the sub-images PA, PC, PB, and PD, but the display device 1 according to the third embodiment differs from the display device 1 according to the first embodiment in that the sub-images PA, PC, PB, and PD on which the flicker suppression processing is performed are periodically changed. The differences from the display device 1 according to the first embodiment will be described below.

[0116] FIG. 27 illustrates the processing concept of the display device 1 according to the third embodiment. (A) illustrates a case where flicker suppression processing is not performed on the one-dot stripe pattern P12, and (B) illustrates a case where the sub-images PA, PC, PB, and PD on which flicker suppression processing is performed are periodically changed. As shown in FIG. 27 , the display device 1 according to the third embodiment differs from the display device 1 according to the first embodiment in that the sub-images PA, PC, PB, and PD on which flicker suppression processing is performed are periodically changed. For example, first, the flicker countermeasure processor 404 changes the pixel values ​​in the detection units of the sub-images PB and PC in the first frame. Next, the flicker countermeasure processor 404 changes the pixel values ​​in the detection units of the sub-images PA and PB in the second frame. Next, the flicker countermeasure processor 404 changes the pixel values ​​in the detection units of the sub-images PC and PD in the third frame. In this way, the flicker countermeasure processing unit 404 periodically changes the combination of two sub-images among the four sub-images PA, PC, PB, and PD, and reduces the pixel value difference between corresponding pixels of the detected pixels in these combinations of two sub-images.

[0117] As described above, the display device 1 according to the third embodiment can periodically change the sub-image on which the flicker suppression process is performed, thereby reducing the number of detected pixels on which the flicker suppression process is performed and dispersing the pixels over time.

[0118] (Fourth embodiment) The display device 1 according to the first embodiment selects an area for performing flicker suppression processing for each frame, but the display device 1 according to the fourth embodiment differs from the display device 1 according to the first embodiment in that it selects frames for performing flicker suppression processing according to the first embodiment. The differences from the display device 1 according to the first embodiment will be described below.

[0119] Fig. 28 is a diagram showing the processing concept of the display device 1 according to the fourth embodiment. As shown in Fig. 28, the display device 1 according to the fourth embodiment differs from the display device 1 according to the first embodiment in that the frame suppression processing according to the first embodiment is performed on odd-numbered frame images PFn-1 and PFn+1, for example, among frame images PFn (n is a natural number).

[0120] In this way, the display device 1 according to the fourth embodiment can distribute areas to which flicker suppression processing is applied or not applied in the time domain in addition to the spatial domain, thereby making it possible to adjust the rate at which flicker suppression processing is applied over time.

[0121] Fifth Embodiment A display device 1 according to a fifth embodiment differs from the display device 1 according to the first embodiment in that the flicker suppression processing is changed for each of a plurality of display areas. The differences from the display device 1 according to the first embodiment will be described below.

[0122] FIG. 29 is a diagram showing the processing concept of the display device 1 according to the fifth embodiment. As shown in FIG. 29, flicker processing within a selected image region G102a of the image signal G100 is differentiated from flicker processing within other regions. For example, flicker processing equivalent to that of the display device 1 according to the first embodiment is performed within the image region G102a at the center of the image within the image signal G100, while no flicker processing is performed on the other image regions. Alternatively, flicker suppression processing with a reduced processing load compared to the flicker suppression processing within the image region G102a is performed on the other image regions. This reduces the processing load and enables increased processing speed.

[0123] 30 is a diagram showing an example in which the selected image area G102B changes for each frame. As shown in Fig. 30, an area detected by gaze detection processing, an area of ​​specific content, etc. is set as image area G102b. This makes it possible to selectively perform flicker suppression processing on an area that is gazed at or an image area where flicker is likely to occur.

[0124] Sixth Embodiment A display device 1 according to a sixth embodiment differs from the display device 1 according to the first embodiment in that the display order of the sub-images PA, PC, PB, and PD is changed so as to suppress the occurrence of flicker. The differences from the display device 1 according to the first embodiment will be described below.

[0125] FIG. 31 is a diagram showing an example of the operation of the display device 1 according to the sixth embodiment. As shown in FIG. 31, an example of the operation of the display device 1 with a one-dot stripe pattern P12 is shown. (A) shows the frame period F. For example, at 60 Hz, it is 16.7 msec. (B) shows the subframe period SF. For example, at 60 Hz, the subframe period is 4.2 msec. (C) shows the potential and the display period. "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. In addition, in (C), the display period is depicted by a rectangular frame. In this example, the light source 11 continues to emit white light. (D) shows the sub-image being displayed. (E) shows the case where the display order is not changed, and (F) shows the case where the display order is changed.

[0126] As shown in FIG. 31E, when the pattern detection unit 402 of the flicker processing unit 400 detects that the image signal Spic has a typical pattern such as the one-dot stripe pattern P12, it causes the flicker countermeasure processing unit 404 to change the display order of the sub-images as shown in FIG. 31F. In this way, the flicker countermeasure processing unit 404 changes the display order of the sub-images PA, PB, PC, and PD to PA, PC, PB, and PD. This makes it possible to change, for example, flicker with a 120-Hz cycle to flicker with a 240-Hz cycle, thereby reducing the visibility of the flicker. Note that, although the sub-images PA, PC, PB, and PD are changed in the entire area of ​​the image signal Spic in this embodiment, this is not limiting. For example, the display order of the sub-images may be changed only in the region of interest.

[0127] Seventh Embodiment A display device 1 according to a seventh embodiment differs from the display device 1 according to the first embodiment in that the pixel value differences between the sub-images PA, PB, PC, and PD are changed so as to suppress the occurrence of flicker. The differences from the display device 1 according to the first embodiment will be described below.

[0128] FIG. 32 is a diagram showing an example of the operation of the display device 1 according to the seventh embodiment. As shown in FIG. 32, an example of the operation of the display device 1 with a one-dot stripe pattern P12 is shown. (A) shows the frame period F. For example, at 60 Hz, this is 16.7 msec. (B) shows the subframe period SF. For example, at 60 Hz, the subframe period is 4.2 msec. (C) shows the potential and the display period. "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. In addition, in (C), the display period is depicted by a rectangular frame. In this example, the light source 11 continues to emit white light. (D) shows the displayed sub-image. (E) shows the case where flicker suppression processing is not performed, and (F) shows the case where flicker suppression processing is performed.

[0129] As shown in FIG. 32E, when the pattern detection unit 402 of the flicker processing unit 400 detects that the image signal Spic is a typical pattern such as the one-dot stripe pattern P12, the flicker countermeasure processing unit 404 reduces the pixel value differences (gradation differences) among the sub-images PA, PB, PC, and PD as shown in FIG. 32F. In this manner, when the pattern detection unit 402 detects a typical pattern, the flicker countermeasure processing unit 404 reduces the pixel value differences among the sub-images PA, PB, PC, and PD. This reduces the visibility of flicker. Note that, although the sub-images PA, PB, PC, and PD are changed in the entire area of ​​the image signal Spic in this embodiment, this is not limiting. For example, the gradation differences of the sub-images may be changed only in the region of interest.

[0130] Eighth Embodiment A display device 1 according to an eighth embodiment differs from the display device 1 according to the first embodiment in that pixel values ​​within a detection unit are averaged. The differences from the display device 1 according to the first embodiment will be described below.

[0131] FIG. 33 is a diagram showing an example of the operation of the display device 1 according to the eighth embodiment. As shown in FIG. 33, an example of the operation of the display device 1 with a one-dot stripe pattern P12 is shown. (A) shows the frame period F. For example, at 60 Hz, it is 16.7 msec. (B) shows the subframe period SF. For example, at 60 Hz, the subframe period is 4.2 msec. (C) shows the potential and the display period. "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. In addition, in (C), the display period is depicted by a rectangular frame. In this example, the light source 11 continues to emit white light. (D) shows the sub-image being displayed. (E) shows an example of pixels in a detection unit detected by the processing range detection unit 412, and (F) shows an example of averaging pixel values ​​in a detection unit detected by the flicker countermeasure processing unit 404.

[0132] As shown in Fig. 33(E), when the pattern detection unit 402 of the flicker processing unit 400 detects that the image signal Spic has a typical pattern that causes flicker, the pattern detection unit 402 instructs the flicker countermeasure processing unit 404 to reduce the pixel value differences (tone differences) among the sub-images PA, PB, PC, and PD, as shown in Fig. 32(F). For example, the flicker countermeasure processing unit 404 executes processing to average the pixel values ​​of the detection units within the detection area detected by the processing range detection unit 412. This eliminates differences in pixel values ​​within the detection units, further suppressing visible flicker.

[0133] Ninth Embodiment A display device 1 according to a ninth embodiment differs from the display device 1 according to the first embodiment in that the pattern of the image signal is changed. The differences from the display device 1 according to the first embodiment will be described below.

[0134] FIG. 34 is a diagram showing an example of the operation of the display device 1 according to the ninth embodiment. As shown in FIG. 34, an example of the operation of the display device 1 with a one-dot stripe pattern P12 is shown. (A) shows the frame period F. For example, at 60 Hz, it is 16.7 msec. (B) shows the subframe period SF. For example, at 60 Hz, the subframe period is 4.2 msec. (C) shows the potential and the display period. "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. In addition, in (C), the display period is depicted by a rectangular frame. In this example, the light source 11 continues to emit white light. (D) shows the sub-image being displayed. (E) shows the sub-images PA, PB, PC, and PD of the 1-dot stripe pattern P12, (F) shows the first two rows of sub-images PA, PB, PC, and PD of the 2-dot stripe pattern P20, and (G) shows the next two rows of sub-images PA, PB, PC, and PD of the 2-dot stripe pattern P20.

[0135] As shown in FIG. 34(E), the one-dot stripe pattern P12 generates flicker with a period of 120 Hz. In contrast, as shown in FIGS. 34(F) and (G), the two-dot stripe pattern P20 does not generate flicker. Therefore, in the display device 1 according to the ninth embodiment, when the pattern detection unit 402 of the flicker processing unit 400 detects that the image signal Spic is a typical pattern that generates flicker, as shown in FIG. 34(E), the flicker countermeasure processing unit 404 changes the pixel values ​​of the sub-images PA, PB, PC, and PD to reduce the pixel value difference (gradation difference), as shown in FIGS. 32(F) and (G). In this way, the flicker countermeasure processing unit 404 converts the image signal of the one-dot stripe pattern P12 into an image signal of the two-dot stripe pattern P20 and outputs it. This makes it possible to suppress flicker while maintaining the geometric characteristics of the input image, which is a stripe pattern.

[0136] (Tenth embodiment) The display device 1 according to the tenth embodiment differs from the display device 1 according to the first embodiment in that the shift direction of the light shift device 32 is shifted in a direction that minimizes the occurrence of flicker. The differences from the display device 1 according to the first embodiment will be described below.

[0137] 35 to 38, a processing example of the display device 1 according to the tenth embodiment will be described. FIG. 35 is a diagram showing an example of changing the shift direction of the light shift device 32 across the entire image. The pattern detection unit 402 analyzes the image signal Spic and determines the shift direction of the light shift device 32. In accordance with this, the flicker countermeasure processing unit 404 changes the output order of the sub-images PA, PB, PC, and PD. This makes it possible to suppress the occurrence of flicker across the entire image.

[0138] FIG. 36 shows an example of the operation of the display device 1 with a one-dot stripe pattern P12 and a one-dot checkerboard pattern P14. (A) shows the frame period F. For example, at 60 Hz, it is 16.7 msec. (B) shows the sub-frame period SF. For example, at 60 Hz, the sub-frame period is 4.2 msec. (C) shows the potential and the display period. "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. In addition, in (C), the display period is depicted by a square frame. In this example, the light source 11 continues to emit white light. (D) shows the sub-image to be displayed. (E) shows the display order of the sub-images PA, PB, PC, and PD of the dot stripe pattern P12, (F) shows the display order of the sub-images PA, PC, PB, and PD of the dot stripe pattern P12, (G) shows the display order of the sub-images PA, PB, PC, and PD of the one-dot checkerboard pattern P14, and (H) shows the display order of the sub-images PA, PC, PB, and PD of the one-dot checkerboard pattern P14.

[0139] As shown in Fig. 36(E), in the one-dot stripe pattern P12, the flicker occurs in a cycle of 120 Hz when the sub-images PA, PB, PC, and PD are displayed in that order. On the other hand, as shown in Fig. 36(F), the flicker occurs in a cycle of 240 Hz when the sub-images PA, PC, PB, and PD are displayed in that order. Therefore, the flicker countermeasure processor 404 selects the display order of the sub-images PA, PC, PB, and PD.

[0140] 36(G), in the one-dot checkerboard pattern P14, the flicker occurs in a cycle of 240 Hz when the sub-images PA, PB, PC, and PD are displayed in that order. On the other hand, as shown in FIG. 36(H), the flicker occurs in a cycle of 120 Hz when the sub-images PA, PC, PB, and PD are displayed in that order. Therefore, the flicker countermeasure processing unit 404 selects the display order PA, PB, PC, and PD.

[0141] 37 is a diagram showing an example of changing the shift direction of the light shift device 32 in the central image area G102c where the line of sight is focused. The pattern detection unit 402 analyzes the image signal Spic of the image area G102c and determines the shift direction of the light shift device 32. In accordance with this, the flicker countermeasure processing unit 404 changes the output order of the sub-images PA, PB, PC, and PD. This makes it possible to suppress the occurrence of flicker in the image area G102c.

[0142] 38 is a diagram showing an example of dynamically changing the shift direction of the light shift device 32 in the image area G102d. The pattern detection unit 402 analyzes the image signal Spic of the image area G102d and determines the shift direction of the light shift device 32. The image area G102d is, for example, an image area determined by eye tracking, or an area where specific content is displayed. Accordingly, the flicker countermeasure processing unit 404 changes the output order of the sub-images PA, PC, PB, and PD. This makes it possible to suppress the occurrence of flicker in the image area G102d.

[0143] Eleventh Embodiment The display device 1 according to the eleventh embodiment differs from the display device 1 according to the first embodiment in that the display frequency is increased when the number of detection units exceeds a predetermined number. The differences from the display device 1 according to the first embodiment will be described below.

[0144] FIG. 39 is a diagram showing an example of the operation of the display device 1 according to the eleventh embodiment. (A) shows the frame period F. For example, at 30 Hz, it is 33.4 msec. (B) shows the subframe period SF. For example, at quadruple speed (240 Hz), the subframe period is 4.2 msec. (C) shows the potential and the display period. "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. In addition, in (C), the display period is depicted by a square frame. In this example, the light source 11 continues to emit white light. (D) shows the cycle of the displayed sub-image.

[0145] (E) indicates the frame period F. For example, in the case of 30 Hz, it is 33.4 msec. (F) indicates the subframe period SF. For example, in the case of quadruple speed (240 Hz), the subframe period is 4.2 msec, and in the case of eight times speed (480 Hz), it is 2.1 msec. (G) indicates the potential and the display period. "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. In addition, in (G), the display period is depicted by a square frame. In this example, the light source 11 continues to emit white light. (H) indicates the cycle of the displayed sub-image.

[0146] As shown in Figure 39, when the number of detection units exceeds a predetermined number during normal driving as shown in (A) to (D), the flicker countermeasure processor 404 increases the frame rate of the frames exceeding the predetermined number, as shown in the latter half of (E) to (H). For example, because flicker becomes less visible as the drive frequency, i.e., display frequency, increases, the flicker countermeasure processor 404 increases the refresh rate when certain conditions are met, such as when the detection area, which is the area of ​​the detection units, exceeds a certain number. In this case, the flicker countermeasure processor 404 can increase the refresh rate and display using technology such as VRR (variable refresh rate). On the other hand, when there is little flicker detection, lowering the refresh rate can also reduce power consumption.

[0147] (Twelfth embodiment) The display device 1 according to the twelfth embodiment differs from the display device 1 according to the first embodiment in that the display order of each layer is shifted so as to minimize the occurrence of flicker in the detection area while maintaining the shift direction of the light shift device 32. The differences from the display device 1 according to the first embodiment will be described below.

[0148] As described above, flicker occurs when the grayscale difference after phase expansion is large. In this case, as the period of the phase with a large grayscale difference becomes slower, the visibility of the flicker increases due to the human visual characteristics. For the same reason, as the driving frequency of the light shift device 32 in the shift direction becomes slower, the visibility of the flicker increases.

[0149] Furthermore, the visibility of flicker increases as the number of detection units increases. Furthermore, the visibility of flicker increases as the brightness of the light shift device 32 (see FIG. 1) increases. On the other hand, if the flicker suppression process is performed on the entire image, the resolution of the entire image will decrease. For this reason, an example will be described below in which the flicker suppression process is performed on the detection area while maintaining the shift direction of the light shift device 32. This makes it possible to perform the flicker suppression process while suppressing a decrease in the overall resolution.

[0150] An example of processing by the display device 1 according to the twelfth embodiment will be described using Fig. 40 and Fig. 41. Fig. 40 is a diagram showing an example of rearrangement of pixels within a division unit of a frame image. As shown in Fig. 40, in the display device 1 according to the twelfth embodiment, the arrangement of pixels within a division unit in the detection area A40a is changed, for example, from the order A, B, C, D to the order A, C, B, D.

[0151] Therefore, before the arrangement of the pixels A, B, C, and D is changed, the pixels in the division unit in the detection area A40a are displayed in the order of pixels A, B, C, and D. On the other hand, after the arrangement of the pixels A, B, C, and D is changed to pixels A, C, B, and D, the pixels are displayed in the order of pixels A, C, B, and D while maintaining the shift direction of the light shift device 32.

[0152] More specifically, the processing range detection unit 412 (see FIG. 13) according to this embodiment detects segmental units to be processed in the first mode (see FIG. 21) or the second mode (see FIG. 21). Furthermore, the processing range detection unit 412 (see FIG. 13) detects a detection area A40a, which is an area where segmental units to be processed are consecutive. In other words, the detection area A40a according to this embodiment is, for example, an area where a predetermined number or more of segmental units are consecutive.

[0153] The pattern detection unit 402 (see FIG. 13 ) according to this embodiment analyzes the image signal Spic and determines the output order of the sub-images PA, PB, PC, and PD in the detection area A40a so as to suppress flicker. Accordingly, the flicker countermeasure processing unit 404 changes the arrangement of pixels A, B, C, and D in the detection area A40a to, for example, pixels A, C, B, and D. This is equivalent to swapping the pixel value of pixel B with the pixel value of pixel C.

[0154] In this way, when the display order of the sub-images PA, PB, PC, and PD in the detection area A40a is changed to the output order of the sub-images PA, PC, PB, and PD, the pixel values ​​in the detection area A40a of the sub-images PC and PB are swapped. In other words, by swapping the pixel values ​​in the detection areas of the sub-images PA, PB, PC, and PD with each other, the display order of the pixels in the detection area A40a is changed while maintaining the shift direction of the light shift device 32.

[0155] FIG. 41 shows an example of the operation of the display device 1 when the detection area A40a has a one-dot stripe pattern P12. (A) shows the frame period F. For example, at 60 Hz, it is 16.7 msec. (B) shows the subframe period SF. For example, at 60 Hz, the subframe period is 4.2 msec. (C) shows the potential and the display period. A "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and a "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. In addition, in (C), the display period is depicted by a rectangular frame. In this example, the light source 11 continues to emit white light. (D) shows the output order of the sub-images PA, PB, PC, and PD. (E) shows the display order of the sub-images PA, PB, PC, and PD of the dot stripe pattern P12 in the detection area, and (F) shows the output order of the sub-images PA, PC, PB, and PD after the pixel values ​​of the sub-images PC and PB in the detection area A40a are swapped. In other words, while maintaining the mechanical shift order of the light shift device 32 (see FIG. 1), the display order in the detection area A40a is equivalent to changing the display order of the sub-images PA, PB, PC, and PD to the display order of the sub-images PA, PC, PB, and PD. (G) shows the display order of the sub-images PA, PC, PB, and PD in the detection area of ​​the dot stripe pattern P12.

[0156] As shown in Fig. 41(E), in the one-dot stripe pattern P12, the display order of the sub-images PA, PB, PC, and PD results in a flicker cycle of 120 Hz. On the other hand, as shown in Fig. 41(G), the display order of the sub-images PA, PC, PB, and PD in the detection area results in a flicker cycle of 240 Hz, so the flicker countermeasure processing unit 404 selects the display order of the sub-images PA, PC, PB, and PD. In this way, by changing the arrangement order of the pixels in the detection area A40a while maintaining the mechanical shift order of the light shift device 32 (see Fig. 1), it is possible to change the display order of the pixels in the detection area A40a and suppress flicker.

[0157] Furthermore, an example of swapping pixel values ​​within division units within the detection area A40a between two sub-images in the display order of the sub-images PA, PB, PC, and PD is sometimes referred to as cross-over. Changing the display order of the sub-images PA, PB, PC, and PD within the detection area, i.e., swapping pixel values ​​within division units within the detection area A40a between the sub-images, is performed, for example, to minimize flicker suppression. For example, pixel values ​​within division units within the detection area A40a are changed so that the display order of the sub-images PA, PB, PC, and PD within the detection area is randomized. Alternatively, the display order of the sub-images PA, PB, PC, and PD within the detection area can be reversed, such as PD, PC, PB, and PA. Furthermore, the process itself for the detection units within the detection area, such as cross-over, reverse order, or random order, may be randomly changed. This process makes it possible to suppress flicker in the detection area while maintaining the resolution of the area outside the detection area.

[0158] (Thirteenth embodiment) The display device 1 according to the thirteenth embodiment differs from the display device 1 according to the first embodiment in that the display device 1 according to the thirteenth embodiment suppresses the increase in resolution in the suppression area A42 while maintaining the shift direction of the light shift device 32. The differences from the display device 1 according to the first embodiment will be described below.

[0159] An example of processing of the display device 1 according to the twelfth embodiment will be described using FIGS. 42 and 43. FIG. 42 is a diagram showing an example of detecting a suppression region A42 from an image G42. The pattern detection unit 402 analyzes the image signal Spic and detects, for example, a character region as the suppression region A42. For example, a character region is a region where characters appear blurred due to flicker when the light shift device 32 is shifted. In this way, the pattern detection unit 402 detects a suppression region A42 where image visibility is maintained better without increasing the resolution than with increasing the resolution. Note that, although a character region is detected as the suppression region A42 in this embodiment, this is not limiting. For example, a linear figure, a pattern region, or the like may be detected as the suppression region A42.

[0160] In this way, the pattern detection unit 402 analyzes the image signal Spic and determines the suppression area A42. In response to this, the flicker countermeasure processing unit 404 changes the pixel values ​​of the sub-images PA, PB, PC, and PD in the suppression area A42. For example, the pixel values ​​of the sub-images PA, PB, PC, and PD in the suppression area A42 are set to the same value.

[0161] In this case, the flicker countermeasure processing unit 404 selects one of the pixel values ​​of the sub-images PA, PB, PC, and PD in the suppression area A42. For example, the pixel value of the sub-image PA in the suppression area A42 is selected, and the pixel values ​​of the sub-images PB, PC, and PD in the suppression area A42 are set as the pixel values ​​of the sub-image PA. Alternatively, the flicker countermeasure processing unit 404 sets the average value of the pixel values ​​of the sub-images PA, PB, PC, and PD in the suppression area A42 as the pixel values ​​of the sub-images PB, PC, and PD in the suppression area A42. As can be seen from this, if the pixel values ​​of the sub-images PA, PB, PC, and PD in the suppression area A42 are set to the same value, flicker will not occur.

[0162] Alternatively, the flicker countermeasure processing unit 404 selects a combination of two of the sub-images PA, PB, PC, and PD within the suppression area A42, and sets the average values ​​of the selected pixel values ​​as the pixel values ​​of the sub-images PA, PB, PC, and PD within the suppression area A42. For example, the average value of the sub-images PA and PB within the suppression area A42 is set as the pixel value of the sub-images PA and PB within the suppression area A42. Similarly, for example, the average value of the sub-images PC and PD within the suppression area A42 is set as the pixel value of the sub-images PC and PD within the suppression area A42.

[0163] FIG. 43 shows an example of the operation of the display device 1 within the suppression region A42. (A) shows the frame period F. For example, at 60 Hz, it is 16.7 msec. (B) shows the subframe period SF. For example, at 60 Hz, the subframe period is 4.2 msec. (C) shows the potential and the display period. A "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and a "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. Also, in (C), the subimages PA, PB, PC, and PD are displayed in sequence, and the display periods are depicted by rectangular frames. In this example, the light source 11 continues to emit white light.

[0164] In (D), the same pixel values ​​as in sub-image PA are displayed in order, and the display period is depicted by a rectangular frame. In (E), the four-pixel average values ​​of sub-images PA, PB, PC, and PD are displayed in order, and the display period is depicted by a rectangular frame. In (F), the two-pixel average values ​​of sub-images PA and PB are displayed in order as the first two sub-images, and the two-pixel average values ​​of sub-images PC and PD are displayed in order as the second two sub-images, and the display period is depicted by a rectangular frame.

[0165] In this way, by assigning the same value to at least two of the sub-images PA, PB, PC, and PD within the suppression area A42, the increase in resolution is suppressed and the occurrence of flicker is also suppressed. Also, by assigning the same value to the sub-images PA, PB, PC, and PD within the suppression area A42, the increase in resolution is stopped and the occurrence of flicker is also stopped. On the other hand, outside the suppression area A42, normal resolution can be maintained.

[0166] (Fourteenth embodiment) The display device 1 according to the fourteenth embodiment differs from the display device 1 according to the first embodiment in that the shift direction of the light shift device 32 is periodically changed according to the image. The differences from the display device 1 according to the first embodiment will be described below.

[0167] As described above, the flicker processing unit 400 (see FIG. 1 ) generates the image signals SpicR, SpicG, and SpicB that have been subjected to the flicker suppression process, and the control signal CTL corresponding to the image signals SpicR, SpicG, and SpicB. The display control unit 380 controls the display operation of the display device 1 by supplying the control signal CTL corresponding to the image signals SpicR, SpicG, and SpicB to the light shift device 32. At this time, the flicker processing unit 400 can generate the control signal CTL that periodically changes the shift direction of the light shift device 32 in accordance with the image.

[0168] 44 is a diagram showing an example in which different control signals CTL are generated for even and odd frames. For example, in even frames, the sub-images PA, PB, PC, and PD are displayed in this order, and in odd frames, the sub-images PA, PC, PB, and PD are displayed in this order. This makes it possible to more efficiently suppress flicker for each frame.

[0169] 45 shows an example in which different control signals CTL for two-phase display are generated for even and odd frames. For example, in even frames, sub-images PA and PC are displayed in that order, and in odd frames, sub-images PB and PD are displayed in that order. This makes it possible to more efficiently suppress flicker for each frame even in the case of display using one-axis (two-phase) shift.

[0170] FIG. 46 shows an example of generating a control signal CTL that causes one out of every ten frames to be unshifted. For example, in frames 1 through 9, the sub-images PA, PB, PC, and PD are displayed in this order, and in frame 10, the sub-image PA is displayed without shifting. This allows for a suppression region, and even when the light shift device 32 is stopped, flicker can be more efficiently suppressed for each frame. Note that the shift order selected in each example is periodic, but is not limited to this. That is, each process may be dynamically changed in accordance with the frame image. Furthermore, the order and combination can be periodically changed to more efficiently suppress flicker. In this way, by configuring the shift direction of the light shift device 32 to be changeable for each frame, flicker can be more efficiently suppressed.

[0171] Fifteenth Embodiment A display device 1 according to a fifteenth embodiment differs from the display device 1 according to the first embodiment in that the duty, which is the ratio between the light emission period and the light emission stop period of the light source 11, is changed according to the image. The differences from the display device 1 according to the first embodiment will be described below.

[0172] As described above, the flicker processing unit 400 (see FIG. 1) generates the image signals SpicR, SpicG, and SpicB that have been subjected to flicker suppression processing, and the control signal CTL corresponding to the image signals SpicR, SpicG, and SpicB. Furthermore, the flicker processing unit 400 generates the control signal CTL2 corresponding to the image signals SpicR, SpicG, and SpicB.

[0173] The control signal CTL2 is a signal that turns on and off the light source 11 in response to the image signals SpicR, SpicG, and SpicB, thereby enabling the light source 11 to repeatedly emit light and not emit light in response to the image signals SpicR, SpicG, and SpicB.

[0174] FIG. 47 shows an example of the light-emitting operation of the display device 1 when the detection region is a one-dot stripe pattern P12. (A) shows the frame period F. For example, at 60 Hz, it is 16.7 msec. (B) shows the sub-frame period SF. For example, at 60 Hz, the sub-frame period is 4.2 msec. (C) shows the potential and the display period. "+" indicates that a positive pixel voltage Vpix is ​​written to the pixel P, and "-" indicates that a negative pixel voltage Vpix is ​​written to the pixel P. In addition, in (C), the display period is depicted by a square frame. In this example, the light source 11 continues to emit white light. (D) shows the sub-image being displayed. (E) shows the display order of the sub-images PA, PB, PC, and PD of the dot stripe pattern P12 within the detection area, and (F) shows the ON signal (high level signal) and OFF signal (low level signal) of the control signal CTL2. The light source 11 emits light when the ON signal (high level signal) is received. On the other hand, the light source 11 does not emit light when the OFF signal (low level signal) is received.

[0175] As shown in Figure 47(E), in the one-dot stripe pattern P12, flicker occurs in the display order of sub-images PA, PB, PC, and PD, with a period of 120 Hz. In this case, as shown in Figure 47(F), the pixel values ​​of sub-images PC and PD exceed the upper threshold of 248. In such a case, for example, the non-emission period t47 of the light source 11 is made longer than the non-emission period t46. This makes the luminance of the sub-images PC and PD appear visually equivalent to a pixel value of less than 248, thereby suppressing the perceived flicker.

[0176] In this way, the non-emission period t47 of the light source 11 is lengthened according to the pixel values ​​of the sub-images PA, PB, PC, and PD, thereby making it possible to reduce the gradation difference while maintaining the pixel values ​​among the sub-images PA, PC, PB, and PD, thereby suppressing flicker.

[0177] Sixteenth Embodiment The display device 1 according to the sixteenth embodiment differs from the display devices 1 according to the first to fifteenth embodiments in that the display device 1 according to the sixteenth embodiment arbitrarily selects frames for performing the flicker suppression processing according to the first to fifteenth embodiments. The differences from the display devices 1 according to the first to fourteenth embodiments will be described below.

[0178] Fig. 48 is a diagram showing the processing concept of the display device 1 according to the 16th embodiment. As shown in Fig. 47, the display device 1 according to the 16th embodiment selectively performs any of the flicker suppression processes according to the first to 15th embodiments on each frame image PFn (n is a natural number).

[0179] In this way, the display device 1 according to the sixteenth embodiment distributes areas to which the flicker suppression process is applied and areas to which it is not applied in the time direction in addition to the spatial domain. Furthermore, as described in the thirteenth embodiment, it is possible to mix pattern processing, which shifts the display order of each layer so as to minimize the occurrence of flicker in the detection area while maintaining the shift direction of the light shift device 32, and suppression processing, which suppresses the increase in resolution in the suppression area A42, as described in the fourteenth embodiment. This makes it possible to adjust the rate at which the flicker suppression process is applied in terms of space, time, and pattern.

[0180] The present technology can be configured as follows:

[0181] (1) An information processing device capable of generating sub-images to be displayed sequentially, comprising: a first processing unit capable of generating, based on a frame image, two or more sub-images out of a plurality of sub-images each having a plurality of pixel values ​​arranged in a predetermined arrangement pattern in the frame image; a detection unit that detects a detection pixel to be processed based on the coordinates of the frame image, based on the display order of corresponding pixels in the two or more sub-images and the pixel value difference between pixels in the display order; and a second processing unit that performs processing to reduce the pixel value difference between corresponding pixels in the detection pixel.

[0182] (2) The information processing device according to (1), wherein the detection unit detects a processing pixel from detection pixels in a detection area based on a detection area having a predetermined number or more of adjacent detection pixels, and the second processing unit reduces a pixel value difference between corresponding pixels in the processing pixels.

[0183] (3) The information processing device according to (1) or (2), wherein the detection unit detects a processing pixel based on a detection region in which a predetermined number or more of detection pixels are adjacent within a predetermined range of the frame image.

[0184] (4) The information processing device according to (2) or (3), wherein the detection unit thins out the detection pixels from the detection region and detects the thinned pixels as the processing pixels.

[0185] (5) The information processing device according to (4), wherein the detection unit thins out the detection pixels from within the detection region based on columns or rows of the sub-image and detects the thinned pixels as the processing pixels.

[0186] (6) The information processing device according to (4), wherein the detection unit thins out the detection pixels from the detection region based on a checkerboard pixel arrangement and detects the thinned pixels as the processing pixels.

[0187] (7) The information processing device described in any one of (1) to (6), wherein the first processing unit further generates two or more second sub-images from a plurality of sub-images each having a plurality of pixel values ​​arranged in the predetermined arrangement pattern in the second frame image based on a second frame image different from the frame image, and the detection unit detects a detection pixel to be processed based on the two or more sub-images, a second display order of corresponding pixels in the two or more second sub-images, and a pixel value difference between pixels in the second display order.

[0188] (8) The information processing device according to any one of (1) to (7), wherein the detection unit detects each of the corresponding pixels in the detection pixel as a detection pixel when one of the corresponding pixels in the detection pixel has a pixel value equal to or greater than a first upper limit value and a pixel to be displayed next has a pixel value equal to or less than a second lower limit value.

[0189] (9) The information processing device according to any one of (1) to (8), wherein the second processing unit does not execute the processing when the frame image corresponds to a predetermined order among consecutive frame images.

[0190] (10) The information processing device according to any one of (1) to (9), wherein the first processing unit generates four sub-images from the plurality of sub-images, and the second processing unit periodically changes a combination of two sub-images from the four sub-images to reduce a pixel value difference between corresponding pixels of the detection pixel in the combination of the two sub-images.

[0191] (11) The information processing device according to any one of (1) to (10), wherein the second processing unit reduces a pixel value difference between corresponding pixels of the detection pixel within a predetermined region in the sub-image.

[0192] (12) The information processing device according to (11), wherein the predetermined area is changed in accordance with an input frame image.

[0193] (13) The information processing device according to any one of (1) to (12), wherein the second processing unit changes a display order of the pixels so as to reduce a pixel value difference between corresponding pixels in the detection pixels.

[0194] (14) The information processing device according to (7), wherein the second processing unit reduces a pixel value difference between pixels in a display order of corresponding pixels of the two or more sub-images and the two or more second sub-images.

[0195] (15) The information processing device according to (7), wherein the second processing unit averages pixel values ​​between pixels in a display order of corresponding pixels of the two or more sub-images and the two or more second sub-images.

[0196] (16) The information processing device according to any one of (1) to (15), wherein the second processing unit changes the frame image to an image in which the number of the detected pixels is reduced.

[0197] (17) The information processing device according to any one of (1) to (16), wherein the second processing unit changes a display order of the pixels so that the number of the detected pixels in the frame image is reduced.

[0198] (18) The information processing device according to any one of (1) to (17), wherein the second processing unit changes a display order of the pixels so that the number of the detected pixels in a predetermined area in the frame image is reduced.

[0199] (19) The information processing device according to any one of (1) to (18), wherein the second processing unit changes a display order of the pixels so that the number of the detected pixels in the frame image is reduced.

[0200] (20) A display device comprising: an information processing device capable of generating sub-images to be displayed in sequence; and a projection device; wherein the information processing device comprises: a first processing unit capable of generating, based on a frame image, two or more sub-images out of a plurality of sub-images, each sub-image having a plurality of pixel values ​​arranged in a predetermined arrangement pattern in the frame image; a detection unit that detects a detection pixel to be processed in the frame image based on the display order of corresponding pixels of the two or more sub-images and the pixel value difference between pixels in the display order; and a second processing unit that executes processing to reduce the pixel value difference between corresponding pixels in the detection pixel; and the projection device comprises: a first optical system including a light source capable of emitting light; a liquid crystal light valve having a plurality of pixels and capable of generating image light by modulating light from the first optical system based on each of the two or more sub-images; a light shifting device capable of shifting the image light in an in-plane direction of the image depending on which of the plurality of sub-images the image light belongs to; and a second optical system that can project the image light processed by the light shifting device.

[0201] (21) An information processing device that generates multiple sub-images that are displayed in a predetermined order while their display positions are changed based on a frame image in which divisional units having multiple pixels are arranged in a matrix, comprising: a first processing unit that generates the multiple sub-images arranged in the matrix order for each pixel selected from the divisional unit according to a predetermined rule; a detection unit that detects the divisional unit to be processed; and a second processing unit that changes the pixel values ​​of pixels corresponding to the divisional unit to be processed based on the predetermined order so as to reduce flicker, which is a repetition of high brightness and low brightness.

[0202] (22) The information processing device according to (21), wherein the second processing unit swaps pixel values ​​of pixels corresponding to the division units among the plurality of sub-images so as to reduce flicker, which is a repetition of high brightness and low brightness, when the pixels of the division units to be processed are displayed in the predetermined order.

[0203] (23) The information processing device according to (21) or (22), wherein the second processing unit swaps pixel values ​​of pixels corresponding to the division units among the plurality of sub-images so that a repetition period of the high luminance and the low luminance increases when the pixels of the division units to be processed are displayed in the predetermined order.

[0204] (24) The information processing device according to any one of (21) to (24), wherein the second processing unit randomly switches between the plurality of sub-images so that a repetition period of the high luminance and the low luminance increases when the pixels of the division unit to be processed are displayed in the predetermined order.

[0205] (25) The information processing device according to any one of (21) to (24), wherein the detection unit detects a division unit to be processed based on a display order of corresponding pixels of the plurality of sub-images and a pixel value difference between pixels in the display order.

[0206] (26) The information processing device according to any one of (21) to (24), wherein the detection unit detects a division unit to be processed based on an area having a predetermined display form in the frame image.

[0207] (27) The information processing device according to (26), wherein the predetermined display form is at least one of a character and a pattern.

[0208] (28) The information processing device according to any one of (21) to (27), wherein the second processing unit changes pixel values ​​of pixels corresponding to the division unit to be processed so as to reduce pixel value differences among the plurality of sub-images.

[0209] (29) The information processing device according to (26), wherein the second processing unit changes a pixel value of a pixel corresponding to the divisional unit to be processed to an average value of pixels corresponding to the divisional unit.

[0210] (30) The information processing device according to any one of (21) to (29), wherein four adjacent pixels are arranged in the division unit, and the first processing unit generates four sub-images by allocating the four adjacent pixels in a predetermined order.

[0211] (31) The information processing device according to any one of (21) to (30), wherein four adjacent pixels are arranged in the division unit, and the first processing unit generates two sub-images by allocating two pixels of the four adjacent pixels in a predetermined order.

[0212] (32) A display device comprising: an information processing device that generates a plurality of sub-images that are displayed in a predetermined order while changing their display positions based on a frame image in which divisional units each having a plurality of pixels are arranged in a matrix; and a projection device; wherein the information processing device comprises: a first processing unit that generates the plurality of sub-images arranged for each pixel selected from each divisional unit of the frame image according to a predetermined rule in accordance with the matrix arrangement order of the divisional units; and a second processing unit that generates a display period control signal that indicates a display period corresponding to the plurality of sub-images; and the projection device comprises: a first optical system including a light source that can emit light; a liquid crystal light valve that has a plurality of pixels and is capable of generating image light during the display period by modulating light from the first optical system based on each of the plurality of sub-images and the display period control signal; a light shifting device that can shift the image light in an in-plane direction of the image depending on which of the plurality of sub-images the image light belongs to; and a second optical system that can project the image light processed by the light shifting device.

[0213] (33) The display device according to (32), wherein the information processing device further includes a detection unit that detects a division unit to be processed, and the second processing unit changes the pixel value of a pixel corresponding to the division unit to be processed so as to reduce flicker, which is a repetition of high brightness and low brightness.

[0214] (34) The display device according to (32) or (33), wherein the frame images are supplied to the information processing device in accordance with a display order, and the second processing unit changes processing content of the second processing unit based on the display order.

[0215] (35) The display device according to any one of (32) to (34), wherein the light shift device changes at least one of a shift direction and a shift order in the in-plane direction in accordance with the frame image.

[0216] (36) The display device according to any one of (32) to (35), wherein a display order of the plurality of sub-images is changed depending on the frame image.

[0217] (37) The information processing device according to (12), wherein the predetermined area is changed depending on an input frame image.

[0218] (38) The information processing device according to (1), wherein the predetermined area increases the number of sub-images to be displayed in the same period when the number of the detected pixels exceeds a predetermined number.

[0219] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0220] 1: Display device, 2: Information processing device, 3: Projection device, 11: Light source, 12: Condenser lens, 13, 15: Dichroic mirror, 14: Total reflection mirror, 16, 17: Total reflection mirror, 18R, 18G, 18B: Field lenses, 20R, 20G, 20B: Liquid crystal light valves, 390: Image processing unit (first processing unit), 400: Flicker processing unit, 402: Pattern detection unit (detection unit), 404: Flicker countermeasure processing unit (second processing unit)

Claims

1. An information processing device capable of generating sub-images to be displayed in sequence, comprising: a first processing unit capable of generating two or more of a plurality of sub-images based on a frame image, each sub-image having a plurality of pixel values ​​arranged in a predetermined arrangement pattern in the frame image; a detection unit that detects a detection pixel to be processed based on the coordinates of the frame image, based on the display order of corresponding pixels of the two or more sub-images and the pixel value difference between pixels in the display order; and a second processing unit that performs processing to reduce the pixel value difference between corresponding pixels in the detection pixel.

2. The information processing device according to claim 1, wherein the detection unit detects a processing pixel from detection pixels in a detection area based on a detection area having a predetermined number or more of adjacent detection pixels, and the second processing unit reduces a pixel value difference between corresponding pixels in the processing pixels.

3. The information processing device according to claim 1, wherein the detection section detects a processing pixel based on a detection region having a predetermined number or more of adjacent detection pixels within a predetermined range of the frame image.

4. The information processing device according to claim 2, wherein the detection section thins out the detection pixels from within the detection region and detects them as the processing pixels.

5. An information processing device as described in claim 1, wherein the detection unit detects each of the detection pixels as a detection pixel when one of the corresponding pixels in the detection pixel has a pixel value equal to or greater than a first upper limit value and the next pixel to be displayed has a pixel value equal to or less than a second lower limit value.

6. The information processing device according to claim 1, wherein the second processing unit reduces a pixel value difference between corresponding pixels of the detection pixels within a predetermined region of the sub-image.

7. The information processing device according to claim 5, wherein the predetermined area is changed according to an input frame image.

8. The information processing device of claim 1, wherein the first processing unit further generates two or more second sub-images among a plurality of sub-images each having a plurality of pixel values ​​arranged in the predetermined arrangement pattern in the second frame image based on a second frame image different from the frame image, and the second processing unit reduces the pixel value difference between pixels in the display order of corresponding pixels of the two or more sub-images and the two or more second sub-images.

9. The information processing device according to claim 1, wherein the second processing section changes a display order of the pixels so as to reduce the number of the detected pixels in the frame image.

10. A display device comprising: an information processing device capable of generating sub-images to be displayed in sequence; and a projection device; wherein the information processing device comprises: a first processing unit capable of generating, based on a frame image, two or more of a plurality of sub-images, each of which has a plurality of pixel values ​​arranged in a predetermined arrangement pattern in the frame image; a detection unit that detects a detection pixel to be processed in the frame image based on a display order of corresponding pixels of the two or more sub-images and a pixel value difference between pixels in the display order; and a second processing unit that executes a process to reduce the pixel value difference between corresponding pixels in the detection pixel; and wherein the projection device comprises: a first optical system including a light source capable of emitting light; a liquid crystal light valve having a plurality of pixels and capable of generating image light by modulating light from the first optical system based on each of the two or more sub-images; a light shifting device capable of shifting the image light in an in-plane direction of the image depending on which of the plurality of sub-images the image light corresponds to; and a second optical system capable of projecting the image light processed by the light shifting device.

11. An information processing device that generates a plurality of sub-images that are displayed in a predetermined order while changing the display position based on a frame image in which divisional units having a plurality of pixels are arranged in a matrix, the information processing device comprising: a first processing unit that generates the plurality of sub-images arranged according to the arrangement order of the matrix for each pixel selected from the divisional unit according to a predetermined rule; a detection unit that detects the divisional unit to be processed; and a second processing unit that changes the pixel value of the pixel corresponding to the divisional unit to be processed based on the predetermined order so as to reduce flicker, which is a repetition of high brightness and low brightness.

12. The information processing device according to claim 11, wherein the detection section detects a division unit to be processed based on a display order of corresponding pixels of the plurality of sub-images and a pixel value difference between pixels in the display order.

13. The information processing device according to claim 11, wherein the detection section detects a division unit to be processed based on an area having a predetermined display form in the frame image.

14. The information processing device according to claim 11, wherein the second processing unit changes the pixel values ​​of pixels corresponding to the divisional unit to be processed so that pixel value differences between the plurality of sub-images are reduced.

15. The information processing device according to claim 11, wherein four adjacent pixels are arranged in the division unit, and the first processing unit generates four sub-images by allocating the four adjacent pixels in a predetermined order.

16. The information processing device according to claim 11, wherein four adjacent pixels are arranged in the division unit, and the first processing unit generates two sub-images by allocating two of the four adjacent pixels in a predetermined order.

17. A display device comprising: an information processing device that generates a plurality of sub-images that are displayed in a predetermined order while changing their display positions based on a frame image in which divisional units having a plurality of pixels are arranged in a matrix; and a projection device, wherein the information processing device has: a first processing unit that generates the plurality of sub-images arranged for each pixel selected from each divisional unit of the frame image according to a predetermined rule in accordance with the matrix arrangement order of the divisional units; and a second processing unit that generates a display period control signal that indicates a display period corresponding to the plurality of sub-images, and the projection device has: a first optical system including a light source capable of emitting light; a liquid crystal light valve having a plurality of pixels and capable of generating image light during the display period by modulating light from the first optical system based on each of the plurality of sub-images and the display period control signal; a light shifting device that is capable of shifting the image light in an in-plane direction of the image depending on which of the plurality of sub-images the image light corresponds to; and a second optical system that is capable of projecting the image light processed by the light shifting device.

18. The display device according to claim 17, wherein the information processing device further comprises a detection unit that detects a divisional unit to be processed, and the second processing unit changes the pixel value of a pixel corresponding to the divisional unit to be processed so as to reduce flicker, which is a repetition of high and low luminance.

19. The display device according to claim 17, wherein the frame images are supplied to the information processing device in accordance with a display order, and the second processing unit changes processing contents of the second processing unit based on the display order.

20. The display device according to claim 17, wherein the display order of the plurality of sub-images is changed in accordance with the frame image.

Images