Semiconductor element

Abstract

The present invention provides an insulated gate-type semiconductor element having a semiconductor layer composed of a gallium oxide-based material. The semiconductor element comprises: a substrate (10) including a Si single crystal; a semiconductor layer (17) (a non-doped layer (11), and an n-type layer (12)) which is provided in contact with the substrate (10) and is composed of a uniaxially oriented gallium oxide-based semiconductor; a gate insulating film (16) provided in contact with the semiconductor layer (17); and a gate electrode (13) provided on the gate insulating film (16). The gate insulating film (16) is composed of a gallium oxide-based semiconductor having a resistivity of 1×104 Ω·cm or more.

Description

semiconductor elements

[0001] The present disclosure relates to semiconductor devices.

[0002] Gallium oxide has been actively researched as a semiconductor material in recent years, and in particular, because of its wide band gap and high breakdown voltage, it has attracted attention as a semiconductor material for power devices.

[0003] Known semiconductor elements include insulated gate structures such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and insulated gate bipolar transistors (IGBTs). The insulated gate structure is a structure in which an insulating film is provided between a semiconductor layer and a metal (electrode). The gate insulating film is typically made of SiO ２ is widely used.

[0004] Insulated gate semiconductor elements using gallium oxide are also being considered. Patent Document 1 describes the use of gallium oxide as a gate insulating film.

[0005] Japanese Patent Application Publication No. 2021-136331

[0006] However, the inventors' investigations have revealed that in a gate insulating semiconductor element using gallium oxide, when a conventionally known material is used as the gate insulating film, many interface states are formed at the interface between the gallium oxide and the gate insulating film.

[0007] The inventors have conducted extensive research into gate insulating semiconductor elements using gallium oxide, and have completed the semiconductor element of the present disclosure.

[0008] The present disclosure has been made in view of the above background, and aims to provide an insulated gate semiconductor element having a semiconductor layer made of a gallium oxide-based material.

[0009] One aspect of the present disclosure provides a gate insulating film having a resistivity of 1×10 or more, the ... ４ The semiconductor element is made of a gallium oxide-based semiconductor having a resistivity of Ω·cm or more.

[0010] According to the above aspect, it is possible to reduce the interface state density in an insulated gate semiconductor element having a semiconductor layer made of a gallium oxide-based material.

[0011] FIG. 1 is a cross-sectional view showing the configuration of a MOSFET according to the first embodiment, taken along a direction perpendicular to the main surface of a substrate.

[0012] The semiconductor element includes a substrate made of single crystal Si, a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate, a gate insulating film provided on and in contact with the semiconductor layer, and a gate electrode provided on the gate insulating film, and the gate insulating film has a resistivity of 1×10 ４ It is made of a gallium oxide semiconductor with a resistivity of Ω·cm or more.

[0013] Semiconductors are materials whose conductivity can be controlled, and gallium oxide-based semiconductors have a wide band gap, making it possible to control their properties from insulating to conductive.

[0014] The semiconductor element may be a MOSFET, an insulated gate bipolar transistor, or an insulated gate HFET (Heterojunction Field Effect Transistor).

[0015] The crystal plane of the main surface of the gate insulating film may be the same as the crystal plane of the main surface of the semiconductor layer.

[0016] The gate insulating film may be a film made of a gallium oxide-based semiconductor having the same composition as the semiconductor layer.

[0017] The gallium oxide based semiconductor may be β-gallium oxide.

[0018] The main surface of the substrate may be a (100) plane, and the main surface of the semiconductor layer may be a (100) plane.

[0019] The

[001] direction of the substrate and the [0-11] direction of the semiconductor layer may coincide with each other.

[0020] 1 is a cross-sectional view showing the configuration of a MOSFET according to Embodiment 1, showing a cross section in a direction perpendicular to a main surface of a substrate. As shown in Fig. 1, the MOSFET according to Embodiment 1 has a substrate 10, a semiconductor layer 17, a gate electrode 13, a source electrode 14, a drain electrode 15, and a gate insulating film 16. In Embodiment 1, the semiconductor layer 17 includes an undoped layer 11 made of an undoped gallium oxide-based compound, and an n-type layer 12 made of an n-type gallium oxide-based compound.

[0021] The substrate 10 is a substrate made of a silicon single crystal in which silicon (Si) atoms are regularly arranged in a three-dimensional manner. Any conventionally known substrate can be used as the substrate 10. For example, a substrate grown by crystal growth using the Czochralski method or the floating zone (FZ) method can be used.

[0022] The plane orientation of the main surface of the substrate 10 is preferably a (100) plane or a (111) plane. These plane orientations facilitate direct crystal growth of gallium oxide on the substrate 10. In particular, from the viewpoint of industrial feasibility, the main surface of the substrate 10 is preferably a (100) plane.

[0023] The surface of the substrate 10 may be modified, for example, by surface treatment with oxygen plasma.

[0024] The non-doped layer 11 is a layer made of non-doped β-gallium oxide, and is provided directly on the substrate 10 without a buffer layer therebetween. That is, the substrate 10 and the non-doped layer 11 are in contact with each other. The non-doped layer 11 is highly resistive, semi-insulating, or insulating. The thickness of the non-doped layer 11 is, for example, 100 nm to 50 μm.

[0025] The buffer layer is a layer inserted for the purpose of relaxing the lattice constant, and typically has a thickness of 20 nm or more. The buffer layer may be made of, for example, the following materials: the same material as the non-doped layer 11, a different material from the non-doped layer 11, a layer formed by gradually changing the composition of a mixed crystal of the same material as the non-doped layer 11 and a different material, or a superlattice structure in which the same material as the non-doped layer 11 and a different material are alternately stacked to a predetermined thickness. In the first embodiment, such a buffer layer is not provided between the substrate 10 and the non-doped layer 11.

[0026] The non-doped layer 11 is a layer provided to prevent current leakage to the substrate 10. By forming the non-doped β-gallium oxide using a predetermined growth method (for example, the PAMBE method), the crystal defect concentration and impurity concentration can be controlled to make the layer highly resistive, semi-insulating, or insulating.

[0027] Here, high resistance means, for example, a resistivity of 1×10 ４ ~1 x 10 ６ Ω cm. Furthermore, semi-insulating means that the resistivity is, for example, 1×10 ６ Insulating refers to a state in which almost no carriers exist, for example, when the carrier concentration is 1 / cm ３ The states are as follows: Insulating properties occur when the band gap is large and the Fermi level is near the center of the band gap. If the Fermi level is slightly off-center, it becomes semi-insulating; if it is further off-center, it becomes highly resistive; and if it is further off-center and close to the conductor or valence band, it becomes conductive. Because beta gallium oxide has a large band gap, it can be in a state ranging from insulating to conductive depending on the position of the Fermi level.

[0028] In embodiment 1, the β-gallium oxide is non-doped to provide high resistance, semi-insulating properties, or insulating properties, but the β-gallium oxide may also be doped with an impurity that forms a deep level, such as Fe, to provide high resistance, semi-insulating properties, or insulating properties.

[0029] The non-doped layer 11 is a uniaxially oriented epitaxial layer on the substrate 10. Here, uniaxial orientation means that at least one of the crystal axes of the β-gallium oxide in the non-doped layer 11 is aligned with one of the crystal axes of Si in the substrate 10. As long as the layer is uniaxially oriented in this way, it may be single crystal or polycrystal. Whether the non-doped layer 11 is uniaxially oriented or not can be confirmed, for example, by the diffraction pattern of X-ray diffraction. Furthermore, whether it is single crystal or polycrystal can also be confirmed by the diffraction pattern of X-ray diffraction.

[0030] When the main surface of the substrate 10 is a (100) plane and the non-doped layer 11 is single crystal, the main surface of the non-doped layer 11 is preferably a (100) plane. The (100) plane of Si and the (100) plane of β-gallium oxide have good lattice matching, allowing the non-doped layer 11 to be formed with high quality. The (100) plane of Si and the (100) plane of β-gallium oxide may form an angle of 10 degrees or less. The crystal plane of the non-doped layer 11 can be identified, for example, by a diffraction peak in θ-2θ measurement of X-ray diffraction.

[0031] Furthermore, it is preferable that the

[001] direction of Si in the substrate 10 and the [0-11] direction of β-gallium oxide in the non-doped layer 11 coincide with each other. This is from the viewpoint of epitaxial growth of the non-doped layer 11. Here, "coincidence" does not mean perfect coincidence, but merely refers to substantial coincidence. For example, if the

[001] direction of Si in the substrate 10 and the

[001] direction of β-gallium oxide in the non-doped layer 11 form an angle of about 23 to 28°, it can be said that the

[001] direction of Si in the substrate 10 and the [0-11] direction of β-gallium oxide in the non-doped layer 11 substantially coincide with each other.

[0032] The n-type layer 12 is a layer made of n-type β-gallium oxide provided on the non-doped layer 11. The thickness of the n-type layer 12 is, for example, 10 nm to 1 μm. The n-type impurity added to form the n-type layer 12 may be Si or Sn. The n-type impurity concentration may be, for example, 1×10 １７ ~1 x 10 ２１ cm －３ Other configurations such as plane orientation are the same as those of the non-doped layer 11.

[0033] The gate insulating film 16 is a film made of an insulator provided in contact with the semiconductor layer 17, and in the first embodiment, is provided in a predetermined region on the n-type layer 12. The material of the gate insulating film 16 is a high-resistance, semi-insulating or insulating β-gallium oxide-based semiconductor. That is, the gate insulating film 16 has a resistivity of 1×10 ４ The gallium oxide semiconductor is a β-gallium oxide semiconductor in which a part of Ga in gallium oxide is replaced with Al or In (Al ２ｘ Ga ２ｙ In ２－２ｘ－２ｙ O ３ , 0≦x≦1, 0<y≦1) and has a β-phase crystal structure. ２ｘ Ga ２（１－ｘ） O ３ , and more preferably 0≦x<1. It is even more preferable that the composition of the n-type layer 12 is the same as that of the n-type layer 12, that is, that the n-type layer 12 is gallium oxide.

[0034] β-gallium oxide semiconductors can be doped with Fe, Si, Mg, etc. to form deep levels, or can be made into high-resistance, semi-insulating, or insulating materials by intrinsic point defects. They can also be made into high-resistance, semi-insulating, or insulating materials by not doping them. For example, the resistivity can theoretically be increased to 1×10 １４ The gate insulating film 16 is preferably semi-insulating or insulating, and more preferably insulating.

[0035] When a high-resistance, semi-insulating, or insulating β-gallium oxide-based semiconductor is used as the gate insulating film 16, it is possible to reduce the formation of interface states at the interface between the n-type layer 12 and the gate insulating film 16. This is because the n-type layer 12 and the gate insulating film 16 are made of the same β-gallium oxide-based semiconductor. For example, when the interface state density is 1×10 １０ ~1×10 １２ cm －２ can be done.

[0036] The gate insulating film 16 may be single crystalline or polycrystalline, but if the n-type layer 12 is single crystalline, the gate insulating film 16 is preferably single crystalline as well. In this case, the main surface of the gate insulating film 16 is preferably the same crystal plane as the main surface of the n-type layer 12. However, an angle of about 10° is permissible. For example, if the main surface of the n-type layer 12 is a (100) plane, the main surface of the gate insulating film 16 is preferably a (100) plane. If the crystal plane of the gate insulating film 16 is set in this manner, the interface state density can be further reduced. Other configurations may be the same as those of the non-doped layer 11.

[0037] The gate electrode 13 is an electrode provided on and in contact with the gate insulating film 16. The material of the gate electrode 13 is Ni, Pt, Au, Ag, Cu, Co, Ir, Ru, Pd, Cr, Mo, W, Ni / Au, Ni / Pt, Pt / Au, W / Au, Pt / Ti / Au, Pt / Au / Ni, Ti / Au / Ni, ITO, or the like.

[0038] The source electrode 14 and the drain electrode 15 are electrodes provided on the semiconductor layer 17 in contact with the semiconductor layer 17, and in the first embodiment, are provided on the n-type layer 12. The source electrode 14 and the drain electrode 15 are provided so as to face each other with the gate electrode 13 sandwiched therebetween in a plan view. The source electrode 14 and the drain electrode 15 are in ohmic contact with the n-type layer 12. The source electrode 14 and the drain electrode 15 may be made of a material such as Ti, Ti / Au, Ti / Al / Au, Ti / Al / Ti / Au, Ti / Al / Ni / Au, Ti / Au / Ni, or Sn.

[0039] As described above, in the MOSFET of the first embodiment, the non-doped layer 11 and the n-type layer 12 are made of gallium oxide, which improves the breakdown voltage. Furthermore, the use of Si for the substrate 10 allows for a large diameter, which is advantageous in terms of mass productivity and cost reduction. Furthermore, the use of a semi-insulating β-gallium oxide-based semiconductor for the gate insulating film 16 reduces the formation of interface states at the interface between the n-type layer 12 and the gate insulating film 16.

[0040] Next, a method for manufacturing the MOSFET according to the first embodiment will be described.

[0041] First, a substrate 10, which is a Si single crystal substrate, is prepared. The substrate 10 is then placed in a furnace and heated to a growth temperature. Thereafter, the pressure in the furnace is reduced to a growth pressure. The ranges of the growth temperature and growth pressure will be described later.

[0042] The surface of the substrate 10 may be treated with oxygen plasma before the formation of the non-doped layer 11. This can reduce the surface roughness of the substrate 10, making it easier to grow gallium oxide on the substrate 10.

[0043] Next, a non-doped layer 11 made of β-gallium oxide is formed on the substrate 10 by plasma-assisted molecular beam epitaxy (PAMBE). In the PAMBE method, a mixed gas containing oxygen and ozone is turned into plasma and supplied to the substrate 10, and gallium is evaporated and a molecular beam is irradiated onto the substrate 10. By turning the mixed gas containing oxygen and ozone into plasma, the ozone is decomposed to generate oxygen molecules and oxygen radicals. The oxygen radicals are formed by singlet oxygen atoms O( １ D) and triplet oxygen atom O( ３ P), and singlet oxygen atoms transition to triplet oxygen atoms at a predetermined rate. These oxygen radicals react with the gallium molecular beam on the substrate surface, causing β-gallium oxide crystal growth on the surface of the substrate 10.

[0044] The growth pressure is preferably 0.001 Pa or more and 0.01 Pa or less. The growth temperature (substrate temperature) is preferably 0° C. or more and 600° C. or less. If the growth temperature and growth pressure are within these ranges, the non-doped layer 11 and the n-type layer 12 can be grown with good crystallinity.

[0045] A mixed gas containing oxygen and ozone can be generated by using an ozonizer to convert oxygen into plasma and then converting part of the oxygen into ozone.

[0046] In the mixed gas containing oxygen and ozone, the ratio of ozone to the total of oxygen and ozone is preferably 10% by volume or more. Although there is no particular upper limit, when the mixed gas containing oxygen and ozone is generated using an ozonizer, it is usually 50% by volume or less. The mixed gas containing oxygen and ozone may be mixed with an inert gas such as Ar and supplied. This makes it easier to generate plasma.

[0047] Next, n-type layer 12 is formed on non-doped layer 11. The method for forming n-type layer 12 may be any conventionally known method, such as CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), sputtering, etc. Non-doped layer 11 and n-type layer 12 may be grown continuously using the PAMBE method similar to that used for non-doped layer 11.

[0048] Next, a gate insulating film 16 is formed in a predetermined region on the n-type layer 12. The method for forming the gate insulating film 16 is the same as the method for forming the non-doped layer 11. However, in order to form a high-resistance, semi-insulating, or insulating β-gallium oxide-based semiconductor, it is preferable to form it by a method such as a PAMBE method or a plasma CVD method. This makes it easier to control the crystal defect concentration and impurity concentration to achieve high resistance. Furthermore, by using the same formation method as the non-doped layer 11, the non-doped layer 11, the n-type layer 12, and the gate insulating film 16 may be grown continuously. By growing them continuously, it is possible to prevent impurities from being mixed into the interface between the n-type layer 12 and the gate insulating film 16.

[0049] Next, the gate electrode 13 is formed on the gate insulating film 16 by a method such as vapor deposition, and the source electrode 14 and the drain electrode 15 are formed on the n-type layer 12 by a method such as vapor deposition. In this way, the MOSFET of the first embodiment is manufactured.

[0050] (Modification of First Embodiment) Although the first embodiment is a MOSFET, the present disclosure can be applied to any insulated gate electronic device. For example, it can also be applied to an insulated gate bipolar transistor (IGBT) or an insulated gate HFET. It can also be applied to a trench gate electronic device. Furthermore, although the MOSFET in the first embodiment is a lateral type, the present disclosure can also be applied to a vertical type.

[0051] Although the present invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present invention. This application is based on a Japanese patent application (Patent Application No. 2023-150630) filed on September 18, 2023, the contents of which are incorporated herein by reference.

[0052] 10: Substrate 11: Non-doped layer 12: N-type layer 13: Gate electrode 14: Source electrode 15: Drain electrode 16: Gate insulating film 17: Semiconductor layer

Claims

1. A semiconductor device comprising: a substrate made of single crystal Si; a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate; a gate insulating film provided on and in contact with the semiconductor layer; and a gate electrode provided on the gate insulating film, the gate insulating film having a resistivity of 1×10 ４ A semiconductor element made of a gallium oxide-based semiconductor with a resistivity of Ω·cm or more.

2. The semiconductor device of claim 1 which is a MOSFET.

3. The semiconductor device according to claim 1, which is an insulated gate bipolar transistor.

4. The semiconductor device according to claim 1, which is an insulated gate HFET.

5. A semiconductor device according to any one of claims 1 to 4, wherein a crystal plane of a principal surface of the gate insulating film is the same as a crystal plane of a principal surface of the semiconductor layer.

6. A semiconductor device according to any one of claims 1 to 4, wherein the gate insulating film is made of a gallium oxide-based semiconductor having the same composition as the semiconductor layer.

7. The semiconductor device according to any one of claims 1 to 4, wherein the gallium oxide based semiconductor is β-gallium oxide.

8. The semiconductor device according to any one of claims 1 to 4, wherein the main surface of the substrate is a (100) surface.

9. The semiconductor device according to claim 8, wherein a primary surface of the semiconductor layer is a (100) surface.

10. The semiconductor element according to any one of claims 1 to 4, wherein the [001] direction of the substrate and the [0-11] direction of the semiconductor layer coincide with each other.

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