Balun transformer for amplifier and amplifier comprising same

Abstract

Provided are a balun transformer for an amplifier and an amplifier comprising same, wherein the balun transformer for an amplifier is formed by integration into a single chip through a complementary metal-oxide semiconductor (CMOS) process, and comprises: a first layer in which metal lines (hereinafter, referred to as "lines of the first layer") for implementing a plurality of inductors (hereinafter, referred to as "inductors of a first coupling unit") for receiving differential signals are spaced apart from each other at a predetermined interval on a plane so as to be horizontally magnetically coupled to each other; and a second layer in which metal lines (hereinafter, referred to as "lines of the second layer") for implementing a plurality of inductors (hereinafter, referred to as "inductors of a second coupling unit") coupled to the first coupling unit to output the differential signals received from the first coupling unit are spaced apart from each other at a predetermined interval on a plane so as to be horizontally magnetically coupled to each other.

Description

Balun transformer for amplifier and amplifier including same

[0001] The present invention relates to an amplifier.

[0002] Phased array systems are used not only in 5G and 6G communications, but also in a wide range of fields, including medicine, aviation, maritime navigation, military operations, and weather forecasting. These phased array systems contain arrays of radio frequency integrated circuits (RFICs) for wireless communications.

[0003] RFICs include RF power amplifiers (RFPAs, hereinafter referred to as “power amplifiers”), low noise amplifiers (LNAs), mixers, oscillators, RF switches, and RF transceivers.

[0004] Among these, the power amplifier functions in the transmitter section of the RFIC to amplify the input signal, thereby helping the antenna module transmit an RF signal with normal and sufficient strength, which has a significant impact on the quality of wireless communication.

[0005] These power amplifiers need to have high linear output power at high modulation signals (OFDM, PAPR > 10 dB) while maintaining efficiency in order to maintain or improve the overall performance of the phased array system to a certain level or higher.

[0006] Meanwhile, phased array systems require numerous RF components, including power amplifiers, which inevitably leads to high manufacturing costs. To minimize implementation costs, complementary metal-oxide semiconductor (CMOS) technology is being utilized.

[0007] This manufacturing process using CMOS technology is a very advantageous technology for implementing RF circuits on a single chip at low cost, but it is insufficient to demonstrate sufficient performance compared to other manufacturing processes that entail high manufacturing costs, such as compound processes.

[0008] Accordingly, various attempts are being made to improve the performance of phased array systems using CMOS technology.

[0009] As part of these efforts, a power amplifier with a differential structure has been proposed. This differential structure creates a virtual ground within the circuit, thereby minimizing circuit performance degradation caused by inductance components that may occur at the ground point.

[0010] Figures 1 and 2 are reference drawings provided to explain a conventional power amplifier having a differential structure as described above.

[0011] For reference, Fig. 1 is a simple example of a power amplifier consisting of a drive amplifier (DA) and a power amplifier (PA) between the input and output, and Fig. 2 is an example of a circuit of a conventional power amplifier.

[0012] Referring to Fig. 1, a conventional power amplifier (10) is provided with an amplifier (11) for implementing high output power, an input balun transformer (IPT1, IPT2) for inputting a signal to the amplifier (11) at one end of the amplifier (11), and connection balun transformers (ITT1, ITT2) for transmitting an amplified signal amplified in the amplifier (11) to the power amplifier side at the other end of the amplifier (11).

[0013] At this time, the amplifier section (11) is arranged in two stages with multiple amplifiers (PA1, PA2) each composed of transistors of a common source structure, and the amplifiers (PA1, PA2) and the connecting balun transformers (ITT1, ITT2) are arranged in a 1:1 correspondence.

[0014] These conventional power amplifiers had the following problems:

[0015] First, as more amplifiers are placed to achieve higher output power, additional balun transformers must be provided at each connection point between the driving amplifier stage and the power amplifier stage. Therefore, the circuit size inevitably increases due to the balun transformers being placed side by side on a plane within the circuit chip.

[0016] At a time when devices to which phased array systems are applied are becoming smaller, this size issue not only limits their utility, but also inevitably leads to increased manufacturing costs due to the expansion of chip size even if performance is improved.

[0017] Second, as circuit size increases, the length of the transmission lines required to implement each component also increases. As transmission line length increases, the resistance component inevitably increases, resulting in reduced output power and inefficient performance.

[0018] [Prior Art Literature]

[0019] [Patent Document]

[0020] (Patent Document 1) Korean Patent Publication No. 10-1881767 (Registration Date: July 19, 2018)

[0021] The present invention was conceived to solve the above-described problems and to achieve miniaturization while ensuring excellent performance.

[0022] In order to achieve this purpose, an amplifier according to an embodiment of the present invention may include an input terminal that receives a single signal and converts it into a differential signal; a first amplifier stage that receives the differential signal from the input terminal and generates a first amplified signal by amplifying the received signal; a second amplifier stage that receives the first amplified signal from the first amplifier stage and generates a second amplified signal by amplifying the first amplified signal; a connection terminal that couples between the first and second amplifier stages to transmit the first amplified signal generated in the first amplified signal to the second amplified stage; and an output terminal that receives the second amplified signal from the second amplifier stage and outputs the second amplified signal, which is a differential signal, as a single signal.

[0023] Here, the first amplifier stage includes a plurality of amplifier units that amplify the differential signal converted by the input terminal to generate the first amplified signal; and at least one amplifier unit among the plurality of amplifier units is configured as a pair of transistors that receive the differential signal as a gate terminal and have a source terminal that is grounded, and can be provided as a common source structure that operates differentially.

[0024] And the connection section includes a first coupling section, both ends of which are electrically connected to the first amplifier section; and a second coupling section, both ends of which are electrically connected to the second amplifier section; and the first coupling section includes inductors (hereinafter referred to as “inductors of the first coupling section”), which are provided in a number corresponding to the plurality of amplifier sections, and each end of which is connected to each drain terminal of a pair of transistors configured in each of the plurality of amplifier sections. , and the second coupling unit includes inductors (hereinafter referred to as “inductors of the second coupling unit”) that are coupled in a 1:1 manner with the inductors of the first coupling unit, which are provided in a number corresponding to the plurality of amplifying units, and a first amplification signal applied to the first coupling unit can be transmitted to the second amplification stage by coupling between the inductors of the first coupling unit and the inductors of the second coupling unit.

[0025] At this time, the inductors provided in at least one of the first coupling part and the second coupling part can form a mutual inductance of polarity.

[0026] For reference, the above-mentioned connection terminal may be a balun transformer for an amplifier formed by integration into a single chip through a complementary metal-oxide semiconductor (CMOS) process.

[0027] At this time, the connecting section includes a first layer in which metal lines (hereinafter referred to as “lines of the first layer”) for implementing the inductors of the first coupling section are arranged at a predetermined interval on a plane so that they are horizontally magnetically coupled to each other; and a second layer in which metal lines (hereinafter referred to as “lines of the second layer”) for implementing the inductors of the second coupling section are arranged at a predetermined interval on a plane so that they are horizontally magnetically coupled to each other; wherein the first layer and the second layer are stacked vertically, and the lines of the first layer and the lines of the second layer that face each other can be vertically magnetically coupled.

[0028] Here, either of the first layer and the second layer may be a top metal layer.

[0029] Meanwhile, in order to achieve this purpose, an amplifier balun transformer according to an embodiment of the present invention is an amplifier balun transformer formed by being integrated into a single chip through a complementary metal-oxide semiconductor (CMOS) process, and includes a first layer in which metal lines (hereinafter referred to as “lines of the first layer”) for implementing a plurality of inductors (hereinafter referred to as “inductors of the first coupling section”) for receiving a differential signal are arranged at a predetermined interval on a plane so as to be horizontally magnetically coupled to each other; And a second layer in which metal lines (hereinafter referred to as “lines of the second layer”) for implementing a plurality of inductors (hereinafter referred to as “inductors of the second coupling section”) for outputting a differential signal received from the first coupling section by being coupled to the first coupling section are arranged at a predetermined interval on a plane so as to be horizontally magnetically coupled to each other; wherein the first layer and the second layer are stacked vertically, and the lines of the first layer and the lines of the second layer that face each other can be vertically magnetically coupled.

[0030] At this time, the first layer may be formed so that both ends of the lines of the first layer are extended to one side, and the differential signal may be input through both ends extended to one side, and the second layer may be formed so that both ends of the lines of the second layer are extended to the other side, and the differential signal received from the lines of the first layer may be output through both ends extended to the other side.

[0031] Here, either of the first layer and the second layer may be a top metal layer.

[0032] As described above, according to the present invention, the following effects can be obtained.

[0033] First, by adding a simple circuit and changing the transformer structure, the area can be reduced by about 40% or more compared to existing power amplifiers, contributing to the miniaturization of the amplifier.

[0034] Second, it is possible to miniaturize the amplifier while still obtaining high efficiency and linear output power, ensuring excellent performance.

[0035] Third, in the semiconductor field, where area is directly related to cost, it can reduce manufacturing costs.

[0036] Fourth, in the case of balun transformers, they can be used not only in power amplifiers but also in all amplifiers that use differential signals, so they can greatly contribute to the development of wireless communications and laser industries.

[0037] Figures 1 and 2 are drawings to explain a conventional power amplifier.

[0038] Figures 3 and 4 are drawings illustrating a power amplifier according to one embodiment of the present invention.

[0039] FIG. 5 is a diagram illustrating a balun transformer for an amplifier according to one embodiment of the present invention.

[0040] Figures 6 and 7 are reference diagrams showing simulation results to explain the effectiveness of the power amplifier proposed by the present invention.

[0041] A preferred embodiment of the present invention will be described in more detail with reference to the attached drawings, but technical parts already known will be omitted or compressed for the sake of brevity.

[0042] It should be noted that references in this specification to “one” or “an” embodiment of the invention are not necessarily to the same embodiment, but rather mean at least one.

[0043] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0044] In the examples below, singular expressions include plural expressions unless the context clearly indicates a different meaning.

[0045] In the examples below, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0046] Each configuration shown in the drawing is arbitrarily shown for convenience of explanation, and therefore the present invention is not necessarily limited to what is shown.

[0047] Hereinafter, a power amplifier is described as an application example of the balun transformer proposed by the present invention, but it is obvious that the technical features of the present invention can be applied to all amplifiers that utilize differential signals, such as low-noise amplifiers.

[0048] <Description of Power Amplifier>

[0049] FIG. 3 illustrates a circuit diagram of a power amplifier according to one embodiment of the present invention, and FIG. 4 illustrates a layout of an IC chip in which the power amplifier illustrated in FIG. 3 is integrated.

[0050] Referring to FIGS. 3 and 4, a power amplifier (100) according to one embodiment of the present invention is configured to include an input terminal (110), a first amplifier stage (120), a second amplifier stage (130), a connection terminal (140), and an output terminal (150).

[0051] For reference, the power amplifier (100) can be divided into a drive amplifier stage (DA) and a power amplifier stage (PA) as illustrated in Fig. 1. Among the configurations described below, some of the input stage (110), the first amplifier stage (120), and the connection stage (140) (e.g., the first coupling unit (141)) may be included in the drive amplifier stage (DA), and some of the connection stage (140) (e.g., the second coupling unit (142)), the second amplifier stage (130), and the output stage (150) may be included in the power amplifier stage (PA).

[0052] The input terminal (110) receives a single signal, for example, a single-ended signal, and converts it into a differential signal.

[0053] As an example of such an input terminal (110), an input balun transformer can be applied.

[0054] The input balun transformer (110) is a primary input inductor (L IN1 ) and secondary input inductor (L IN2 ) is composed of.

[0055] Primary input inductor (L IN1 ) A single signal is input at one end, and the other end is grounded.

[0056] Secondary input inductor (L IN2 ) is the primary input inductor (L IN1 ) is coupled with the primary input inductor (L IN1 ) converts the input single signal into a differential signal.

[0057] Here the secondary input inductor (L IN2 ) can transmit a differential signal by being connected to each gate terminal of the transistors (Tr1, Tr3) provided in the first amplifier stage (120) described later.

[0058] And the secondary input inductor (L IN2 ) can transmit a differential signal by being connected to each gate terminal of the transistors (Tr2, Tr4) provided in the first amplifier stage (120).

[0059] At this time, the secondary input inductor (L IN2) have a phase difference of 180° between one end and the other end of the differential signal provided to the first amplifier stage (120), and can have phases of 0° and 180°, respectively.

[0060] And the secondary input inductor (L IN2 ) can be applied with a bias voltage (VG1) to the transistors (Tr1 to Tr4) provided in the first amplifier stage (120).

[0061] For reference, the center tap (T1) is equipped with only a resistor (R1), and the size of the resistor is 10 kΩ, so it can support a stable supply of bias voltage (VG1) even without an additional capacitor.

[0062] The first amplifier stage (120) receives a differential signal from the input stage (110) and generates a first amplified signal by amplifying the received signal. At this time, the first amplified signal may be a differential signal.

[0063] The first amplifier stage (120) includes a plurality of amplifier units (e.g., a first amplifier unit (121) and a second amplifier unit (122)).

[0064] The first amplifier (121) is configured with a pair of transistors (e.g., a first transistor (Tr1) and a second transistor (Tr2)) that receive a differential signal as a gate terminal and have a source terminal that is grounded, and is provided with a common source structure that operates differentially.

[0065] To explain more specifically, the first transistor (Tr1) configured in the first amplifier section (121) receives a differential signal (phase is 0°) as a gate terminal, grounds the source terminal, and outputs the first amplification signal (phase is 0°) as a drain terminal.

[0066] And, the second transistor (Tr2) receives a differential signal (phase is 180°) as input to the gate terminal, grounds the source terminal, and outputs the first amplified signal (phase is 180°) as the drain terminal.

[0067] The second amplifier (122) is configured with a common source structure that operates differentially and is composed of a pair of transistors (e.g., a third transistor (Tr3) and a fourth transistor (Tr4)) whose gate terminals receive a differential signal and whose source terminals are grounded.

[0068] To explain more specifically, the third transistor (Tr3) configured in the second amplifier section (122) receives a differential signal (phase of 0°) as a gate terminal, grounds the source terminal, and outputs the first amplification signal (phase of 0°) as a drain terminal.

[0069] And, the fourth transistor (Tr4) receives a differential signal (phase is 180°) as the gate terminal, grounds the source terminal, and outputs the first amplified signal (phase is 180°) as the drain terminal.

[0070] The first amplifier unit (121) and the second amplifier unit (122) configured in the first amplifier stage (120) are connected in parallel, and can amplify the output of the first amplification signal provided to the second amplifier stage (130) through the connection terminal (140) described later.

[0071] For example, the first amplified signal may be a signal that amplifies the gain of the operating frequency band of the power amplifier.

[0072] This first amplifier stage (120) pre-amplifies the differential signal, and the second amplifier stage (130) described later post-amplifies the amplified signal received from the first amplifier stage (120), thereby enabling the power amplifier (100) proposed by the present invention to implement high output power.

[0073] For reference, the first amplifier stage (120) may further include a stabilizing unit (123) provided on the path from the input stage (110) to the first amplifier unit (121) and the second amplifier unit (122).

[0074] At this time, the stabilization unit (123) is provided as a parallel resistor-capacitor pair (RC pair).

[0075] This stabilizing part (123) is firstly a secondary input inductor (L IN2) and the other end is connected to the gate of each of the first to fourth transistors (Tr1, Tr2, Tr3, Tr4).

[0076] The stabilization unit (123) can prevent the amplification of oscillation phenomena within the circuit and ultimately contribute to circuit stabilization.

[0077] The second amplifier stage (130) receives the first amplification signal from the first amplifier stage (120) and generates a second amplification signal by amplifying the first amplification signal.

[0078] The second amplifier stage (130) includes a plurality of amplifier units (e.g., a third amplifier unit (131) and a fourth amplifier unit (132)).

[0079] The third amplifier (131) receives a differential signal as a gate terminal and includes a pair of transistors (e.g., the fifth transistor (Tr5) and the sixth transistor (Tr6)) whose source terminal is grounded. At this time, the pair of transistors (Tr 5, Tr6) is provided as a common source structure that operates differentially.

[0080] And, a common gate structure transistor (e.g., the seventh transistor (Tr7) and the eighth transistor (Tr8)) that receives a differential signal as a source terminal and has a gate terminal that is grounded is disposed at the drain terminal of each of the fifth transistor (Tr5) and the sixth transistor (Tr6).

[0081] To explain more specifically, the fifth transistor (Tr5) configured in the third amplifier section (131) receives a first amplified signal (phase is 0°) as its gate terminal, has its source terminal grounded, and outputs an amplified signal (phase is 0°) as its drain terminal. At this time, the seventh transistor (Tr7) receives an amplified signal (phase is 0°) from the drain terminal of the fifth transistor (Tr5) as its source terminal, has its gate terminal grounded, and outputs a second amplified signal (phase is 0°) as its drain terminal.

[0082] And, the sixth transistor (Tr6) configured in the third amplifier section (131) receives the first amplified signal (phase is 180°) as its gate terminal, grounds its source terminal, and outputs the amplified signal (phase is 180°) as its drain terminal. At this time, the eighth transistor (Tr8) receives the amplified signal (phase is 180°) from the drain terminal of the sixth transistor (Tr6) as its source terminal, grounds its gate terminal, and outputs the second amplified signal (phase is 180°) as its drain terminal.

[0083] For reference, the 7th transistor (Tr7), the 8th transistor (Tr8), and the 11th transistor (Tr 11 ) and the 12th transistor (Tr 12 ) Each gate terminal is equipped with a capacitor in the path to ground, and a resistor in the path branched from it for each transistor (Tr 7, Tr 8, Tr 11, Tr 12 ) can support a stable supply of bias voltage (VCG).

[0084] The fourth amplifier (132) receives a differential signal as a gate terminal and is a pair of transistors whose source terminals are grounded (e.g., the ninth transistor (Tr9) and the tenth transistor (Tr 10 )) is included. At this time, the above pair of transistors (Tr 9, Tr 10 ) is provided as a common source structure that operates differentially.

[0085] And the 9th transistor (Tr9) and the 10th transistor (Tr 10 ) Each drain terminal receives a differential signal as a source terminal, and a transistor of a common gate structure whose gate terminal is grounded (e.g., the 11th transistor (Tr) 11 ) and the 12th transistor (Tr 12 )) are placed respectively.

[0086] Transistors included in the fourth amplifier section (132) (Tr9 to Tr 12) corresponds to the transistors (Tr5 to Tr8) included in the third amplifier section (131) described above, so a detailed description thereof will be omitted.

[0087] For reference, the 7th transistor (Tr7) and the 8th transistor (Tr8) included in the 3rd amplifier unit (131) and the 11th transistor (Tr) included in the 4th amplifier unit (132) 11 ) and the 12th transistor (Tr 12 ) The differential signal output from the differential signal of the same phase is combined into a single signal path and transmitted to the output terminal (150) described later.

[0088] Since the configuration of this second amplifier stage (130) is one embodiment, it goes without saying that the configuration may be increased or decreased depending on the implementation.

[0089] Meanwhile, a pair of transistors provided in the first amplifier stage (120) and the second amplifier stage (130) are connected to a neutralization capacitor (C n ) can be equipped.

[0090] Let us explain the first amplifier section (121) of the first amplifier stage (120) as an example. The first amplifier section (121) is connected to the gate terminal of the first transistor (Tr1) at one end and to the drain terminal of the second transistor (Tr2) at the other end. The first neutralization capacitor (C) n1 ) and a second neutralization capacitor (C) having one end connected to the gate terminal of the second transistor (Tr2) and the other end connected to the drain terminal of the first transistor (Tr1). n2 ) may be included.

[0091] In addition, a neutralizing capacitor (C) coupled to a pair of transistors provided in the first amplifier stage (120) and the second amplifier stage (130) n ) has the same layout structure, so its detailed description will be omitted.

[0092] These neutralizing capacitors (C n) are the first to fourth transistors (Tr1, Tr2, Tr3, Tr4), the fifth to sixth transistors (Tr5, Tr6,) and the ninth to tenth transistors (Tr9, Tr 10 ,) can compensate for each gate-train parasitic capacitance and contribute to improving the stability of the overall circuit.

[0093] The connecting unit (140) couples the first amplifier stage (120) and the second amplifier stage (130) to transmit the first amplification signal generated in the first amplifier stage (120) to the second amplifier stage (130).

[0094] The connecting section (140) may include a first coupling section (141) and a second coupling section (142).

[0095] The first coupling section (141) is electrically connected at both ends to the first amplifier section (120).

[0096] The first coupling unit (141) is provided with a number corresponding to a plurality of amplifier units (121, 122), and includes inductors (hereinafter referred to as “inductors (L1, L2) of the first coupling unit”), each end of which is connected to the respective drain terminals of a pair of transistors (Tr1, Tr2) configured in each of the plurality of amplifier units (121, 122).

[0097] To explain more specifically, the first coupling part (141) includes a first inductor (L1) and a second inductor (L2) as inductors of the first coupling part.

[0098] At this time, both ends of the first inductor (L1) are connected to each drain terminal of a pair of transistors (e.g., the first transistor (Tr1) and the second transistor (Tr2)) configured in the first amplifier section (121).

[0099] And both ends of the second inductor (L2) are connected to the respective drain terminals of a pair of transistors (e.g., the third transistor (Tr3) and the fourth transistor (Tr4)) configured in the second amplifier section (122).

[0100] The first inductor (L1) and the second inductor (L2) may be arranged to form a mutual inductance of polarity and be magnetically coupled. In this case, the first inductor (L1) and the second inductor (L2) form a mutual inductance of polarity, thereby enabling the mutual inductance of polarity to be utilized to obtain the inductance value required as a configuration of the first coupling unit (141). Accordingly, the physical sizes of the first inductor (L1) and the second inductor (L2) required to obtain the required inductance value are reduced. This may contribute to the miniaturization of the amplifier.

[0101] Meanwhile, a driving voltage (VDD) for the first to fourth transistors (Tr1, Tr2, Tr3, Tr4) can be applied through a path branched from a grounded center tap (T2) shared by the first inductor (L1) and the second inductor (L2). At this time, a capacitor (C2) can be provided on the path toward the center tap (T2) to ensure a stable supply of the driving voltage (VDD).

[0102] The driving voltage (VDD) can be, for example, 1 V.

[0103] The second coupling unit (142) includes inductors (L1, L2) of the first coupling unit, which are provided in a number corresponding to a plurality of amplifier units (121, 122), and are coupled in a 1:1 matching manner (hereinafter, 'second coupling inductors (L3, L4)').

[0104] To explain more specifically, the second coupling part (142) includes a third inductor (L3) and a fourth inductor (L4) as inductors of the second coupling part.

[0105] At this time, both ends of the third inductor (L3) are connected to the respective drain terminals of a pair of transistors (e.g., the fifth transistor (Tr5) and the sixth transistor (Tr6)) configured in the third amplifier section (131).

[0106] And both ends of the fourth inductor (L4) are connected to a pair of transistors (e.g., the ninth transistor (Tr9) and the tenth transistor (Tr)) configured in the fourth amplifier (132).10 )) is connected to each drain terminal.

[0107] The third inductor (L3) and the fourth inductor (L4) may be arranged to form a mutual inductance of polarity and be magnetically coupled. In this case, the third inductor (L3) and the fourth inductor (L4) form a mutual inductance of polarity, thereby enabling the use of the mutual inductance of polarity to obtain the inductance value required as a configuration of the second coupling unit (142). Accordingly, the physical sizes of the third inductor (L3) and the fourth inductor (L4) required to obtain the required inductance value are reduced. This can also contribute to the miniaturization of the amplifier.

[0108] Meanwhile, the third inductor (L3) may have a grounded center tap (T3). The bias voltage (VG2) for the fifth transistor (Tr5) and the sixth transistor (Tr6) configured in the second amplifier stage (130) may be applied through the center tap (T3) of the third inductor (L3). At this time, a capacitor (C3) is provided in the path leading to the center tap (T3), and a resistor (R3) is provided in the path branched from the center tap (T3) to support a stable supply of the bias voltage (VG2).

[0109] And the fourth inductor (L4) may have a center tap (T4) that is grounded. Through the center tap (T4) provided by the fourth inductor (L4), the ninth transistor (Tr9) and the tenth transistor (Tr) configured in the second amplifier stage (130) are connected. 10 ) can be applied with a bias voltage (VG2). At this time, a capacitor (C4) is provided in the path toward the center tap (T4), and a resistor (R4) is provided in the path branched from the center tap (T4) to apply the bias voltage (V G ) can support a stable supply.

[0110] For reference, in the case of the first amplifier stage (120) illustrated in FIGS. 3 and 4, it is a 2-way structure equipped with two amplifier sections, but by additionally providing 2n amplifier sections, it can be implemented in an expanded manner as 4-way, 6-way, 8-way, ..., 2n-way (where n is a natural number).

[0111] In this case, it goes without saying that inductors configured in each of the first coupling part (141) and the second coupling part (142) of the connecting section (140) are additionally provided.

[0112] The above-mentioned connection (140) may be a balun transformer for an amplifier formed by integration into a single chip through a complementary metal-oxide semiconductor (CMOS) process.

[0113] Connection terminal (140) For example, a balun transformer for an amplifier is provided in a three-dimensional layered structure, and the area occupied by the balun transformer in the power amplifier (100) can be drastically reduced.

[0114] A detailed description of the specific shape of this connection (140) or balun transformer will be provided later.

[0115] The output terminal (150) receives the second amplification signal from the second amplification terminal (130) and outputs the second amplification signal, which is a differential signal, as a single signal.

[0116] As an example of such an output terminal (150), an output balun transformer can be applied.

[0117] The output balun transformer is a primary output inductor (L OUT1 ) and secondary output inductor (L OUT2 ) is composed of.

[0118] Primary output inductor (L OUT1 ) A differential signal is input to both ends.

[0119] Here the primary output inductor (L OUT1 ) is equipped with transistors (Tr7 and Tr) in the second amplifier stage (130). 11) is connected to each drain terminal, thereby transmitting a signal of the same phase (e.g., 0°).

[0120] And the primary output inductor (L OUT1 ) is equipped with transistors (Tr8 and Tr) in the second amplifier stage (130). 12 ) is connected to each drain terminal, thereby transmitting a signal of the same phase (e.g., 180).

[0121] That is, the primary output inductor (L OUT1 ) have a phase difference of 180° between one end and the other end of the differential signal provided to the output terminal (150), and have phases of 0° and 180°, respectively.

[0122] And the primary output inductor (L OUT1 ) is connected to the 5th to 10th transistors (Tr5 to Tr) through a branched path from the grounded center tap (T4). 10 ) can be applied with a driving voltage (VDD). At this time, a capacitor (C5) can be provided in the path toward the center tap (T5) to ensure that the driving voltage (VDD) is supplied stably.

[0123] The driving voltage (VDD) can be, for example, 2 V.

[0124] Secondary output inductor (L OUT2 ) is the primary output inductor (L OUT1 ) is coupled with the primary output inductor (L OUT1 ) converts the input differential signal into a single signal.

[0125] Secondary output inductor (L OUT2 ) can output a single signal at one end and the other end can be grounded. The secondary output inductor (L OUT2 ) may be provided with a capacitor for output matching in a branched stage from a stage that outputs a single signal.

[0126] Meanwhile, the operation of the above-described power amplifier (100) can be summarized as follows.

[0127] First, when a single signal is input to the input terminal (110), the input terminal (110) converts it into a differential signal and transmits it to the first amplifier stage (120).

[0128] The differential signal transmitted to the first amplifier stage (120) is provided to both the first amplifier unit (121) and the second amplifier unit (122), and each amplifier unit (121, 122) generates a first amplified signal by amplifying the gain in the operating frequency band.

[0129] The first amplification signal generated in the first amplifier stage (120) is provided to the second amplifier stage (130) through the connection stage (140). More specifically, the first amplification signal is provided to both ends of each of the first inductor (L1) and the second inductor (L2). The first amplification signal flowing through the first inductor (L1) is provided to the second amplifier stage (130) by being induced in the third inductor (L3) coupled with the first inductor (L1), and the first amplification signal flowing through the second inductor (L2) is provided to the second amplifier stage (130) by being induced in the fourth inductor (L4) coupled with the second inductor (L2).

[0130] The first amplification signal induced in the third inductor (L3) and the fourth inductor (L4) secures sufficient output power within the second amplification stage (130) and is then output as a second amplification signal through the output stage (150) located at the rear end of the second amplification stage (130).

[0131] Description of Balun Transformer

[0132] FIG. 5a is a perspective view of a balun transformer for an amplifier (hereinafter, collectively referred to as a “balun transformer”) according to one embodiment of the present invention, and FIGS. 5b to 5c are plan views of the upper and lower surfaces of the balun transformer illustrated in FIG. 5a, respectively.

[0133] For reference, the balun transformer (200) illustrated in FIG. 5 is related to the connection terminal (140) in the power amplifier (100) described above. That is, the balun transformer (200) proposed according to the present embodiment can propose the actual structure of the first inductor (L1), the second inductor (L2), the third inductor (L3), and the fourth inductor (L4), which are components of the connection terminal (140) in the power amplifier (100) of the embodiment described above.

[0134] Hereinafter, the structure of the balun transformer (200) proposed by the present invention will be described with reference to FIG. 5. However, since the balun transformer (200) is intended to perform the functions of the first inductor (L1), the second inductor (L2), the third inductor (L3), and the fourth inductor (L4) described above, its operation may be partially replaced with the description of the functions and operations of the first inductor (L1), the second inductor (L2), the third inductor (L3), and the fourth inductor (L4) described above.

[0135] Referring to FIG. 5a, it may include a first layer (210) and a second layer (220).

[0136] In the first layer (210), metal lines (hereinafter referred to as “lines (211, 212) of the first layer”) for implementing the inductors (L1, L2) of the first coupling section are arranged at a predetermined interval on a plane so as to be horizontally magnetically coupled to each other.

[0137] The lines of the first layer may include a first transmission line (211) and a second transmission line (212).

[0138] A first transmission line (211) may be provided in the first layer (210) to implement a first inductor (L1). The first transmission line (211) may receive a first amplification signal through both ends (E1) extended to the left.

[0139] The second transmission line (212) is provided in the first layer (210) to implement the second inductor (L2), and may be provided on the inner side of the first transmission line (211) on a plane. The second transmission line (212) may be provided to receive the first amplification signal through both ends (E2) extended to the left.

[0140] At this time, the first transmission line (211) and the second transmission line (212) can be horizontally magnetically coupled to each other while being spaced apart from each other by a predetermined interval (e.g., 2 μm).

[0141] Referring to FIG. 5b, the first transmission line (211) and the second transmission line (212) are arranged to share a center tap (T2) through an extension line formed to extend to the right, and a driving voltage (VDD) for transistors connected to the front ends of each of the above-described ends (E1, E2) can be applied through the center tap (T2).

[0142] At this time, the first transmission line (211) and the second transmission line (212) can form a mutual inductance of polarity and be magnetically coupled. In this case, the actual inductance of the first inductor (L1) and the second inductor (L2) implemented in the first layer (210) increases, so that the designer or manufacturer can design or manufacture the first transmission line (211) and the second transmission line (212) in a miniaturized form. This can contribute to miniaturizing not only the balun transformer (200) but also all amplifiers including it.

[0143] In the second layer (220), metal lines (hereinafter referred to as “lines (221, 222) of the second layer”) for implementing the inductors (L3, L4) of the first coupling section are arranged at a predetermined interval on a plane so as to be horizontally magnetically coupled to each other.

[0144] The lines of the second layer may include a third transmission line (221) and a fourth transmission line (222).

[0145] A third transmission line (221) may be provided in the second layer (220) to implement a third inductor (L3). The third transmission line (221) may output a first amplified signal through both ends (E3) extended to the right.

[0146] The fourth transmission line (222) is provided in the second layer (220) to implement the fourth inductor (L4), and may be provided on the inner side of the third transmission line (221) on a plane. The fourth transmission line (222) can output the first amplified signal through both ends (E4) extended to the right.

[0147] At this time, the third transmission line (221) and the fourth transmission line (222) can also be horizontally magnetically coupled to each other while being spaced apart by a predetermined interval (e.g., 2 μm).

[0148] To explain in more detail with reference to Fig. 5c, the third transmission line (221) and the fourth transmission line (222) are arranged to be individually connected to the center taps (T3, T4) through separate extension lines extended to the left.

[0149] That is, in the case of the third transmission line (221), it is connected to the center tap (T3) through an extension line formed to the left, and a bias voltage (VG2) can be applied through the center tap (T3).

[0150] And, in the case of the 4th transmission line (222), it is connected to the center tap (T4) through an extension line formed to extend to the left, and a bias voltage (VG2) is provided so that it can be applied through the center tap (T4).

[0151] At this time, the third transmission line (221) and the fourth transmission line (222) can be magnetically coupled to form a mutual inductance of polarity. In this case, the actual inductance of the third inductor (L3) and the fourth inductor (L4) implemented in the second layer (220) increases, so that the transmission line length of the balun transformer (200) can be minimized, and this can contribute to miniaturizing not only the balun transformer (200) but also all amplifiers including it.

[0152] For reference, the first layer (210) and the second layer (220) are stacked vertically, and the lines (211, 212) of the first layer and the lines (221, 222) of the second layer, which are opposed to each other, can be vertically magnetically coupled.

[0153] To explain more specifically, the first transmission line (211) may be arranged to be stacked on the third transmission line (221), and the second transmission line (221) may be arranged to be stacked on the fourth transmission line (222). Accordingly, the first amplified signal flowing on the first transmission line (211) and the second transmission line (212) may be induced on the third transmission line (221) and the fourth transmission line (222), respectively.

[0154] When the first amplified signal is induced to the third transmission line (221) and the fourth transmission line (222), the first amplified signal induced through each of the two ends (E3 and E4) extending to the right can be output to the output terminal (150) connected to the rear end of the balun transformer (200).

[0155] Meanwhile, the transformer (200) may be provided with either the first layer (210) or the second layer (220) as a top metal layer. The top metal layer refers to M9 among the nine metal layers, M1 to M9, used in the CMOS process, and is thicker and has a wider cross-sectional area than other metal layers, resulting in superior power transfer efficiency.

[0156] More specifically, by providing the first transmission line (211) and the second transmission line (212) configured in the first layer (210) as a top metal layer, it can contribute to increasing the efficiency of transmission of the amplified signal between the first amplifier stage (120) and the second amplifier stage (130).

[0157] The proposed balun transformer (200) has been described limited to the connection terminal (140) of the power amplifier configuration described above, but the three-dimensional stacked structure of stacked inductors configured in the balun transformer (200) can of course also be applied to the input terminal (110) or output terminal (150) balun transformer.

[0158] <Description of the performance of a power amplifier to which the balun transformer proposed by the present invention is applied>

[0159] Figures 6 and 7 are reference diagrams showing simulation results to explain the effectiveness of the power amplifier proposed by the present invention.

[0160] First, Fig. 6 illustrates the load-pull simulation results of the power amplifier proposed by the present invention.

[0161] Figure 6a shows the simulation results of finding the impedance point that indicates the maximum output power by measuring the output power of each transistor configured in the power amplifier while changing the output impedance.

[0162] And, Fig. 6b shows the load-pull simulation results at a specific operating frequency (e.g., 14 GHz).

[0163] Using the results shown in Fig. 6a, the impedance point at which maximum output power is achieved is found, and power matching is performed accordingly. Fig. 6b illustrates the simulation results for the power amplifier finally manufactured with reference to the results shown in Fig. 6a.

[0164] In particular, the closer the real part of the input impedance value is to 50 Ω and the closer the imaginary part value is to 0, the higher the output voltage and power efficiency.

[0165] Referring to this, the simulation result of Fig. 6b shows a significant result indicating that the performance of the power amplifier (100) proposed by the present invention is excellent, as the real part value of the input impedance is close to 50 at 52.62.

[0166] Next, FIGS. 7a to 7f are graphs showing six representative indices indicating the performance of the power amplifier (100) proposed by the present invention.

[0167] Figure 7a shows the results of the power added efficiency (PAE) of a power amplifier through one-tone harmonic simulation.

[0168] Figure 7b shows the results of the 1-tone harmonic simulation for P1dB (1dB Compression Point), which is the output power level at which the gain of the power amplifier is reduced by 1 dB.

[0169] Figures 7c to 7f illustrate results regarding gain, stability, input return loss, and output return loss according to frequency change of the power amplifier, respectively.

[0170] For reference, the simulation results illustrated in Fig. 7 were derived in a frequency range of 13 to 15 GHz (hereinafter referred to as “target frequency”). In particular, the simulations illustrated in Figs. 7a and 7b show the results of sweeping the target frequency in 1 GHz units (S1: 13 GHz, S2: 14 GHz, S3: 15 GHz).

[0171] The graphs illustrated in Figures 7a to 7f suggest that the power amplifier (100) proposed by the present invention exhibits excellent performance overall, including linearity, PAE, maximum output, and stability. Since those skilled in the art will likely have no difficulty understanding the simulation results illustrated in Figure 7, a detailed description thereof will be omitted.

[0172] As a result, the simulation results shown in FIGS. 6 and 7 indicate that the power amplifier (100) proposed by the present invention can be miniaturized while ensuring performance equivalent to or improved over existing amplifiers.

[0173] As described above, the specific description of the present invention has been made by way of embodiments with reference to the drawings, but since the above-described embodiments have only described preferred examples of the present invention, the present invention should not be understood as being limited to the above-described embodiments, and the scope of the rights of the present invention should be understood by the claims described below and their equivalents.

Claims

1. An input terminal that receives a single signal and converts it into a differential signal; A first amplifier stage that receives the differential signal from the input terminal and generates a first amplified signal by amplifying the received signal; A second amplifier stage that receives the first amplification signal from the first amplifier stage and generates a second amplification signal by amplifying the first amplification signal; A connection terminal that transmits the first amplification signal generated in the first amplification terminal to the second amplification terminal by coupling between the first amplification terminal and the second amplification terminal; and An output terminal that receives the second amplification signal from the second amplification terminal and outputs the second amplification signal, which is a differential signal, as a single signal; characterized in that it includes; amplifier.

2. In paragraph 1, The above first amplifier stage, A plurality of amplifiers that amplify the differential signal converted by the input terminal to generate the first amplified signal; At least one of the above multiple amplifiers is characterized in that it is configured as a common source structure that operates differentially, and is composed of a pair of transistors that receive the differential signal as a gate terminal and have a source terminal grounded. amplifier.

3. In paragraph 2, The above connection terminal is, A first coupling unit whose ends are electrically connected to the first amplifier stage; and A second coupling unit, wherein both ends are electrically connected to the second amplifier stage; The above first coupling part, Inductors (hereinafter referred to as “inductors of the first coupling section”) are provided in a number corresponding to the plurality of amplifier sections, and each end thereof is connected to each drain terminal of a pair of transistors configured in each of the plurality of amplifier sections; The above second coupling part, It includes inductors (hereinafter referred to as “inductors of the second coupling section”) that are coupled in a 1:1 matching manner with the inductors of the first coupling section that are provided in a number corresponding to the above-mentioned plurality of amplifiers, The first amplification signal applied to the first coupling unit is characterized in that it is transmitted to the second amplification stage by coupling between the inductors of the first coupling unit and the inductors of the second coupling unit. amplifier.

4. In paragraph 3, The inductors provided in at least one of the first coupling part and the second coupling part are characterized in that they form a mutual inductance of polarity. amplifier.

5. In paragraph 4, The above connection terminal is characterized in that it is a balun transformer for an amplifier formed by integration into a single chip through a complementary metal-oxide semiconductor (CMOS) process. amplifier.

6. In paragraph 5, The above connection terminal is, A first layer in which metal lines (hereinafter referred to as “lines of the first layer”) for implementing the inductors of the first coupling section are arranged at a predetermined interval on a plane so that they are horizontally magnetically coupled to each other; and A second layer in which metal lines (hereinafter referred to as “lines of the second layer”) for implementing the inductors of the second coupling section are arranged at a predetermined interval on a plane so that they are horizontally magnetically coupled to each other; The first layer and the second layer are stacked vertically, and the lines of the first layer and the lines of the second layer, which are opposed to each other, are characterized in that they are vertically magnetically coupled. amplifier.

7. In paragraph 5, Characterized in that one of the first layer and the second layer is a top metal layer. amplifier.

8. A balun transformer for an amplifier formed by integration into a single chip through a complementary metal-oxide semiconductor (CMOS) process. A first layer in which metal lines (hereinafter referred to as “lines of the first layer”) for implementing a plurality of inductors (hereinafter referred to as “inductors of the first coupling section”) for receiving a differential signal are arranged at a predetermined interval on a plane so that they are horizontally magnetically coupled to each other; and A second layer is provided with metal lines (hereinafter referred to as “lines of the second layer”) for implementing a plurality of inductors (hereinafter referred to as “inductors of the second coupling section”) for outputting a differential signal received from the first coupling section by being coupled to the first coupling section, and are arranged at a predetermined interval on a plane so that they are horizontally magnetically coupled to each other; The first layer and the second layer are stacked vertically, and the lines of the first layer and the lines of the second layer, which are opposed to each other, are characterized in that they are vertically magnetically coupled. Balun transformer for amplifier.

9. In paragraph 8, The first layer is formed such that both ends of the lines of the first layer are extended to one side, and the differential signal is input through both ends extended to one side. The second layer is characterized in that both ends of the lines of the second layer are formed to extend to the other side, and the differential signal received from the lines of the first layer is output through the ends extended to the other side. Balun transformer for amplifier.

10. In paragraph 8, Characterized in that one of the first layer and the second layer is a top metal layer. Balun transformer for amplifier.

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