CXL native memory

Abstract

Versatile high-performance memory systems capable of supporting high-speed data transfer for various memory types and flexible data formats is disclosed. In particular, the memory system corresponds to a native memory device which comprises a memory array and a memory controller coupled to the memory array via a native memory interface. The memory controller comprises a CXL (Compute Express Link) interface to connect the memory controller to one or more connected devices, and the native memory interface supports only minimal logic for the memory array. Furthermore, the memory array and the memory controller are configured to translate packet information received via the CXL interface into direct memory cell control information and access data on the memory array according to the direct memory cell control information.

Description

CXL Native MemoryCROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present invention is a non-Provisional Application of and claims priority to U.S. Provisional Patent Application No. 63 / 539,805, filed on September 21, 2023. The U.S. Provisional Patent Application is hereby incorporated by reference in its entirety.FIELD OF THE INVENTION

[0002] The Subject innovation relates generally to memory systems and in particular, to systems and methodologies that can facilitate the utilization of a memory module as a target device that can operate in response to instructions and data received from an external processorBACKGROUND AND RELATED ART

[0003] For decades, Double Date Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) memory has been the undisputed leader for main memory. It offers versatility, being used to construct memory modules like Dual In-Line Memory Modules (DIMMs) for traditional computing systems, as well as directly integrated into embedded systems or specialized platforms.

[0004] However, the improvement offered by DDR memory interfaces has diminished over time. Typical systems circa 2000 allowed four DIMMs to be daisy chained on a memory channel. By late that decade, the electrical challenges from speed increases forced a reduction to three DIMMs, and down to two in the decade to follow. The next generation of DDR DIMMs will reduce support to a single DIMM on a channel. During that time, per-DRAM capacity improvedfrom 64 megabits per device to 16 gigabits per device, however that improvement has degraded from a quadrupling every 3 years to quadrupling every 15 years. This leaves a significant gap between the needs of computing systems and memory available for new applications. This is generally referred to as the “memory wall”.

[0005] One emerging approach to addressing the memory wall is Compute Express Link (CXL), an open standard designed for high-speed, high-capacity connections between CPUs and various devices including memory, storage, and communications. CXL builds upon the serial PCI Express (PCIe) interface and provides three distinct protocols: CXL. io, CXL. cache, and CXL. mem. CXL. io is the superset of traditional PCIe and manages configuration, device discovery, RDMA (Remote Direct Memory Access), and I / O operations efficiently. CXL. cache is designed to minimize latency as it allows peripheral devices to coherently access and cache the host-attached memory. CXL. mem enables host CPUs to access device memory in a coherent manner using load / store commands, where the memory in a CXL device could be either volatile memory (e.g., RAM) or non-volatile memory (e.g., flash memory).

[0006] Universal Chiplet Interconnect Express (UCIe) is a variant of CXL optimized for bare chips mounted on a shared substrate. The concepts in this invention apply to UCIe as well as CXL.

[0007] The DDR SDRAM interface and the DIMMs that deploy DDR are optimized to only support the DDR protocol in a deterministic fashion: all timing is predictable and under the control of the processor to which is it attached. DDR is half duplex, only allowing reads or writes but not both simultaneously. Unlike DDR, CXL is non-deterministic. Requests for reads or writes may be completed immediately upon receipt or may be delayed. This flexibility allows for new memory media types and operations, isolating the memory protocol from the CXL protocol. CXL also supports full duplex operation, with reads and writes occurring at the same time.

[0008] In this disclosure, we disclose an innovative memory solution referred to here as "CXL native memory", which can offer various new features to fulfill the needs for flexible highspeed memory.BRIEF SUMMARY OF THE INVENTION

[0009] In this invention, we disclose the concept and architecture of CXL native memory. In practice, CXL native memory can come in various form factors such as a chip or a chiplet. What truly makes this memory architecture different is its ability to directly interface with CXL- capable hosts or CXL switches. At its core, CXL native memory consists of a CXL controller chiplet and one or more memory units. The access port from the host, such as a CPU or switch, is via CXL. Memory is accessed through the CXL native memory logic on one or more memory ports. Rather than use a standard DDR memory interface, including DDR or LPDDR, the memory unit interfaces are driven directly by the CXL native memory control logic which translates the CXL packet information into direct memory cell controls such as banks, rows, and columns.

[0010] Also unique to this invention is the dual use of CXL. mem protocol for high performance low latency memory access while also using CXL. io protocols for extended functions that are not as latency sensitive, including feature control. Memory allocation protocol executed over CXL .io is used for determining the valid state of memory regions, which can advantageously enable or disable accesses to the memory array regions. These extended features include processing in memory (PIM) functions including fill and matrix operations; memory regions beyond the power-of-2 sizes typically provided; on the fly definition of trimmed memory blocks; combinations of refresh and error check scrub functions; refresh control that incorporates attack vector amelioration.

[0011] The present invention refers to the memory chip architecture that employs either aCXL or UCIe-compliant interface on a host port and one or more memory control interfaces. The CXL native memory controller derives sufficient information from the CXL packets to optimally drive memory allocation and distribution to align with the CXL data packet load of 64 bytes, including distributing the payload across one or more memory devices or interfaces. Typical DDR restrictions, such as “page size” (the number of bits accessed on core activations), or “burst length” (the number of word-wide transfers for each read or write access) need not be used by the CXL native memory controller. Instead, memory accesses are optimized for the CXL data packet sizes.

[0012] Error correction codes (ECC) and metadata (data stored alongside application data to indicate system-specific modes) are typically fixed in DDR interfaces and do not align well with CXL packets. CXL native memory may allocate ECC and metadata regions in the memory units in configurations not feasible with DDR memories. For example, any ECC or RAID parity that can enhance device reliability can be placed in a designated position among memories as every positions are manageable for the allocation and deallocation by CXL native memory controllers.

[0013] CXL native memory controllers introduce more intelligent refresh management, a notable difference from traditional DDR memory. Conventional DDR memory relies on a periodic refresh mechanism, implemented based on address counters on each DRAM for the data retention. On-DRAM refresh counters are limited to only managing refresh functions; specifically, they do not incorporate support for error check scrub or security attack actions.

[0014] Moreover, the controller will be limited further when self-refresh mode is enabled. However, the CXL native memory controller can take full charge of the refresh process. For example, it can replace standard refresh commands with tailored-range refresh commands, strategically designed for power conservation or performance enhancement. DRAM error check scrub which corrects data which may have been corrupted may be merged with standard refresh operations to increase data reliability. DDR functions such as Directed Refresh Management(DRFM) which detect and ameliorate malicious software attacks such as rowhammer are replaced by counters built into the CXL native memory controller, and data integrity is managed by the controller logic. This includes detection of attack victim regions and refresh of victim regions and adjacent regions. Unused memory regions may also be excluded from attack protection, reducing power loss.

[0015] Leveraging CXL protocols, including CXL. mem, CXL. io, and CXL. cache, CXL native memory enhances memory functionality. For example, beyond efficient memory access through CXL. mem, CXL native memory can introduce a number of "application" commands via CXL. io and CXL. cache. For example, a block-fill command to populate memory address regions with specific data patterns may be combined with program-defined metadata, streamlining software programming and enhancing the usefulness of the memory array. Another example is that the memory can support periodic memory check scrubbing operations to check memory health across memory address ranges interspersed with standard refresh commands in order to achieve a scrubbing of all memory over a user-defined time period without unduly burdening memory performance. This error check scrub function can detect unrepairable memory as well and initiate DRAM repairs such as row replacement. These additional benefits enabled by CXL native memory can enhance memory versatility and efficiency, which caters to diverse applications and systems.BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Fig. 1 illustrates the architecture for CXL native memory with CXL interface connected directly to a Host (e.g., CPU) or to a CXL Switch

[0017] Fig. 2 illustrates the architecture for CXL native memory with UCIe interface

[0018] Fig. 3 illustrates the architecture for CXL native memory with dual interfaces

[0019] Fig. 4 illustrates the example of memory data allocation over different memory components

[0020] Fig. 5 illustrates an example implementation of trim command in CXL native memory

[0021] Fig. 6 illustrates an example implementation of block-fill command in CXL native memory

[0022] Fig. 7 illustrates an example implementation of a PIM multiply-accumulate (MAC) command in CXL native memory

[0023] Fig. 8 illustrates an example implementation of CXL native memory with nonvolatile memory (e.g., flash) only or both volatile memory (e.g., DRAM) and non-volatile memory (e.g., flash)

[0024] Fig. 9 illustrates an example implementation of CXL native memory with both volatile and non-volatile memories with an external energy source provided to maintain data persistence for the volatile memory during power failureDETAILED DESCRIPTION OF THE INVENTION

[0025] The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0026] CXL connections enable configurations that are difficult or impossible for DDR DIMMs including memory pooling and memory sharing. However, CXL does not displace DIMMs in all applications, but typically provides a path for memory expansion, therebyalleviating the memory wall. Data centers are likely, though not required, to have memory both on DIMMs and on CXL

[0027] For non-data center applications, such as mobile computers, direct connection to LPDDR devices are more common than DDR, and while memory expansion may be a secondary requirement, a small physical size and very low power are primary requirements. In these applications, a CXL memory solution would likely replace the LPDDR rather than be in addition to it.

[0028] Memory expansion allows for the seamless scaling of memory capacity to meet evolving workload demands. Memory pooling optimizes resource utilization and ensures memory is allocated where needed most, avoiding stranded memory. Memory sharing enables multiple processors to access the same memory pool, reducing redundancy and latency. These capabilities in modem computing environments are particularly valuable in the context of server environment.

[0029] This approach can enable the establishment of a direct link between the host processor and a memory chip equipped with a CXL interface or through a switch fabric. CXL native memory presents a combination of CXL controller and memory that combines various aspects of the CXL interface to enhance the use of the memory behind it. These features include direct translation of the address and data information contained in the CXL command packets to memory cell addresses and contents; power reduction features; memory access optimizations; combinations of error correction codes and metadata for end user applications; combinations of volatile and non-volatile memories.

[0030] Where DDR DIMMs are always a direct attachment to a processor, the CXL connection may be direct from processor to CXL module, or over a switch fabric that allows multiple processors to access multiple memory resources.

[0031] In this disclosure, we first define our invented architecture for CXL native memory. As illustrated in Fig. 1 A and Fig. IB, the core of CXL native memory 110 shall export a CXL interface, and ensures compatibility with CXL protocols like CXL. io and CXL. mem. This interface plays the role in establishing direct connections between CXL native memory 110, and either host processors 120 (Fig. 1A) or a port of a CXL switch 130 (Fig. IB). Within the CXL native memory 110, there are two key components inside: CXL controller 112 and native memory array 114 (also call “naked” memory array in this disclosure, where native (naked) is defined as a memory array with minimal logic such as word line and bit line drivers and receivers, but lacking standard DRAM control functions such as decoders and refresh counters. The memory array may include row activation counters, however the response to row activation violations are executed in the memory controller chip and not the naked memory array. The CXL controller shall incorporate memory cell control logic and be capable of directly managing the memory array 114. The interface connecting the CXL controller 112 and memory array 114 is versatile and supports various memory configurations. For example, the memory array may be on separate chips connected to the CXL native controller chip, or may be integrated into the same chip. The memory array may be DRAM, MRAM, PCRAM, or any other memory core technology and the memory control logic in the CXL native controller will adapt the protocol to match the memory array type.

[0032] CXL is a non-deterministic protocol. This means that it allows for an arbitrary time period between the reception of a read or write command on the host port and the completion of the read or write to the memory array on the memory port by controlling when completion responses are sent to the host. Other industry interfaces such as UCIe and others are similarly non-deterministic. This invention substantially assumes a non-deterministic host port, and therefore may be adapted to use any of these interfaces as a host port. In contrast, DDR SDRAM protocols such as DDR5, LPDDR5, HBM, and others are deterministic and require a more restricted response timing to read and write requests and therefore make native memory controlmore difficult or impossible. One important feature of volatile memory array such as DRAM is the strict requirement for host-directed refresh operations, whereas non-deterministic protocols require the remote memory controller to perform refresh and delay read or write responses to the host until the refresh completes.

[0033] Ideally, the architecture of CXL native memory provides abundant internal bandwidth to ensure that it does not become a performance bottleneck. For example, if the CXL native memory adopts a 32GB / s bandwidth host interface (based on PCIe Gen5 with 8 lanes), the internal bandwidth connecting the CXL controller and memory dies should meet or exceed 64GB / s. This internal interface design accommodates the full-duplex nature of the host CXL interface and generates a combined 64GB / s bandwidth demand to memory dies internally. CXL native memory controllers may include multiple data write buffers to retain data on-chip while waiting for the memory array to be available, such as during refresh operations or when used with memory types with long write recovery times. The non-deterministic nature of the CXL protocol allows for throttling of the interface to accommodate the timing of emptying the write buffers.

[0034] The memory device within CXL native memory can be volatile memories, nonvolatile memories, or a combination of both.

[0035] If CXL native memory opts for volatile memories, such as DRAM or SRAM, it functions like a conventional main memory. This configuration can offer a moderate memory capacity with excellent access performance. Conversely, adopting solely non-volatile memories like flash memory or emerging memory technologies in CXL native memory, it can offer persistency that data remains intact even in the event of a power loss.

[0036] One option involves using both non-volatile and volatile memories within CXL native memory. In this scenario, volatile memories can function as a cache for non-volatile memories.

[0037] This arrangement strikes a good balance between the cost and the performance. The actual implementation can vary, tailored to specific objectives and optimization goals according to diverse application needs. If data persistence is required for the volatile memory region, external energy sources can be supplied to keep the memory valid. The volatile memory may also be copied to non-volatile memory during this energy sourced period.

[0038] Fig. 2 illustrates one embodiment wherein CXL native memory 110 exports a UCIe compliant interface so that CXL native memory can be integrated with other UCIe-compliant chiplet 220 on a same substrate 210. Nevertheless, other packaging technologies may also be used for the native memory device. For example, the memory array and the memory controller can be integrated on the same chip. Tn another example, the memory array and the memory7controller can be on separated dies, but packaged directly on top of each other, which is called 3D packaging. This invented configuration retains full compatibility with CXL protocols while ensuring compliance with die-to-die serial-bus interconnect standards. In this configuration, the embodiment can be compatible with other UCIe-compliant chiplets or chips featuring UCIe interfaces.

[0039] Fig. 3 further depicts an embodiment where CXL native memory 310 exports both a CXL interface and a DDR interface. For example, the CXL native memory can be connected to Host 310 through both the CXL interface and the DDR interface. In this scenario, the DDR interface can be utilized for typical memory access and probably can meet low-latency requirements for some specific applications. On the other hand, in addition to memory access (using CXL. mem), the CXL interface can handle a series of background operations (using CXL. io or CXL. mem), such as DMA, error checking, or high-level protocol access (e g., NVMe). This example embodiment of CXL native memory can enhance memory with more functionality and adaptability to diverse computing needs. One possible implementation is that the DDR interface will connect to a part of the DDR memories while the CXL controller manages the remaining memories.

[0040] In contrast to typical DDR memory interfaces that require the conversion of incoming memory addresses into a rank-bank-row-column format, the CXL controller embedded into the CXL native memory can have high flexibility. For example, the CXL controller within the CXL native memory can accept Flow Control Unit (FLIT) addresses in a linear format and have the freedom of mapping them in any desired way into the memory array. For example, the native memory can align the memory array interface with FLIT size.

[0041] Fig. 4 provides an embodiment example of memory data allocation across various memory components. The memory access unit is 64 bytes in CXL FLIT protocol. With the full control of memory dies within CXL native memory (410 in Fig. 4A and 420 in Fig. 4B), the CXL controller (412 in Fig. 4A and 422 in Fig. 4B) can dictate data layouts and bit locations. In the illustrated example, four 16 byte portions of a 64-byte data unit are allocated to four different memories (414a-d) in Fig. 4A. In Fig. 4B, each 64-byte data unit is allocated to a single memory 424a among the four different memories (424a-d). Other combinations of data allocation are also supported. The allocation strategy shall take into account memory characteristics such as performance and power efficiency. CXL also provides for a larger 256-byte FLIT which may be operated on as four-64 byte FLITs.

[0042] In addition to the conventional memory access provided by CXL. mem, the architecture of CXL native memory can introduce a range of innovative "application" commands facilitated by CXL. io, CXL. mem, and CXL. cache. These application commands can be tailored to various use cases, significantly enhancing the capabilities of CXL native memory. In this disclosure, we will introduce three exemplary embodiments of these application commands. In order to support these innovative "application" commands, the CXL native memory according to the present invention is configured to support some key operations comprising refresh control, error check scrub, or any combination of them.

[0043] Fig. 5 illustrates one implementation of the "trim" command in CXL native memory510, where the CXL native memory 510 is connected to host 520 via CXL interface. The CXL native memory 510 comprise a CXL native memory controller 512 and memories 514. In this illustration, without loss of generality, each memory is an array 514’ consisting of numerous memory rows, and each row is composed of tens, hundreds, or even thousands of bits for access. The "trim" application command, sent over CXL, provides a unique advantage by allowing the controller to identify memory rows that can be freed based on the software or the host knowledge. If a particular memory row no longer stores valid data or is freed by any user, the CXL native controller can choose not to refresh that row during the subsequent refresh process. This command has the potential of eliminating many unnecessary refresh operations and can enhance both access performance and power efficiency. Methods for trimming memory, or conversely marking memory regions as valid, may be initiated by operating system free() or malloc() calls, respectively, or to CXL memory pool or memory share free and allocate functions.

[0044] In contrast to current DDR memory capabilities, which offer a limited "pattern write" feature with the ability to fill an area with just 64 or 128 bits, the block-fill command in CXL native memory can offer a better performance benefit. Fig. 6 provides an exemplary embodiment of an application command within CXL native memory 610: the "block-fill" command, where the CXL native memory 610 is connected to host 620 via CXL interface. The CXL native memory 610 comprise a CXL native memory controller 612 and memories 614. In this example, the block-fill command, sent over CXL, utilizes a predefined data pattern, such as the pattern "01010," to efficiently fill specified rows, i.e., rows E and F of the memory array 614’. For scenarios that require a large memory region filled, this command drastically reduces software initialization time. Unlike other industry block fill functions, since the CXL native controller incorporates metadata in the memory array interfaces, it provides more flexible control over content of the metadata during block fill operations which may include content such as ownership, time stamp, or other essential metadata as defined by the user application.

[0045] The CXL controller embedded within CXL native memory is capable of executing PIM functions on memory regions. These PIM functions are versatile, ranging from general- purpose tasks like search operations to advanced artificial intelligence functions such as matrix operations. Fig. 7 illustrates an exemplary application command within CXL native memory 710: the Processing in Memory (PIM) command, where the CXL native memory 710 is connected to host 720 via CXL interface. The CXL native memory 710 comprise a CXL native memory controller 712 and memories 714 (with detailed view of the memory array 714’). As these functions may be accessed over the CXL. io protocol, they act independently of the memory interface CXL. mem, allowing for both operations to be used simultaneously, and the CXL native controller manages interactions to prevent data corruption.

[0046] The CXL native memory device can also perform effective rowhammer attack rowhammer mitigation by incorporating Rowhammer Activation Counters (PRAC) integrated into the memory array, the CXL memory controller receives information regarding status of the PRAC and initiates rowhammer attack mitigation in response to the information regarding the status of the PRAC. For example, the rowhammer attack mitigation comprises invoking the error check scrubbing operation, the memory refreshing operation, or both. As the CXL native memory controller can also operate with non-volatile memories such as MRAM, the rowhammer mitigation operation may be directed to only use error check scrub since refresh is not a valid MRAM operation.

[0047] Fig. 8A, Fig. 8B and Fig. 9 depict the different situations how non-volatile CXL native memory can be supported. Fig. 8A illustrates a non-volatile CXL native memory 810 is composed of CXL native memory controller 812 coupled with non-volatile memory 814 (e.g. MRAM). Fig. 8B illustrates a more universal CXL native memory architecture 820 where the CXL native memory controller 822 is coupled with both volatile memory 826 and non-volatile memory 824, and only a portion of the memory space is non-volatile. Fig. 9 illustrates a differentdesign 910 where the volatile memory 916 is protected by energy source 918 (and controller hardware / firmware) during power outage, and hence the entire memory space can be nonvolatile. For example, when power failure is detected, the CXL native memory controller 912 can be configured to transform certain data or all data in the volatile memory 916 or inside the CXL native memory controller 912 to the nonvolatile memory 914.

[0048] Multiply-accumulate operation, often abbreviated as MAC, plays a key role in numerous machine learning and artificial intelligence applications. Tasks like convolution, matrix multiplication, and neural network inference rely on MAC operations for their computations. CXL native memory can implement a PIM architecture, where memory is enhanced with logic performing MAC operations and other PIM functions.

[0049] As depicted in the example, the host sends a PIM command, such as the MAC of rows C and D, to CXL native memory. The CXL controller interprets the command and executes it through a series of memory controller operations. In this implementation, the CXL controller accesses memory to retrieve the specified rows, C and D, storing them in an internal buffer within the controller or into a result row E.

[0050] It is worth noting that this example serves as an illustration. The actual implementation of PIM commands may vary based on factors like memory layout and the specific matrix requirements dictated by the PIM command. This adaptability underscores the versatility and potential applications of CXL native memory in diverse scenarios.

[0051] The above description is presented to enable a person of ordinary skill in the art to practice the present invention as provided in the context of a particular application and its requirement. Various modifications to the described embodiments will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments.Therefore, the present invention is not intended to be limited to the particular embodimentsshown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. In the above detailed description, various specific details are illustrated in order to provide a thorough understanding of the present invention. Nevertheless, it will be understood by those skilled in the art that the present invention may be practiced.

[0052] The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described examples are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims

AMENDED CLAIMS received by the International Bureau on 20 Jan. 2025 (20.01 .2025)1. A native memory device comprising: a memory array; and a memory controller coupled to the memory array via a native memory interface, wherein the memory controller comprises a CXL (Compute Express Link) interface to connect the memory controller to one or more connected devices, and wherein the native memory interface supports only minimal logic for the memory array; wherein the memory array and the memory controller are configured to: translate packet information received via the CXL interface into direct memory cell control information; and access data on the memory array according to the direct memory cell control information; and accept, via the CXL interface, Flow Control Unit (FLIT) addresses in a linear format and map the FLIT addresses into another format to align the native memory interface with FLIT size2. The native memory device of Claim 1, wherein the memory controller and the memory array are disposed on a same substrate.

3. The native memory device of Claim 1, wherein the memory controller and the memory array are connected die-to-die vertically.

4. The native memory device of Claim 1, wherein the memory controller and the memory array are integrated into a same chip.

5. The native memory device of Claim 1, wherein the direct memory cell control information comprises memory banks, memory rows, memory columns, or a combination thereof.

6. The native memory device of Claim 1, wherein the memory controller further comprises a UCIe (Universal Chiplet Interface Express) interface to connect the memory controller to said one or more connected devices.

7. The native memory device of Claim 1, wherein the memory array comprises volatile memory, non-volatile memory, or both.19AMENDED SHEET (ARTICLE 19)8. The native memory device of Claim 7, wherein the memory controller is further configured to enter a safe mode upon detection of system power failure.

9. The native memory device of Claim 8, wherein at least a portion of data stored in the volatile memory is transferred to the non-volatile memory or an external non-volatile memory upon the detection of system power failure.

10. Cancelled.

11. The native memory device of Claim 1, wherein row width of the memory array is aligned to FLIT width.

12. The native memory device of Claim 1, wherein the memory controller is further configured to map wide data to a single memory device or multiple memory devices in the memory array.

13. The native memory device of Claim 1, wherein the memory controller is further configured to receive an application command via the CXL interface, and in response to the application command, if a particular memory row of the memory array no longer stores valid data or is freed by any user, the memory controller stops refreshing the particular memory row of the memory array during a subsequent refresh process.

14. The native memory device of Claim 1, wherein the memory controller is further configured to receive an application command via the CXL interface, and in response to the application command, the memory controller writes a predefined data pattern into one or more particular memory rows of the memory array.

15. The native memory device of Claim 1, further comprising one or more processing units coupled to the memory array and the memory controller is further configured to receive an application command via the CXL interface, and in response to the application command, the memory controller initiates one or more controls to cause data stored in the memory array processed by said one or more processing units.

16. The native memory device of Claim 1, wherein the memory controller is further configured to perform memory refreshing operation, rowhammer detection operation and error check scrubbing operation.20AMENDED SHEET (ARTICLE 19)17. The native memory device of Claim 16, wherein the memory refresh operation is scheduled per requirements of the memory array.

18. The native memory device of Claim 17, further comprising one or more Rowhammer Activation Counters (PRAC) integrated into the memory array, wherein the CXL memory controller receives information regarding status of the PRAC and initiates rowhammer attack mitigation in response to the information regarding the status of the PRAC.

19. The native memory device of Claim 18, wherein the rowhammer attack mitigation comprises invoking the error check scrubbing operation, the memory refreshing operation, or both.21AMENDED SHEET (ARTICLE 19)STATEMENT UNDER ARTICLE 19(1)Claim 1 has been amended to include limitations of Claim 10. According to the International Search Report:“Claims 10-12 meet the criteria set forth under PCT Article 33(2)-(3) because the prior art fails to teach or fairly suggest the particular combination of elements recited in dependent claim 10.Regarding claim 10, none of the prior art teaches the memory controller is further configured to accept, via the CXL interface, Flow Control Unit (FLIT) addresses in a linear format and to map the FLIT addresses into another format to align the native memory interface with FLIT size. ■Claims 11-12 are dependent on claim 10, and therefore meet the criteria for substantially the same reasons.”Accordingly, the amended Claim 1 should be allowable.Claims 2-9 and 11-19 are dependent from Claim 1. At least the same reason as above, Claims 2-9 and 11-19 should be allowable.

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