Linear nitrogen-polar deep-recess GAN mishemts through corrugation

Abstract

A transistor comprising a channel comprising at least one of corrugations, undulations, or a plurality of crystal planes oriented along a direction; a drain contact to the channel; a source contact to the channel; and a gate contact coupled to the channel so as to modulate a flow of current comprising mobile charge carriers between the source contact and the drain contact.

Description

[0001] LINEAR NITROGEN-POLAR DEEP-RECESS GAN MISHEMTS THROUGH CORRUGATION CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit under 35 U.S.C. Section 119(e) of U.S. Provisional Application No.63 / 520,168, filed August 17, 2023, by Henry T. Collins, Emre Akso, Nirupam Hatui, Christopher J. Clymore, Matthew Guidry, Stacia Keller, and Umesh K. Mishra, entitled “LINEAR NITROGEN-POLAR DEEP-RECESS GAN MISHEMTS THROUGH CORRUGATION,” (30794.0839USP1), which application is incorporated by reference herein. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT This invention was made with Government support under Grant Nos. N00014- 23-1-2078 and N00014-23-1-2152 awarded by the Office of Naval Research. The Government has certain rights in the invention. BACKGROUND OF THE INVENTION 1. Field of the Invention. The present disclosure relates to High Electron Mobility Transistors (HEMTs) and methods for making and using the same. 2. Description of the Related Art. Nitrogen-polar deep-recess GaN Metal Insulator Semiconductor High Electron Mobility Transistors (MISHEMTs) have emerged as a leading technology for mm- wave power amplification. Recent results demonstrated a power density of 8.84 W / mm (663 mW) with an associated PAE of 27% [1] and a single-cell W-band power record of 712 mW output power with an associated power density of 7.1 W / mm and 31.7% PAE [2]. Nitrogen-polar GaN is also an appealing candidate for receiver and transceiver applications. Due to a high critical electric field of 3.3 MV / cm, a GaN LNA is inherently more resilient against interference from high-power transmitters than an LNA fabricated using a peer material system such as InP, GaAs, or SiGe. Linearity can be assessed by the metric of OIP3 / PDC. OIP3 is expressed to first order in terms of the dominant source of nonlinearity, which is the transconductance (gm), as where g3m is the cube of the first order transconductance, gm3is the third order transconductance, and RLis the load resistance [3]. OIP3 scales to first order with gate periphery, i.e. a device with double the periphery and power consumption (PDC) will have double the OIP3, so OIP3 / PDCis the preferred figure of merit. A simultaneously high gmand low gm3are desirable to maximize OIP3. Other work explored the mm-wave linearity of GaN MISHEMTs. A high OIP3 is achievable if the amplifier is biased near the gm3zero crossing. In the Nitrogen-polar orientation, Shrestha et al. and Guidry et al. demonstrated peak OIP3 / PDCvalues of 15 dB and 20 dB, respectively, as measured by 30 GHz two-tone load-pull measurements [4], [5]. In the Ga-polar orientation, Moon et al. demonstrated an OIP3 / PDCof 20 dB at 30 GHz [6]. However, for circuit applications, an OIP3 / PDCpeak which is broad with respect to gate bias is desirable. A broad OIP3 / PDCpeak mitigates the sensitivity of linearity to changes in bias or threshold voltage shifts. One other method to linearize the device and broaden its OIP3 / PDCpeak is to combine devices with different threshold voltages realized through different gate recess depths (US20210399121A1), but this has the drawback of requiring more complex fabrication processes. What is needed, then, are improved methods of making linear HEMT devices. The present invention satisfies this need. SUMMARY OF THE INVENTION Nitrogen-polar Gallium Nitride (GaN) High electron mobility transistors (HEMTs) are well-established as a key technology in amplifiers for modern high- speed communication systems. In such communication systems, amplifier linearity is essential. Linear amplification prevents distortion from spurious signals with frequencies which are close to that of the fundamental tone. A common metric for evaluating amplifier linearity is OIP3 / PDC, where OIP3 is the output-referred 3rd order intercept point and PDC is the DC power, and higher values of OIP3 / PDC are better. Reducing the third-order transconductance of the amplifier directly improves OIP3 / PDC. One method to accomplish this is derivative superposition. At the device (transistor) level, a changing threshold voltage along the width of the gate reduces the third-order transconductance by reducing the slope of the first-order transconductance. In this invention, derivative superposition is implemented through surface undulations induced by step-bunching due to metal organic chemical vapor deposition (MOCVD) epitaxial growth on a miscut SiC substrate. This is deemed 'Corrugation'. Such an approach to improving linearity differs from circuit-level or other device-level methods. Corrugated Nitrogen-polar GaN MISHEMTs demonstrated an OIP3 / PDC which is robust against changes to gate bias. Linearity which is relatively insensitive to changes in gate bias is useful for circuit applications. Illustrative embodiments of the present invention include, but are not limited to, the following. 1. A transistor, comprising: a channel comprising at least one of undulations or a plurality of crystal planes oriented along a direction; a drain contact to the channel; a source contact to the channel; and a gate contact coupled to the channel so as to modulate a flow of current comprising mobile charge carriers between the source contact and the drain contact. 2. The transistor of clause 1, wherein the undulations or crystal planes modulate or vary a threshold voltage of the transistor across the gate width so as to tailor a transfer characteristic of the transistor structure. 3. The transistor of clause 1, wherein the undulations or crystal planes modulate or vary a threshold voltage of the transistor across the gate width so as to tailor linearity of the transistor. 4. The transistor of any of the clauses 1-3, wherein the transistor is a High Electron Mobility Transistor (HEMT) or MISHEMT, a field effect transistor (e.g., metal oxide semiconductor field effect transistor MOSFET or metal insulator semiconductor field effect transistor MISFET), and the gate is coupled to the channel via a dielectric, a p-n junction, or a Schottky barrier. 5. The transistor of any of the clauses 1-3, wherein the transistor is a III- Nitride HEMT. 6. The transistor of any of the clauses 1-3, wherein the transistor is an N- polar III-Nitride HEMT. 7. The transistor of any of the clauses 1-6, wherein the undulations have peaks and valleys that are aligned nearly (e.g., within 10 degrees of) along the <11- 20>(i.e., the peaks and valleys are nearly perpendicular to the <-1-100> direction). 8. The transistor of any of the clauses 1-6, wherein the undulations are random having no specific direction. 9. The transistor of any of the clauses 1-8, wherein the gate width is nearly (e.g. within 10 degrees of) parallel to the peaks and valleys of the undulations / step bunching (i.e., the current can flow along the peaks and valleys). 10. The transistor of any of the clauses 1-9, wherein the transistor structure is grown on a substrate comprising a vicinal substrate having an orientation or miscut along a direction and the undulations comprise step bunching formed or induced by growth on the vicinal substrate. 11. The transistor of any of the clauses 1-10, wherein the undulations or crystal planes vary at least one of the parameters: electron charge density, threshold voltage, or gate capacitance along the gate width to tailor a transfer characteristic. 12. The transistor of any of the clauses 1-11, wherein an angle of the gate width to the direction is configured to achieve derivative superposition. 13. The transistor of any of the clauses 1-12, wherein the direction at least reduces a slope of the transconductance as compared to transistor without the undulations. 14. The transistor of any of the clauses 1-13, wherein the undulations are configured (e.g., size, orientation, spacing) such that the transistor has a magnitude of gm3 / (gm)3of less than 2.5x10-7(mm2 / A2) over a drain current range of 0.25 to 0.8 A / mm. 15. The transistor of any of the clauses, wherein the transistor has a gate length of 5 nm-1000 nm and a channel length of 10 nm- 2000 nm. 16. The transistor of any of the clauses, wherein the undulations comprising step bunches comprise a plurality of steps or terraces between the source and the drain, wherein a spacing between the undulations is periodic or non-periodic. 17. A transistor, comprising: a channel comprising a III-nitride material comprising a crystal having a plane within 15 degrees of the Nitrogen-polar (000-1) plane or a gallium polar (0001) plane, wherein the channel comprises at least one of undulations oriented or multiple crystal planes oriented along a direction; a source contact and a drain contact to the channel; coupled to the channel so as to modulate a flow of current comprising mobile charge carriers between the source contact and the drain contact, wherein the gate contact has a gate width perpendicular to the flow 18. The transistor of clause 17, wherein: the III-nitride material comprises one or more layers of ScvGawAlxInyBzN where 0≦v≦1, 0≦w≦1, 0≦x≦1, 0≦y≦1, 0≦z≦1, and v+w+x+y+z=1 19. The transistor of clause 17 or 18, wherein: the channel comprises GaN comprising a two dimensional electron gas or a two dimensional hole gas confined in the channel by a back barrier; a cap comprises a cap structure on the channel and the cap structure comprises a second material including: a first aluminum containing nitride layer on or above the channel; a first GaN layer on or above the first aluminum containing nitride layer; 20. The transistor of any of the clauses 1-19 comprising the transistor structure of any of the clauses 16-18. 21. The transistor of any of the clauses operating a frequency greater than 1MHz. 22. A method of making a transistor, comprising: growing a heterostructure comprising a channel layer and a barrier layer on a buffer layer on vicinal or miscut substrate under growth conditions that induce step bunching in the channel layer or the barrier layer or both, wherein the miscut or vicinal substrate has a growth surface oriented at an angle in a direction; forming a source contact and a drain contact to the channel layer; and depositing a gate contact on the channel layer, the gate contact for modulating a flow of current comprising mobile charge carriers between the source contact and the drain contact, so that the gate contact has a gate width perpendicular to the flow. 23. The method of clause 22, wherein the conditions include growing on a miscut more than 2 degrees under equilibrium conditions for growth of the crystal (high temperature, low precursor flow for low growth rate) 24. The method of clause 21 or 22, wherein: the heterostructure comprises: an N-polar III-Nitride structure comprising: a III-nitride barrier layer on or above a substrate; a III-nitride channel layer on the III-nitride barrier layer, wherein the barrier layer confines mobile charge carriers in the channel layer; optionally a III-nitride cap on the channel layer, forming the gate comprises: etching a recess having a depth profile in the III-nitride cap layer using lithographic patterning; and depositing gate metal in the recess. 25. The method of any of the clauses 22-24, further comprising depositing passivation above the cap. 26. The method of any of the clauses 22-25, wherein the heterostructure is grown by MOCVD. 27. The transistor of any of the clauses 1-21 manufactured using the method of any of the clauses 22-26. 28. A receiver (e.g., comprising at a minimum a low-noise amplifier), transmitter (e.g., comprising at a minimum a power amplifier) comprising the transistor of any of the clauses 1-27. 29. The transistor of any of the clauses 1-28, wherein the undulations have a height in a range of 1-100 nm and a peak-to-trough spacing in a range of 10-10000 nm. 30. The transistor of any of the clauses 1-29, wherein the transistor and the channel comprise any elemental (e.g. Silicon) or compound semiconductor (e.g. Gallium Arsenide). BRIEF DESCRIPTION OF THE DRAWINGS The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee Referring now to the drawings or figures (fig.) in which like reference numbers represent corresponding parts throughout: Fig.1: AFM scan of a 3x3 µm2region of the 2.5 nm Al0.28Ga0.72N etch stop layer situated directly above the GaN channel.. Surface undulations with a peak-to- trough spacing of approximately 20 nm suggest that the channel is corrugated. Gate width was oriented along the direction. Fig.2A: Cross-sectional schematic of the Corrugated HEMT. Undulations occur in the direction of the gate width in this demonstration. Fig.2B. Schematic showing orientation of undulations with respect to gate (e.g. in Fig.2A) and current flow in one or more examples, wherein the undulations are parallel to the gate width (into the page) Fig.2C. A cross-sectional TEM captured by Eurofins EAG Laboratories taken along the direction showing the GaN channel thickness ranged from to . Channel thickness varied significantly along the gate fingers of the MISHEMTs, resulting in a superposition of continuously varying threshold voltages. Fig.2D. A top-view microscope image of a completed MISHEMT Fig.3: DC transfer characteristic exhibiting a peak transconductance of 434 mS / mm. Fig.4A: DC output characteristic exhibiting an Imaxof 2.03 A / mm at VGS= 1V and VDS= 6V. Fig.4B. Large-area recessed profile of a standard N-polar MISHEMT (blue) and corrugated MISHEMT (red). Fig.5: 1stand 3rdorder pulsed transconductance curves for quiescent bias condition (VGS,Q, VDS,Q) = (-3.00 V, 0.00 V). Fig.6: Gain vs frequency extracted from small signal s-parameter measurements. Fig.7: One-tone 30 GHz power sweep with a peak PAE of 51% at VDS= 7 V. Fig.8: Two-tone 30 GHz power sweep at VDS= 7 V with a tone spacing of 1 MHz showing a peak OIP3 / PDCof 11.95 dB. Fig.9A: Bias sweep with Total Pin, available-4.75 dBm and VDS= 7 V. A high OIP3 / PDCand Gtare observed over a large gate bias range. Fig.9B. A comparison of bias sweeps between the corrugated MISHEMT and the standard MISHEMT with (○) denoting OIP3 / PDC and ( ) denoting Fig.10: Bias sweep showing OIP3 / PDCand Gtwith respect to drain current density where total Pin, available-4.75 dBm and VDS= 7 V. Fig.11: Results of the bias sweep re-plotted to show OIP3 / PDCvs Gt. Figs.12A-12B. Single-tone power sweep with a peak power density of and associated PAE of (Figure 12A) and single-tone power sweep with a peak power density of and an associated PAE of (Figure 12B). Fig.12C: One-tone 94 GHz power sweep. Peak power density is 4.9 W / mm with a PAE of 33.9% at VDS= 12 V. Fig.13. Flowchart illustrating a method of making a device. DETAILED DESCRIPTION OF THE INVENTION In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. Technical Description This invention implements channel corrugation in an N-polar deep-recess MISHEMT to broaden the OIP3 / PDCpeak without sacrificing gain. In this way the linearization does not require more complex processing than a conventional transistor which simplifies the fabrication and could reduce cost. Example Epitaxial Growth and Device Fabrication A Nitrogen-polar deep recess GaN MISHEMT structure on a SiC substrate was grown via MOCVD. The nominal structure consisted of a GaN:Fe buffer layer, 9 nm GaN with Si doping of 5 x 1018cm-3, 28 nm graded AlxGa1-xN back-barrier (x: 5% to 41%) with Si doping of 7 x 1018cm-3, a 9 nm Al0.41Ga0.59N spacer, 11 nm GaN channel, 2.5 nm Al0.28Ga0.72N etch stop layer, 28 nm GaN cap, and 5 nm MOCVD deposited Si3N4on a substrate with a miscut angle of 4º. An AFM scan taken after deposition of the 2.5 nm Al0.28Ga0.72N etch stop layer (situated directly above the GaN channel) is shown in Figure (Fig.) 1. Surface undulations due to step bunching in III-V heterostructures on vicinal substrates are related to substrate miscut orientation and growth parameters [7], [8], [9]. High-magnitude undulations allow for the fabrication of a “Corrugated” MISHEMT where the gate width is oriented along the direction to achieve the maximum effect of the undulations on the transfer characteristics of the device. The transfer characteristics can be tuned by the orientation of the gate fingers relative to the undulations. There are several ways in which the surface undulations can cause a change in electron charge density, threshold voltage, and gate capacitance along the gate width. This is due to a combination of variation of crystal planes with various polarizations, variations in channel layer thickness, and gate and insulator electrostatics. Variations in the thickness of the layers composing the barrier can contribute as well. The growth conditions are chosen to achieve this objective. The result would be a derivative superposition of equivalent small and large signal circuit elements. An example of transconductance derivative superposition by changes in fabrication method is presented in

[0010] . In that example, two discrete threshold voltages were realized. Here a continuous variation in threshold voltage is observed and described in the next section. Considering only transconductance derivative superposition, the superposition of different threshold voltages leads to reduction of the slope of the transconductance and thus a lower gm3and higher OIP3 / PDC, as shown in eq.1. Device fabrication followed the deep-recess N-polar GaN MISHEMT process outlined in

[0011] and

[0012] . Following fabrication, the Corrugated MISHEMT was passivated with 20 nm of PECVD Si3N4. A cross-section schematic of the completed device is shown in Figure 2A. Fig.2B shows the best overall performance is expected to be when the gate width is parallel to the undulations (e.g., the gate width is parallel to the <1-100> direction for the HEMT for which electrical measurement data is presented). In the example shown, the width of the gate crosses over many peaks and valleys and the current may flow parallel to the <11-20> direction. Example Characterization Measured devices had a Pi-feed layout, 2 x 37.5 µm gate width (WG), 420 nm source-to-drain spacing (LSD), 70 nm gate-to-source spacing (LGS), and 68 nm gate length (LG), unless otherwise stated. DC transfer and output curves are shown in Figures 3 and 4, respectively. Peak gmis 434 mS / mm and Imaxis 2.03 A / mm at a VDSof 6 V and a VGSof 1 V. Large-area measurements were taken on a recessed structure of both a corrugated MISHEMT and standard 12-nm channel N-polar deep-recess MISHEMT (Fig.4B). Compared to a standard MISHEMT, the corrugated MISHEMT exhibited a more gradual reduction of capacitance with decreasing . Such a gradual reduction can be attributed to varying channel thicknesses and thus varying threshold voltages. Pulsed IV measurements were taken with a 650 ns pulse width and 0.065% duty cycle. Pulsed was measured with a quiescent gate bias ( ) of -3 V , quiescent drain bias ( ) of 0 V , and pulsed drain bias ( ) of 7 V. A Savitzky- Golay filter was applied to smooth the data for the calculation of . Pulsed gmand gm3curves are shown in Figure 5. The broad gmrise, and thus low gm3values even at VGSvalues away from the zero-crossing where gm3=0, suggest the device will exhibit a high OIP3 / PDCover a broad range of VGS. Small signal performance was measured by S-parameter measurements up to 67 GHz. Pad losses were de-embedded using on- wafer open and short structures. Figure 6 shows the extracted gain from the small signal bias-dependent s-parameter measurements. Extracted fmaxis 212.6 GHz with an associated ftof 119.0 GHz at a VGSof -2 V, VDSof 12 V, and IDSof 0.942 A / mm. Large signal performance was characterized at 30 GHz via one and two-tone load-pull measurements at a vendor, Maury Microwave. Devices were matched to maximize OIP3 / PDCwhile minimizing the corresponding reduction in transducer gain (Gt). One- tone performance is shown in Figure 7. At a quiescent bias of -3.8 V VGS, 7 V VDS, and 210 mA / mm IDS, the device exhibited a Gtof 5.4 dB, Gpof 10.2 dB, and a maximum PAE of 51% with a power density of 1.93 W / mm at 30 GHz. Two-tone measurements were taken with a center frequency of 30 GHz and a tone spacing of 1 MHz. Matching conditions were selected to maximize OIP3 / PDC while maintaining a reasonable linear of greater than 8 dB . Selected was and was .For two-tone measurements, total Pinand Pout(sum of the two tones for both the input and output) are presented. Figure 8 shows the result of a two-tone power sweep, with the intermodulation products cut off below the noise floor of -65 dBm (to prevent reporting incorrect OIP3 / PDCobtained in regimes below the noise floor of the system). The quiescent bias conditions were VGSof -3.8 V, VDSof 7 V, and IDSof 208 mA / mm. The Corrugated MISHEMT demonstrates a maximum OIP3 / PDCof 11.95 dB with an associated OIP3 of 32.56 dB and Gtof 8.46 dB at a total Pin, availableof -1.67 dBm. The split in the I3 high and low in Fig.8 can most likely be attributed to the bias tee. In order to evaluate the bias sensitivity of OIP3 / PDCin the Corrugated MISHEMT, the bias was swept while the two tone measurement was conducted. Figure 9A shows a bias sweep comparing the OIP3 / PDCand Gtwith respect to VGS. Total Pin, availablewas -4.75 dBm. The Corrugated MISHEMT maintained an OIP3 / PDCabove 8 dB, with a first peak value of 11.61 dB, across a bias window ΔVGSof ~0.5V between VGSof -4.1 V and -3.6 V. A second broad peak in OIP3 / PDCis observed between VGSof -3.3 V and -3.0 V. Figure 10 shows the same bias sweep with OIP3 / PDCand Gtplotted against drain current density. OIP3 / PDCabove 8 dB was observed for drain current values of 174 mA / mm to 257 mA / mm (first peak) and 331 mA / mm to 403 mA / mm (second peak). OIP3 / PDCcan be traded for Gtthrough matching. Figure 11 shows the result of plotting OIP3 / PDCversus Gtfor the Corrugated MISHEMT for different bias points. Gtof over 8 dB was maintained for OIP3 / PDCvalues above 8 dB which is very attractive for broadband circuits at high operating frequencies.30-GHz linearity and gain remained high over two useful current ranges and was insensitive to small changes in , which is valuable for real circuit applications. For comparison, a bias sweep at of 7 V was conducted on of standard N-polar deep-recess MISHEMT with scaled dimensions. The matching conditions for the standard MISHEMT were and with total of -3.75 dBm . The comparison of OIP3 / PDC and associated for the corrugated and standard MISHEMTs is shown in Figure 9B. The corrugated MISHEMT exhibits an OIP3 / PDC peak, which is broader with gate bias and demonstrates a much higher associated . For measurements, the same MISHEMT characterized by two-tone load-pull was biased with a quiescent condition of of of 7 V , and of (the same bias condition used for the twotone measurements). Matching conditions were . Peak output power density was 1.9 W / mm with associated PAE of (Fig.8). The corrugated MISHEMT measured at 94 GHz had a Pi-feed layout, of of of 70 nm , and of 76 nm . Quiescent bias conditions were of - 3.35 V , of 12 V , and of . Matching conditions were selected to maximize a combination of and PAE with of and of . Fig.8 shows a peak power density of and associated PAE of . W-band performance was evaluated with one-tone load-pull at 94 GHz. A Corrugated MISHEMT with a Pi-feed layout, WGof 2 x 37.5 µm, LSDof 540 nm, LGSof 70 nm, and LGof 76 nm was biased at a VDSof 12 V and VGSof -3.35 V, with an IDSof 400 mA / mm. Figure 12 shows the resulting W-band power sweep. Peak power density is 4.9 W / mm and the associated PAE is 33.9%. Table 1 lists the source and load reflection coefficients used for each presented device measurement. These numbers are at or near state-of-the-art values for the drain voltage and gate length. This shows that the corrugated device structure can be expected to provide very good power performance while also having the benefit of improved linear operation for multi-tone or other modulated signals. More specifically, channel corrugation allows for a bias-insensitive OIP3 / PDC at lower input power without sacrificing power density and efficiency at higher input power. Therefore, the N-polar deep-recess corrugated GaN MISHEMT is attractive for both receiver and transmitter applications.

[0002] Table 1: Source and Load Reflection Coefficients for Presented Large Signal Measurements. Advantages and Improvements Linear amplifiers are desired in mm-wave communication systems in order to prevent distortion due to inter-modulation products. Traditional circuit-level and system-level techniques to improve linearity introduce additional cost and / or degradation in performance due to trading off other performance parameters against the linearity. At the device level, improved linearity in Nitrogen-polar GaN MISHEMTs has been shown through a dual threshold voltage structure to achieve derivative superposition. However, this was implemented by etching regions of the gate, introducing additional cost and fabrication complexity. In the Corrugated MISHEMT discussed herein, high linearity with low bias sensitivity was achieved by inducing step bunching during the MOCVD epitaxial growth of the device structure. This reduces cost and complexity compared to alternative device-level derivative superposition methods. Furthermore, the corrugations do not lead to a degradation in mm-wave power or efficiency compared to the state-of-the-art. This invention focuses on the metric of OIP3 / PDC to quantify linearity. A high and bias-insensitive OIP3 / PDC suggests the Corrugated HEMT will exhibit a low Adjacent Channel Power Ratio (ACPR) which is bias-insensitive. The Corrugated MISHEMT is appealing for both receiver (low-noise amplifier) and transmitter (power amplifier) applications, as well as other circuits. The Corrugated MISHEMT provides a versatile tool with value for microwave and mm-wave transceiver applications. Benefits of inducing this thickness variation by growth rather than etching include: 1. Maintaining a pristine as-grown channel. Etching would inevitably lead to surface and sub-surface damage to the crystal and potential changes to the surface states. 2. Improving control of OIP3 / PDC Bias-insensitivity. In the typical etch- defined multi-Vt structure (i.e. ref

[0010] in the document), a separate etch would be required for each threshold voltage. In a dual-Vt structure such as that in

[0010] , the aim was to achieve OIP3 / PDC bias-insensitivity by flattening the gm curve when the two Vt segments were superposed. In our as-grown device, the channel thickness (and thus threshold voltage) varies continuously. This greatly simplifies the fabrication process and should lead to a more reliable OIP3 / PDC bias-insensitivity, as we have a continuous superposition of threshold voltages rather than some number of etch- induced discrete superpositions. Process Steps Fig.13 is a flowchart illustrating a method of making a transistor, comprising the following steps. Block 1300 represents growing a heterostructure (e.g., by MOCVD) comprising a channel layer and a barrier layer on a buffer layer on vicinal or miscut substrate under growth conditions that induce step bunching in the channel layer or the barrier layer or both, wherein the miscut or vicinal substrate has a growth surface oriented at an angle in a direction. In one or more examples, the conditions include growing on a miscut more than 2 degrees under equilibrium conditions for growth of the crystal (high temperature, low precursor flow for low growth rate) Block 1302 represents forming a source contact and a drain contact to the channel layer. Block 1304 represents depositing a gate contact on the channel layer, the gate contact for modulating a flow of current comprising mobile charge carriers between the source contact and the drain contact, so that the gate contact has a gate width perpendicular to the flow. The orientation of the gate width with respect to the undulations is tailored to control transistor (e.g., transconductance) performance. Block 1306 represents the end result, a transistor. Example devices and methods include, but are not limited to, the following. 1. A transistor 200, comprising: a channel 202 comprising at least one of undulations 204 or a plurality of crystal planes oriented along a direction; a drain contact (D) to the channel; a source contact (S) to the channel; and a gate contact (G) coupled to the channel so as to modulate a flow of current comprising mobile charge carriers between the source contact and the drain contact. 2. The transistor of example 1, wherein the undulations or crystal planes modulate or vary a threshold voltage of the transistor across the gate width so as to tailor a transfer characteristic of the transistor structure. 3. The transistor of example 1, wherein the undulations or crystal planes modulate or vary a threshold voltage of the transistor across the gate width 212 so as to tailor linearity of the transistor. 4. The transistor of any of the examples 1-3, wherein the transistor is a HEMT or MISHEMT, a field effect transistor (e.g., MOSFET or MISFET), and the gate is coupled to the channel via a dielectric, a p-n junction, or a Schottky barrier. 5. The transistor of any of the examples 1-3, wherein the transistor is a III-Nitride HEMT. 6. The transistor of any of the examples 1-3, wherein the transistor is an N-polar III-Nitride HEMT. 7. The transistor of any of the examples 1-6, wherein the undulations are aligned nearly (e.g., within 10 degrees of) along the (i.e., the peaks and valleys are nearly perpendicular to the <11-20> direction, in the <1-100> direction) (or a cross sectional line through peaks and valleys is in the <1-100> direction as illustrated in Fig.1). 8. The transistor of any of the examples 1-6, wherein the undulations are random having no specific direction. 9. The transistor of any of the examples 1-8, wherein the gate width is nearly (e.g. within 10 degrees of) parallel to the peaks and valleys of the undulations / step bunching (i.e., the current can flow along the peaks and valleys). Fig. 2B shows the best overall performance is expected to be when the gate width is parallel to the undulations (e.g., the <1-100> direction for the HEMT for which electrical measurement data is presented). 10. The transistor of any of the examples 1-9, wherein the transistor structure is grown on a substrate 214 comprising a vicinal substrate having an orientation or miscut along a direction and the undulations comprise step bunching formed or induced by growth on the vicinal substrate. 11. The transistor of any of the examples 1-10, wherein the undulations or crystal planes vary at least one of the parameters: electron charge density, threshold voltage, or gate capacitance along the gate width to tailor a transfer characteristic. 12. The transistor of any of the examples 1-11, wherein an angle of the gate width to the direction is configured to achieve derivative superposition. 13. The transistor of any of the examples 1-12, wherein the direction at least reduces a slope of the transconductance as compared to transistor without the undulations. 14. The transistor of any of the examples 1-13, wherein the undulations are configured (e.g., size, orientation, spacing) such that the transistor has a magnitude of gm3 / gm1 of less than 0.05 (V-2) over a drain current range of 0.15 to 0.75 A / mm. 15. The transistor of any of the examples 1-14, wherein the transistor has a gate length of 5 nm-1000 nm and a channel length of 10 nm- 2000 nm. 16. The transistor of any of the examples 1-15, wherein the undulations comprising step bunches comprise a plurality of steps or terraces between the source and the drain, wherein a spacing between the undulations is periodic or non-periodic. 17. A transistor 200, comprising: a channel 202 comprising a III-nitride material comprising a crystal having a plane within 15 degrees of the Nitrogen-polar (000-1) plane or a gallium polar (0001) plane, wherein the channel 202 comprises at least one of undulations 204 oriented, or multiple crystal planes oriented, along a direction 216; a source contact (S) and a drain contact (D) to the channel; coupled to the channel so as to modulate a flow of current comprising mobile charge carriers between the source contact and the drain contact, wherein the gate contact (G) has a gate width 212 perpendicular to the flow 18. The transistor of example 17, wherein: the III-nitride material comprises one or more layers of ScvGawAlxInyBzN where 0≦v≦1, 0≦w≦1, 0≦x≦1, 0≦y≦1, 0≦z≦1, and v+w+x+y+z=1 19. The transistor of example 17 or 18, wherein: the channel 202 comprises GaN comprising a two dimensional electron gas or a two dimensional hole gas 218 confined in the channel by a back barrier 220; a cap comprises a cap structure on the channel and the cap structure comprises a second material including: a first aluminum 222 containing nitride layer on or above the channel; a first GaN layer 224 on or above the first aluminum containing nitride layer; 20. The transistor of any of the examples 1-16 comprising the transistor structure of any of the examples 17-19. 21. The transistor of any of the examples 1-20 operating a frequency greater than 1MHz. 22. A receiver (e.g., comprising at a minimum a low-noise amplifier), transmitter (e.g., comprising at a minimum a power amplifier) comprising the transistor of any of the examples 1-21. 23. The transistor of any of the examples 1-22, wherein the undulations have a height H in a range of 1-100 nm and a peak-to-trough spacing S in a range of 10-10000 nm. The transistor of any of the examples 1-23, wherein the transistor and the channel comprise any elemental (e.g. Silicon) or compound semiconductor (e.g. Gallium Arsenide). The transistor of any of the examples 1-24, wherein growth on a miscut vicinal substrate leads to undulations of the growth surface due to step- bunching [9],

[0010] ,

[0011] ,

[0012] . and such undulations allow for the growth of a channel with a thickness that changes with location along the direction of the miscut. The transistor of any of the examples 1-25, wherein the undulations comprise a variation in a thickness of the channel, the thickness alternately increasing and decreasing across the gate width, e.g., so that the channel has thickness varying in a range of 0-40 nanometers or 0-200 nanometers (nm). The transistor of any of the examples 1-26, wherein the channel thickness T variation (e.g., resulting from the undulations) along the gate width is from 0 to 40 nm or 0-200 nm, (e.g., 0 ≤ T ≤ 40 nm or 0 ≤ T ≤ 200 nm). The transistor of any of the examples 1-27, wherein the channel thickness alternates or undulates or varies between a thinner region / thinner regions (e.g., trough(s)) and a thicker region / thicker regions (e.g., peak(s)) along the gate width, with the thickness T varying within the range of 0-200 nm or 0-40 nm or 1.5 nm- 12 nm (e.g., 0 ≤ T ≤ 40 nm or 0 ≤ T ≤ 200 nm or 1.5 nm ≤ T ≤ 12 nm or 1.5 nm ≤ T ≤ 200 nm or 1 ≤ T ≤ 40 nm). The transistor of any of the examples 1-28 wherein the undulations comprising the channel thickness variation are “as grown” , eliminating any damage, or characterized in not comprising any damage, to the channel that would result from etching and optionally greatly simplifies the HEMT fabrication process. The transistor of any of the examples 1-29 wherein the undulations comprising the thickness variation of the channel are non-etched. The transistor of any of the examples 1-20 wherein the undulations comprise a continuous thickness variation of the channel. 32. The transistor of any of the examples wherein “III-nitride” (as well as the terms “Group-III nitride”, or “III-N”, or “nitride,” used generally) refer to any alloy composition of the (Sc,Ga,Al,In,B)N semiconductors having the formula ScvGawAlxInyBzN where 0≦v≦1, 0≦w≦1, 0≦x≦1, 0≦y≦1, 0≦z≦1, and v+w+x+y+z=1. These terms are intended to be broadly construed to include respective nitrides of the single species, Sc, Ga, Al, In and B, as well as binary, ternary, quaternary and pentanary compositions of such Group III metal species. Accordingly, it will be appreciated that the discussion of the invention hereinafter in reference to GaN materials is applicable to the formation of various other (Sc,Ga,Al,In,B)N material species. Furthermore, (Sc,Ga,Al,In,B)N materials within the scope of the invention may include minor quantities of dopants and / or other impurity or inclusional materials. 33. The transistor of any of the examples wherein the term “N- polar” refers to the (000-1) plane of III-nitride materials. 34. The transistor of any of the examples wherein the “threshold voltage” may be defined as the gate to source voltage necessary to turn on a transistor’s channel. References The following references are incorporated by reference herein [1] B. Romanczyk et al., “W-Band Power Performance of SiN-Passivated N-Polar GaN Deep Recess HEMTs,” IEEE Electron Device Lett., vol.41, no.3, pp. 349–352, Mar.2020, doi: 10.1109 / LED.2020.2967034. [2] E. Akso et al., “First Demonstration of Four-Finger N-polar GaN HEMT Exhibiting Record 712-mW Output Power With 31.7% PAE at 94 GHz,” IEEE Microw. Wirel. Technol. Lett., pp.1–4, 2023, doi: 10.1109 / LMWT.2023.3239532. [3] Shrestha, Pawana, “Design, Fabrication and Characterization of Highly Linear N-Polar GaN MIS-HEMT for mm-Wave Receiver Applications,” University of California Santa Barbara, 2020. [4] P. Shrestha et al., “High Linearity and High Gain Performance of N- Polar GaN MIS-HEMT at 30 GHz,” IEEE Electron Device Lett., vol.41, no.5, pp. 681–684, May 2020, doi: 10.1109 / LED.2020.2980841. [5] M. Guidry et al., “Improved N-polar GaN mm-wave Linearity, Efficiency, and Noise,” in 2022 IEEE / MTT-S International Microwave Symposium - IMS 2022, Jun.2022, pp.291–294. doi: 10.1109 / IMS37962.2022.9865510. [6] J.-S. Moon et al., “High-speed Graded-channel GaN HEMTs with Linearity and Efficiency,” in 2020 IEEE / MTT-S International Microwave Symposium (IMS), Aug.2020, pp.573–575. doi: 10.1109 / IMS30576.2020.9223775. [7] M. Shinohara and N. Inoue, “Behavior and mechanism of step bunching during metalorganic vapor phase epitaxy of GaAs,” Appl. Phys. Lett., vol. 66, no.15, pp.1936–1938, Apr.1995, doi: 10.1063 / 1.113282. [8] S. Keller et al., “Recent progress in metal-organic chemical vapor deposition of N-polar group-III nitrides,” Semicond. Sci. Technol., vol.29, no.11, p. 113001, Aug.2014, doi: 10.1088 / 0268-1242 / 29 / 11 / 113001. [9] C. Lund et al., “Metal-organic chemical vapor deposition of N-polar InN quantum dots and thin films on vicinal GaN,” J. Appl. Phys., vol.123, no.5, p. 055702, Feb.2018, doi: 10.1063 / 1.5009904.

[0010] P. Shrestha et al., “A Novel Concept using Derivative Superposition at the Device-Level to Reduce Linearity Sensitivity to Bias in N-polar GaN MISHEMT,” in 2020 Device Research Conference (DRC), Jun.2020, pp.1–2. doi: 10.1109 / DRC50226.2020.9135169.

[0011] B. Romanczyk et al., “Demonstration of Constant 8 W / mm Power Density at 10, 30, and 94 GHz in State-of-the-Art Millimeter-Wave N-Polar GaN MISHEMTs,” IEEE Trans. Electron Devices, vol.65, no.1, pp.45–50, Jan.2018, doi: 10.1109 / TED.2017.2770087.

[0012] W. Liu et al., “6.2 W / Mm and Record 33.8% PAE at 94 GHz From N- Polar GaN Deep Recess MIS-HEMTs With ALD Ru Gates,” IEEE Microw. Wirel. Compon. Lett., vol.31, no.6, pp.748–751, Jun.2021, doi: 10.1109 / LMWC.2021.3067228.

[0013] N-Polar GaN MISHEMT With Bias-Insensitive Linearity at 30 GHzHenry Collins , Emre Akso , Nirupam Hatui, Christopher J. Clymore, Christian Wurm, Robert Hamwey , Matthew Guidry , Member, IEEE, Stacia Keller , and Umesh K. Mishra , Life Fellow, IEEE. IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS, VOL.34, NO.3, MARCH 2024. Conclusion This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS 1. A transistor, comprising: a channel comprising at least one of undulations or a plurality of crystal planes oriented along a direction; a drain contact to the channel; a source contact to the channel; and a gate contact coupled to the channel so as to modulate a flow of current comprising mobile charge carriers between the source contact and the drain contact.

2. The transistor of claim 1, wherein the undulations or crystal planes modulate or vary a threshold voltage of the transistor across the gate width so as to tailor a transfer characteristic of the transistor structure.

3. The transistor of claim 1, wherein the undulations or crystal planes modulate or vary a threshold voltage of the transistor across the gate width so as to tailor linearity of the transistor.

4. The transistor of claim 1, wherein the transistor is a HEMT or MISHEMT, a field effect transistor, and the gate is coupled to the channel via a dielectric, a p-n junction, or a Schottky barrier.

5. The transistor of claim 1, wherein the transistor is a III-Nitride HEMT.

6. The transistor of claim 1, wherein the transistor is an N-polar III- Nitride HEMT.

7. The transistor of claim 1, wherein the undulations have peaks and valleys that are aligned within 10 degrees of along the <11-20>.

8. The transistor of claim 1, wherein the undulations are random having no specific direction.

9. The transistor of claim 1, wherein the gate width is within 10 degrees of parallel to the peaks and valleys of the undulations / step bunching so that the current can flow along the peaks and valleys.

10. The transistor of claim 1, wherein the transistor structure is grown on a substrate comprising a vicinal substrate having an orientation or miscut along a direction and the undulations comprise step bunching formed or induced by growth on the vicinal substrate.

11. The transistor of claim 1, wherein the undulations or crystal planes vary at least one of the parameters: electron charge density, threshold voltage, or gate capacitance along the gate width to tailor a transfer characteristic.

12. The transistor of claim 1, wherein an angle of the gate width to the direction is configured to achieve derivative superposition.

13. The transistor of claim 1, wherein the direction at least reduces a slope of the transconductance as compared to transistor without the undulations.

14. The transistor of claim 1, wherein the undulations are configured such that the transistor has a magnitude of gm3 / (gm)3of less than 2.5x10-7(mm2 / A2) over a drain current range of 0.25 to 0.8 A / mm.

15. The transistor of claim 1, wherein the transistor has a gate length of 5 nm-1000 nm and a channel length of 10 nm- 2000 nm.

16. The transistor of claim 1, wherein the undulations comprising step bunches comprise a plurality of steps or terraces between the source and the drain, wherein a spacing between the undulations is periodic or non-periodic.

17. A transistor, comprising: a channel comprising a III-nitride material comprising a crystal having a plane within 15 degrees of the Nitrogen-polar (000-1) plane or a gallium polar (0001) plane, wherein the channel comprises at least one of undulations oriented or multiple crystal planes oriented along a direction; a source contact and a drain contact to the channel; coupled to the channel so as to modulate a flow of current comprising mobile charge carriers between the source contact and the drain contact, wherein the gate contact has a gate width perpendicular to the flow 18. The transistor of claim 17, wherein: the III-nitride material comprises one or more layers of ScvGawAlxInyBzN where 0≦v≦1, 0≦w≦1, 0≦x≦1, 0≦y≦1, 0≦z≦1, and v+w+x+y+z=1 19. The transistor of claim 17, wherein: the channel comprises GaN comprising a two dimensional electron gas or a two dimensional hole gas confined in the channel by a back barrier; a cap comprises a cap structure on the channel and the cap structure comprises a second material including: a first aluminum containing nitride layer on or above the channel; a first GaN layer on or above the first aluminum containing nitride layer; 20. The transistor of claim 1 comprising the transistor structure of any of the claim 17.

21. The transistor of claim 1 operating a frequency greater than 1MHz.

22. A method of making a transistor, comprising: growing a heterostructure comprising a channel layer and a barrier layer on a buffer layer on vicinal or miscut substrate under growth conditions that induce step bunching in the channel layer or the barrier layer or both, wherein the miscut or vicinal substrate has a growth surface oriented at an angle in a direction; forming a source contact and a drain contact to the channel layer; and depositing a gate contact on the channel layer, the gate contact for modulating a flow of current comprising mobile charge carriers between the source contact and the drain contact, so that the gate contact has a gate width perpendicular to the flow.

23. The method of claim 22, wherein the conditions include growing on a miscut more than 2 degrees under equilibrium conditions for growth of the crystal (high temperature, low precursor flow for low growth rate) 24. The method of claim 21, wherein: the heterostructure comprises: an N-polar III-Nitride structure comprising: a III-nitride barrier layer on or above a substrate; a III-nitride channel layer on the III-nitride barrier layer, wherein the barrier layer confines mobile charge carriers in the channel layer; optionally a III-nitride cap on the channel layer, forming the gate comprises: etching a recess having a depth profile in the III-nitride cap layer using lithographic patterning; and depositing gate metal in the recess.

25. The method of claim 22, further comprising depositing passivation above the cap.

26. The method of claim 22, wherein the heterostructure is grown by MOCVD.

27. The transistor of claim 1 manufactured using the method of claim 22.

28. A receiver or transmitter comprising the transistor of claim 1.

29. The transistor of claim 1, wherein the undulations have a height in a range of 1-100 nm and a peak-to-trough spacing in a range of 10-10000 nm.

30. The transistor of claim 1, wherein the transistor and the channel comprise any elemental or compound semiconductor.

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