Semiconductor device

Abstract

Disclosed in the present application is a semiconductor device. The semiconductor device comprises a substrate; a drift layer; first trenches, each spaced trench comprising two sub-trench parts spaced apart in a first direction, and the sub-trench parts comprising a plurality of gate trench groups and a plurality of dummy gate trenches; second trenches, the second trenches being spaced apart between the two sub-trench parts in the first direction; first connection trenches, one of the two first connection trenches connecting the ends of the plurality of second trenches in the first direction, the other one thereof connecting the other ends of the plurality of second trenches in the first direction, and the first connection trenches being connected to the ends of the dummy gate trenches adjacent to the second trenches; and second connection trenches, the second connection trenches connecting the ends of gate trenches in the gate trench groups adjacent to the second trenches. Therefore, the present application can prevent the mutual interference of an insulated gate bipolar transistor region and a fast recovery diode region in a manufacturing process, ensure the respective performance of the two regions, and improve the current-carrying capacity of semiconductor devices.

Description

semiconductor devices Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device. Background Art

[0002] With the development of science and technology, the application of semiconductor devices is becoming more and more extensive. During the design and manufacturing of semiconductor devices, trenches are provided, where gates can be formed to ensure the normal operation of the semiconductor devices.

[0003] In the related art, the grooves are mostly strip-shaped, and the electrostatic protection of the semiconductor device is easily invalidated at the edge of the groove, resulting in low stability and reliability of the semiconductor device.

[0004] Summary of the Invention

[0005] In the first aspect, the present application discloses a semiconductor device comprising: a substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductive type, the drift layer being arranged between the first main surface and the second main surface; a first trench, the first trench extending from the first main surface toward the second main surface and reaching the drift layer, the first trench extending in a first direction and being multiple, the multiple first trenches being spaced apart in a second direction, a portion of the multiple first trenches being first spaced trenches, the first spaced trenches being multiple including first sub-trenches and second sub-trenches spaced apart in the first direction; a second trench, the second trench extending from the first main surface toward the second main surface and reaching the drift layer, the second trench extending in the first direction and being multiple, the second trench being spaced apart in the first direction between the first sub-trench and the second sub-trench. A first connecting groove extends from the first main surface toward the second main surface and reaches the drift layer. The first connecting groove extends in the second direction. There are two first connecting grooves. One of the two first connecting grooves connects one end of multiple second grooves, and the other connects the other ends of multiple second grooves.

[0006] In a second aspect, the present application further discloses a semiconductor device, comprising: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer, the drift layer being disposed on the semiconductor substrate and located between the first main surface and the second main surface; a ring layer, the ring layer being disposed on a side of the drift layer facing the first main surface, the surface of the ring layer on a side away from the drift layer constituting a portion of the first main surface; a main trench portion, the main trench portion being disposed in the ring layer and extending in a first direction, the main trench portion comprising a plurality of gate trench groups and a plurality of dummy gate trench portions, the plurality of gate trench groups being spaced apart in a second direction, at least one dummy gate trench portion being disposed between two adjacent gate trench groups, the gate trench group comprising at least two gate trench portions spaced apart in the second direction; and a connecting trench portion, the connecting trench portion being disposed in the ring layer and extending in the second direction, the connecting trench portion being located at an edge of an active area of ​​the semiconductor device, the connecting trench portion connecting at least one end of at least two gate trench portions in each gate trench group, wherein the first direction is perpendicular to the second direction.

[0007] In a third aspect, the present application further discloses a semiconductor device, comprising: a substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductive type, the drift layer being arranged between the first main surface and the second main surface; a first trench, the first trench extending from the first main surface toward the second main surface and reaching the drift layer, the first trench extending in a first direction and being multiple, the multiple first trenches being spaced apart in a second direction, and a portion of the multiple first trenches being spaced apart trenches; the spaced apart trench comprising two sub-trench portions spaced apart in the first direction, the sub-trench portions comprising a plurality of gate trench groups and a plurality of dummy gate trenches, the plurality of gate trench groups being spaced apart in the second direction, at least one dummy gate trench being arranged between two adjacent gate trench groups, the gate trench group comprising at least two gate trenches spaced apart in the second direction, wherein the gate trench is electrically connected to the gate of the semiconductor device, and the dummy gate trench is electrically connected to the emitter of the semiconductor device; the second trench, The second trench extends from the first main surface toward the second main surface and reaches the drift layer, the second trench extends in the first direction, there are multiple second trench parts and are spaced apart from each other in the second direction, and the second trench is spaced apart between two sub-trench parts in the first direction; a first connecting trench, the first connecting trench extends from the first main surface toward the second main surface and reaches the drift layer, the first connecting trench extends in the second direction, there are two first connecting trenches, one of the two first connecting trenches connects one end of the multiple second trenches in the first direction, and the other connects the other end of the multiple second trenches in the first direction; a second connecting trench, the second connecting trench extends from the first main surface toward the second main surface and reaches the drift layer, the second connecting trench extends in the second direction, the second connecting trench connects one end of the gate trench in the gate trench group adjacent to the second trench, and connects one end of two adjacent gate trench groups adjacent to the second trench.

[0008] In a fourth aspect, the present application further discloses a semiconductor device, comprising: a substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductive type, the drift layer being arranged between the first main surface and the second main surface; a first trench, the first trench extending from the first main surface toward the second main surface and reaching the drift layer, the first trench extending in a first direction and being multiple, the multiple first trenches being spaced apart in a second direction, and a portion of the multiple first trenches being spaced apart trenches; the spaced apart trench comprising two sub-trench portions spaced apart in the first direction, the sub-trench portions comprising a plurality of gate trench groups and a plurality of dummy gate trenches, the plurality of gate trench groups being spaced apart in the second direction, at least one dummy gate trench being arranged between two adjacent gate trench groups, the gate trench group comprising at least two gate trenches spaced apart in the second direction, wherein the gate trench is electrically connected to the gate of the semiconductor device, and the dummy gate trench is electrically connected to the emitter of the semiconductor device; a second trench, the first Two trenches extend from the first main surface toward the second main surface and reach the drift layer, the second trench extends in the first direction, there are multiple second trench parts and are spaced apart from each other in the second direction, and the second trench is spaced apart between two sub-trench parts in the first direction; a first connecting trench, the first connecting trench extends from the first main surface toward the second main surface and reaches the drift layer, the first connecting trench extends in the second direction, there are two first connecting trenches, one of the two first connecting trenches connects one end of the multiple second trenches in the first direction, and the other connects the other end of the multiple second trenches in the first direction, and the first connecting trench is connected to an end of the dummy gate trench adjacent to the second trench; a second connecting trench, the second connecting trench extends from the first main surface toward the second main surface and reaches the drift layer, the second connecting trench extends in the second direction, and the second connecting trench connects an end of the gate trench in the gate trench group adjacent to the second trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG1 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0010] FIG2 is a top view of a semiconductor device according to some embodiments of the present disclosure;

[0011] FIG3 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0012] 4 is a cross-sectional view of a semiconductor device along line AA according to some embodiments of the present disclosure;

[0013] 5 is a cross-sectional view of a semiconductor device along line BB according to some embodiments of the present disclosure;

[0014] FIG6 is a cross-sectional view of structure 1 according to some embodiments of the present disclosure;

[0015] FIG7 is a cross-sectional view of structure 2 according to some embodiments of the present disclosure;

[0016] FIG8 is a cross-sectional view of structure 3 according to some embodiments of the present disclosure;

[0017] FIG9 is a cross-sectional view of structure 4 according to some embodiments of the present disclosure;

[0018] FIG10 is a cross-sectional view of structure 5 according to some embodiments of the present disclosure;

[0019] FIG11 is a cross-sectional view of structure 6 according to some embodiments of the present disclosure;

[0020] FIG12 is a cross-sectional view of structure 7 according to some embodiments of the present disclosure;

[0021] FIG13 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0022] FIG14 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0023] FIG15 is a cross-sectional view of a semiconductor device along the AA direction according to some embodiments of the present disclosure;

[0024] FIG16 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0025] FIG17 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0026] FIG18 is a cross-sectional view of structure 1 according to some embodiments of the present disclosure;

[0027] FIG19 is a cross-sectional view of structure 2 according to some embodiments of the present disclosure;

[0028] FIG20 is a cross-sectional view of structure 3 according to some embodiments of the present disclosure;

[0029] FIG21 is a cross-sectional view of structure 4 according to some embodiments of the present disclosure;

[0030] FIG22 is a cross-sectional view of structure 5 according to some embodiments of the present disclosure;

[0031] FIG23 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0032] FIG24 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0033] FIG25 is a cross-sectional view of a semiconductor device along the AA direction according to some embodiments of the present disclosure;

[0034] FIG26 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0035] FIG27 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0036] FIG28 is a cross-sectional view of structure 1 according to some embodiments of the present disclosure;

[0037] FIG29 is a cross-sectional view of structure 2 according to some embodiments of the present disclosure;

[0038] FIG30 is a cross-sectional view of structure 3 according to some embodiments of the present disclosure;

[0039] FIG31 is a cross-sectional view of structure 4 according to some embodiments of the present disclosure;

[0040] FIG32 is a cross-sectional view of structure 5 according to some embodiments of the present disclosure;

[0041] FIG33 is a top view of a semiconductor device according to some embodiments of the present disclosure;

[0042] FIG34 is a schematic diagram of area A in FIG1 ;

[0043] FIG35 is a schematic diagram of area B in FIG1 ;

[0044] FIG36 is a cross-sectional view of a semiconductor device along the AA direction according to some embodiments of the present disclosure;

[0045] FIG37 is a cross-sectional view of a semiconductor device along line BB according to some embodiments of the present disclosure;

[0046] FIG38 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0047] FIG39 is a state diagram of a manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0048] FIG40 is a state diagram of a manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0049] FIG41 is a state diagram of a manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0050] FIG. 42 is a state diagram of a manufacturing process of a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean a fixed connection, a removable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediary. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0055] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0056] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0057] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0058] RC-IGBT (reverse conducting-Insulated Gate Bipolar Transistor) integrates IGBT (Insulated Gate Bipolar Transistor) and FRD (Fast Recovery Diode) into the same chip, making it have both forward and reverse conduction characteristics. It has many advantages such as small size, high power density, low cost and high reliability.

[0059] In related technologies, in the structure of RC-IGBT, the FRD region is often made by disconnecting the trench to separate the IGBT region from the FRD region. However, in this way, the FRD region is easily affected by processes such as injection in the IGBT region, thereby deteriorating the performance of the FRD region and even the RC-IGBT.

[0060] In the semiconductor device 100 proposed in the present application, one of the two first connecting trenches connects one end of the plurality of second trenches, and the other of the two first connecting trenches connects the other ends of the plurality of second trenches. In this way, the first connecting trenches can enclose the plurality of second trenches, separate the insulated gate bipolar transistor region and the fast recovery diode region, prevent the insulated gate bipolar transistor region and the fast recovery diode region from interfering with each other in the process, ensure the performance of the two regions, and improve the reliability of the semiconductor device.

[0061] The following describes a semiconductor device 100 according to some embodiments of the present disclosure with reference to Figures 1-12. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P represent the conductivity type of the semiconductor. In this application, the first conductivity type is N-type and the second conductivity type is P-type. The first direction is the X direction, the second direction is the Y direction, and the vertical direction is the Z direction.

[0062] 1 to 5 , the semiconductor device 100 according to the present application may mainly include a substrate 180. The substrate 180 is a basic component of the semiconductor device 100 of the present application and may provide a mounting base for at least some other components of the semiconductor device 100.

[0063] The semiconductor device 100 of the present application may also mainly include a drift layer 110 of the first conductivity type. Specifically, the drift layer 110 of the first conductivity type is arranged in the substrate 180 and is located between the first main surface 181 and the second main surface 182. A well region 111 of the second conductivity type is also provided in the substrate 180. The well region 111 is provided on the side of the drift layer 110 close to the first main surface 181. An emitter layer 112 of the first conductivity type is also provided in the well region 111. In addition, a field stop layer 115 of the first conductivity type is also provided in the substrate 180. The field stop layer 115 is provided on the side of the drift layer 110 close to the second main surface 182. A collector layer 116 of the second conductivity type and a short-circuit region 117 of the first conductivity type are provided on the side of the field stop layer 115 close to the second main surface 182. Furthermore, a dielectric layer 113 is provided on the first main surface 181 , an emitter metal layer 114 is provided on the side of the dielectric layer 113 facing away from the first main surface 181 , and a collector metal layer 118 is further provided on the second main surface 182 side of the substrate 180 .

[0064] The semiconductor device 100 may include an active region 101. The semiconductor device 100 may further include a terminal region 102 disposed outside the active region 101. The collector layer 116 and the short-circuit region 117 are both located in the active region 101. The emitter metal layer 114 may serve not only as an emitter terminal for the region corresponding to the collector layer 116, but also as an anode terminal for the region corresponding to the short-circuit region 117. The collector metal layer 118 may serve not only as a collector terminal for the region corresponding to the collector layer 116, but also as a cathode terminal for the region corresponding to the short-circuit region 117. In this way, the region corresponding to the collector layer 116 can achieve forward conduction of the semiconductor device 100, and the region corresponding to the short-circuit region 117 can achieve reverse conduction of the semiconductor device 100, so that the semiconductor device 100 has both forward and reverse conduction characteristics.

[0065] In some embodiments, the semiconductor device 100 of the present application may also mainly include a first trench 120, which is located in the area corresponding to the collector layer 116, and the first trench 120 extends from the first main surface 181 toward the second main surface 182 and reaches the drift layer 110, and the first trench 120 is extended in the first direction. By setting the first trench 120 as a plurality, the plurality of first trenches 120 are spaced apart in the second direction, and an oxide insulating layer 170 and a polysilicon 171 are sequentially arranged in the first trench 120, the normal operation of the area corresponding to the collector layer 116 and even the semiconductor device 100 can be ensured.

[0066] Furthermore, a portion of the plurality of first trenches 120 is a first spacing trench 121. There are a plurality of first spacing trenches 121, and the first spacing trenches 121 may mainly include first sub-trenches 1211 spaced apart in the first direction. The first spacing trenches 121 may also include second sub-trenches 1212 spaced apart from the first sub-trenches 1211 in the first direction.

[0067] The semiconductor device 100 of the present application may also mainly include a second trench 130, and the second trench 130 extends from the first main surface 181 toward the second main surface 182 and reaches the drift layer 110, the second trench 130 extends in the first direction, and the second trench 130 is at least partially located in the area corresponding to the short-circuit zone 117.

[0068] The region where the multiple first trenches 120 are located is defined as the insulated gate bipolar transistor region 1011, and the region where the multiple second trenches 130 are located is defined as the fast recovery diode region 1014. By providing multiple second trenches 130 corresponding to the multiple first spacing trenches 121, not only can the junction depth and doping concentration of the well region 111 of the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 be the same, ensuring that the two regions have the same withstand voltage, but also the process steps of the semiconductor device 100 can be simplified, thereby simplifying the manufacturing process of the semiconductor device 100.

[0069] Furthermore, by spacing the second trench 130 between the first sub-trench 1211 and the second sub-trench 1212, the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 can be disconnected, thereby disconnecting the region corresponding to the short-circuit region 117 and the region corresponding to the collector layer 116, thereby ensuring the performance of each of the two regions and ensuring the operating performance of the semiconductor device 100.

[0070] In addition, it should be understood that the number of second grooves 130 can also be set to multiple, and the number of first grooves 130 is greater than the number of first spacing grooves 121, so that some first grooves 130 can be set corresponding to multiple first spacing grooves 121, and the amount of substrate 180 used can be reduced, thereby reducing the preparation cost of the semiconductor device 100 of the present application.

[0071] In combination with Figures 3-5, the semiconductor device 100 may further include a first connecting trench 140, which extends from the first main surface 181 toward the second main surface 182 and reaches the drift layer 110. The first connecting trench 140 extends in the second direction. There are two first connecting trenches 140, one of the two first connecting trenches 140 connects one end of the multiple second trenches 130, and the other connects the other end of the multiple second trenches 130, so that the two first connecting trenches 140 can be distributed on both sides of the second trench 130.

[0072] Specifically, one ends of the plurality of second trenches 130 are flush with each other, and the other ends of the plurality of second trenches 130 are flush with each other. By providing the first connecting trench 140, the first connecting trench 140 extends from the first main surface 181 toward the second main surface 182 and reaches the drift layer 110. The first connecting trench 140 extends in the second direction, and two first connecting trenches 140 are provided. In this way, one of the two first connecting trenches 140 can extend in the second direction while connecting one end of the plurality of second trenches 130, and the other of the two first connecting trenches 140 can extend in the second direction. One can be extended in the second direction while connecting the other ends of the multiple second trenches 130, so that the two first connecting trenches 140 can enclose the multiple second trenches 130, that is, the two first connecting trenches 140 can separate the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014, thereby preventing the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 from interfering with each other in the process, ensuring the performance of each of the two regions, ensuring the working performance of the semiconductor device 100, and improving the reliability of the semiconductor device 100.

[0073] Thus, by connecting one end of the plurality of second trenches 130 with one of the two first connecting trenches 140 and connecting the other end of the plurality of second trenches 130 with the other of the two first connecting trenches 140, the first connecting trench 140 can enclose the plurality of second trenches 130, separate the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014, prevent the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 from interfering with each other in the process, ensure the performance of each of the two regions, and ensure the reliability of the semiconductor device 100.

[0074] In some embodiments, in combination with Figure 3, one of the multiple second trenches 130 that is adjacent to the first trench 120 on one side in the second direction is defined as a first boundary trench 1321, and one of the multiple second trenches 130 that is adjacent to the first trench 120 on the other side in the second direction is defined as a second boundary trench 1322. In this way, the interior of the area enclosed by the first boundary trench 1321, the second boundary trench 1322 and the two first connecting trenches 140 is the fast recovery diode region 1014. The two first connecting trenches 140 can serve as the boundaries of the fast recovery diode region 1014 in the first direction, thereby achieving the enclosure of the fast recovery diode region 1014, preventing the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 from interfering with each other in the process, ensuring the performance of the two regions, and ensuring the reliability of the semiconductor device 100.

[0075] As shown in Figure 1, one of the two first connection trenches 140 corresponding to the first sub-trench 1211 is spaced apart from the first sub-trench 1211, and one of the two first connection trenches 140 corresponding to the second sub-trench 1212 is spaced apart from the second sub-trench 1212. In this way, the first connection trench 140 can be spaced apart from the insulated gate bipolar transistor region 1011, so that the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 can be spaced apart. In some embodiments, the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 can be separated, which can more reliably prevent the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 from interfering with each other in the process, ensure the performance of the two regions, and ensure the structural reliability of the semiconductor device 100.

[0076] In combination with Figures 3 and 4, the semiconductor device 100 may further include a second connecting trench 150, which extends from the first main surface 181 toward the second main surface 182 and reaches the drift layer 110, and is extended in the second direction. There are two second connecting trenches 150, one of the two second connecting trenches 150 connects one end of the multiple first sub-trenches 1211 adjacent to the second trench 130, and the other connects one end of the multiple second sub-trenches 1212 adjacent to the second trench 130.

[0077] Specifically, since the second groove 130 is spaced between the first sub-groove 1211 and the second sub-groove 1212, that is, the first sub-groove 1211 has an end adjacent to the second groove 130, the second sub-groove 1212 has an end adjacent to the second groove 130, and the ends of multiple first sub-grooves 1211 adjacent to the second groove 130 are flush with each other, and the ends of multiple second sub-grooves 1212 adjacent to the second groove 130 are flush with each other.

[0078] By setting two second connecting grooves 150, the second connecting grooves 150 extend from the surface of the drift layer 110 toward the drift layer 110, and the second connecting grooves 150 extend in the second direction. In this way, while one of the two second connecting grooves 150 extends in the second direction, multiple first sub-grooves 1211 adjacent to one end of the second groove 130 can be connected. While the other of the two second connecting grooves 150 extends in the second direction, multiple second sub-grooves 1212 adjacent to one end of the second groove 130 can be connected. In this way, the first sub-grooves 1211 of the insulated gate bipolar transistor region 1011 can be connected, and the second sub-grooves 1212 of the insulated gate bipolar transistor region 1011 can be connected, thereby ensuring the normal operation of the insulated gate bipolar transistor region 1011.

[0079] 2 and 3 , the plurality of first trenches 120 may include a plurality of first main trenches 122. The plurality of first trenches 120 may further include a plurality of first spacing trenches 121, wherein the plurality of first main trenches 122 are respectively located on both sides of the plurality of first spacing trenches 121 in the second direction, and both ends of the second connecting trench 150 in the second direction are respectively connected to the first main trenches 122 on both sides.

[0080] In some embodiments, one of the multiple first main trenches 122 on one side adjacent to the multiple first spacing trenches 121 in the second direction is a third boundary trench 1221, and one of the multiple first main trenches 122 on the other side adjacent to the multiple first spacing trenches 121 in the second direction is a fourth boundary trench 1222. The outside of the area enclosed by the third boundary trench 1221, the fourth boundary trench 1222 and the two second connecting trenches 150 is the insulated gate bipolar transistor area 1011, and the inside of the area enclosed by the third boundary trench 1221, the fourth boundary trench 1222 and the two second connecting trenches 150 is the fast recovery diode area 1014.

[0081] Specifically, one of the multiple first main grooves 122 on one side adjacent to the multiple first spacing grooves 121 in the second direction is defined as the third boundary groove 1221, and one of the multiple first main grooves 122 on the other side adjacent to the multiple first spacing grooves 121 in the second direction is defined as the fourth boundary groove 1222, by connecting the two ends of the second direction of the second connecting groove 150 to the first main grooves 122 on both sides, that is, connecting the two ends of the second direction of the second connecting groove 150 to the third boundary groove 1221 and the fourth boundary groove 1222, respectively.

[0082] On one hand, the plurality of first spacing trenches 121 and the first main trench 122 can be connected via the second connection trench 150 , thereby ensuring the normal operation of the IGBT region 1011 and even the semiconductor device 100 .

[0083] On the other hand, the outside of the area enclosed by the third boundary trench 1221, the fourth boundary trench 1222 and the two second connection trenches 150 is the insulated gate bipolar transistor region 1011. In this way, the two second connection trenches 150 can serve as the boundary of the insulated gate bipolar transistor region 1011 in the first direction, and can better separate the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014. In some embodiments, this can prevent the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 from interfering with each other in the process, thereby improving the reliability of the semiconductor device 100.

[0084] As shown in FIG3 , a portion of the second trench 130 is a second spacing trench 131. The second spacing trench 131 may primarily include a third sub-trench 1311. The second spacing trench 131 may further include a fourth sub-trench 1312. The second spacing trench 131 may further include a fifth sub-trench 1313. The third sub-trench 1311 and the fifth sub-trench 1313 are respectively disposed at opposite ends of the fourth sub-trench 1312 in the first direction and are spaced apart from the fourth sub-trench 1312.

[0085] Specifically, by respectively arranging the third sub-trench 1311 and the fifth sub-trench 1313 at the two ends of the first direction of the fourth sub-trench 1312 and spaced apart from the fourth sub-trench 1312, the fast recovery diode area 1014 can be divided. The fourth sub-trench 1312 is located in the area corresponding to the short-circuit area 117, and the area corresponding to the short-circuit area 117 is defined as the fast recovery diode main conductive area 1012, thereby avoiding mutual interference between the insulated gate bipolar transistor area 1011 and the fast recovery diode main conductive area 1012 in the process, and ensuring the respective performance of the insulated gate bipolar transistor area 1011 and the fast recovery diode main conductive area 1012.

[0086] In combination with Figures 3 and 4, the semiconductor device 100 may further include a third connecting trench 160, which extends from the first main surface 181 toward the second main surface 182 and reaches the drift layer 110, and is extended in the second direction. There are two third connecting trenches 160, one of the two third connecting trenches 160 connects one end of the multiple fourth sub-trenches 1312, and the other connects the other end of the multiple fourth sub-trenches 1312.

[0087] Specifically, one ends of the multiple fourth sub-grooves 1312 are flush with each other, and the other ends of the multiple fourth sub-grooves 1312 are flush with each other. By setting the third connecting groove 160, one of the two third connecting grooves 160 can be extended in the second direction while connecting one ends of the multiple fourth sub-grooves 1312, and the other of the two third connecting grooves 160 can be extended in the second direction while connecting the other ends of the multiple fourth sub-grooves 1312.

[0088] In this way, not only can the multiple fourth sub-trenches 1312 be connected to ensure the normal operation of the fast recovery diode main conductive region 1012, but the multiple fourth sub-trenches 1312 can also be enclosed, that is, the two third connecting trenches 160 can enclose the fast recovery diode main conductive region 1012, so that in some embodiments, the fast recovery diode main conductive region 1012 and the insulated gate bipolar transistor region 1011 can be separated, which can more effectively and reliably avoid mutual interference between the fast recovery diode main conductive region 1012 and the insulated gate bipolar transistor region 1011 in the process, and can ensure the performance of each of the two regions, thereby ensuring the working performance of the semiconductor device 100.

[0089] In some embodiments, as shown in Figures 2 and 3, one of the two third connecting grooves 160 connects the multiple third sub-grooves 1311 adjacent to one end of the fourth sub-groove 1312, and the other connects the multiple fifth sub-grooves 1313 adjacent to one end of the fourth sub-groove 1312.

[0090] Specifically, since the third sub-groove 1311, the fourth sub-groove 1312 and the fifth sub-groove 1313 are arranged in sequence in the first direction, the third sub-groove 1311 has an end adjacent to the fourth sub-groove 1312, the fifth sub-groove 1313 has an end adjacent to the fourth sub-groove 1312, and the ends of the multiple third sub-grooves 1311 adjacent to the fourth sub-groove 1312 are flush with each other, and the ends of the multiple fifth sub-grooves 1313 adjacent to the fourth sub-groove 1312 are flush with each other.

[0091] By extending one of the two third connecting grooves 160 in the second direction and connecting the multiple third sub-grooves 1311 adjacent to one end of the fourth sub-grooves 1312, and by extending the other of the two third connecting grooves 160 in the second direction and connecting the multiple fifth sub-grooves 1313 adjacent to one end of the fourth sub-grooves 1312, the multiple third sub-grooves 1311 and the multiple fifth sub-grooves 1313 can be connected, thereby avoiding interference between the processes of the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012.

[0092] In some embodiments, two fourth sub-grooves 1312 on both sides of the second direction of the multiple fourth sub-grooves 1312 are defined as the fifth boundary groove 13121 and the sixth boundary groove 13122, respectively. In this way, the fifth boundary groove 13121, the sixth boundary groove 13122 and the two third connection grooves 160 are all located in the fast recovery diode area 1014, and the area inside the area enclosed by the fifth boundary groove 13121, the sixth boundary groove 13122 and the two third connection grooves 160 is the fast recovery diode main conductive area 1012, and the part of the fast recovery diode area 1014 located outside the fast recovery diode main conductive area 1012 is the fast recovery diode transition area 1013.

[0093] As described above, the active area 101 of the semiconductor device 100 can include: an insulated gate bipolar transistor region 1011, a fast recovery diode main conductive region 1012 and a fast recovery diode transition region 1013. The first connection trench 140, the third connection trench 160 and the fast recovery diode transition region 1013 can jointly play a role in separating the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012, thereby more effectively and reliably avoiding mutual interference between the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012 in the process, ensuring the performance of the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012, and thus improving the reliability of the semiconductor device 100.

[0094] As shown in FIG5 , the dielectric layer 113 may primarily include a first dielectric layer 1131. The first dielectric layer 1131 corresponds to the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012. The second dielectric layer 1132 corresponds to the fast recovery diode transition region 1013. The first dielectric layer 1131 is provided with a plurality of spaced contact holes 11311. The emitter metal layer 114 passes through the contact holes 11311 and contacts the first main surface 181. The dielectric layer 113 may further include a second dielectric layer 1132. The second dielectric layer 1132 is a continuous layer that blocks the emitter metal layer 114 and the first main surface 181.

[0095] Specifically, the dielectric layer 113 can protect the well region 111 and reduce the risk of damage to the semiconductor device 100. By making the first dielectric layer 1131 correspond to the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012, and opening a plurality of spaced contact holes 11311 on the first dielectric layer 1131, the emitter metal layer 114 can penetrate the contact holes 11311 and contact the emitter metal layer 114 or the well region 111 of the first main surface 181, thereby ensuring the normal conduction of current from the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012, and ensuring the normal operation of the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012.

[0096] In some embodiments, by making the second dielectric layer 1132 correspond to the fast recovery diode transition region 1013 and setting the second dielectric layer 1132 as a continuous layer, the dielectric layer 113 can be blocked between the emitter metal layer 114 and the first main surface 181. In this way, the dielectric layer 113 can more reliably protect the first main surface 181 of the transition region, thereby improving the structural reliability of the fast recovery diode transition region 1013.

[0097] As shown in Figure 3, at least a portion of one of the two first connecting grooves 140 connects the third sub-groove 1311 away from one end of the fourth sub-groove 1312, and at least a portion of the other of the two first connecting grooves 140 connects the fifth sub-groove 1313 away from one end of the fourth sub-groove 1312.

[0098] Specifically, the second trench 130 may mainly include: a second main trench 132, the number of which is plural. The second trench 130 may also include a plurality of second spacing trenches 131, the plurality of second main trenches 132 being respectively located on both sides of the plurality of second spacing trenches 131 in the second direction, one end of the plurality of second main trenches 132 being flush with an end of the third sub-trench 1311 away from the fourth sub-trench 1312, and the other end of the plurality of second main trenches 132 being flush with an end of the fifth sub-trench 1313 away from the fourth sub-trench 1312.

[0099] By making one of the two first connecting trenches 140 connect one end of the plurality of second trenches 130, and the other connect the other end of the plurality of second trenches 130, that is: when one of the two first connecting trenches 140 is extended in the second direction, it at least partially connects the plurality of third sub-trenches 1311 away from one end of the fourth sub-trench 1312, and the other part thereof connects one end of the plurality of second main trenches 132; when the other of the two first connecting trenches 140 is extended in the second direction, it at least partially connects the plurality of fifth sub-trenches 1313 away from one end of the fourth sub-trench 1312, and the other part thereof connects the other end of the plurality of second main trenches 132, thereby ensuring that the first connecting trench 140 encloses the main conductive region 1012 and the transition region of the fast recovery diode, thereby ensuring the working performance of the semiconductor device 100.

[0100] It should be noted that the processes in the first trench 120, the second trench 130, the first connecting trench 140, the second connecting trench 150 and the third connecting trench 160 are the same, and an oxide insulating layer 170 can be generated therein and polysilicon 171 can be deposited. The widths and depths of the first trench 120, the second trench 130, the first connecting trench 140, the second connecting trench 150 and the third connecting trench 160 can be set to be the same, so that the first trench 120, the second trench 130, the first connecting trench 140, the second connecting trench 150 and the third connecting trench 160 can be etched simultaneously, which can simplify the process steps of the semiconductor device 100.

[0101] 4 , the first connection groove 140 and the second connection groove 150 are spaced apart by a distance D1 in the first direction, and the first connection groove 140 and the third connection groove 160 are spaced apart by a distance D2 in the first direction. D1 and D2 satisfy the relationship: D1<D2.

[0102] Specifically, the second connection trench 150 is located between the insulated gate bipolar transistor region 1011 and the fast recovery diode transition region 1013, the third connection trench 160 is located between the fast recovery diode transition region 1013 and the fast recovery diode main conductive region 1012, and the first connection trench 140 is located in the fast recovery diode transition region 1013 and between the second connection trench 150 and the third connection trench 160.

[0103] By setting the spacing distance between the first connecting groove 140 and the second connecting groove 150 in the first direction to be the same as the spacing distance between the multiple first grooves 120 in the second direction, the manufacture of the first connecting groove 140 and the second connecting groove 150 can be facilitated, and by setting the spacing distance between the first connecting groove 140 and the second connecting groove 150 in the first direction to be smaller than the spacing distance between the first connecting groove 140 and the third connecting groove 160 in the first direction, the area of ​​the fast recovery diode transition region 1013 can be increased, thereby enhancing the separation effect of the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012.

[0104] In some embodiments, D2 satisfies the relationship: D2 ≥ 30 μm. Specifically, the distance between the first connection trench 140 and the third connection trench 160 in the first direction is set to be no less than 30 μm. This allows the area of ​​the fast recovery diode transition region 1013 to be set within a reasonable range, preventing the area of ​​the fast recovery diode transition region 1013 from being too small. This allows the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012 to be more effectively and reliably separated, thereby avoiding mutual interference between the two regions during the manufacturing process, ensuring the performance of the two regions, and improving the reliability of the semiconductor device 100.

[0105] It should be noted that the greater the spacing distance between the first connecting trench 140 and the third connecting trench 160 in the first direction, the better the separation effect on the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012 will be. However, it will also cause the overall area of ​​the semiconductor device 100 to increase. Therefore, in actual production, the appropriate spacing distance between the first connecting trench 140 and the third connecting trench 160 in the first direction can be selected according to the actual application scenario and requirements to achieve a balance between the separation effect between the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012 and the overall area of ​​the semiconductor device 100.

[0106] The following describes a method for manufacturing a semiconductor device 100 by way of example with reference to FIG. 6 to FIG. 12 . The semiconductor device 100 is an RC-IGBT.

[0107] As shown in FIG6 , an N-substrate material is provided to form a structure 1 .

[0108] As shown in FIG7 , based on Structure 1, first trench 120, second trench 130, first connecting trench 140, second connecting trench 150, and third connecting trench 160 are etched, and an oxidized insulating layer 170 is grown in the first trench 120, second trench 130, first connecting trench 140, second connecting trench 150, and third connecting trench 160. This forms Structure 2.

[0109] As shown in FIG8 , polysilicon 171 is deposited on the basis of structure 2 to form structure 3.

[0110] As shown in FIG9 , based on structure 3 , polysilicon 171 is etched to form structure 4 .

[0111] As shown in FIG10 , based on structure 4 , a P-well region 111 and an N+ emitter layer 112 are implanted in sequence to form structure 5 .

[0112] As shown in FIG. 11 , on the basis of structure 5 , a dielectric layer 113 is deposited, and contact holes 11311 are etched on the dielectric layer 113 to form structure 6 .

[0113] As shown in FIG12 , based on Structure 6, metal layer sputtering is performed to form an emitter metal layer 114. Then, backside N+ field stop layer 115 implantation, backside P+ collector layer 116 implantation, backside FRD region N+ short-circuit region 117 implantation, laser annealing, and backside metal sputtering are performed to form a collector metal layer 118. Finally, a semiconductor device 100 having Structure 7 is formed.

[0114] Other structures and operations of the semiconductor device 100 according to some embodiments of the present disclosure are known to those skilled in the art and will not be described in detail here.

[0115] RC-IGBT (reverse conducting-Insulated Gate Bipolar Transistor) integrates IGBT (Insulated Gate Bipolar Transistor) and FRD (Fast Recovery Diode) into the same chip, making it have both forward and reverse conduction characteristics. It has many advantages such as small size, high power density, low cost and high reliability.

[0116] In related technologies, in the structure of RC-IGBT, the FRD region is often made by disconnecting the trench to separate the IGBT region from the FRD region. However, this not only leads to a deterioration in the current-carrying capacity of the device, but also makes the FRD region susceptible to the influence of processes such as the injection of the IGBT region, thereby deteriorating the performance of the FRD region and even the RC-IGBT.

[0117] In the semiconductor device 200 proposed in some embodiments of the present disclosure, by making one of the two first connecting trenches connect one end of the multiple second trenches in the first direction, and the other connecting the other end of the multiple second trenches in the first direction, and the first connecting trench is connected to the end of the dummy gate trench adjacent to the second trench, and the second connecting trench is connected to the end of the gate trench in the gate trench group adjacent to the second trench, this not only prevents the insulated gate bipolar transistor region and the fast recovery diode region from interfering with each other in the process and ensures the performance of each of the two regions, but also improves the current flow capacity of the semiconductor device, thereby improving the working performance of the semiconductor device.

[0118] The following describes a semiconductor device 200 according to some embodiments of the present disclosure with reference to Figures 13-22. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P represent the conductivity type of the semiconductor. In this application, the first conductivity type is N-type and the second conductivity type is P-type.

[0119] 13 to 19 , the semiconductor device 200 according to the present application may mainly include: a substrate 280 , which is a basic component of the semiconductor device 100 of the present application, and may provide an installation base for at least some of the other components of the semiconductor device 100 .

[0120] The semiconductor device 200 of the present application may also mainly include a drift layer 210 of the first conductivity type. Specifically, the drift layer 210 of the first conductivity type is arranged in the substrate 280 and is located between the first main surface 281 and the second main surface 282. A well region 211 of the second conductivity type is also provided in the substrate 280. The well region 211 is provided on the side of the drift layer 210 close to the first main surface 281. A second emitter layer 212 of the first conductivity type is also provided in the well region 211. In addition, a field stop layer 215 of the first conductivity type is also provided in the substrate 280. The field stop layer 215 is provided on the side of the drift layer 210 close to the second main surface 282. A collector layer 216 of the second conductivity type and a first emitter layer 217 of the first conductivity type are provided on the side of the field stop layer 215 close to the second main surface 282. In addition, a dielectric layer 213 is provided on the first main surface 281, an emitter metal layer 214 is provided on the side of the dielectric layer 213 facing away from the first main surface 281, and a collector metal layer 218 is also provided on the second main surface 282 of the substrate 280, thus forming the basic structure of the semiconductor device 200.

[0121] The semiconductor device 200 may include an active region. The semiconductor device 200 may also include a terminal region disposed outside the active region. The region corresponding to the collector layer 216 is the insulated gate bipolar transistor region 201, and the region corresponding to the first emitter layer 217 is the fast recovery diode region 202. That is, the active region of the semiconductor device 200 may include the insulated gate bipolar transistor region 201 and the fast recovery diode region 202. The emitter metal layer 214 may serve not only as the emitter terminal of the insulated gate bipolar transistor region 201 but also as the anode terminal of the fast recovery diode region 202. The collector metal layer 218 may serve not only as the collector terminal of the insulated gate bipolar transistor region 201 but also as the cathode terminal of the fast recovery diode region 202. In this way, the insulated gate bipolar transistor region 201 can achieve forward conduction of the semiconductor device 200, and the fast recovery diode region 202 can achieve reverse conduction of the semiconductor device 200, so that the semiconductor device 200 has both forward and reverse conduction characteristics.

[0122] In some embodiments, the semiconductor device 200 of the present application may also mainly include a first trench 220, which extends from the first main surface 281 toward the second main surface 282 and reaches the drift layer 210, and the first trench 220 extends in the first direction, and the first trench 220 is set to be multiple, and the multiple first trenches 220 are spaced apart in the second direction, wherein a part of the multiple first trenches 220 is a spaced trench 221, and the spaced trench 221 may mainly include two sub-groove portions 2221 spaced apart in the first direction, and the sub-groove portions 2221 may include multiple gate trench groups 2222 and multiple dummy gate trenches 2223, and the multiple gate trench groups 2222 are spaced apart in the second direction, and at least one dummy gate trench 2223 is set between two adjacent gate trench groups 2222, and the gate trench group 2222 includes at least two gate trenches 22221 spaced apart in the second direction.

[0123] Specifically, both the gate trench 22221 and the dummy gate trench 2223 are provided with an oxide insulating layer 270, and polysilicon 271 is deposited. The second emitter layer 212 is provided on both sides of the gate trench 22221 in the second direction. The gate trench 22221 has a conductive channel with current flow capability and can be electrically connected to the gate to ensure normal operation of the insulated gate bipolar transistor region 201 and even the semiconductor device 200. However, the second emitter layer 212 is not provided on both sides of the dummy gate trench 2223 in the second direction and does not have current flow capability. The dummy gate trench 2223 can be electrically connected to the emitter. While ensuring the withstand voltage capability of the semiconductor device 200, the Miller capacitance is reduced and the current density is lowered, thereby improving the short-circuit capability of the semiconductor device 200.

[0124] In some embodiments, the semiconductor device 200 of the present application may also mainly include a second trench 230, which extends from the first main surface 281 toward the second main surface 282 and reaches the drift layer 210. The second trench 230 is extended in the first direction. By setting the second trench 230 as multiple and corresponding to multiple first spacing trenches 221, not only can the junction depth and doping concentration of the well region 211 of the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 be the same, ensuring that the two regions have the same withstand voltage, but also the process steps of the semiconductor device 200 can be simplified, and by setting the second trench 230 between the two sub-trench portions 2221 in the first direction, the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 can be separated, thereby ensuring the performance of each of the two regions and ensuring the working performance of the semiconductor device 200.

[0125] In addition, it should be understood that the number of second grooves 230 can also be set to multiple, and the number of first grooves 230 is greater than the number of first spacing grooves 221, so that some first grooves 230 can be set corresponding to multiple first spacing grooves 221, and the amount of substrate 280 used can be reduced, thereby reducing the preparation cost of the semiconductor device 200 of the present application.

[0126] In combination with Figures 13-15, the semiconductor device 200 may also include: a first connecting trench 240, the first connecting trench 240 extends from the first main surface 281 toward the second main surface 282 and reaches the drift layer 210, the first connecting trench 240 extends in the second direction, there are two first connecting trenches 240, one of the two first connecting trenches 240 connects one end of the multiple second trenches 230 in the first direction, and the other connects the other end of the multiple second trenches 230 in the first direction, and the first connecting trench 240 is connected to one end of the second trench 230 adjacent to the dummy gate trench 2223.

[0127] Specifically, one ends of the multiple second trenches 230 are flush with each other, and the other ends of the multiple second trenches 230 are flush with each other. By setting the first connecting trench 240, the first connecting trench 240 extends from the first main surface 281 toward the second main surface 282 and reaches the drift layer 210. The first connecting trench 240 is extended in the second direction, and the first connecting trench 240 is set as two, so that one of the two first connecting trenches 240 can be extended in the second direction while connecting one end of the multiple second trenches 230, and the other of the two first connecting trenches 240 can be extended in the second direction while connecting the other end of the multiple second trenches 230.

[0128] On the one hand, the two first connection trenches 240 can enclose the multiple second trenches 230, that is, the two first connection trenches 240 can separate the insulated gate bipolar transistor region 201 and the fast recovery diode region 202, thereby preventing the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 from interfering with each other in the process, thereby ensuring the performance of the two regions. On the other hand, the two first connection trenches 240 can increase the current capacity of the fast recovery diode region 202, thereby improving the working performance of the semiconductor device 200 and improving the reliability of the semiconductor device 200.

[0129] In some embodiments, considering that the dummy gate trench 2223 and the second trench 230 are of the same potential, the dummy gate trench 2223 and the second trench 230 are both connected to the emitter. By connecting one end of the dummy gate trench 2223 adjacent to the second trench 230 to the first connecting trench 240, not only can the connection between the dummy gate trench 2223 and the second trench 230 be achieved through the first connecting trench 240, the connection between the dummy gate trench 2223 and the second trench 230 can be facilitated, the production process of the semiconductor device 200 can be simplified, and the current flow capacity of the semiconductor device 200 can be improved in some embodiments.

[0130] In combination with Figures 13-15, the semiconductor device 200 may further include: a second connecting trench 250, the second connecting trench 250 extends from the first main surface 281 toward the second main surface 282 and reaches the drift layer 210, the second connecting trench 250 is extended in the second direction, and the second connecting trench 250 connects the gate trench 22221 in the gate trench group 2222 to one end of the second trench 230 adjacent to the gate trench 2222.

[0131] Specifically, the gate trench 22221 in each gate trench group 2222 is flush with one end of the second trench 230. A second connecting trench 250 can be set. When the second connecting trench 250 is extended along the second direction, the gate trench 22221 in the gate trench group 2222 can be connected to one end of the second trench 230. This not only improves the current flow capacity of the semiconductor device 200, but also encloses one end of the gate trench 22221 in the gate trench group 2222 adjacent to the second trench 230, thereby avoiding mutual interference between the gate trench group 2222 and the second trench 230 in the process, that is, it can prevent the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 from interfering with each other in the process, thereby ensuring the performance of the two regions.

[0132] Thus, by making one of the two first connecting trenches 240 connect one end of the multiple second trenches 230 in the first direction, and the other connecting the other end of the multiple second trenches 230 in the first direction, and connecting the first connecting trench 240 to the end of the dummy gate trench 2223 adjacent to the second trench 230, and making the second connecting trench 250 connect the gate trench 22221 in the gate trench group 2222 adjacent to the end of the second trench 230, this not only prevents the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 from interfering with each other in the process and ensures the performance of each of the two regions, but also improves the current carrying capacity of the semiconductor device 200, thereby improving the working performance of the semiconductor device 200.

[0133] 13-15 , one end of the dummy gate trench 2223 adjacent to the second trench 230 protrudes from one end of the gate trench 22221 adjacent to the second trench 230 , and one end of the dummy gate trench 2223 adjacent to the second trench 230 extends toward the second trench 230 and is connected to the first connection trench 240 .

[0134] Specifically, one end of the dummy gate trench 2223 adjacent to the second trench 230 protrudes from one end of the gate trench 22221 adjacent to the second trench 230. On the premise of setting a second connecting trench 250 to connect the gate trench 22221 in each gate trench group 2222, the end of the dummy gate trench 2223 adjacent to the second trench 230 can be extended toward the second trench 230, so that the dummy gate trench 2223 is connected to the first connecting trench 240. This not only facilitates the connection between the dummy gate trench 2223 and the corresponding second trench 230 and the emitter, thereby simplifying the manufacturing process of the semiconductor device 200, but also improves the current flow capacity of the semiconductor device 200 and enhances the working performance of the semiconductor device 200.

[0135] As shown in Figures 13 to 15, the multiple second trenches 230 may include a first sub-trench 232, and there are multiple first sub-trenches 232. The multiple first sub-trenches 232 correspond to the multiple dummy gate trenches 2223 and are connected to each other. In this way, not only can the circuit distribution of the semiconductor device 200 be more uniform, but the dummy gate trenches 2223 and the corresponding first sub-trenches 232 can also be conveniently etched synchronously, which can simplify the manufacturing process of the semiconductor device 200.

[0136] In some embodiments, in combination with Figures 13-15, the multiple second trenches 230 may also include a second sub-trench 231, and there are multiple second sub-trenches 231. The multiple second sub-trenches 231 and the multiple gate trenches 22221 correspond to each other in the first direction and are spaced apart from each other. In this way, under the premise of avoiding interference between the second sub-trenches 231 and the gate trenches 22221 in the process, not only can the circuit distribution of the semiconductor device 200 be made more uniform and the working performance of the semiconductor device 200 be improved, but also the gate trench 22221 and the corresponding second sub-trench 231 can be conveniently etched synchronously, which can simplify the manufacturing process of the semiconductor device 200.

[0137] It should be noted that, in other embodiments of the present application, as shown in combination with Figures 16 and 17, when there is no dummy gate trench 2223 between two adjacent gate trench groups 2222, that is, when no dummy gate trench 2223 is provided in the insulated gate bipolar transistor region 201 and only the gate trench 22221 is provided, it can be understood that the multiple gate trenches 22221 of each sub-trench portion 2221 form a gate trench group 2222, and it is only necessary to connect the ends of the multiple gate trenches 22221 adjacent to the second trench 230 through the second connecting trench 250, and to connect one of the two first connecting trenches 240 to one end of the multiple second trenches 230 in the first direction, and the other to connect the other ends of the multiple second trenches 230 in the first direction. This not only prevents the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 from interfering with each other in the process and ensures the performance of the two regions, but also increases the current carrying capacity of the two regions, thereby improving the operating performance of the semiconductor device 200.

[0138] As described above, two of the second trenches 230 on both sides of the second direction are defined as the first boundary trench 233 and the second boundary trench 234, so that the interior of the area enclosed by the first boundary trench 233, the second boundary trench 234 and the two first connection trenches 240 is the fast recovery diode area 202, and the exterior of the area enclosed by the first boundary trench 233, the second boundary trench 234 and the two first connection trenches 240 is the insulated gate bipolar transistor area 201.

[0139] Considering that the first connection trench 240 is located at the junction of the fast recovery diode region 202 and the insulated gate bipolar transistor region 201, by arranging the first connection trench 240 and the second connection trench 250 at intervals in the first direction, not only can the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 be separated, but also the mutual interference between the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 in the process can be avoided more effectively and reliably, thereby ensuring the performance of the insulated gate bipolar transistor region 201 and the fast recovery diode region 202, but also the current carrying capacity of the semiconductor device 200 can be increased, thereby improving the working performance of the semiconductor device 200.

[0140] 14 and 15 , the spacing distance between the first connecting groove 240 and the second connecting groove 250 in the first direction is D1, the spacing distance between two adjacent first grooves 220 in the second direction is D2, and the spacing distance between two adjacent second grooves 230 in the second direction is D3. D1, D2, and D3 satisfy the relationship: D1=D2=D3.

[0141] Specifically, by setting the spacing distance between the first connecting groove 240 and the second connecting groove 250 in the first direction, the spacing distance between two adjacent first grooves 220 in the second direction, and the spacing distance between two adjacent second grooves 230 in the second direction to be equal, the distribution of the first connecting groove 240 and the second connecting groove 250 can be made more uniform, which can improve the uniformity of the circuit distribution of the semiconductor device 200 and improve the working performance of the semiconductor device 200.

[0142] In addition, the processes in the first trench 220, the second trench 230, the first connecting trench 240 and the second connecting trench 250 are the same, and an oxide insulating layer 270 can be generated inside them and polysilicon 271 can be deposited. The widths and depths of the first trench 220, the second trench 230, the first connecting trench 240 and the second connecting trench 250 can be set to be the same, so that the first trench 220, the second trench 230, the first connecting trench 240 and the second connecting trench 250 can be etched synchronously, which can simplify the process steps of the semiconductor device 200.

[0143] In some embodiments, D1 satisfies the relationship: 1.5 μm ≤ D1 ≤ 2 μm. Specifically, D1 can be set to 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, or 1.9 μm. The specific value of D1 is not limited in this application. Thus, the spacing distance between the first connection trench 240 and the second connection trench 250 in the first direction can be set within a reasonable range. This not only avoids the spacing distance between the first connection trench 240 and the second connection trench 250 in the first direction being too small, resulting in poor separation effect between the insulated gate bipolar transistor region 201 and the fast recovery diode region 202, causing the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 to still interfere with each other in the process, but also avoids the spacing distance between the first connection trench 240 and the second connection trench 250 in the first direction being too large, resulting in an excessively large overall area of ​​the semiconductor device 200. In this way, a balance can be achieved between the separation effect between the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 and the overall area of ​​the semiconductor device 200. In some embodiments, the structural design of the semiconductor device 200 can be optimized and the working performance of the semiconductor device 200 can be improved.

[0144] The following describes a method for manufacturing a semiconductor device 200 by way of example with reference to FIG. 15 and FIG. 18 to FIG. 22 . The semiconductor device 200100 is an RC-IGBT.

[0145] As shown in FIG18 , an N-substrate material is provided to form a structure 1 .

[0146] As shown in FIG19 , based on Structure 1, the first trench 220, the second trench 230, the first connecting trench 240 and the second connecting trench 250 are etched, and an oxidized insulating layer 270 is grown to form Structure 2.

[0147] As shown in FIG. 20 , based on structure 2 , polysilicon 271 is deposited and etched, and then a P-well region 211 and an N+ second emitter layer 212 are sequentially implanted to form structure 3 .

[0148] As shown in FIG. 21 , on the basis of structure 3 , a dielectric layer 213 is deposited, and contact holes are etched on the dielectric layer 213 to form structure 4 .

[0149] As shown in FIG22 , on the basis of structure 4 , metal layer sputtering is performed to prepare an emitter metal layer 214 to form structure 5 .

[0150] As shown in FIG15 , based on structure 5, the back N+ field stop layer 215 is implanted, the back P+ collector layer 216 is implanted, the back FRD region N+ first emitter layer 217 is implanted, laser annealing is performed, and back metal sputtering is performed to prepare a collector metal layer 218. Finally, a semiconductor device 200 is formed.

[0151] Other structures and operations of the semiconductor device 200 according to some embodiments of the present disclosure are known to those skilled in the art and will not be described in detail here.

[0152] RC-IGBT (reverse conducting-Insulated Gate Bipolar Transistor) integrates IGBT (Insulated Gate Bipolar Transistor) and FRD (Fast Recovery Diode) into the same chip, making it have both forward and reverse conduction characteristics. It has many advantages such as small size, high power density, low cost and high reliability.

[0153] In related technologies, in the structure of RC-IGBT, the FRD region is often made by disconnecting the trench to separate the IGBT region from the FRD region. However, this not only leads to a deterioration in the current-carrying capacity of the device, but also makes the FRD region susceptible to the influence of processes such as the injection of the IGBT region, thereby deteriorating the performance of the FRD region and even the RC-IGBT.

[0154] In the semiconductor device 300 proposed in some embodiments of the present disclosure, one of the two first connecting trenches connects one end of the multiple second trenches in the first direction, and the other connects the other end of the multiple second trenches in the first direction, and the second connecting trench connects one end of the gate trench in the gate trench group adjacent to the second trench, and connects one end of the adjacent second trenches of two adjacent gate trench groups. This not only prevents the insulated gate bipolar transistor region and the fast recovery diode region from interfering with each other in the process and ensures the performance of each of the two regions, but also improves the current flow capacity of the semiconductor device, thereby improving the working performance of the semiconductor device.

[0155] The following describes a semiconductor device 300 according to some embodiments of the present disclosure with reference to Figures 23-32. The semiconductor device 300 may be an RC-IGBT. In the following description, N and P represent the conductivity type of the semiconductor. In this application, the first conductivity type is N-type and the second conductivity type is P-type.

[0156] 23 to 25 , the semiconductor device 300 according to the present application may mainly include: a substrate 380 , which is a basic component of the semiconductor device 300 of the present application, and may provide an installation base for at least some of the other components of the semiconductor device 300 .

[0157] The semiconductor device 300 of the present application may also mainly include a drift layer 310 of the first conductivity type. Specifically, the drift layer 310 of the first conductivity type is arranged in the substrate 380 and is located between the first main surface 381 and the second main surface 382. A well region 311 of the second conductivity type is also provided in the substrate 380. The well region 311 is provided on the side of the drift layer 310 close to the first main surface 381. A second emitter layer 312 of the first conductivity type is also provided in the well region 311. In addition, a field stop layer 315 of the first conductivity type is also provided in the substrate 380. The field stop layer 315 is provided on the side of the drift layer 310 close to the second main surface 382. A collector layer 316 of the second conductivity type and a first emitter layer 317 of the first conductivity type are provided on the side of the field stop layer 315 close to the second main surface 382. In addition, a dielectric layer 313 is provided on the first main surface 381, an emitter metal layer 314 is provided on the side of the dielectric layer 313 facing away from the first main surface 381, and a collector metal layer 318 is also provided on the second main surface 382 side of the substrate 380. In this way, the basic structure of the semiconductor device 300 can be formed.

[0158] The semiconductor device 300 may include an active region. The semiconductor device 300 may also include a terminal region disposed outside the active region. The region corresponding to the collector layer 316 is the insulated gate bipolar transistor region 301, and the region corresponding to the first emitter layer 317 is the fast recovery diode region 302. Specifically, the active region of the semiconductor device 300 may include the insulated gate bipolar transistor region 301 and the fast recovery diode region 302. The emitter metal layer 314 may serve not only as the emitter terminal of the insulated gate bipolar transistor region 301 but also as the anode terminal of the fast recovery diode region 302. The collector metal layer 318 may serve not only as the collector terminal of the insulated gate bipolar transistor region 301 but also as the cathode terminal of the fast recovery diode region 302. In this way, the insulated gate bipolar transistor region 301 can achieve forward conduction of the semiconductor device 300, and the fast recovery diode region 302 can achieve reverse conduction of the semiconductor device 300, so that the semiconductor device 300 has both forward and reverse conduction characteristics.

[0159] In some embodiments, the semiconductor device 300 of the present application may also mainly include a first trench 320, which extends from the first main surface 381 toward the second main surface 382 and reaches the drift layer 310, and the first trench 320 extends in the first direction, and the first trench 320 is set to be multiple, and the multiple first trenches 320 are spaced apart in the second direction, wherein a part of the multiple first trenches 320 is a spaced trench 321, and the spaced trench 321 may mainly include two sub-groove portions 3221 spaced apart in the first direction, and the sub-groove portions 3221 may include multiple gate trench groups 3222 and multiple dummy gate trenches 3223, and the multiple gate trench groups 3222 are spaced apart in the second direction, and at least one dummy gate trench 3223 is set between two adjacent gate trench groups 3222, and the gate trench group 3222 includes at least two gate trenches 32221 spaced apart in the second direction.

[0160] Specifically, both the gate trench 32221 and the dummy gate trench 3223 are provided with an oxide insulating layer 370, and polysilicon 371 is deposited. Second emitter layers 312 are provided on both sides of the gate trench 32221 in the second direction. Gate trench 32221 has a conductive channel with current-carrying capability and can be electrically connected to the gate, ensuring normal operation of the insulated gate bipolar transistor region 301 and, therefore, the semiconductor device 300. However, the dummy gate trench 3223 is not provided with second emitter layers 312 on both sides in the second direction and does not have current-carrying capability. The dummy gate trench 3223 can be electrically connected to the emitter, thereby reducing Miller capacitance and current density while ensuring the withstand voltage capability of the semiconductor device 300, thereby improving the short-circuit capability of the semiconductor device 300.

[0161] In some embodiments, the semiconductor device 300 of the present application may also mainly include a second trench 330, which extends from the first main surface 381 toward the second main surface 382 and reaches the drift layer 310. The second trench 330 is extended in the first direction. By setting the second trench 330 as multiple and corresponding to the multiple first spacing trenches 321, not only can the junction depth and doping concentration of the well region 311 of the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 be the same, ensuring that the two regions have the same withstand voltage, but also the process steps of the semiconductor device 300 can be simplified, and by setting the second trench 330 between the two sub-trench portions 3221 in the first direction, the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 can be separated, thereby ensuring the performance of each of the two regions and ensuring the working performance of the semiconductor device 300.

[0162] In combination with Figures 23 to 25, the semiconductor device 300 may further include: a first connecting trench 340, the first connecting trench 340 extends from the first main surface 381 toward the second main surface 382 and reaches the drift layer 310, the first connecting trench 340 extends in the second direction, there are two first connecting trenches 340, one of the two first connecting trenches 340 connects one end of the multiple second trenches 330 in the first direction, and the other connects the other end of the multiple second trenches 330 in the first direction.

[0163] Specifically, one ends of the multiple second trenches 330 are flush with each other, and the other ends of the multiple second trenches 330 are flush with each other. By setting the first connecting trench 340, the first connecting trench 340 extends from the first main surface 381 toward the second main surface 382 and reaches the drift layer 310. The first connecting trench 340 is extended in the second direction, and the first connecting trench 340 is set as two, so that one of the two first connecting trenches 340 can be extended in the second direction while connecting one end of the multiple second trenches 330, and the other of the two first connecting trenches 340 can be extended in the second direction while connecting the other end of the multiple second trenches 330.

[0164] On the one hand, the two first connection trenches 340 can enclose the multiple second trenches 330, that is, the two first connection trenches 340 can separate the insulated gate bipolar transistor region 301 and the fast recovery diode region 302, thereby preventing the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other in the process, thereby ensuring the performance of the two regions. On the other hand, the two first connection trenches 340 can increase the current carrying capacity of the fast recovery diode region 302, thereby improving the working performance of the semiconductor device 300 and improving the reliability of the semiconductor device 300.

[0165] In combination with Figures 23 and 24, the semiconductor device 300 may further include: a second connecting trench 350, the second connecting trench 350 extends from the first main surface 381 toward the second main surface 382 and reaches the drift layer 310, the second connecting trench 350 is extended in the second direction, the second connecting trench 350 connects the gate trench 32221 in the gate trench group 3222 adjacent to one end of the second trench 330, and connects the two adjacent gate trench groups 3222 adjacent to one end of the second trench 330.

[0166] Specifically, the gate trench 32221 in each gate trench group 3222 is flush with one end of the second trench 330 adjacent to the gate trench 330. By setting the second connecting trench 350, the second connecting trench 350 can connect one end of the gate trench 32221 in the gate trench group 3222 adjacent to the second trench 330 when extending along the second direction, and the end portions of multiple gate trenches 32221 in two adjacent gate trench groups 3222 adjacent to the second trench 330 are flush. While the second connecting trench 350 connects one end of the gate trench 32221 in the gate trench group 3222 adjacent to the second trench 330, it can continue to extend to connect one end of the second trench 330 adjacent to the two adjacent gate trench groups 3222.

[0167] That is, the second connecting groove 350 can connect all the gate trenches 32221 in the sub-groove portion 3221 to one end adjacent to the second trench 330, and the second connecting groove 350 can enclose all the gate trenches 32221 in the sub-groove portion 3221 outside, thereby not only improving the current-carrying capacity of the insulated gate bipolar transistor region 301 and even the semiconductor device 300, but also enclosing one end adjacent to the second trench 330 of the gate trench 32221 in each gate trench group 3222, avoiding mutual interference between the gate trench group 3222 and the second trench 330 in the process, preventing the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other in the process, and ensuring the performance of the two regions.

[0168] Thus, by making one of the two first connecting trenches 340 connect one end of the multiple second trenches 330 in the first direction, and the other connect the other end of the multiple second trenches 330 in the first direction, and making the second connecting trench 350 connect the gate trench 32221 in the gate trench group 3222 adjacent to one end of the second trench 330, and connecting the two adjacent gate trench groups 3222 adjacent to one end of the second trench 330, this can not only prevent the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other in the process and ensure the performance of each of the two regions, but also improve the current carrying capacity of the semiconductor device 300, thereby improving the working performance of the semiconductor device 300.

[0169] 23 and 24 , one end of the gate trench 32221 adjacent to the second trench 330 protrudes beyond one end of the dummy gate trench 3223 adjacent to the second trench 330 , and the dummy gate trench 3223 and the second connection trench 350 are spaced apart from each other in the first direction.

[0170] Specifically, one end of the gate trench 32221 adjacent to the second trench 330 protrudes from one end of the dummy gate trench 3223 adjacent to the second trench 330. By making the end of the dummy gate trench 3223 adjacent to the second trench 330 and the second connecting trench 350 also spaced apart in the first direction, the second connecting trench 350 can separate the dummy gate trench 3223 from the first connecting trench 340 in the first direction, thereby avoiding mutual interference between the dummy gate trench 3223 and the first connecting trench 340 or the second trench 330 in the process. In some embodiments, the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 are prevented from interfering with each other in the process, thereby ensuring the performance of the two regions.

[0171] In some embodiments, the semiconductor device 300 may further include: a third connecting trench 360, the third connecting trench 360 extending from the first main surface 381 toward the second main surface 382 and reaching the drift layer 310, the third connecting trench 360 extending in the second direction, at least two dummy gate trenches 3223 are arranged between two adjacent gate trench groups 3222, and the third connecting trench 360 connects one end of the dummy gate trench 3223 between the two adjacent gate trench groups 3222 adjacent to the second trench 330.

[0172] Specifically, when at least two dummy gate trenches 3223 are provided between two adjacent gate trench groups 3222, one end of at least two dummy gate trenches 3223 between the two adjacent gate trench groups 3222 is flush with one end of the second trench 330. By providing a third connecting trench 360, the third connecting trench 360 is extended in the second direction and is spaced apart from the second connecting trench 350 in the second direction. In this way, while the third connecting trench 360 is extended in the second direction, one end of the dummy gate trench 3223 between the two adjacent gate trench groups 3222 that is adjacent to the second trench 330 can be connected. This not only makes all the dummy gate trenches 3223 between the two adjacent gate trench groups 3222 connected, but also makes the third connecting trench 360 play a role in current conduction, thereby improving the current conduction capacity of the semiconductor device 300, and the dummy gate trenches 3223 between the two adjacent gate trench groups 3222 can be connected. The end adjacent to the second trench 330 is enclosed, which can prevent the IGBT region 301 and the fast recovery diode region 302 from interfering with each other during the manufacturing process in some embodiments, thereby ensuring the operating performance of the semiconductor device 300 .

[0173] As shown in FIG24 , the plurality of second trenches 330 may include a first sub-trench 331, wherein the plurality of first sub-trenches 331 correspond to and are spaced apart from the plurality of gate trenches 32221. The plurality of second trenches 330 may also include a second sub-trench 332, wherein the plurality of second sub-trenches 332 correspond to and are spaced apart from the plurality of dummy gate trenches 3223. In this manner, while preventing the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other during the manufacturing process, not only can the circuit distribution of the semiconductor device 300 be made more uniform, thereby improving the operating performance of the semiconductor device 300, but also the first sub-trench 331 and the corresponding gate trench 32221 can be conveniently etched simultaneously, and the second sub-trench 332 and the corresponding dummy gate trench 3223 can be conveniently etched simultaneously, thereby simplifying the manufacturing process of the semiconductor device 300.

[0174] It should be noted that, in other embodiments of the present application, as shown in Figures 28 and 29, when there is no dummy gate trench 3223 between two adjacent gate trench groups 3222, that is, when no dummy gate trench 3223 is provided in the insulated gate bipolar transistor region 301 and only the gate trench 32221 is provided, the semiconductor device 300 does not need to provide the third connecting trench 360. It is only necessary to connect the ends of the multiple gate trenches 32221 adjacent to the second trench 330 through the second connecting trench 350, and to connect one of the two first connecting trenches 340 to one end of the multiple second trenches 330 in the first direction, and the other to connect the other ends of the multiple second trenches 330 in the first direction. This not only prevents the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other in the process and ensures the performance of the two regions, but also increases the current carrying capacity of the two regions, thereby improving the working performance of the semiconductor device 300.

[0175] As described above, two of the second trenches 330 on both sides of the second direction are defined as the first boundary trench 333 and the second boundary trench 334, so that the interior of the area enclosed by the first boundary trench 333, the second boundary trench 334 and the two first connection trenches 340 is the fast recovery diode area 302, and the exterior of the area enclosed by the first boundary trench 333, the second boundary trench 334 and the two first connection trenches 340 is the insulated gate bipolar transistor area 301.

[0176] Considering that the first connection trench 340 is located at the junction of the fast recovery diode region 302 and the insulated gate bipolar transistor region 301, by arranging the first connection trench 340 and the second connection trench 350 at intervals in the first direction, not only can the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 be separated, effectively and reliably avoiding mutual interference between the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 in the process, thereby ensuring the performance of the insulated gate bipolar transistor region 301 and the fast recovery diode region 302, but also the current carrying capacity of the semiconductor device 300 can be increased, thereby improving the working performance of the semiconductor device 300.

[0177] As shown in Figures 24 and 25, the spacing distance between the first connecting groove 340 and the second connecting groove 350 in the first direction is D1, the spacing distance between two adjacent first grooves 320 in the second direction is D2, and the spacing distance between two adjacent second grooves 330 in the second direction is D3. D1, D2 and D3 satisfy the relationship: D1=D2=D3.

[0178] Specifically, by setting the spacing distance between the first connecting groove 340 and the second connecting groove 350 in the first direction, the spacing distance between two adjacent first grooves 320 in the second direction, and the spacing distance between two adjacent second grooves 330 in the second direction to be equal, the distribution of the first connecting groove 340 and the second connecting groove 350 can be made more uniform, which can improve the uniformity of the circuit distribution of the semiconductor device 300 and improve the working performance of the semiconductor device 300.

[0179] In addition, the processes in the first trench 320, the second trench 330, the first connecting trench 340, the second connecting trench 350, and the third connecting trench 360 are the same, and an oxide insulating layer 370 can be generated therein and polysilicon 371 can be deposited. The widths and depths of the first trench 320, the second trench 330, the first connecting trench 340, the second connecting trench 350, and the third connecting trench 360 can be set to be the same, so that the first trench 320, the second trench 330, the first connecting trench 340, the second connecting trench 350, and the third connecting trench 360 can be etched simultaneously, which can simplify the process steps of the semiconductor device 300.

[0180] In some embodiments, D1 satisfies the relationship: 1.5 μm ≤ D1 ≤ 2 μm. Specifically, D1 can be set to 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, or 1.9 μm. The specific value of D1 is not limited in this application. Thus, the spacing distance between the first connection trench 340 and the second connection trench 350 in the first direction can be set within a reasonable range. This not only avoids the spacing distance between the first connection trench 340 and the second connection trench 350 in the first direction being too small, resulting in the spacing distance between the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 being too small, resulting in the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 still interfering with each other in the process, but also avoids the spacing distance between the first connection trench 340 and the second connection trench 350 in the first direction being too large, resulting in the overall area of ​​the semiconductor device 300 being too large. In this way, a balance can be achieved between the separation effect of the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 and the overall area of ​​the semiconductor device 300. In some embodiments, the structural design of the semiconductor device 300 can be optimized and the working performance of the semiconductor device 300 can be improved.

[0181] The following describes a method for manufacturing a semiconductor device 300 by way of example with reference to FIG. 25 and FIG. 28 to FIG. 32 . The semiconductor device 300 is an RC-IGBT.

[0182] As shown in FIG28 , an N-substrate material is provided to form a structure 1 .

[0183] As shown in FIG29 , based on Structure 1, the first trench 320 , the second trench 330 , the first connecting trench 340 , the second connecting trench 350 , and the third connecting trench 360 are etched, and an oxidized insulating layer 370 is grown to form Structure 2 .

[0184] As shown in FIG30 , based on structure 2 , polysilicon 371 is deposited and etched, and then a P-well region 311 and an N+ second emitter layer 312 are sequentially implanted to form structure 3 .

[0185] As shown in FIG31 , on the basis of structure 3 , a dielectric layer 313 is deposited, and contact holes are etched on the dielectric layer 313 to form structure 4 .

[0186] As shown in FIG32 , on the basis of structure 4 , metal layer sputtering is performed to prepare an emitter metal layer 314 to form structure 5 .

[0187] As shown in FIG25 , based on structure 5, the back N+ field stop layer 315 is implanted, the back P+ collector layer 316 is implanted, the back FRD region N+ first emitter layer 317 is implanted, laser annealing is performed, and back metal sputtering is performed to prepare a collector metal layer 318. Finally, a semiconductor device 300 is formed.

[0188] Other structures and operations of the semiconductor device 300 according to some embodiments of the present disclosure are known to those skilled in the art and will not be described in detail here.

[0189] With the development of science and technology, the application of semiconductor devices is becoming more and more extensive. During the design and manufacturing of semiconductor devices, trenches are provided, where gates can be formed to ensure the normal operation of the semiconductor devices.

[0190] In the related art, the grooves are mostly strip-shaped, and the electrostatic protection of the semiconductor device is easily invalidated at the edge of the groove, resulting in low stability and reliability of the semiconductor device.

[0191] In the semiconductor device 400 proposed in some embodiments of the present disclosure, a connecting groove portion is provided, the connecting groove portion is provided in the ring layer and extended in the second direction, the connecting groove portion is located at the edge of the active area of ​​the semiconductor device, and the connecting groove portion connects at least one end of at least two gate groove portions in each gate groove group. This can not only optimize the electric field distribution of the semiconductor device, improve the electrostatic protection capability and insulation breakdown withstand voltage capability of the semiconductor device, but also improve the turn-on speed of the semiconductor device and reduce the turn-on loss.

[0192] 33 to 42 , a semiconductor device 400 according to some embodiments of the present disclosure is described. In the following description, N and P represent the conductivity type of the semiconductor. In this application, the first conductivity type is set to P type and the second conductivity type is set to N type.

[0193] As shown in Figures 33 to 38 , the semiconductor device 400 according to the present application may primarily include a semiconductor substrate 410. The substrate 410 is a basic component of the semiconductor device 400 of the present application and may provide a mounting base for at least some of the other components of the semiconductor device 400. The semiconductor substrate 410 has a first main surface 401 and a second main surface 402 opposite to the first main surface 401.

[0194] The semiconductor device 400 of the present application may further include a drift layer 411 , which is disposed between the first main surface 401 and the second main surface 402 .

[0195] The semiconductor device 400 of the present application may further include a ring layer 412, which is also disposed on the semiconductor substrate 410 and located between the first main surface 401 and the second main surface 420. Specifically, the ring layer 412 is disposed on the side of the drift layer 411 facing the first main surface 401, and the surface of the ring layer 412 facing away from the drift layer 411 constitutes a portion of the first main surface 401. In addition, an oxide insulating layer 413, a polycrystalline layer 414, and an interlayer dielectric layer 415 are stacked on the ring layer 412. A field stop layer 417 and a collector layer 418 are also disposed below the drift layer 411.

[0196] The ring layer 412 of the semiconductor device 400 of the present application may also be provided with a main groove portion 420, which extends in the first direction, so that a gate can be formed at the main groove portion 420, and an emitter metal layer 416 is provided on the interlayer dielectric layer 415, and a collector metal layer (not shown in the figure) is provided under the collector layer 418, thereby forming the basic structure of the semiconductor device 400 and ensuring the normal operation of the semiconductor device 400.

[0197] The main trench portion 420 may primarily include a plurality of gate trench groups 423 spaced apart in the second direction, with the first direction being perpendicular to the second direction. The main trench portion 420 may further include a plurality of dummy gate trench portions 422, with at least one dummy gate trench portion 422 disposed between two adjacent gate trench groups 423. The gate trench group 423 includes at least two gate trench portions 421 spaced apart in the second direction.

[0198] Specifically, both the gate groove portion 421 and the dummy gate groove portion 422 are provided with an oxide insulating layer 413, and polysilicon is deposited, but the first conductive type dopant is injected into the gate groove portion 421, and a second conductive type well region is provided. A gate can be formed at the gate groove portion 421, and it has a conductive channel and a current-carrying capability to ensure the normal operation of the semiconductor device 400. The first conductive type dopant is not injected into the dummy gate groove portion 422, and the second conductive type well region is not provided. It has no conductive channel and no current-carrying capability. The dummy gate groove portion 422 can be connected to the emitter to reduce the Miller capacitance and reduce the current density.

[0199] At least two gate trench portions 421 are formed into a gate trench group 423, at least one dummy gate trench portion 422 is formed into a dummy gate trench group 424, and both the gate trench group 423 and the dummy gate trench group 424 are arranged in plurality, and the plurality of gate trench groups 423 and the plurality of dummy gate trench groups 424 are alternately arranged in sequence in the second direction. In this way, the arrangement of the plurality of gate trench portions 421 and the plurality of dummy gate trench portions 422 in the second direction can be more reasonable, thereby improving the working performance of the semiconductor device 400 in some embodiments.

[0200] In combination with Figures 33-36 and Figure 38, the semiconductor device 400 of the present application may further include: a connecting groove portion 430, the connecting groove portion 430 is arranged in the ring layer 412, and extends in the second direction, the connecting groove portion 430 is located at the edge of the active area 403 of the semiconductor device 400, and the connecting groove portion 430 connects at least one end of at least two gate groove portions 421 in each gate groove group 423, wherein the first direction is perpendicular to the second direction.

[0201] Specifically, at least two gate groove portions 421 in each gate groove group 423 are spaced apart in the second direction, that is, the ends of at least two gate groove portions 421 in each gate groove group 423 are also spaced apart in the second direction. Considering that the electric field distribution in the area where the ends of the gate groove portions 421 are located is relatively concentrated, the distribution of the electric field is not uniform, and electrostatic protection failure is likely to occur, and the insulation breakdown withstand voltage capability is also low, by arranging the connecting groove portion 430 in the ring layer 412, the connecting groove portion 430 is spaced apart in the second direction. The connecting groove portion 430 is extended in two directions, and the connecting groove portion 430 is located at the edge of the active area 403 of the semiconductor device 400, so that the connecting groove portion 430 connects at least one end of at least two gate groove portions 421 in each gate groove group 423. In this way, in each gate groove group 423, the connecting groove portion 430 can surround at least two gate groove portions 421 at at least one end in the first direction, so that the connecting groove portion 430 is connected to at least two gate groove portions 421 in each gate groove group 423.

[0202] On the one hand, the connecting groove portion 430 surrounds the outside of the end portions of at least two gate groove portions 421 in each gate groove group 423, which can optimize the electric field distribution at the end portions of at least two gate groove portions 421 in each gate groove group 423, making the electric field distribution at the end portions of at least two gate groove portions 421 in each gate groove group 423 more uniform, thereby effectively improving the electrostatic protection capability of the semiconductor device 400, avoiding electrostatic failure of the semiconductor device 400 at the end portions of the main groove portion 420, and improving the insulation withstand voltage breakdown capability of the semiconductor device 400, thereby improving the reliability of the semiconductor device 400.

[0203] On the other hand, the connecting trench portion 430 can serve as a gate path, thereby increasing the gate path, improving the turn-on speed of the semiconductor device 400, and reducing turn-on loss.

[0204] Therefore, by setting the connecting groove portion 430, the connecting groove portion 430 is set in the ring layer 412 and extended in the second direction, the connecting groove portion 430 is located at the edge of the active area 403 of the semiconductor device 400, and the connecting groove portion 430 connects at least one end of at least two gate groove portions 421 in each gate groove group 423. This can not only optimize the electric field distribution of the semiconductor device 400, improve the electrostatic protection capability and insulation breakdown withstand voltage capability of the semiconductor device 400, but also improve the turn-on speed of the semiconductor device 400 and reduce the turn-on loss.

[0205] As shown in FIG38 , connecting trench portions 430 are provided at both ends of at least two gate trench portions 421 in each gate trench group 423. Specifically, the gate trench portion 421 has two ends in a first direction. By providing connecting trench portions 430 at both ends of at least two gate trench portions 421 in each gate trench group 423, the connecting trench portion 430 at one end can connect one end of the at least two gate trench portions 421, thereby connecting them, and the connecting trench portion 430 at the other end can connect the other ends of the at least two gate trench portions 421, thereby connecting them. In this way, all ends of each gate trench group 423 can be connected to the connecting trench portion 430, thereby avoiding the existence of unconnected ends of each gate trench group 423. In some embodiments, the electric field distribution of the semiconductor device 400 can be optimized, the electrostatic protection capability and dielectric breakdown capability of the semiconductor device 400 can be improved, and the turn-on speed of the semiconductor device 400 can be increased in some embodiments.

[0206] It should be noted that the semiconductor device 400 may also include a gate pad 440, which is used to connect to the gate and serve as a gate lead-out terminal. The gate groove portion 421 and the dummy gate groove portion 422 are disconnected at the gate pad 440. Therefore, a connecting groove portion 430 can also be provided at the end of the gate groove group 423 close to the gate pad 440, so that the connecting groove portion 430 connects the end of the gate groove group 423 close to the gate pad 440, thereby more reliably improving the electrostatic protection capability of the semiconductor device 400 and improving the turn-on speed of the semiconductor device 400.

[0207] In some embodiments of the present application, a dummy gate trench portion 422 is disposed between at least two gate trench portions 421 in each gate trench group 423. Specifically, a dummy gate trench portion 422 may be disposed between at least two gate trench portions 421 in each gate trench group 423, and the length of the dummy gate trench portion 422 in the first direction is no greater than the length of the gate trench portion 421. This prevents the dummy gate trench portion 422 from affecting the connection between at least one end of the at least two gate trench portions 421 in each gate trench group 423 by the connecting trench portion 430.

[0208] In a specific embodiment of the present application, as shown in FIG38 , each gate trench group 423 may primarily include two gate trench portions 421, and a connecting trench portion 430 connects at least one end of the two gate trench portions 421 in each gate trench group 423. Specifically, each gate trench group 423 may primarily include two gate trench portions 421, and the connecting trench portion 430 connects at least one end of the two gate trench portions 421 in each gate trench group 423. This can make the number of gate trench portions 421 in each gate trench group 423 more reasonably arranged and also facilitate the arrangement of the connecting trench portion 430.

[0209] 33 to 35 , the connecting trench portion 430 connects at least one end of the plurality of gate trench groups 423 .

[0210] Specifically, considering that the connecting groove portion 430 connects at least two gate groove portions 421 in each gate groove group 423, although the electric field distribution of the semiconductor device 400 can be optimized to a certain extent and the electrostatic protection capability and insulation breakdown capability of the semiconductor device 400 can be improved, the multiple gate groove groups 423 are still in an unconnected state, and each gate groove group 423 still has an end area in the second direction, and the electric field will still be concentrated here. The electrostatic protection capability and insulation breakdown capability of the semiconductor device 400 still need to be improved.

[0211] By making the connecting groove portion 430 connect at least one end of multiple gate groove groups 423, it is convenient to connect the connecting groove portion 430 with at least one end of all gate groove portions 421 of the semiconductor device 400, so that the connecting groove portion 430 can surround at least one end of all gate groove portions 421 of the semiconductor device 400, and the connecting groove portion 430 is connected to at least one end of all gate groove portions 421 of the semiconductor device 400.

[0212] On the one hand, the connecting groove portion 430 surrounds the outside of the end portions of all the gate groove portions 421, which can not only optimize the electric field distribution at the end portions of all the gate groove portions 421, making the electric field distribution at the end portions of all the gate groove portions 421 more uniform and avoiding electric field concentration at the end portions of all the gate groove portions 421, but also increase the gate oxide thickness at the end portions of all the gate groove portions 421, thereby effectively improving the electrostatic protection capability of the semiconductor device 400, avoiding electrostatic failure of the semiconductor device 400 at the end portions of the gate groove portions 421, and improving the reliability of the semiconductor device 400.

[0213] On the other hand, the connecting groove portion 430 can serve as a gate path, thereby increasing the gate path, improving the turn-on speed of the semiconductor device 400 , reducing turn-on loss, and improving the operating performance of the semiconductor device 400 .

[0214] On the other hand, in order to ensure the normal extraction of current, it is necessary to set a contact hole 419 in the semiconductor device 400. The contact hole 419 can connect the gate with other materials to realize the function of the circuit. By setting the connecting groove portion 430, the connecting groove portion 430 is connected to the end portions of multiple gate groove portions 421. In this way, under the premise of ensuring the normal operation of the semiconductor device 400, the contact hole 419 can be directly set in the connecting groove portion 430, thereby facilitating the manufacture of the contact hole 419 and reducing the manufacturing difficulty of the contact hole 419 and even the semiconductor device 400.

[0215] In this way, not only can the electric field distribution of the semiconductor device 400 be optimized and the electrostatic protection capability of the semiconductor device 400 be improved, but also the turn-on speed of the semiconductor device 400 can be increased, the turn-on loss can be reduced, and the manufacturing difficulty of the semiconductor device 400 can be reduced.

[0216] In some embodiments of the present application, in combination with Figures 33-35, the length of the gate groove portion 421 in the first direction is greater than the length of the dummy gate groove portion 422 in the first direction, the two ends of the gate groove portion 421 in the first direction protrude from the two ends of the dummy gate groove portion 422 in the first direction, and the connecting groove portion 430 is in the shape of a long strip and is spaced apart from the dummy gate groove portion 422.

[0217] Specifically, considering that the dummy gate groove portion 422 has no conductive ability, the end of the dummy gate groove portion 422 will not experience electrostatic failure. When the length of the gate groove portion 421 in the first direction is greater than the length of the dummy gate groove portion 422 in the first direction, and the two ends of the gate groove portion 421 in the first direction protrude from the two ends of the dummy gate groove portion 422 in the first direction, it is only necessary to connect the connecting groove portion 430 with each gate groove group 423, and there is no need to connect multiple dummy gate groove groups 424. The connecting groove portion 430 is in a long strip shape and is spaced apart from the dummy gate groove portion 422, which can improve the electrostatic protection capability of the semiconductor device 400 and the turn-on speed of the semiconductor device 400, thereby reducing the manufacturing cost of the semiconductor device 400.

[0218] In other embodiments of the present application, the connecting trench portion 430 connects the plurality of gate trench groups 423 and at least one end of the plurality of dummy gate trench portions 422. Specifically, the connecting trench portion 430 can also connect the plurality of gate trench groups 423 and at least one end of the plurality of dummy gate trench portions 422. That is, the connecting trench portion 430 can connect at least one end of all the main trench portions 420. This facilitates the provision of the connecting trench portion 430 while optimizing the electric field distribution of the semiconductor device 400, thereby reducing the difficulty of manufacturing the semiconductor device 400.

[0219] In some embodiments, the length of the dummy gate trench 422 in the first direction is equal to the length of the gate trench 421 in the first direction, and both ends of the gate trench 421 in the first direction are flush with both ends of the dummy gate trench 422. Specifically, when the length of the dummy gate trench 422 in the first direction of the semiconductor device 400 is equal to the length of the gate trench 421 in the first direction, and both ends of the gate trench 421 in the first direction are flush with both ends of the dummy gate trench 422 in the first direction, the connecting trench 430 can be directly connected between the ends of the gate trench 421 and the ends of the dummy gate trench 422, so that the connecting trench 430 passes through the active area 403 of the semiconductor device 400 in the first direction, making the structure of the semiconductor device 400 simpler and more reliable.

[0220] In some further embodiments of the present application, a connecting trench portion 430 connects at least one end of a plurality of dummy gate trench portions 422. Specifically, while a connecting trench portion 430 is provided to connect at least one end of a plurality of gate trench portions 421 in each gate trench group 423, an additional connecting trench portion 430 may be provided to connect at least one end of a plurality of dummy gate trench portions 422 between two adjacent gate trench groups 423. In this way, on the one hand, the connecting trench portion 430 can also optimize the electric field distribution at at least one end of the plurality of dummy gate trench portions 422, avoid electric field concentration, and improve the reliability of the semiconductor device 400. On the other hand, it can also facilitate the separate design of the connecting trench portion 430 and the dummy gate trench portion 422, thereby expanding the application scenarios of the semiconductor device 400.

[0221] In some embodiments, the length of the dummy gate trench portion 422 in the first direction is greater than the length of the gate trench portion 421 in the first direction, and both ends of the dummy gate trench portion 422 in the first direction protrude beyond both ends of the gate trench portion 421 in the first direction. Specifically, when the length of the dummy gate trench portion 422 in the first direction of the semiconductor device 400 is greater than the length of the gate trench portion 421 in the first direction, and both ends of the dummy gate trench portion 422 in the first direction protrude beyond both ends of the gate trench portion 421 in the first direction, a separate connecting trench portion 430 can be provided within each gate trench group 423, and a separate connecting trench portion 430 can be provided between the multiple dummy gate trench portions 422 between two adjacent gate trench groups 423, thereby preventing the two from interfering with each other and ensuring the electrostatic protection capability and dielectric breakdown withstand voltage capability of the semiconductor device 400.

[0222] As shown in Figures 36 and 37, the main groove portion 420 and the connecting groove portion 430 are both extended in the direction from the first main surface 401 toward the second main surface 402. In the direction from the first main surface 401 to the second main surface 402, the depth of the main groove portion 420 is L, and the depth of the connecting groove portion 430 is L2. L1 and L2 satisfy the relationship: L1≤L2.

[0223] Specifically, by setting the depth of the connecting groove portion 430 to be no less than the depth of the main groove portion 420 in the direction from the first main surface 401 to the second main surface 402, the connecting groove portion 430 can completely connect the main groove portion 420 in the direction from the first main surface 401 to the second main surface 402, thereby avoiding insufficient depth of the connecting groove portion 430, and the bottom of the main groove portion 420 is not connected to the connecting groove portion 430, resulting in uneven electric field distribution below the main groove portion 420, and the electrostatic protection of the semiconductor device 400 is still prone to failure. In this way, the optimization of the electric field at each position of the end of the main groove portion 420 can be guaranteed, and the electrostatic protection capability of the semiconductor device 400 can be improved in some embodiments.

[0224] 36 and 37 , the width of the main groove portion 420 in the second direction is W1 , and the width of the connecting groove portion 430 in the first direction is W2 , and W1 and W2 satisfy the relationship: W1 ≤ W2 .

[0225] Specifically, the width of the connecting groove portion 430 in the first direction can affect the size of the path of the connecting groove portion 430. By setting the width of the connecting groove portion 430 in the first direction to be no less than the width of the main groove portion 420 in the second direction, the path capacity of the connecting groove portion 430 can be increased in some embodiments while increasing the gate path through the connecting groove portion 430, thereby improving the turn-on speed of the semiconductor device 400 and reducing the loss of the semiconductor device 400 in some embodiments.

[0226] In some embodiments, the depth of the connecting groove portion 430 can be set to be the same as the depth of the main groove portion 420 in the direction from the first main surface 401 to the second main surface 402, and the width of the connecting groove portion 430 in the first direction can be set to be the same as the width of the main groove portion 420 in the second direction. In this way, while improving the electrostatic protection capability of the semiconductor device 400 and improving the switching speed of the semiconductor device 400, the synchronous etching of the main groove portion 420 and the connecting groove portion 430 can be facilitated, and the structures are the same or almost the same, thereby reducing processing complexity and improving production efficiency.

[0227] As shown in Figures 36 and 37 , the main trench portion 420 and the connecting trench portion 430 are both spaced apart from the drift layer 411. Specifically, the main trench portion 420 and the connecting trench portion 430 are etched and formed on the ring layer 412. By spaced apart from the drift layer 411, that is, by not penetrating the ring layer 412, the main trench portion 420 and the connecting trench portion 430 are spaced apart from the drift layer 411. This ensures that the field ring layer 412 exists between the main trench portion 420 and the connecting trench portion 430 and the drift layer 411, thereby ensuring the electrical performance of the semiconductor device 400.

[0228] 33 and 35 , the semiconductor body 410 may include an active area 403. The semiconductor body 410 may further include a termination area 404, which is disposed around the outside of the active area 403. The main trench portion 420 is disposed in the active area 403, and the connecting trench portion 430 is located between the active area 403 and the termination area 404.

[0229] Specifically, the active region 403 can bear most of the forward current during forward conduction and can also bear a high blocking voltage when a reverse voltage is applied. When a reverse voltage is applied to the semiconductor device 400, the terminal region 404 can alleviate the electric field crowding at the edge of the active region 403, thereby achieving the purpose of improving the reverse breakdown voltage of the semiconductor device 400.

[0230] In some embodiments, the main groove portion 420 is arranged in the active area 403, and the end of the main groove portion 420 is located between the active area 403 and the terminal area 404. By arranging the connecting groove portion 430 between the active area 403 and the terminal area 404, the connecting groove portion 430 can block the diffusion of the electric field in the active area 403, and can more effectively and reliably avoid the failure of electrostatic protection in the area between the active area 403 and the terminal area 404, thereby improving the electrostatic protection capability of the semiconductor device 400.

[0231] The following describes a method for manufacturing a semiconductor device 400400 by way of example with reference to FIG. 39 to FIG. 42 :

[0232] As shown in FIG39 , a substrate is provided, the substrate being an N-type drift layer 411 , and P-type dopants are implanted into the substrate to form the N-type drift layer 411 and the P-type ring layer 412 .

[0233] As shown in FIG. 40 , a connection groove portion 430 is etched in the collar layer 412 , and an oxidized insulating layer 413 is grown over the collar layer 412 .

[0234] As shown in FIG. 41 , polysilicon deposition and polycrystalline etching are performed on the oxidized insulating layer 413 to form a polycrystalline layer 414 .

[0235] As shown in Figure 42, an interlayer dielectric is grown above the polycrystalline layer 414 to form an interlayer dielectric layer 415, metal sputtering is performed above the interlayer dielectric layer 415 to form an emitter metal layer 416, and a field stop layer 417, a collector layer 418 and a collector metal layer are prepared below the drift layer 411, finally forming a semiconductor device 400.

[0236] It should be noted that this manufacturing method only uses the manufacturing of the connecting groove portion 430 as an example. While etching the connecting groove portion 430 on the ring layer 412, the main groove portion 420 can be simultaneously etched, which is not described in detail here. In addition, this manufacturing method only illustrates a portion of the manufacturing process. The other structures and operations of the semiconductor device 400 according to some embodiments of the present disclosure are well known to those skilled in the art and will not be described in detail here.

[0237] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A semiconductor device comprising: A substrate having a first main surface and a second main surface opposite to the first main surface; A drift layer of a first conductivity type, wherein the drift layer is disposed between the first main surface and the second main surface; a first trench, wherein the first trench extends from the first main surface toward the second main surface and reaches the drift layer, wherein the first trench extends in a first direction and is in plurality, wherein the plurality of first trenches are spaced apart in a second direction, wherein a portion of the plurality of first trenches is a first spaced trench, and the first spaced trench is a plurality of first sub-trenches and second sub-trenches spaced apart in the first direction; a second trench, the second trench extending from the first main surface toward the second main surface and reaching the drift layer, the second trench extending in the first direction and being in plurality, the second trench being spaced apart between the first sub-trench and the second sub-trench in the first direction; A first connecting groove, wherein the first connecting groove extends from the first main surface toward the second main surface and reaches the drift layer, the first connecting groove is extended in the second direction, there are two first connecting grooves, one of the two first connecting grooves connects one end of a plurality of the second grooves, and the other connects the other ends of the plurality of the second grooves.

2. The semiconductor device according to claim 1, wherein One of the plurality of second grooves that is adjacent to the first groove on one side in the second direction is a first boundary groove, and one of the plurality of second grooves that is adjacent to the first groove on the other side in the second direction is a second boundary groove, and the area enclosed by the first boundary groove, the second boundary groove and the two first connection grooves is a fast recovery diode area.

3. The semiconductor device according to claim 2, wherein: One of the two first connecting grooves corresponding to the first sub-groove is spaced apart from the first sub-groove, and one of the two first connecting grooves corresponding to the second sub-groove is spaced apart from the second sub-groove.

4. The semiconductor device according to claim 3, wherein: It also includes a second connecting groove, which extends from the first main surface toward the second main surface and reaches the drift layer. The second connecting groove is extended in the second direction. There are two second connecting grooves, one of the two second connecting grooves connects one end of multiple first sub-grooves adjacent to the second groove, and the other connects one end of multiple second sub-grooves adjacent to the second groove.

5. The semiconductor device according to claim 4, wherein: The first plurality of grooves include a first main groove and a plurality of first spacing grooves. The first main grooves are multiple and are respectively located on both sides of the first spacing grooves in the second direction. Both ends of the second connecting groove in the second direction are respectively connected to the first main grooves on both sides.

6. The semiconductor device according to claim 5, wherein: One of the multiple first main trenches that is adjacent to one side of the multiple first spacing trenches in the second direction is a third boundary trench, and one of the multiple first main trenches that is adjacent to the other side of the multiple first spacing trenches in the second direction is a fourth boundary trench, and the outside of the area enclosed by the third boundary trench, the fourth boundary trench and the two second connection trenches is an insulated gate bipolar transistor area.

7. The semiconductor device according to claim 6, wherein: It also includes a third connecting groove, a part of the second groove is a second spacing groove, the second spacing groove includes a third sub-groove, a fourth sub-groove and a fifth sub-groove, the third sub-groove and the fifth sub-groove are respectively arranged at the two ends of the fourth sub-groove in the first direction and are respectively spaced from the fourth sub-groove, the third connecting groove extends from the first main surface toward the second main surface and reaches the drift layer, the third connecting groove extends in the second direction, there are two third connecting grooves, one of the two third connecting grooves connects one end of multiple fourth sub-grooves, and the other connects the other ends of multiple fourth sub-grooves.

8. The semiconductor device according to claim 7, wherein: One of the two third connecting trenches connects one end of the plurality of third sub-trenches adjacent to the fourth sub-trench, and the other connects one end of the plurality of fifth sub-trenches adjacent to the fourth sub-trench.

9. The semiconductor device according to claim 7, wherein: Two of the fourth sub-grooves on both sides of the second direction of the plurality of fourth sub-grooves are respectively the fifth boundary trench and the sixth boundary trench, and the fifth boundary trench, the sixth boundary trench and the two third connection trenches are all located in the fast recovery diode area and the area enclosed together is the main conductive area of ​​the fast recovery diode.

10. The semiconductor device according to claim 9, wherein The portion of the fast recovery diode region that is located outside the fast recovery diode main conductive region is a fast recovery diode transition region.

11. The semiconductor device according to claim 10, wherein A dielectric layer is arranged on the first main surface, and an emitter metal layer is arranged on the side of the dielectric layer away from the first main surface. The dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer corresponds to the insulated gate bipolar transistor region and the main conductive region of the fast recovery diode, and the second dielectric layer corresponds to the transition region of the fast recovery diode. A plurality of contact holes arranged at intervals are opened on the first dielectric layer, and the emitter metal layer passes through the contact holes and contacts the first main surface. The second dielectric layer is a continuous layer and blocks the emitter metal layer and the first main surface.

12. The semiconductor device according to claim 7, wherein: At least a portion of one of the two first connecting grooves connects an end of the third sub-groove away from the fourth sub-groove, and at least a portion of the other of the two first connecting grooves connects an end of the fifth sub-groove away from the fourth sub-groove.

13. The semiconductor device according to claim 7, wherein: The first connection groove and the second connection groove are spaced apart by a distance D1 in the first direction, and the first connection groove and the third connection groove are spaced apart by a distance D2 in the first direction. D1 and D2 satisfy the relationship: D1<D2.

14. The semiconductor device according to claim 13, wherein: D2 satisfies the relationship: D2 ≥ 30 μm.

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